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1 /*
2 * Emulation of Linux signals
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu.h"
21 #include "user-internals.h"
22 #include "signal-common.h"
23 #include "linux-user/trace.h"
24 #include "target/arm/cpu-features.h"
25 #include "gcs-internal.h"
26
27 struct target_sigcontext {
28 uint64_t fault_address;
29 /* AArch64 registers */
30 uint64_t regs[31];
31 uint64_t sp;
32 uint64_t pc;
33 uint64_t pstate;
34 /* 4K reserved for FP/SIMD state and future expansion */
35 char __reserved[4096] __attribute__((__aligned__(16)));
36 };
37
38 struct target_ucontext {
39 abi_ulong tuc_flags;
40 abi_ulong tuc_link;
41 target_stack_t tuc_stack;
42 target_sigset_t tuc_sigmask;
43 /* glibc uses a 1024-bit sigset_t */
44 char __unused[1024 / 8 - sizeof(target_sigset_t)];
45 /* last for future expansion */
46 struct target_sigcontext tuc_mcontext;
47 };
48
49 /*
50 * Header to be used at the beginning of structures extending the user
51 * context. Such structures must be placed after the rt_sigframe on the stack
52 * and be 16-byte aligned. The last structure must be a dummy one with the
53 * magic and size set to 0.
54 */
55 struct target_aarch64_ctx {
56 uint32_t magic;
57 uint32_t size;
58 };
59
60 #define TARGET_FPSIMD_MAGIC 0x46508001
61
62 struct target_fpsimd_context {
63 struct target_aarch64_ctx head;
64 uint32_t fpsr;
65 uint32_t fpcr;
66 uint64_t vregs[32 * 2]; /* really uint128_t vregs[32] */
67 };
68
69 #define TARGET_ESR_MAGIC 0x45535201
70
71 struct target_esr_context {
72 struct target_aarch64_ctx head;
73 uint64_t esr;
74 };
75
76 #define TARGET_FPMR_MAGIC 0x46504d52
77
78 struct target_fpmr_context {
79 struct target_aarch64_ctx head;
80 uint64_t fpmr;
81 };
82
83 #define TARGET_EXTRA_MAGIC 0x45585401
84
85 struct target_extra_context {
86 struct target_aarch64_ctx head;
87 uint64_t datap; /* 16-byte aligned pointer to extra space cast to __u64 */
88 uint32_t size; /* size in bytes of the extra space */
89 uint32_t reserved[3];
90 };
91
92 #define TARGET_SVE_MAGIC 0x53564501
93
94 struct target_sve_context {
95 struct target_aarch64_ctx head;
96 uint16_t vl;
97 uint16_t flags;
98 uint16_t reserved[2];
99 /* The actual SVE data immediately follows. It is laid out
100 * according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of
101 * the original struct pointer.
102 */
103 };
104
105 #define TARGET_SVE_VQ_BYTES 16
106
107 #define TARGET_SVE_SIG_ZREG_SIZE(VQ) ((VQ) * TARGET_SVE_VQ_BYTES)
108 #define TARGET_SVE_SIG_PREG_SIZE(VQ) ((VQ) * (TARGET_SVE_VQ_BYTES / 8))
109
110 #define TARGET_SVE_SIG_REGS_OFFSET \
111 QEMU_ALIGN_UP(sizeof(struct target_sve_context), TARGET_SVE_VQ_BYTES)
112 #define TARGET_SVE_SIG_ZREG_OFFSET(VQ, N) \
113 (TARGET_SVE_SIG_REGS_OFFSET + TARGET_SVE_SIG_ZREG_SIZE(VQ) * (N))
114 #define TARGET_SVE_SIG_PREG_OFFSET(VQ, N) \
115 (TARGET_SVE_SIG_ZREG_OFFSET(VQ, 32) + TARGET_SVE_SIG_PREG_SIZE(VQ) * (N))
116 #define TARGET_SVE_SIG_FFR_OFFSET(VQ) \
117 (TARGET_SVE_SIG_PREG_OFFSET(VQ, 16))
118 #define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \
119 (TARGET_SVE_SIG_PREG_OFFSET(VQ, 17))
120
121 #define TARGET_SVE_SIG_FLAG_SM 1
122
123 #define TARGET_ZA_MAGIC 0x54366345
124
125 struct target_za_context {
126 struct target_aarch64_ctx head;
127 uint16_t vl;
128 uint16_t reserved[3];
129 /* The actual ZA data immediately follows. */
130 };
131
132 #define TARGET_ZA_SIG_REGS_OFFSET \
133 QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES)
134 #define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \
135 (TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N))
136 #define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \
137 TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES)
138
139 #define TARGET_TPIDR2_MAGIC 0x54504902
140
141 struct target_tpidr2_context {
142 struct target_aarch64_ctx head;
143 uint64_t tpidr2;
144 };
145
146 #define TARGET_ZT_MAGIC 0x5a544e01
147
148 struct target_zt_context {
149 struct target_aarch64_ctx head;
150 uint16_t nregs;
151 uint16_t reserved[3];
152 /* ZTn register data immediately follows */
153 };
154
155 #define TARGET_ZT_SIG_REG_BYTES (512 / 8)
156 #define TARGET_ZT_SIG_REGS_SIZE(n) (TARGET_ZT_SIG_REG_BYTES * (n))
157 #define TARGET_ZT_SIG_CONTEXT_SIZE(n) (sizeof(struct target_zt_context) + \
158 TARGET_ZT_SIG_REGS_SIZE(n))
159 #define TARGET_ZT_SIG_REGS_OFFSET sizeof(struct target_zt_context)
160 QEMU_BUILD_BUG_ON(TARGET_ZT_SIG_REG_BYTES != \
161 sizeof_field(CPUARMState, za_state.zt0));
162
163 #define TARGET_GCS_MAGIC 0x47435300
164 #define GCS_SIGNAL_CAP(X) ((X) & TARGET_PAGE_MASK)
165
166 struct target_gcs_context {
167 struct target_aarch64_ctx head;
168 uint64_t gcspr;
169 uint64_t features_enabled;
170 uint64_t reserved;
171 };
172
173 struct target_rt_sigframe {
174 struct target_siginfo info;
175 struct target_ucontext uc;
176 };
177
178 struct target_rt_frame_record {
179 uint64_t fp;
180 uint64_t lr;
181 };
182
183 static void target_setup_general_frame(struct target_rt_sigframe *sf,
184 CPUARMState *env, target_sigset_t *set)
185 {
186 int i;
187
188 __put_user(0, &sf->uc.tuc_flags);
189 __put_user(0, &sf->uc.tuc_link);
190
191 target_save_altstack(&sf->uc.tuc_stack, env);
192
193 for (i = 0; i < 31; i++) {
194 __put_user(env->xregs[i], &sf->uc.tuc_mcontext.regs[i]);
195 }
196 __put_user(env->xregs[31], &sf->uc.tuc_mcontext.sp);
197 __put_user(env->pc, &sf->uc.tuc_mcontext.pc);
198 __put_user(pstate_read(env), &sf->uc.tuc_mcontext.pstate);
199
200 __put_user(env->exception.vaddress, &sf->uc.tuc_mcontext.fault_address);
201
202 for (i = 0; i < TARGET_NSIG_WORDS; i++) {
203 __put_user(set->sig[i], &sf->uc.tuc_sigmask.sig[i]);
204 }
205 }
206
207 static void target_setup_fpsimd_record(struct target_fpsimd_context *fpsimd,
208 CPUARMState *env)
209 {
210 int i;
211
212 __put_user(TARGET_FPSIMD_MAGIC, &fpsimd->head.magic);
213 __put_user(sizeof(struct target_fpsimd_context), &fpsimd->head.size);
214 __put_user(vfp_get_fpsr(env), &fpsimd->fpsr);
215 __put_user(vfp_get_fpcr(env), &fpsimd->fpcr);
216
217 for (i = 0; i < 32; i++) {
218 uint64_t *q = aa64_vfp_qreg(env, i);
219 #if TARGET_BIG_ENDIAN
220 __put_user(q[0], &fpsimd->vregs[i * 2 + 1]);
221 __put_user(q[1], &fpsimd->vregs[i * 2]);
222 #else
223 __put_user(q[0], &fpsimd->vregs[i * 2]);
224 __put_user(q[1], &fpsimd->vregs[i * 2 + 1]);
225 #endif
226 }
227 }
228
229 static void target_setup_esr_record(struct target_esr_context *ctx,
230 CPUARMState *env)
231 {
232 __put_user(TARGET_ESR_MAGIC, &ctx->head.magic);
233 __put_user(sizeof(*ctx), &ctx->head.size);
234 __put_user(env->cp15.esr_el[1], &ctx->esr);
235 }
236
237 static void target_setup_extra_record(struct target_extra_context *extra,
238 uint64_t datap, uint32_t extra_size)
239 {
240 __put_user(TARGET_EXTRA_MAGIC, &extra->head.magic);
241 __put_user(sizeof(struct target_extra_context), &extra->head.size);
242 __put_user(datap, &extra->datap);
243 __put_user(extra_size, &extra->size);
244 }
245
246 static void target_setup_end_record(struct target_aarch64_ctx *end)
247 {
248 __put_user(0, &end->magic);
249 __put_user(0, &end->size);
250 }
251
252 static void target_setup_sve_record(struct target_sve_context *sve,
253 CPUARMState *env, int size)
254 {
255 int i, j, vq = sve_vq(env);
256
257 memset(sve, 0, sizeof(*sve));
258 __put_user(TARGET_SVE_MAGIC, &sve->head.magic);
259 __put_user(size, &sve->head.size);
260 __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl);
261 if (FIELD_EX64(env->svcr, SVCR, SM)) {
262 __put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags);
263 }
264
265 /* Note that SVE regs are stored as a byte stream, with each byte element
266 * at a subsequent address. This corresponds to a little-endian store
267 * of our 64-bit hunks.
268 */
269 for (i = 0; i < 32; ++i) {
270 uint64_t *z = (void *)sve + TARGET_SVE_SIG_ZREG_OFFSET(vq, i);
271 for (j = 0; j < vq * 2; ++j) {
272 __put_user_e(env->vfp.zregs[i].d[j], z + j, le);
273 }
274 }
275 for (i = 0; i <= 16; ++i) {
276 uint16_t *p = (void *)sve + TARGET_SVE_SIG_PREG_OFFSET(vq, i);
277 for (j = 0; j < vq; ++j) {
278 uint64_t r = env->vfp.pregs[i].p[j >> 2];
279 __put_user_e(r >> ((j & 3) * 16), p + j, le);
280 }
281 }
282 }
283
284 static void target_setup_za_record(struct target_za_context *za,
285 CPUARMState *env, int size)
286 {
287 int vq = sme_vq(env);
288 int vl = vq * TARGET_SVE_VQ_BYTES;
289 int i, j;
290
291 memset(za, 0, sizeof(*za));
292 __put_user(TARGET_ZA_MAGIC, &za->head.magic);
293 __put_user(size, &za->head.size);
294 __put_user(vl, &za->vl);
295
296 if (size == TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
297 return;
298 }
299 assert(size == TARGET_ZA_SIG_CONTEXT_SIZE(vq));
300
301 /*
302 * Note that ZA vectors are stored as a byte stream,
303 * with each byte element at a subsequent address.
304 */
305 for (i = 0; i < vl; ++i) {
306 uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
307 for (j = 0; j < vq * 2; ++j) {
308 __put_user_e(env->za_state.za[i].d[j], z + j, le);
309 }
310 }
311 }
312
313 static void target_setup_tpidr2_record(struct target_tpidr2_context *tpidr2,
314 CPUARMState *env)
315 {
316 __put_user(TARGET_TPIDR2_MAGIC, &tpidr2->head.magic);
317 __put_user(sizeof(struct target_tpidr2_context), &tpidr2->head.size);
318 __put_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2);
319 }
320
321 static void target_setup_zt_record(struct target_zt_context *zt,
322 CPUARMState *env, int size)
323 {
324 uint64_t *z;
325
326 memset(zt, 0, sizeof(*zt));
327 __put_user(TARGET_ZT_MAGIC, &zt->head.magic);
328 __put_user(size, &zt->head.size);
329 /*
330 * The record format allows for multiple ZT regs, but
331 * currently there is only one, ZT0.
332 */
333 __put_user(1, &zt->nregs);
334 assert(size == TARGET_ZT_SIG_CONTEXT_SIZE(1));
335
336 /* ZT0 is the same byte-stream format as SVE regs and ZA */
337 z = (void *)zt + TARGET_ZT_SIG_REGS_OFFSET;
338 for (int i = 0; i < ARRAY_SIZE(env->za_state.zt0); i++) {
339 __put_user_e(env->za_state.zt0[i], z + i, le);
340 }
341 }
342
343 static bool target_setup_gcs_record(struct target_gcs_context *ctx,
344 CPUARMState *env, uint64_t return_addr)
345 {
346 uint64_t mode = gcs_get_el0_mode(env);
347 uint64_t gcspr = env->cp15.gcspr_el[0];
348
349 if (mode & PR_SHADOW_STACK_ENABLE) {
350 /* Push a cap for the signal frame. */
351 gcspr -= 8;
352 if (put_user_u64(GCS_SIGNAL_CAP(gcspr), gcspr)) {
353 return false;
354 }
355
356 /* Push a gcs entry for the trampoline. */
357 if (put_user_u64(return_addr, gcspr - 8)) {
358 return false;
359 }
360 env->cp15.gcspr_el[0] = gcspr - 8;
361 }
362
363 __put_user(TARGET_GCS_MAGIC, &ctx->head.magic);
364 __put_user(sizeof(*ctx), &ctx->head.size);
365 __put_user(gcspr, &ctx->gcspr);
366 __put_user(mode, &ctx->features_enabled);
367 __put_user(0, &ctx->reserved);
368
369 return true;
370 }
371
372 static void target_setup_fpmr_record(struct target_fpmr_context *ctx,
373 CPUARMState *env)
374 {
375 __put_user(TARGET_FPMR_MAGIC, &ctx->head.magic);
376 __put_user(sizeof(*ctx), &ctx->head.size);
377 __put_user(env->vfp.fpmr, &ctx->fpmr);
378 }
379
380 static void target_restore_general_frame(CPUARMState *env,
381 struct target_rt_sigframe *sf)
382 {
383 sigset_t set;
384 uint64_t pstate;
385 int i;
386
387 target_to_host_sigset(&set, &sf->uc.tuc_sigmask);
388 set_sigmask(&set);
389
390 for (i = 0; i < 31; i++) {
391 __get_user(env->xregs[i], &sf->uc.tuc_mcontext.regs[i]);
392 }
393
394 __get_user(env->xregs[31], &sf->uc.tuc_mcontext.sp);
395 __get_user(env->pc, &sf->uc.tuc_mcontext.pc);
396 __get_user(pstate, &sf->uc.tuc_mcontext.pstate);
397 pstate_write(env, pstate);
398 }
399
400 static void target_restore_fpsimd_record(CPUARMState *env,
401 struct target_fpsimd_context *fpsimd)
402 {
403 uint32_t fpsr, fpcr;
404 int i;
405
406 __get_user(fpsr, &fpsimd->fpsr);
407 vfp_set_fpsr(env, fpsr);
408 __get_user(fpcr, &fpsimd->fpcr);
409 vfp_set_fpcr(env, fpcr);
410
411 for (i = 0; i < 32; i++) {
412 uint64_t *q = aa64_vfp_qreg(env, i);
413 #if TARGET_BIG_ENDIAN
414 __get_user(q[0], &fpsimd->vregs[i * 2 + 1]);
415 __get_user(q[1], &fpsimd->vregs[i * 2]);
416 #else
417 __get_user(q[0], &fpsimd->vregs[i * 2]);
418 __get_user(q[1], &fpsimd->vregs[i * 2 + 1]);
419 #endif
420 }
421 }
422
423 static bool target_restore_sve_record(CPUARMState *env,
424 struct target_sve_context *sve,
425 int size, int *svcr)
426 {
427 int i, j, vl, vq, flags;
428 bool sm;
429
430 __get_user(vl, &sve->vl);
431 __get_user(flags, &sve->flags);
432
433 sm = flags & TARGET_SVE_SIG_FLAG_SM;
434
435 /* The cpu must support Streaming or Non-streaming SVE. */
436 if (sm
437 ? !cpu_isar_feature(aa64_sme, env_archcpu(env))
438 : !cpu_isar_feature(aa64_sve, env_archcpu(env))) {
439 return false;
440 }
441
442 /*
443 * Note that we cannot use sve_vq() because that depends on the
444 * current setting of PSTATE.SM, not the state to be restored.
445 */
446 vq = sve_vqm1_for_el_sm(env, 0, sm) + 1;
447
448 /* Reject mismatched VL. */
449 if (vl != vq * TARGET_SVE_VQ_BYTES) {
450 return false;
451 }
452
453 /* Accept empty record -- used to clear PSTATE.SM. */
454 if (size <= sizeof(*sve)) {
455 return true;
456 }
457
458 /* Reject non-empty but incomplete record. */
459 if (size < TARGET_SVE_SIG_CONTEXT_SIZE(vq)) {
460 return false;
461 }
462
463 *svcr = FIELD_DP64(*svcr, SVCR, SM, sm);
464
465 /*
466 * Note that SVE regs are stored as a byte stream, with each byte element
467 * at a subsequent address. This corresponds to a little-endian load
468 * of our 64-bit hunks.
469 */
470 for (i = 0; i < 32; ++i) {
471 uint64_t *z = (void *)sve + TARGET_SVE_SIG_ZREG_OFFSET(vq, i);
472 for (j = 0; j < vq * 2; ++j) {
473 __get_user_e(env->vfp.zregs[i].d[j], z + j, le);
474 }
475 }
476 for (i = 0; i <= 16; ++i) {
477 uint16_t *p = (void *)sve + TARGET_SVE_SIG_PREG_OFFSET(vq, i);
478 for (j = 0; j < vq; ++j) {
479 uint16_t r;
480 __get_user_e(r, p + j, le);
481 if (j & 3) {
482 env->vfp.pregs[i].p[j >> 2] |= (uint64_t)r << ((j & 3) * 16);
483 } else {
484 env->vfp.pregs[i].p[j >> 2] = r;
485 }
486 }
487 }
488 return true;
489 }
490
491 static bool target_restore_za_record(CPUARMState *env,
492 struct target_za_context *za,
493 int size, int *svcr)
494 {
495 int i, j, vl, vq;
496
497 if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) {
498 return false;
499 }
500
501 __get_user(vl, &za->vl);
502 vq = sme_vq(env);
503
504 /* Reject mismatched VL. */
505 if (vl != vq * TARGET_SVE_VQ_BYTES) {
506 return false;
507 }
508
509 /* Accept empty record -- used to clear PSTATE.ZA. */
510 if (size <= TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
511 return true;
512 }
513
514 /* Reject non-empty but incomplete record. */
515 if (size < TARGET_ZA_SIG_CONTEXT_SIZE(vq)) {
516 return false;
517 }
518
519 *svcr = FIELD_DP64(*svcr, SVCR, ZA, 1);
520
521 for (i = 0; i < vl; ++i) {
522 uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
523 for (j = 0; j < vq * 2; ++j) {
524 __get_user_e(env->za_state.za[i].d[j], z + j, le);
525 }
526 }
527 return true;
528 }
529
530 static void target_restore_tpidr2_record(CPUARMState *env,
531 struct target_tpidr2_context *tpidr2)
532 {
533 __get_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2);
534 }
535
536 static void target_restore_fpmr_record(CPUARMState *env,
537 struct target_fpmr_context *fpmr)
538 {
539 __get_user(env->vfp.fpmr, &fpmr->fpmr);
540 }
541
542 static bool target_restore_zt_record(CPUARMState *env,
543 struct target_zt_context *zt, int size,
544 int svcr)
545 {
546 uint16_t nregs;
547 uint64_t *z;
548
549 if (!(FIELD_EX64(svcr, SVCR, ZA))) {
550 return false;
551 }
552
553 __get_user(nregs, &zt->nregs);
554
555 if (nregs != 1) {
556 return false;
557 }
558
559 z = (void *)zt + TARGET_ZT_SIG_REGS_OFFSET;
560 for (int i = 0; i < ARRAY_SIZE(env->za_state.zt0); i++) {
561 __get_user_e(env->za_state.zt0[i], z + i, le);
562 }
563 return true;
564 }
565
566 static bool target_restore_gcs_record(CPUARMState *env,
567 struct target_gcs_context *ctx,
568 bool *rebuild_hflags)
569 {
570 TaskState *ts = get_task_state(env_cpu(env));
571 uint64_t cur_mode = gcs_get_el0_mode(env);
572 uint64_t new_mode, gcspr;
573
574 __get_user(new_mode, &ctx->features_enabled);
575 __get_user(gcspr, &ctx->gcspr);
576
577 /*
578 * The kernel pushes the value through the hw register:
579 * write_sysreg_s(gcspr, SYS_GCSPR_EL0) in restore_gcs_context,
580 * then read_sysreg_s(SYS_GCSPR_EL0) in gcs_restore_signal.
581 * Since the bottom 3 bits are RES0, this can (CONSTRAINED UNPREDICTABLE)
582 * force align the value. Mirror the choice from gcspr_write().
583 */
584 gcspr &= ~7;
585
586 if (new_mode & ~(PR_SHADOW_STACK_ENABLE |
587 PR_SHADOW_STACK_WRITE |
588 PR_SHADOW_STACK_PUSH)) {
589 return false;
590 }
591 if ((new_mode ^ cur_mode) & ts->gcs_el0_locked) {
592 return false;
593 }
594 if (new_mode & ~cur_mode & PR_SHADOW_STACK_ENABLE) {
595 return false;
596 }
597
598 if (new_mode & PR_SHADOW_STACK_ENABLE) {
599 uint64_t cap;
600
601 /* Pop and clear the signal cap. */
602 if (get_user_u64(cap, gcspr)) {
603 return false;
604 }
605 if (cap != GCS_SIGNAL_CAP(gcspr)) {
606 return false;
607 }
608 if (put_user_u64(0, gcspr)) {
609 return false;
610 }
611 gcspr += 8;
612 } else {
613 new_mode = 0;
614 }
615
616 env->cp15.gcspr_el[0] = gcspr;
617 if (new_mode != cur_mode) {
618 *rebuild_hflags = true;
619 gcs_set_el0_mode(env, new_mode);
620 }
621 return true;
622 }
623
624 static int target_restore_sigframe(CPUARMState *env,
625 struct target_rt_sigframe *sf)
626 {
627 struct target_aarch64_ctx *ctx, *extra = NULL;
628 struct target_fpsimd_context *fpsimd = NULL;
629 struct target_sve_context *sve = NULL;
630 struct target_za_context *za = NULL;
631 struct target_tpidr2_context *tpidr2 = NULL;
632 struct target_zt_context *zt = NULL;
633 struct target_gcs_context *gcs = NULL;
634 struct target_fpmr_context *fpmr = NULL;
635 uint64_t extra_datap = 0;
636 bool used_extra = false;
637 bool rebuild_hflags = false;
638 int sve_size = 0;
639 int za_size = 0;
640 int zt_size = 0;
641 int svcr = 0;
642
643 target_restore_general_frame(env, sf);
644
645 ctx = (struct target_aarch64_ctx *)sf->uc.tuc_mcontext.__reserved;
646 while (ctx) {
647 uint32_t magic, size, extra_size;
648
649 __get_user(magic, &ctx->magic);
650 __get_user(size, &ctx->size);
651 switch (magic) {
652 case 0:
653 if (size != 0) {
654 goto err;
655 }
656 if (used_extra) {
657 ctx = NULL;
658 } else {
659 ctx = extra;
660 used_extra = true;
661 }
662 continue;
663
664 case TARGET_FPSIMD_MAGIC:
665 if (fpsimd || size != sizeof(struct target_fpsimd_context)) {
666 goto err;
667 }
668 fpsimd = (struct target_fpsimd_context *)ctx;
669 break;
670
671 case TARGET_ESR_MAGIC:
672 break; /* ignore */
673
674 case TARGET_SVE_MAGIC:
675 if (sve || size < sizeof(struct target_sve_context)) {
676 goto err;
677 }
678 sve = (struct target_sve_context *)ctx;
679 sve_size = size;
680 break;
681
682 case TARGET_ZA_MAGIC:
683 if (za || size < sizeof(struct target_za_context)) {
684 goto err;
685 }
686 za = (struct target_za_context *)ctx;
687 za_size = size;
688 break;
689
690 case TARGET_TPIDR2_MAGIC:
691 if (tpidr2 || size != sizeof(struct target_tpidr2_context) ||
692 !cpu_isar_feature(aa64_sme, env_archcpu(env))) {
693 goto err;
694 }
695 tpidr2 = (struct target_tpidr2_context *)ctx;
696 break;
697
698 case TARGET_ZT_MAGIC:
699 if (zt || size != TARGET_ZT_SIG_CONTEXT_SIZE(1) ||
700 !cpu_isar_feature(aa64_sme2, env_archcpu(env))) {
701 goto err;
702 }
703 zt = (struct target_zt_context *)ctx;
704 zt_size = size;
705 break;
706
707 case TARGET_GCS_MAGIC:
708 if (gcs
709 || size != sizeof(struct target_gcs_context)
710 || !cpu_isar_feature(aa64_gcs, env_archcpu(env))) {
711 goto err;
712 }
713 gcs = (struct target_gcs_context *)ctx;
714 break;
715
716 case TARGET_FPMR_MAGIC:
717 if (fpmr
718 || size != sizeof(struct target_fpmr_context)
719 || !cpu_isar_feature(aa64_fpmr, env_archcpu(env))) {
720 goto err;
721 }
722 fpmr = (struct target_fpmr_context *)ctx;
723 break;
724
725 case TARGET_EXTRA_MAGIC:
726 if (extra || size != sizeof(struct target_extra_context)) {
727 goto err;
728 }
729 __get_user(extra_datap,
730 &((struct target_extra_context *)ctx)->datap);
731 __get_user(extra_size,
732 &((struct target_extra_context *)ctx)->size);
733 extra = lock_user(VERIFY_READ, extra_datap, extra_size, 0);
734 if (!extra) {
735 return 1;
736 }
737 break;
738
739 default:
740 /* Unknown record -- we certainly didn't generate it.
741 * Did we in fact get out of sync?
742 */
743 goto err;
744 }
745 ctx = (void *)ctx + size;
746 }
747
748 /* Require FPSIMD always. */
749 if (fpsimd) {
750 target_restore_fpsimd_record(env, fpsimd);
751 } else {
752 goto err;
753 }
754
755 if (gcs && !target_restore_gcs_record(env, gcs, &rebuild_hflags)) {
756 goto err;
757 }
758
759 /* SVE data, if present, overwrites FPSIMD data. */
760 if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) {
761 goto err;
762 }
763 if (za && !target_restore_za_record(env, za, za_size, &svcr)) {
764 goto err;
765 }
766 if (tpidr2) {
767 target_restore_tpidr2_record(env, tpidr2);
768 }
769 if (fpmr) {
770 target_restore_fpmr_record(env, fpmr);
771 }
772 /*
773 * NB that we must restore ZT after ZA so the check that there's
774 * no ZT record if SVCR.ZA is 0 gets the right value of SVCR.
775 */
776 if (zt && !target_restore_zt_record(env, zt, zt_size, svcr)) {
777 goto err;
778 }
779 if (env->svcr != svcr) {
780 env->svcr = svcr;
781 rebuild_hflags = true;
782 }
783 if (rebuild_hflags) {
784 arm_rebuild_hflags(env);
785 }
786 unlock_user(extra, extra_datap, 0);
787 return 0;
788
789 err:
790 unlock_user(extra, extra_datap, 0);
791 return 1;
792 }
793
794 static abi_ulong get_sigframe(struct target_sigaction *ka,
795 CPUARMState *env, int size)
796 {
797 abi_ulong sp;
798
799 sp = target_sigsp(get_sp_from_cpustate(env), ka);
800
801 sp = (sp - size) & ~15;
802
803 return sp;
804 }
805
806 typedef struct {
807 int total_size;
808 int extra_base;
809 int extra_size;
810 int std_end_ofs;
811 int extra_ofs;
812 int extra_end_ofs;
813 } target_sigframe_layout;
814
815 static int alloc_sigframe_space(int this_size, target_sigframe_layout *l)
816 {
817 /* Make sure there will always be space for the end marker. */
818 const int std_size = sizeof(struct target_rt_sigframe)
819 - sizeof(struct target_aarch64_ctx);
820 int this_loc = l->total_size;
821
822 if (l->extra_base) {
823 /* Once we have begun an extra space, all allocations go there. */
824 l->extra_size += this_size;
825 } else if (this_size + this_loc > std_size) {
826 /* This allocation does not fit in the standard space. */
827 /* Allocate the extra record. */
828 l->extra_ofs = this_loc;
829 l->total_size += sizeof(struct target_extra_context);
830
831 /* Allocate the standard end record. */
832 l->std_end_ofs = l->total_size;
833 l->total_size += sizeof(struct target_aarch64_ctx);
834
835 /* Allocate the requested record. */
836 l->extra_base = this_loc = l->total_size;
837 l->extra_size = this_size;
838 }
839 l->total_size += this_size;
840
841 return this_loc;
842 }
843
844 static void target_setup_frame(int usig, struct target_sigaction *ka,
845 target_siginfo_t *info, target_sigset_t *set,
846 CPUARMState *env)
847 {
848 target_sigframe_layout layout = {
849 /* Begin with the size pointing to the reserved space. */
850 .total_size = offsetof(struct target_rt_sigframe,
851 uc.tuc_mcontext.__reserved),
852 };
853 int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0, tpidr2_ofs = 0;
854 int zt_ofs = 0, esr_ofs = 0, gcs_ofs = 0, fpmr_ofs = 0;
855 int sve_size = 0, za_size = 0, tpidr2_size = 0, zt_size = 0;
856 struct target_rt_sigframe *frame;
857 struct target_rt_frame_record *fr;
858 abi_ulong frame_addr, return_addr;
859
860 /* FPSIMD record is always in the standard space. */
861 fpsimd_ofs = alloc_sigframe_space(sizeof(struct target_fpsimd_context),
862 &layout);
863
864 /*
865 * In user mode, ESR_EL1 is only set by cpu_loop while queueing the
866 * signal, and it's only valid for the one sync insn.
867 */
868 if (env->cp15.esr_el[1]) {
869 esr_ofs = alloc_sigframe_space(sizeof(struct target_esr_context),
870 &layout);
871 }
872
873 if (env->cp15.gcspr_el[0]) {
874 gcs_ofs = alloc_sigframe_space(sizeof(struct target_gcs_context),
875 &layout);
876 }
877
878 if (cpu_isar_feature(aa64_fpmr, env_archcpu(env))) {
879 fpmr_ofs = alloc_sigframe_space(sizeof(struct target_fpmr_context),
880 &layout);
881 }
882
883 /* SVE state needs saving only if it exists. */
884 if (cpu_isar_feature(aa64_sve, env_archcpu(env)) ||
885 cpu_isar_feature(aa64_sme, env_archcpu(env))) {
886 sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(sve_vq(env)), 16);
887 sve_ofs = alloc_sigframe_space(sve_size, &layout);
888 }
889 if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
890 tpidr2_size = sizeof(struct target_tpidr2_context);
891 tpidr2_ofs = alloc_sigframe_space(tpidr2_size, &layout);
892 /* ZA state needs saving only if it is enabled. */
893 if (FIELD_EX64(env->svcr, SVCR, ZA)) {
894 za_size = TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(env));
895 } else {
896 za_size = TARGET_ZA_SIG_CONTEXT_SIZE(0);
897 }
898 za_ofs = alloc_sigframe_space(za_size, &layout);
899 }
900 if (cpu_isar_feature(aa64_sme2, env_archcpu(env)) &&
901 FIELD_EX64(env->svcr, SVCR, ZA)) {
902 /* If SME ZA storage is enabled, we must also save SME2 ZT0 */
903 zt_size = TARGET_ZT_SIG_CONTEXT_SIZE(1);
904 zt_ofs = alloc_sigframe_space(zt_size, &layout);
905 }
906
907 if (layout.extra_ofs) {
908 /* Reserve space for the extra end marker. The standard end marker
909 * will have been allocated when we allocated the extra record.
910 */
911 layout.extra_end_ofs
912 = alloc_sigframe_space(sizeof(struct target_aarch64_ctx), &layout);
913 } else {
914 /* Reserve space for the standard end marker.
915 * Do not use alloc_sigframe_space because we cheat
916 * std_size therein to reserve space for this.
917 */
918 layout.std_end_ofs = layout.total_size;
919 layout.total_size += sizeof(struct target_aarch64_ctx);
920 }
921
922 /* We must always provide at least the standard 4K reserved space,
923 * even if we don't use all of it (this is part of the ABI)
924 */
925 layout.total_size = MAX(layout.total_size,
926 sizeof(struct target_rt_sigframe));
927
928 /*
929 * Reserve space for the standard frame unwind pair: fp, lr.
930 * Despite the name this is not a "real" record within the frame.
931 */
932 fr_ofs = layout.total_size;
933 layout.total_size += sizeof(struct target_rt_frame_record);
934
935 frame_addr = get_sigframe(ka, env, layout.total_size);
936 trace_user_setup_frame(env, frame_addr);
937 frame = lock_user(VERIFY_WRITE, frame_addr, layout.total_size, 0);
938 if (!frame) {
939 goto give_sigsegv;
940 }
941
942 if (ka->sa_flags & TARGET_SA_RESTORER) {
943 return_addr = ka->sa_restorer;
944 } else {
945 return_addr = default_rt_sigreturn;
946 }
947
948 target_setup_general_frame(frame, env, set);
949 target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env);
950 if (esr_ofs) {
951 target_setup_esr_record((void *)frame + esr_ofs, env);
952 /* Leave ESR_EL1 clear while it's not relevant. */
953 env->cp15.esr_el[1] = 0;
954 }
955 if (gcs_ofs &&
956 !target_setup_gcs_record((void *)frame + gcs_ofs, env, return_addr)) {
957 goto give_sigsegv;
958 }
959 if (fpmr_ofs) {
960 target_setup_fpmr_record((void *)frame + fpmr_ofs, env);
961 }
962 target_setup_end_record((void *)frame + layout.std_end_ofs);
963 if (layout.extra_ofs) {
964 target_setup_extra_record((void *)frame + layout.extra_ofs,
965 frame_addr + layout.extra_base,
966 layout.extra_size);
967 target_setup_end_record((void *)frame + layout.extra_end_ofs);
968 }
969 if (sve_ofs) {
970 target_setup_sve_record((void *)frame + sve_ofs, env, sve_size);
971 }
972 if (za_ofs) {
973 target_setup_za_record((void *)frame + za_ofs, env, za_size);
974 }
975 if (tpidr2_ofs) {
976 target_setup_tpidr2_record((void *)frame + tpidr2_ofs, env);
977 }
978 if (zt_ofs) {
979 target_setup_zt_record((void *)frame + zt_ofs, env, zt_size);
980 }
981
982 /* Set up the stack frame for unwinding. */
983 fr = (void *)frame + fr_ofs;
984 __put_user(env->xregs[29], &fr->fp);
985 __put_user(env->xregs[30], &fr->lr);
986
987 env->xregs[0] = usig;
988 env->xregs[29] = frame_addr + fr_ofs;
989 env->xregs[30] = return_addr;
990 env->xregs[31] = frame_addr;
991 env->pc = ka->_sa_handler;
992
993 /* Invoke the signal handler as if by indirect call. */
994 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
995 env->btype = 2;
996 }
997
998 /*
999 * Invoke the signal handler with a clean SME state: both SM and ZA
1000 * disabled and TPIDR2_EL0 cleared.
1001 */
1002 aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
1003 env->cp15.tpidr2_el0 = 0;
1004
1005 if (info) {
1006 frame->info = *info;
1007 env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info);
1008 env->xregs[2] = frame_addr + offsetof(struct target_rt_sigframe, uc);
1009 }
1010
1011 unlock_user(frame, frame_addr, layout.total_size);
1012 return;
1013
1014 give_sigsegv:
1015 unlock_user(frame, frame_addr, layout.total_size);
1016 force_sigsegv(usig);
1017 }
1018
1019 void setup_rt_frame(int sig, struct target_sigaction *ka,
1020 target_siginfo_t *info, target_sigset_t *set,
1021 CPUARMState *env)
1022 {
1023 target_setup_frame(sig, ka, info, set, env);
1024 }
1025
1026 void setup_frame(int sig, struct target_sigaction *ka,
1027 target_sigset_t *set, CPUARMState *env)
1028 {
1029 target_setup_frame(sig, ka, 0, set, env);
1030 }
1031
1032 long do_rt_sigreturn(CPUARMState *env)
1033 {
1034 struct target_rt_sigframe *frame = NULL;
1035 abi_ulong frame_addr = env->xregs[31];
1036
1037 trace_user_do_rt_sigreturn(env, frame_addr);
1038 if (frame_addr & 15) {
1039 goto badframe;
1040 }
1041
1042 if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) {
1043 goto badframe;
1044 }
1045
1046 if (target_restore_sigframe(env, frame)) {
1047 goto badframe;
1048 }
1049
1050 target_restore_altstack(&frame->uc.tuc_stack, env);
1051
1052 unlock_user_struct(frame, frame_addr, 0);
1053 return -QEMU_ESIGRETURN;
1054
1055 badframe:
1056 unlock_user_struct(frame, frame_addr, 0);
1057 force_sig(TARGET_SIGSEGV);
1058 return -QEMU_ESIGRETURN;
1059 }
1060
1061 long do_sigreturn(CPUARMState *env)
1062 {
1063 return do_rt_sigreturn(env);
1064 }
1065
1066 void setup_sigtramp(abi_ulong sigtramp_page)
1067 {
1068 uint32_t *tramp = lock_user(VERIFY_WRITE, sigtramp_page, 8, 0);
1069 assert(tramp != NULL);
1070
1071 /*
1072 * mov x8,#__NR_rt_sigreturn; svc #0
1073 * Since these are instructions they need to be put as little-endian
1074 * regardless of target default or current CPU endianness.
1075 */
1076 __put_user_e(0xd2801168, &tramp[0], le);
1077 __put_user_e(0xd4000001, &tramp[1], le);
1078
1079 default_rt_sigreturn = sigtramp_page;
1080 unlock_user(tramp, sigtramp_page, 8);
1081 }