| 1 | /* |
| 2 | * qemu user cpu loop |
| 3 | * |
| 4 | * Copyright (c) 2003-2008 Fabrice Bellard |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "qemu.h" |
| 22 | #include "user-internals.h" |
| 23 | #include "user/cpu_loop.h" |
| 24 | #include "signal-common.h" |
| 25 | #include "elf.h" |
| 26 | #include "internal.h" |
| 27 | #include "fpu_helper.h" |
| 28 | |
| 29 | # ifdef TARGET_ABI_MIPSO32 |
| 30 | # define MIPS_SYSCALL_NUMBER_UNUSED -1 |
| 31 | static const int8_t mips_syscall_args[] = { |
| 32 | #include "syscall-args-o32.c.inc" |
| 33 | }; |
| 34 | # endif /* O32 */ |
| 35 | |
| 36 | /* Break codes */ |
| 37 | enum { |
| 38 | BRK_OVERFLOW = 6, |
| 39 | BRK_DIVZERO = 7 |
| 40 | }; |
| 41 | |
| 42 | static void do_tr_or_bp(CPUMIPSState *env, unsigned int code, bool trap) |
| 43 | { |
| 44 | target_ulong pc = env->active_tc.PC; |
| 45 | |
| 46 | switch (code) { |
| 47 | case BRK_OVERFLOW: |
| 48 | force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, pc); |
| 49 | break; |
| 50 | case BRK_DIVZERO: |
| 51 | force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, pc); |
| 52 | break; |
| 53 | default: |
| 54 | if (trap) { |
| 55 | force_sig(TARGET_SIGTRAP); |
| 56 | } else { |
| 57 | force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, pc); |
| 58 | } |
| 59 | break; |
| 60 | } |
| 61 | } |
| 62 | |
| 63 | void cpu_loop(CPUMIPSState *env) |
| 64 | { |
| 65 | CPUState *cs = env_cpu(env); |
| 66 | int trapnr, si_code; |
| 67 | unsigned int code; |
| 68 | abi_long ret; |
| 69 | # ifdef TARGET_ABI_MIPSO32 |
| 70 | unsigned int syscall_num; |
| 71 | # endif |
| 72 | |
| 73 | for(;;) { |
| 74 | cpu_exec_start(cs); |
| 75 | trapnr = cpu_exec(cs); |
| 76 | cpu_exec_end(cs); |
| 77 | qemu_process_cpu_events(cs); |
| 78 | |
| 79 | switch(trapnr) { |
| 80 | case EXCP_SYSCALL: |
| 81 | env->active_tc.PC += 4; |
| 82 | # ifdef TARGET_ABI_MIPSO32 |
| 83 | syscall_num = env->active_tc.gpr[2] - 4000; |
| 84 | if (syscall_num >= sizeof(mips_syscall_args)) { |
| 85 | /* syscall_num is larger that any defined for MIPS O32 */ |
| 86 | ret = -TARGET_ENOSYS; |
| 87 | } else if (mips_syscall_args[syscall_num] == |
| 88 | MIPS_SYSCALL_NUMBER_UNUSED) { |
| 89 | /* syscall_num belongs to the range not defined for MIPS O32 */ |
| 90 | ret = -TARGET_ENOSYS; |
| 91 | } else { |
| 92 | /* syscall_num is valid */ |
| 93 | int nb_args; |
| 94 | abi_ulong sp_reg; |
| 95 | abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; |
| 96 | |
| 97 | nb_args = mips_syscall_args[syscall_num]; |
| 98 | sp_reg = env->active_tc.gpr[29]; |
| 99 | switch (nb_args) { |
| 100 | /* these arguments are taken from the stack */ |
| 101 | case 8: |
| 102 | if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { |
| 103 | goto done_syscall; |
| 104 | } |
| 105 | /* fall through */ |
| 106 | case 7: |
| 107 | if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { |
| 108 | goto done_syscall; |
| 109 | } |
| 110 | /* fall through */ |
| 111 | case 6: |
| 112 | if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { |
| 113 | goto done_syscall; |
| 114 | } |
| 115 | /* fall through */ |
| 116 | case 5: |
| 117 | if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { |
| 118 | goto done_syscall; |
| 119 | } |
| 120 | /* fall through */ |
| 121 | default: |
| 122 | break; |
| 123 | } |
| 124 | ret = do_syscall(env, env->active_tc.gpr[2], |
| 125 | env->active_tc.gpr[4], |
| 126 | env->active_tc.gpr[5], |
| 127 | env->active_tc.gpr[6], |
| 128 | env->active_tc.gpr[7], |
| 129 | arg5, arg6, arg7, arg8); |
| 130 | } |
| 131 | done_syscall: |
| 132 | # else |
| 133 | ret = do_syscall(env, env->active_tc.gpr[2], |
| 134 | env->active_tc.gpr[4], env->active_tc.gpr[5], |
| 135 | env->active_tc.gpr[6], env->active_tc.gpr[7], |
| 136 | env->active_tc.gpr[8], env->active_tc.gpr[9], |
| 137 | env->active_tc.gpr[10], env->active_tc.gpr[11]); |
| 138 | # endif /* O32 */ |
| 139 | if (ret == -QEMU_ERESTARTSYS) { |
| 140 | env->active_tc.PC -= 4; |
| 141 | break; |
| 142 | } |
| 143 | if (ret == -QEMU_ESIGRETURN || ret == -QEMU_ESETPC) { |
| 144 | /* |
| 145 | * Returning from a successful sigreturn syscall or from |
| 146 | * control flow diversion in a plugin callback. |
| 147 | * Avoid clobbering register state. |
| 148 | */ |
| 149 | break; |
| 150 | } |
| 151 | if ((abi_ulong)ret >= (abi_ulong)-1133) { |
| 152 | env->active_tc.gpr[7] = 1; /* error flag */ |
| 153 | ret = -ret; |
| 154 | } else { |
| 155 | env->active_tc.gpr[7] = 0; /* error flag */ |
| 156 | } |
| 157 | env->active_tc.gpr[2] = ret; |
| 158 | break; |
| 159 | case EXCP_CpU: |
| 160 | case EXCP_RI: |
| 161 | case EXCP_DSPDIS: |
| 162 | force_sig(TARGET_SIGILL); |
| 163 | break; |
| 164 | case EXCP_AdEL: |
| 165 | case EXCP_AdES: |
| 166 | force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, |
| 167 | env->CP0_BadVAddr); |
| 168 | break; |
| 169 | case EXCP_INTERRUPT: |
| 170 | /* just indicate that signals should be handled asap */ |
| 171 | break; |
| 172 | case EXCP_DEBUG: |
| 173 | force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, |
| 174 | env->active_tc.PC); |
| 175 | break; |
| 176 | case EXCP_FPE: |
| 177 | si_code = TARGET_FPE_FLTUNK; |
| 178 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { |
| 179 | si_code = TARGET_FPE_FLTINV; |
| 180 | } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_DIV0) { |
| 181 | si_code = TARGET_FPE_FLTDIV; |
| 182 | } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_OVERFLOW) { |
| 183 | si_code = TARGET_FPE_FLTOVF; |
| 184 | } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_UNDERFLOW) { |
| 185 | si_code = TARGET_FPE_FLTUND; |
| 186 | } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INEXACT) { |
| 187 | si_code = TARGET_FPE_FLTRES; |
| 188 | } |
| 189 | force_sig_fault(TARGET_SIGFPE, si_code, env->active_tc.PC); |
| 190 | break; |
| 191 | case EXCP_OVERFLOW: |
| 192 | force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->active_tc.PC); |
| 193 | break; |
| 194 | /* The code below was inspired by the MIPS Linux kernel trap |
| 195 | * handling code in arch/mips/kernel/traps.c. |
| 196 | */ |
| 197 | case EXCP_BREAK: |
| 198 | /* |
| 199 | * As described in the original Linux kernel code, the below |
| 200 | * checks on 'code' are to work around an old assembly bug. |
| 201 | */ |
| 202 | code = env->error_code; |
| 203 | if (code >= (1 << 10)) { |
| 204 | code >>= 10; |
| 205 | } |
| 206 | do_tr_or_bp(env, code, false); |
| 207 | break; |
| 208 | case EXCP_TRAP: |
| 209 | do_tr_or_bp(env, env->error_code, true); |
| 210 | break; |
| 211 | case EXCP_ATOMIC: |
| 212 | cpu_exec_step_atomic(cs); |
| 213 | break; |
| 214 | default: |
| 215 | EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); |
| 216 | abort(); |
| 217 | } |
| 218 | process_pending_signals(env); |
| 219 | } |
| 220 | } |
| 221 | |
| 222 | void init_main_thread(CPUState *cs, struct image_info *info) |
| 223 | { |
| 224 | CPUArchState *env = cpu_env(cs); |
| 225 | |
| 226 | struct mode_req { |
| 227 | bool single; |
| 228 | bool soft; |
| 229 | bool fr1; |
| 230 | bool frdefault; |
| 231 | bool fre; |
| 232 | }; |
| 233 | |
| 234 | static const struct mode_req fpu_reqs[] = { |
| 235 | [MIPS_ABI_FP_ANY] = { true, true, true, true, true }, |
| 236 | [MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true }, |
| 237 | [MIPS_ABI_FP_SINGLE] = { true, false, false, false, false }, |
| 238 | [MIPS_ABI_FP_SOFT] = { false, true, false, false, false }, |
| 239 | [MIPS_ABI_FP_OLD_64] = { false, false, false, false, false }, |
| 240 | [MIPS_ABI_FP_XX] = { false, false, true, true, true }, |
| 241 | [MIPS_ABI_FP_64] = { false, false, true, false, false }, |
| 242 | [MIPS_ABI_FP_64A] = { false, false, true, false, true } |
| 243 | }; |
| 244 | |
| 245 | /* |
| 246 | * Mode requirements when .MIPS.abiflags is not present in the ELF. |
| 247 | * Not present means that everything is acceptable except FR1. |
| 248 | */ |
| 249 | static struct mode_req none_req = { true, true, false, true, true }; |
| 250 | |
| 251 | struct mode_req prog_req; |
| 252 | struct mode_req interp_req; |
| 253 | target_ulong entry = info->entry; |
| 254 | |
| 255 | env->active_tc.gpr[29] = info->start_stack; |
| 256 | env->active_tc.PC = entry & ~(target_ulong)1; |
| 257 | if (entry & 1) { |
| 258 | env->hflags |= MIPS_HFLAG_M16; |
| 259 | } |
| 260 | |
| 261 | #ifdef TARGET_ABI_MIPSO32 |
| 262 | # define MAX_FP_ABI MIPS_ABI_FP_64A |
| 263 | #else |
| 264 | # define MAX_FP_ABI MIPS_ABI_FP_SOFT |
| 265 | #endif |
| 266 | if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN) |
| 267 | || (info->interp_fp_abi > MAX_FP_ABI && |
| 268 | info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) { |
| 269 | fprintf(stderr, "qemu: Unexpected FPU mode\n"); |
| 270 | exit(1); |
| 271 | } |
| 272 | |
| 273 | prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req |
| 274 | : fpu_reqs[info->fp_abi]; |
| 275 | interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req |
| 276 | : fpu_reqs[info->interp_fp_abi]; |
| 277 | |
| 278 | prog_req.single &= interp_req.single; |
| 279 | prog_req.soft &= interp_req.soft; |
| 280 | prog_req.fr1 &= interp_req.fr1; |
| 281 | prog_req.frdefault &= interp_req.frdefault; |
| 282 | prog_req.fre &= interp_req.fre; |
| 283 | |
| 284 | bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 || |
| 285 | env->insn_flags & ISA_MIPS_R6; |
| 286 | |
| 287 | if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { |
| 288 | env->CP0_Config5 |= (1 << CP0C5_FRE); |
| 289 | if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { |
| 290 | env->hflags |= MIPS_HFLAG_FRE; |
| 291 | } |
| 292 | } else if ((prog_req.fr1 && prog_req.frdefault) || |
| 293 | (prog_req.single && !prog_req.frdefault)) { |
| 294 | if ((env->active_fpu.fcr0 & (1 << FCR0_F64) |
| 295 | && cpu_has_mips_r2_r6) || prog_req.fr1) { |
| 296 | env->CP0_Status |= (1 << CP0St_FR); |
| 297 | env->hflags |= MIPS_HFLAG_F64; |
| 298 | } |
| 299 | } else if (prog_req.fr1) { |
| 300 | env->CP0_Status |= (1 << CP0St_FR); |
| 301 | env->hflags |= MIPS_HFLAG_F64; |
| 302 | } else if (!prog_req.fre && !prog_req.frdefault && |
| 303 | !prog_req.fr1 && !prog_req.single && !prog_req.soft) { |
| 304 | fprintf(stderr, "qemu: Can't find a matching FPU mode\n"); |
| 305 | exit(1); |
| 306 | } |
| 307 | |
| 308 | if (env->insn_flags & ISA_NANOMIPS32) { |
| 309 | return; |
| 310 | } |
| 311 | if (((info->elf_flags & EF_MIPS_NAN2008) != 0) != |
| 312 | ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) { |
| 313 | if ((env->active_fpu.fcr31_rw_bitmask & |
| 314 | (1 << FCR31_NAN2008)) == 0) { |
| 315 | fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n"); |
| 316 | exit(1); |
| 317 | } |
| 318 | if ((info->elf_flags & EF_MIPS_NAN2008) != 0) { |
| 319 | env->active_fpu.fcr31 |= (1 << FCR31_NAN2008); |
| 320 | } else { |
| 321 | env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008); |
| 322 | } |
| 323 | restore_snan_bit_mode(env); |
| 324 | } |
| 325 | } |