| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include "qemu/osdep.h" |
| 4 | #include "qemu.h" |
| 5 | #include "loader.h" |
| 6 | #include "target_elf.h" |
| 7 | |
| 8 | |
| 9 | const char *get_elf_cpu_model(uint32_t eflags) |
| 10 | { |
| 11 | #ifdef TARGET_PPC64 |
| 12 | return "POWER9"; |
| 13 | #else |
| 14 | return "750"; |
| 15 | #endif |
| 16 | } |
| 17 | |
| 18 | /* |
| 19 | * Feature masks for the Aux Vector Hardware Capabilities (AT_HWCAP). |
| 20 | * See arch/powerpc/include/asm/cputable.h. |
| 21 | */ |
| 22 | enum { |
| 23 | QEMU_PPC_FEATURE_32 = 0x80000000, |
| 24 | QEMU_PPC_FEATURE_64 = 0x40000000, |
| 25 | QEMU_PPC_FEATURE_601_INSTR = 0x20000000, |
| 26 | QEMU_PPC_FEATURE_HAS_ALTIVEC = 0x10000000, |
| 27 | QEMU_PPC_FEATURE_HAS_FPU = 0x08000000, |
| 28 | QEMU_PPC_FEATURE_HAS_MMU = 0x04000000, |
| 29 | QEMU_PPC_FEATURE_HAS_4xxMAC = 0x02000000, |
| 30 | QEMU_PPC_FEATURE_UNIFIED_CACHE = 0x01000000, |
| 31 | QEMU_PPC_FEATURE_HAS_SPE = 0x00800000, |
| 32 | QEMU_PPC_FEATURE_HAS_EFP_SINGLE = 0x00400000, |
| 33 | QEMU_PPC_FEATURE_HAS_EFP_DOUBLE = 0x00200000, |
| 34 | QEMU_PPC_FEATURE_NO_TB = 0x00100000, |
| 35 | QEMU_PPC_FEATURE_POWER4 = 0x00080000, |
| 36 | QEMU_PPC_FEATURE_POWER5 = 0x00040000, |
| 37 | QEMU_PPC_FEATURE_POWER5_PLUS = 0x00020000, |
| 38 | QEMU_PPC_FEATURE_CELL = 0x00010000, |
| 39 | QEMU_PPC_FEATURE_BOOKE = 0x00008000, |
| 40 | QEMU_PPC_FEATURE_SMT = 0x00004000, |
| 41 | QEMU_PPC_FEATURE_ICACHE_SNOOP = 0x00002000, |
| 42 | QEMU_PPC_FEATURE_ARCH_2_05 = 0x00001000, |
| 43 | QEMU_PPC_FEATURE_PA6T = 0x00000800, |
| 44 | QEMU_PPC_FEATURE_HAS_DFP = 0x00000400, |
| 45 | QEMU_PPC_FEATURE_POWER6_EXT = 0x00000200, |
| 46 | QEMU_PPC_FEATURE_ARCH_2_06 = 0x00000100, |
| 47 | QEMU_PPC_FEATURE_HAS_VSX = 0x00000080, |
| 48 | QEMU_PPC_FEATURE_PSERIES_PERFMON_COMPAT = 0x00000040, |
| 49 | |
| 50 | QEMU_PPC_FEATURE_TRUE_LE = 0x00000002, |
| 51 | QEMU_PPC_FEATURE_PPC_LE = 0x00000001, |
| 52 | |
| 53 | /* Feature definitions in AT_HWCAP2. */ |
| 54 | QEMU_PPC_FEATURE2_ARCH_2_07 = 0x80000000, /* ISA 2.07 */ |
| 55 | QEMU_PPC_FEATURE2_HAS_HTM = 0x40000000, /* Hardware Transactional Memory */ |
| 56 | QEMU_PPC_FEATURE2_HAS_DSCR = 0x20000000, /* Data Stream Control Register */ |
| 57 | QEMU_PPC_FEATURE2_HAS_EBB = 0x10000000, /* Event Base Branching */ |
| 58 | QEMU_PPC_FEATURE2_HAS_ISEL = 0x08000000, /* Integer Select */ |
| 59 | QEMU_PPC_FEATURE2_HAS_TAR = 0x04000000, /* Target Address Register */ |
| 60 | QEMU_PPC_FEATURE2_VEC_CRYPTO = 0x02000000, |
| 61 | QEMU_PPC_FEATURE2_HTM_NOSC = 0x01000000, |
| 62 | QEMU_PPC_FEATURE2_ARCH_3_00 = 0x00800000, /* ISA 3.00 */ |
| 63 | QEMU_PPC_FEATURE2_HAS_IEEE128 = 0x00400000, /* VSX IEEE Bin Float 128-bit */ |
| 64 | QEMU_PPC_FEATURE2_DARN = 0x00200000, /* darn random number insn */ |
| 65 | QEMU_PPC_FEATURE2_SCV = 0x00100000, /* scv syscall */ |
| 66 | QEMU_PPC_FEATURE2_HTM_NO_SUSPEND = 0x00080000, /* TM w/o suspended state */ |
| 67 | QEMU_PPC_FEATURE2_ARCH_3_1 = 0x00040000, /* ISA 3.1 */ |
| 68 | QEMU_PPC_FEATURE2_MMA = 0x00020000, /* Matrix-Multiply Assist */ |
| 69 | }; |
| 70 | |
| 71 | abi_ulong get_elf_hwcap(CPUState *cs) |
| 72 | { |
| 73 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 74 | uint32_t features = 0; |
| 75 | |
| 76 | /* |
| 77 | * We don't have to be terribly complete here; the high points are |
| 78 | * Altivec/FP/SPE support. Anything else is just a bonus. |
| 79 | */ |
| 80 | #define GET_FEATURE(flag, feature) \ |
| 81 | do { if (cpu->env.insns_flags & flag) { features |= feature; } } while (0) |
| 82 | #define GET_FEATURE2(flags, feature) \ |
| 83 | do { \ |
| 84 | if ((cpu->env.insns_flags2 & flags) == flags) { \ |
| 85 | features |= feature; \ |
| 86 | } \ |
| 87 | } while (0) |
| 88 | GET_FEATURE(PPC_64B, QEMU_PPC_FEATURE_64); |
| 89 | GET_FEATURE(PPC_FLOAT, QEMU_PPC_FEATURE_HAS_FPU); |
| 90 | GET_FEATURE(PPC_ALTIVEC, QEMU_PPC_FEATURE_HAS_ALTIVEC); |
| 91 | GET_FEATURE(PPC_SPE, QEMU_PPC_FEATURE_HAS_SPE); |
| 92 | GET_FEATURE(PPC_SPE_SINGLE, QEMU_PPC_FEATURE_HAS_EFP_SINGLE); |
| 93 | GET_FEATURE(PPC_SPE_DOUBLE, QEMU_PPC_FEATURE_HAS_EFP_DOUBLE); |
| 94 | GET_FEATURE(PPC_BOOKE, QEMU_PPC_FEATURE_BOOKE); |
| 95 | GET_FEATURE(PPC_405_MAC, QEMU_PPC_FEATURE_HAS_4xxMAC); |
| 96 | GET_FEATURE2(PPC2_DFP, QEMU_PPC_FEATURE_HAS_DFP); |
| 97 | GET_FEATURE2(PPC2_VSX, QEMU_PPC_FEATURE_HAS_VSX); |
| 98 | GET_FEATURE2((PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | |
| 99 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206), |
| 100 | QEMU_PPC_FEATURE_ARCH_2_06); |
| 101 | |
| 102 | #undef GET_FEATURE |
| 103 | #undef GET_FEATURE2 |
| 104 | |
| 105 | return features; |
| 106 | } |
| 107 | |
| 108 | abi_ulong get_elf_hwcap2(CPUState *cs) |
| 109 | { |
| 110 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 111 | uint32_t features = 0; |
| 112 | |
| 113 | #define GET_FEATURE(flag, feature) \ |
| 114 | do { if (cpu->env.insns_flags & flag) { features |= feature; } } while (0) |
| 115 | #define GET_FEATURE2(flag, feature) \ |
| 116 | do { if (cpu->env.insns_flags2 & flag) { features |= feature; } } while (0) |
| 117 | |
| 118 | GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL); |
| 119 | GET_FEATURE2(PPC2_ISA207, (QEMU_PPC_FEATURE2_ARCH_2_07 | |
| 120 | QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR)); |
| 121 | GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 | |
| 122 | QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128); |
| 123 | GET_FEATURE2(PPC2_ISA310, QEMU_PPC_FEATURE2_ARCH_3_1 | |
| 124 | QEMU_PPC_FEATURE2_MMA); |
| 125 | |
| 126 | #undef GET_FEATURE |
| 127 | #undef GET_FEATURE2 |
| 128 | |
| 129 | return features; |
| 130 | } |
| 131 | |
| 132 | void elf_core_copy_regs(target_elf_gregset_t *r, const CPUPPCState *env) |
| 133 | { |
| 134 | for (int i = 0; i < ARRAY_SIZE(env->gpr); i++) { |
| 135 | r->pt.gpr[i] = tswapal(env->gpr[i]); |
| 136 | } |
| 137 | |
| 138 | r->pt.nip = tswapal(env->nip); |
| 139 | r->pt.msr = tswapal(env->msr); |
| 140 | r->pt.ctr = tswapal(env->ctr); |
| 141 | r->pt.link = tswapal(env->lr); |
| 142 | r->pt.xer = tswapal(cpu_read_xer(env)); |
| 143 | r->pt.ccr = tswapal(ppc_get_cr(env)); |
| 144 | } |