| 1 | /* |
| 2 | * Emulation of Linux signals |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | #include "qemu/osdep.h" |
| 20 | #include "qemu.h" |
| 21 | #include "user-internals.h" |
| 22 | #include "signal-common.h" |
| 23 | #include "linux-user/trace.h" |
| 24 | #include "user/tswap-target.h" |
| 25 | #include "vdso-asmoffset.h" |
| 26 | |
| 27 | /* See arch/powerpc/include/asm/ucontext.h. Only used for 32-bit PPC; |
| 28 | on 64-bit PPC, sigcontext and mcontext are one and the same. */ |
| 29 | struct target_mcontext { |
| 30 | target_ulong mc_gregs[48]; |
| 31 | /* Includes fpscr. */ |
| 32 | uint64_t mc_fregs[33]; |
| 33 | |
| 34 | #if defined(TARGET_PPC64) |
| 35 | /* Pointer to the vector regs */ |
| 36 | target_ulong v_regs; |
| 37 | /* |
| 38 | * On ppc64, this mcontext structure is naturally *unaligned*, |
| 39 | * or rather it is aligned on a 8 bytes boundary but not on |
| 40 | * a 16 byte boundary. This pad fixes it up. This is why we |
| 41 | * cannot use ppc_avr_t, which would force alignment. This is |
| 42 | * also why the vector regs are referenced in the ABI by the |
| 43 | * v_regs pointer above so any amount of padding can be added here. |
| 44 | */ |
| 45 | target_ulong pad; |
| 46 | /* VSCR and VRSAVE are saved separately. Also reserve space for VSX. */ |
| 47 | struct { |
| 48 | uint64_t altivec[34 + 16][2]; |
| 49 | } mc_vregs; |
| 50 | #else |
| 51 | target_ulong mc_pad[2]; |
| 52 | |
| 53 | /* We need to handle Altivec and SPE at the same time, which no |
| 54 | kernel needs to do. Fortunately, the kernel defines this bit to |
| 55 | be Altivec-register-large all the time, rather than trying to |
| 56 | twiddle it based on the specific platform. */ |
| 57 | union { |
| 58 | /* SPE vector registers. One extra for SPEFSCR. */ |
| 59 | uint32_t spe[33]; |
| 60 | /* |
| 61 | * Altivec vector registers. One extra for VRSAVE. |
| 62 | * On ppc32, we are already aligned to 16 bytes. We could |
| 63 | * use ppc_avr_t, but choose to share the same type as ppc64. |
| 64 | */ |
| 65 | uint64_t altivec[33][2]; |
| 66 | } mc_vregs; |
| 67 | #endif |
| 68 | }; |
| 69 | |
| 70 | QEMU_BUILD_BUG_ON(offsetof(struct target_mcontext, mc_fregs) |
| 71 | != offsetof_mcontext_fregs); |
| 72 | #if defined(TARGET_PPC64) |
| 73 | QEMU_BUILD_BUG_ON(offsetof(struct target_mcontext, v_regs) |
| 74 | != offsetof_mcontext_vregs_ptr); |
| 75 | #else |
| 76 | QEMU_BUILD_BUG_ON(offsetof(struct target_mcontext, mc_vregs) |
| 77 | != offsetof_mcontext_vregs); |
| 78 | #endif |
| 79 | |
| 80 | /* See arch/powerpc/include/asm/sigcontext.h. */ |
| 81 | struct target_sigcontext { |
| 82 | target_ulong _unused[4]; |
| 83 | int32_t signal; |
| 84 | #if defined(TARGET_PPC64) |
| 85 | int32_t pad0; |
| 86 | #endif |
| 87 | target_ulong handler; |
| 88 | target_ulong oldmask; |
| 89 | target_ulong regs; /* struct pt_regs __user * */ |
| 90 | #if defined(TARGET_PPC64) |
| 91 | struct target_mcontext mcontext; |
| 92 | #endif |
| 93 | }; |
| 94 | |
| 95 | /* Indices for target_mcontext.mc_gregs, below. |
| 96 | See arch/powerpc/include/asm/ptrace.h for details. */ |
| 97 | enum { |
| 98 | TARGET_PT_R0 = 0, |
| 99 | TARGET_PT_R1 = 1, |
| 100 | TARGET_PT_R2 = 2, |
| 101 | TARGET_PT_R3 = 3, |
| 102 | TARGET_PT_R4 = 4, |
| 103 | TARGET_PT_R5 = 5, |
| 104 | TARGET_PT_R6 = 6, |
| 105 | TARGET_PT_R7 = 7, |
| 106 | TARGET_PT_R8 = 8, |
| 107 | TARGET_PT_R9 = 9, |
| 108 | TARGET_PT_R10 = 10, |
| 109 | TARGET_PT_R11 = 11, |
| 110 | TARGET_PT_R12 = 12, |
| 111 | TARGET_PT_R13 = 13, |
| 112 | TARGET_PT_R14 = 14, |
| 113 | TARGET_PT_R15 = 15, |
| 114 | TARGET_PT_R16 = 16, |
| 115 | TARGET_PT_R17 = 17, |
| 116 | TARGET_PT_R18 = 18, |
| 117 | TARGET_PT_R19 = 19, |
| 118 | TARGET_PT_R20 = 20, |
| 119 | TARGET_PT_R21 = 21, |
| 120 | TARGET_PT_R22 = 22, |
| 121 | TARGET_PT_R23 = 23, |
| 122 | TARGET_PT_R24 = 24, |
| 123 | TARGET_PT_R25 = 25, |
| 124 | TARGET_PT_R26 = 26, |
| 125 | TARGET_PT_R27 = 27, |
| 126 | TARGET_PT_R28 = 28, |
| 127 | TARGET_PT_R29 = 29, |
| 128 | TARGET_PT_R30 = 30, |
| 129 | TARGET_PT_R31 = 31, |
| 130 | TARGET_PT_NIP = 32, |
| 131 | TARGET_PT_MSR = 33, |
| 132 | TARGET_PT_ORIG_R3 = 34, |
| 133 | TARGET_PT_CTR = 35, |
| 134 | TARGET_PT_LNK = 36, |
| 135 | TARGET_PT_XER = 37, |
| 136 | TARGET_PT_CCR = 38, |
| 137 | /* Yes, there are two registers with #39. One is 64-bit only. */ |
| 138 | TARGET_PT_MQ = 39, |
| 139 | TARGET_PT_SOFTE = 39, |
| 140 | TARGET_PT_TRAP = 40, |
| 141 | TARGET_PT_DAR = 41, |
| 142 | TARGET_PT_DSISR = 42, |
| 143 | TARGET_PT_RESULT = 43, |
| 144 | TARGET_PT_REGS_COUNT = 44 |
| 145 | }; |
| 146 | |
| 147 | |
| 148 | struct target_ucontext { |
| 149 | target_ulong tuc_flags; |
| 150 | target_ulong tuc_link; /* ucontext_t __user * */ |
| 151 | struct target_sigaltstack tuc_stack; |
| 152 | #if !defined(TARGET_PPC64) |
| 153 | int32_t tuc_pad[7]; |
| 154 | target_ulong tuc_regs; /* struct mcontext __user * |
| 155 | points to uc_mcontext field */ |
| 156 | #endif |
| 157 | target_sigset_t tuc_sigmask; |
| 158 | #if defined(TARGET_PPC64) |
| 159 | target_sigset_t unused[15]; /* Allow for uc_sigmask growth */ |
| 160 | struct target_sigcontext tuc_sigcontext; |
| 161 | #else |
| 162 | int32_t tuc_maskext[30]; |
| 163 | int32_t tuc_pad2[3]; |
| 164 | struct target_mcontext tuc_mcontext; |
| 165 | #endif |
| 166 | }; |
| 167 | |
| 168 | #if !defined(TARGET_PPC64) |
| 169 | /* See arch/powerpc/kernel/signal_32.c. */ |
| 170 | struct target_sigframe { |
| 171 | struct target_sigcontext sctx; |
| 172 | struct target_mcontext mctx; |
| 173 | int32_t abigap[56]; |
| 174 | }; |
| 175 | |
| 176 | QEMU_BUILD_BUG_ON(offsetof(struct target_sigframe, mctx) |
| 177 | != offsetof_sigframe_mcontext); |
| 178 | #endif |
| 179 | |
| 180 | #if defined(TARGET_PPC64) |
| 181 | |
| 182 | #define TARGET_TRAMP_SIZE 6 |
| 183 | |
| 184 | struct target_rt_sigframe { |
| 185 | /* sys_rt_sigreturn requires the ucontext be the first field */ |
| 186 | struct target_ucontext uc; |
| 187 | target_ulong _unused[2]; |
| 188 | uint32_t trampoline[TARGET_TRAMP_SIZE]; |
| 189 | target_ulong pinfo; /* struct siginfo __user * */ |
| 190 | target_ulong puc; /* void __user * */ |
| 191 | struct target_siginfo info; |
| 192 | /* 64 bit ABI allows for 288 bytes below sp before decrementing it. */ |
| 193 | char abigap[288]; |
| 194 | } __attribute__((aligned(16))); |
| 195 | |
| 196 | QEMU_BUILD_BUG_ON(offsetof(struct target_rt_sigframe, |
| 197 | uc.tuc_sigcontext.mcontext) |
| 198 | != offsetof_rt_sigframe_mcontext); |
| 199 | |
| 200 | #else |
| 201 | |
| 202 | struct target_rt_sigframe { |
| 203 | struct target_siginfo info; |
| 204 | struct target_ucontext uc; |
| 205 | int32_t abigap[56]; |
| 206 | }; |
| 207 | |
| 208 | QEMU_BUILD_BUG_ON(offsetof(struct target_rt_sigframe, uc.tuc_mcontext) |
| 209 | != offsetof_rt_sigframe_mcontext); |
| 210 | |
| 211 | #endif |
| 212 | |
| 213 | #ifdef TARGET_PPC64 |
| 214 | #define RT_SIGFRAME_ADJUST 0 |
| 215 | #else |
| 216 | /* |
| 217 | * For 32-bit rt sigframes we have an extra 16 bytes of gap |
| 218 | * on top of __SIGNAL_FRAMESIZE; this is to get the siginfo |
| 219 | * and ucontext in the same positions as in older kernels. |
| 220 | * See Linux's arch/powerpc/kernel/signal_32.c. |
| 221 | */ |
| 222 | #define RT_SIGFRAME_ADJUST 16 |
| 223 | #endif |
| 224 | |
| 225 | #if defined(TARGET_PPC64) |
| 226 | |
| 227 | struct target_func_ptr { |
| 228 | target_ulong entry; |
| 229 | target_ulong toc; |
| 230 | }; |
| 231 | |
| 232 | #endif |
| 233 | |
| 234 | /* See arch/powerpc/kernel/signal.c. */ |
| 235 | static target_ulong get_sigframe(struct target_sigaction *ka, |
| 236 | CPUPPCState *env, |
| 237 | int frame_size) |
| 238 | { |
| 239 | target_ulong oldsp; |
| 240 | |
| 241 | oldsp = target_sigsp(get_sp_from_cpustate(env), ka); |
| 242 | |
| 243 | return (oldsp - frame_size) & ~0xFUL; |
| 244 | } |
| 245 | |
| 246 | #if TARGET_BIG_ENDIAN == HOST_BIG_ENDIAN |
| 247 | #define PPC_VEC_HI 0 |
| 248 | #define PPC_VEC_LO 1 |
| 249 | #else |
| 250 | #define PPC_VEC_HI 1 |
| 251 | #define PPC_VEC_LO 0 |
| 252 | #endif |
| 253 | |
| 254 | |
| 255 | static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) |
| 256 | { |
| 257 | target_ulong msr = env->msr; |
| 258 | int i; |
| 259 | uint32_t ccr = 0; |
| 260 | |
| 261 | /* In general, the kernel attempts to be intelligent about what it |
| 262 | needs to save for Altivec/FP/SPE registers. We don't care that |
| 263 | much, so we just go ahead and save everything. */ |
| 264 | |
| 265 | /* Save general registers. */ |
| 266 | for (i = 0; i < ARRAY_SIZE(env->gpr); i++) { |
| 267 | __put_user(env->gpr[i], &frame->mc_gregs[i]); |
| 268 | } |
| 269 | __put_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]); |
| 270 | __put_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]); |
| 271 | __put_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]); |
| 272 | __put_user(cpu_read_xer(env), &frame->mc_gregs[TARGET_PT_XER]); |
| 273 | |
| 274 | ccr = ppc_get_cr(env); |
| 275 | __put_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]); |
| 276 | |
| 277 | /* Save Altivec registers if necessary. */ |
| 278 | if (env->insns_flags & PPC_ALTIVEC) { |
| 279 | uint32_t *vrsave; |
| 280 | for (i = 0; i < 32; i++) { |
| 281 | ppc_avr_t *avr = cpu_avr_ptr(env, i); |
| 282 | ppc_avr_t *vreg = (ppc_avr_t *)&frame->mc_vregs.altivec[i]; |
| 283 | |
| 284 | __put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); |
| 285 | __put_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); |
| 286 | } |
| 287 | #if defined(TARGET_PPC64) |
| 288 | vrsave = (uint32_t *)&frame->mc_vregs.altivec[33]; |
| 289 | /* 64-bit needs to put a pointer to the vectors in the frame */ |
| 290 | __put_user(h2g(frame->mc_vregs.altivec), &frame->v_regs); |
| 291 | #else |
| 292 | vrsave = (uint32_t *)&frame->mc_vregs.altivec[32]; |
| 293 | #endif |
| 294 | __put_user((uint32_t)env->spr[SPR_VRSAVE], vrsave); |
| 295 | } |
| 296 | |
| 297 | #if defined(TARGET_PPC64) |
| 298 | /* Save VSX second halves */ |
| 299 | if (env->insns_flags2 & PPC2_VSX) { |
| 300 | uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34]; |
| 301 | for (i = 0; i < 32; i++) { |
| 302 | uint64_t *vsrl = cpu_vsrl_ptr(env, i); |
| 303 | __put_user(*vsrl, &vsregs[i]); |
| 304 | } |
| 305 | } |
| 306 | #endif |
| 307 | |
| 308 | /* Save floating point registers. */ |
| 309 | if (env->insns_flags & PPC_FLOAT) { |
| 310 | for (i = 0; i < 32; i++) { |
| 311 | uint64_t *fpr = cpu_fpr_ptr(env, i); |
| 312 | __put_user(*fpr, &frame->mc_fregs[i]); |
| 313 | } |
| 314 | __put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]); |
| 315 | } |
| 316 | |
| 317 | #if !defined(TARGET_PPC64) |
| 318 | /* Save SPE registers. The kernel only saves the high half. */ |
| 319 | if (env->insns_flags & PPC_SPE) { |
| 320 | for (i = 0; i < ARRAY_SIZE(env->gprh); i++) { |
| 321 | __put_user(env->gprh[i], &frame->mc_vregs.spe[i]); |
| 322 | } |
| 323 | __put_user(env->spe_fscr, &frame->mc_vregs.spe[32]); |
| 324 | } |
| 325 | #endif |
| 326 | |
| 327 | /* Store MSR. */ |
| 328 | __put_user(msr, &frame->mc_gregs[TARGET_PT_MSR]); |
| 329 | } |
| 330 | |
| 331 | static void encode_trampoline(int sigret, uint32_t *tramp) |
| 332 | { |
| 333 | /* Set up the sigreturn trampoline: li r0,sigret; sc. */ |
| 334 | __put_user(0x38000000 | sigret, &tramp[0]); |
| 335 | __put_user(0x44000002, &tramp[1]); |
| 336 | } |
| 337 | |
| 338 | static void restore_user_regs(CPUPPCState *env, |
| 339 | struct target_mcontext *frame, int sig) |
| 340 | { |
| 341 | target_ulong save_r2 = 0; |
| 342 | target_ulong msr; |
| 343 | target_ulong xer; |
| 344 | target_ulong ccr; |
| 345 | |
| 346 | int i; |
| 347 | |
| 348 | if (!sig) { |
| 349 | save_r2 = env->gpr[2]; |
| 350 | } |
| 351 | |
| 352 | /* Restore general registers. */ |
| 353 | for (i = 0; i < ARRAY_SIZE(env->gpr); i++) { |
| 354 | __get_user(env->gpr[i], &frame->mc_gregs[i]); |
| 355 | } |
| 356 | __get_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]); |
| 357 | __get_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]); |
| 358 | __get_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]); |
| 359 | |
| 360 | __get_user(xer, &frame->mc_gregs[TARGET_PT_XER]); |
| 361 | cpu_write_xer(env, xer); |
| 362 | |
| 363 | __get_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]); |
| 364 | ppc_set_cr(env, ccr); |
| 365 | if (!sig) { |
| 366 | env->gpr[2] = save_r2; |
| 367 | } |
| 368 | /* Restore MSR. */ |
| 369 | __get_user(msr, &frame->mc_gregs[TARGET_PT_MSR]); |
| 370 | |
| 371 | /* If doing signal return, restore the previous little-endian mode. */ |
| 372 | if (sig) { |
| 373 | ppc_store_msr(env, ((env->msr & ~(1ull << MSR_LE)) | |
| 374 | (msr & (1ull << MSR_LE)))); |
| 375 | } |
| 376 | |
| 377 | /* Restore Altivec registers if necessary. */ |
| 378 | if (env->insns_flags & PPC_ALTIVEC) { |
| 379 | ppc_avr_t *v_regs; |
| 380 | uint32_t *vrsave; |
| 381 | #if defined(TARGET_PPC64) |
| 382 | uint64_t v_addr; |
| 383 | /* 64-bit needs to recover the pointer to the vectors from the frame */ |
| 384 | __get_user(v_addr, &frame->v_regs); |
| 385 | v_regs = g2h(env_cpu(env), v_addr); |
| 386 | #else |
| 387 | v_regs = (ppc_avr_t *)frame->mc_vregs.altivec; |
| 388 | #endif |
| 389 | for (i = 0; i < 32; i++) { |
| 390 | ppc_avr_t *avr = cpu_avr_ptr(env, i); |
| 391 | ppc_avr_t *vreg = &v_regs[i]; |
| 392 | |
| 393 | __get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); |
| 394 | __get_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); |
| 395 | } |
| 396 | #if defined(TARGET_PPC64) |
| 397 | vrsave = (uint32_t *)&v_regs[33]; |
| 398 | #else |
| 399 | vrsave = (uint32_t *)&v_regs[32]; |
| 400 | #endif |
| 401 | __get_user(env->spr[SPR_VRSAVE], vrsave); |
| 402 | } |
| 403 | |
| 404 | #if defined(TARGET_PPC64) |
| 405 | /* Restore VSX second halves */ |
| 406 | if (env->insns_flags2 & PPC2_VSX) { |
| 407 | uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34]; |
| 408 | for (i = 0; i < 32; i++) { |
| 409 | uint64_t *vsrl = cpu_vsrl_ptr(env, i); |
| 410 | __get_user(*vsrl, &vsregs[i]); |
| 411 | } |
| 412 | } |
| 413 | #endif |
| 414 | |
| 415 | /* Restore floating point registers. */ |
| 416 | if (env->insns_flags & PPC_FLOAT) { |
| 417 | uint64_t fpscr; |
| 418 | for (i = 0; i < 32; i++) { |
| 419 | uint64_t *fpr = cpu_fpr_ptr(env, i); |
| 420 | __get_user(*fpr, &frame->mc_fregs[i]); |
| 421 | } |
| 422 | __get_user(fpscr, &frame->mc_fregs[32]); |
| 423 | ppc_store_fpscr(env, (uint32_t) fpscr); |
| 424 | } |
| 425 | |
| 426 | #if !defined(TARGET_PPC64) |
| 427 | /* Save SPE registers. The kernel only saves the high half. */ |
| 428 | if (env->insns_flags & PPC_SPE) { |
| 429 | for (i = 0; i < ARRAY_SIZE(env->gprh); i++) { |
| 430 | __get_user(env->gprh[i], &frame->mc_vregs.spe[i]); |
| 431 | } |
| 432 | __get_user(env->spe_fscr, &frame->mc_vregs.spe[32]); |
| 433 | } |
| 434 | #endif |
| 435 | } |
| 436 | |
| 437 | #if !defined(TARGET_PPC64) |
| 438 | void setup_frame(int sig, struct target_sigaction *ka, |
| 439 | target_sigset_t *set, CPUPPCState *env) |
| 440 | { |
| 441 | struct target_sigframe *frame; |
| 442 | struct target_sigcontext *sc; |
| 443 | target_ulong frame_addr, newsp; |
| 444 | int err = 0; |
| 445 | |
| 446 | frame_addr = get_sigframe(ka, env, sizeof(*frame)); |
| 447 | trace_user_setup_frame(env, frame_addr); |
| 448 | if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 1)) |
| 449 | goto sigsegv; |
| 450 | sc = &frame->sctx; |
| 451 | |
| 452 | __put_user(ka->_sa_handler, &sc->handler); |
| 453 | __put_user(set->sig[0], &sc->oldmask); |
| 454 | __put_user(set->sig[1], &sc->_unused[3]); |
| 455 | __put_user(h2g(&frame->mctx), &sc->regs); |
| 456 | __put_user(sig, &sc->signal); |
| 457 | |
| 458 | /* Save user regs. */ |
| 459 | save_user_regs(env, &frame->mctx); |
| 460 | |
| 461 | env->lr = default_sigreturn; |
| 462 | |
| 463 | /* Turn off all fp exceptions. */ |
| 464 | env->fpscr = 0; |
| 465 | |
| 466 | /* Create a stack frame for the caller of the handler. */ |
| 467 | newsp = frame_addr - SIGNAL_FRAMESIZE; |
| 468 | err |= put_user(env->gpr[1], newsp, target_ulong); |
| 469 | |
| 470 | if (err) |
| 471 | goto sigsegv; |
| 472 | |
| 473 | /* Set up registers for signal handler. */ |
| 474 | env->gpr[1] = newsp; |
| 475 | env->gpr[3] = sig; |
| 476 | env->gpr[4] = frame_addr + offsetof(struct target_sigframe, sctx); |
| 477 | |
| 478 | env->nip = (target_ulong) ka->_sa_handler; |
| 479 | |
| 480 | /* Signal handlers are entered in big-endian mode. */ |
| 481 | ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); |
| 482 | |
| 483 | unlock_user_struct(frame, frame_addr, 1); |
| 484 | return; |
| 485 | |
| 486 | sigsegv: |
| 487 | unlock_user_struct(frame, frame_addr, 1); |
| 488 | force_sigsegv(sig); |
| 489 | } |
| 490 | #endif /* !defined(TARGET_PPC64) */ |
| 491 | |
| 492 | void setup_rt_frame(int sig, struct target_sigaction *ka, |
| 493 | target_siginfo_t *info, |
| 494 | target_sigset_t *set, CPUPPCState *env) |
| 495 | { |
| 496 | struct target_rt_sigframe *rt_sf; |
| 497 | struct target_mcontext *mctx = 0; |
| 498 | target_ulong rt_sf_addr, newsp = 0; |
| 499 | int i, err = 0; |
| 500 | #if defined(TARGET_PPC64) |
| 501 | struct target_sigcontext *sc = 0; |
| 502 | struct image_info *image = get_task_state(thread_cpu)->info; |
| 503 | #endif |
| 504 | |
| 505 | rt_sf_addr = get_sigframe(ka, env, sizeof(*rt_sf)); |
| 506 | if (!lock_user_struct(VERIFY_WRITE, rt_sf, rt_sf_addr, 1)) |
| 507 | goto sigsegv; |
| 508 | |
| 509 | rt_sf->info = *info; |
| 510 | |
| 511 | __put_user(0, &rt_sf->uc.tuc_flags); |
| 512 | __put_user(0, &rt_sf->uc.tuc_link); |
| 513 | target_save_altstack(&rt_sf->uc.tuc_stack, env); |
| 514 | #if !defined(TARGET_PPC64) |
| 515 | __put_user(h2g (&rt_sf->uc.tuc_mcontext), |
| 516 | &rt_sf->uc.tuc_regs); |
| 517 | #endif |
| 518 | for (i = 0; i < TARGET_NSIG_WORDS; i++) { |
| 519 | __put_user(set->sig[i], &rt_sf->uc.tuc_sigmask.sig[i]); |
| 520 | } |
| 521 | |
| 522 | #if defined(TARGET_PPC64) |
| 523 | mctx = &rt_sf->uc.tuc_sigcontext.mcontext; |
| 524 | |
| 525 | sc = &rt_sf->uc.tuc_sigcontext; |
| 526 | __put_user(h2g(mctx), &sc->regs); |
| 527 | __put_user(sig, &sc->signal); |
| 528 | #else |
| 529 | mctx = &rt_sf->uc.tuc_mcontext; |
| 530 | #endif |
| 531 | |
| 532 | save_user_regs(env, mctx); |
| 533 | |
| 534 | env->lr = default_rt_sigreturn; |
| 535 | |
| 536 | /* Turn off all fp exceptions. */ |
| 537 | env->fpscr = 0; |
| 538 | |
| 539 | /* Create a stack frame for the caller of the handler. */ |
| 540 | newsp = rt_sf_addr - (SIGNAL_FRAMESIZE + RT_SIGFRAME_ADJUST); |
| 541 | err |= put_user(env->gpr[1], newsp, target_ulong); |
| 542 | |
| 543 | if (err) |
| 544 | goto sigsegv; |
| 545 | |
| 546 | /* Set up registers for signal handler. */ |
| 547 | env->gpr[1] = newsp; |
| 548 | env->gpr[3] = (target_ulong) sig; |
| 549 | env->gpr[4] = (target_ulong) h2g(&rt_sf->info); |
| 550 | env->gpr[5] = (target_ulong) h2g(&rt_sf->uc); |
| 551 | env->gpr[6] = (target_ulong) h2g(rt_sf); |
| 552 | |
| 553 | #if defined(TARGET_PPC64) |
| 554 | if (get_ppc64_abi(image) < 2) { |
| 555 | /* ELFv1 PPC64 function pointers are pointers to OPD entries. */ |
| 556 | struct target_func_ptr *handler = |
| 557 | (struct target_func_ptr *)g2h(env_cpu(env), ka->_sa_handler); |
| 558 | env->nip = tswapl(handler->entry); |
| 559 | env->gpr[2] = tswapl(handler->toc); |
| 560 | } else { |
| 561 | /* ELFv2 PPC64 function pointers are entry points. R12 must also be set. */ |
| 562 | env->gpr[12] = env->nip = ka->_sa_handler; |
| 563 | } |
| 564 | #else |
| 565 | env->nip = (target_ulong) ka->_sa_handler; |
| 566 | #endif |
| 567 | |
| 568 | #if TARGET_BIG_ENDIAN |
| 569 | /* Signal handlers are entered in big-endian mode. */ |
| 570 | ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); |
| 571 | #else |
| 572 | /* Signal handlers are entered in little-endian mode. */ |
| 573 | ppc_store_msr(env, env->msr | (1ull << MSR_LE)); |
| 574 | #endif |
| 575 | |
| 576 | unlock_user_struct(rt_sf, rt_sf_addr, 1); |
| 577 | return; |
| 578 | |
| 579 | sigsegv: |
| 580 | unlock_user_struct(rt_sf, rt_sf_addr, 1); |
| 581 | force_sigsegv(sig); |
| 582 | |
| 583 | } |
| 584 | |
| 585 | #if !defined(TARGET_PPC64) |
| 586 | long do_sigreturn(CPUPPCState *env) |
| 587 | { |
| 588 | struct target_sigcontext *sc = NULL; |
| 589 | struct target_mcontext *sr = NULL; |
| 590 | target_ulong sr_addr = 0, sc_addr; |
| 591 | sigset_t blocked; |
| 592 | target_sigset_t set; |
| 593 | |
| 594 | sc_addr = env->gpr[1] + SIGNAL_FRAMESIZE; |
| 595 | if (!lock_user_struct(VERIFY_READ, sc, sc_addr, 1)) |
| 596 | goto sigsegv; |
| 597 | |
| 598 | __get_user(set.sig[0], &sc->oldmask); |
| 599 | __get_user(set.sig[1], &sc->_unused[3]); |
| 600 | |
| 601 | target_to_host_sigset_internal(&blocked, &set); |
| 602 | set_sigmask(&blocked); |
| 603 | |
| 604 | __get_user(sr_addr, &sc->regs); |
| 605 | if (!lock_user_struct(VERIFY_READ, sr, sr_addr, 1)) |
| 606 | goto sigsegv; |
| 607 | restore_user_regs(env, sr, 1); |
| 608 | |
| 609 | unlock_user_struct(sr, sr_addr, 1); |
| 610 | unlock_user_struct(sc, sc_addr, 1); |
| 611 | return -QEMU_ESIGRETURN; |
| 612 | |
| 613 | sigsegv: |
| 614 | unlock_user_struct(sr, sr_addr, 1); |
| 615 | unlock_user_struct(sc, sc_addr, 1); |
| 616 | force_sig(TARGET_SIGSEGV); |
| 617 | return -QEMU_ESIGRETURN; |
| 618 | } |
| 619 | #endif /* !defined(TARGET_PPC64) */ |
| 620 | |
| 621 | /* See arch/powerpc/kernel/signal_32.c. */ |
| 622 | static int do_setcontext(struct target_ucontext *ucp, CPUPPCState *env, int sig) |
| 623 | { |
| 624 | struct target_mcontext *mcp; |
| 625 | target_ulong mcp_addr; |
| 626 | sigset_t blocked; |
| 627 | target_sigset_t set; |
| 628 | |
| 629 | if (copy_from_user(&set, h2g(ucp) + offsetof(struct target_ucontext, tuc_sigmask), |
| 630 | sizeof (set))) |
| 631 | return 1; |
| 632 | |
| 633 | #if defined(TARGET_PPC64) |
| 634 | mcp_addr = h2g(ucp) + |
| 635 | offsetof(struct target_ucontext, tuc_sigcontext.mcontext); |
| 636 | #else |
| 637 | __get_user(mcp_addr, &ucp->tuc_regs); |
| 638 | #endif |
| 639 | |
| 640 | if (!lock_user_struct(VERIFY_READ, mcp, mcp_addr, 1)) |
| 641 | return 1; |
| 642 | |
| 643 | target_to_host_sigset(&blocked, &set); |
| 644 | set_sigmask(&blocked); |
| 645 | restore_user_regs(env, mcp, sig); |
| 646 | |
| 647 | unlock_user_struct(mcp, mcp_addr, 1); |
| 648 | return 0; |
| 649 | } |
| 650 | |
| 651 | long do_rt_sigreturn(CPUPPCState *env) |
| 652 | { |
| 653 | struct target_rt_sigframe *rt_sf = NULL; |
| 654 | target_ulong rt_sf_addr; |
| 655 | |
| 656 | rt_sf_addr = env->gpr[1] + SIGNAL_FRAMESIZE + RT_SIGFRAME_ADJUST; |
| 657 | if (!lock_user_struct(VERIFY_READ, rt_sf, rt_sf_addr, 1)) |
| 658 | goto sigsegv; |
| 659 | |
| 660 | if (do_setcontext(&rt_sf->uc, env, 1)) |
| 661 | goto sigsegv; |
| 662 | |
| 663 | target_restore_altstack(&rt_sf->uc.tuc_stack, env); |
| 664 | |
| 665 | unlock_user_struct(rt_sf, rt_sf_addr, 1); |
| 666 | return -QEMU_ESIGRETURN; |
| 667 | |
| 668 | sigsegv: |
| 669 | unlock_user_struct(rt_sf, rt_sf_addr, 1); |
| 670 | force_sig(TARGET_SIGSEGV); |
| 671 | return -QEMU_ESIGRETURN; |
| 672 | } |
| 673 | |
| 674 | /* This syscall implements {get,set,swap}context for userland. */ |
| 675 | abi_long do_swapcontext(CPUArchState *env, abi_ulong uold_ctx, |
| 676 | abi_ulong unew_ctx, abi_long ctx_size) |
| 677 | { |
| 678 | struct target_ucontext *uctx; |
| 679 | struct target_mcontext *mctx; |
| 680 | |
| 681 | /* For ppc32, ctx_size is "reserved for future use". |
| 682 | * For ppc64, we do not yet support the VSX extension. |
| 683 | */ |
| 684 | if (ctx_size < sizeof(struct target_ucontext)) { |
| 685 | return -TARGET_EINVAL; |
| 686 | } |
| 687 | |
| 688 | if (uold_ctx) { |
| 689 | TaskState *ts = get_task_state(thread_cpu); |
| 690 | |
| 691 | if (!lock_user_struct(VERIFY_WRITE, uctx, uold_ctx, 1)) { |
| 692 | return -TARGET_EFAULT; |
| 693 | } |
| 694 | |
| 695 | #ifdef TARGET_PPC64 |
| 696 | mctx = &uctx->tuc_sigcontext.mcontext; |
| 697 | #else |
| 698 | /* ??? The kernel aligns the pointer down here into padding, but |
| 699 | * in setup_rt_frame we don't. Be self-compatible for now. |
| 700 | */ |
| 701 | mctx = &uctx->tuc_mcontext; |
| 702 | __put_user(h2g(mctx), &uctx->tuc_regs); |
| 703 | #endif |
| 704 | |
| 705 | save_user_regs(env, mctx); |
| 706 | host_to_target_sigset(&uctx->tuc_sigmask, &ts->signal_mask); |
| 707 | |
| 708 | unlock_user_struct(uctx, uold_ctx, 1); |
| 709 | } |
| 710 | |
| 711 | if (unew_ctx) { |
| 712 | int err; |
| 713 | |
| 714 | if (!lock_user_struct(VERIFY_READ, uctx, unew_ctx, 1)) { |
| 715 | return -TARGET_EFAULT; |
| 716 | } |
| 717 | err = do_setcontext(uctx, env, 0); |
| 718 | unlock_user_struct(uctx, unew_ctx, 1); |
| 719 | |
| 720 | if (err) { |
| 721 | /* We cannot return to a partially updated context. */ |
| 722 | force_sig(TARGET_SIGSEGV); |
| 723 | } |
| 724 | return -QEMU_ESIGRETURN; |
| 725 | } |
| 726 | |
| 727 | return 0; |
| 728 | } |
| 729 | |
| 730 | void setup_sigtramp(abi_ulong sigtramp_page) |
| 731 | { |
| 732 | uint32_t *tramp = lock_user(VERIFY_WRITE, sigtramp_page, 2 * 8, 0); |
| 733 | assert(tramp != NULL); |
| 734 | |
| 735 | #ifdef TARGET_ARCH_HAS_SETUP_FRAME |
| 736 | default_sigreturn = sigtramp_page; |
| 737 | encode_trampoline(TARGET_NR_sigreturn, tramp + 0); |
| 738 | #endif |
| 739 | |
| 740 | default_rt_sigreturn = sigtramp_page + 8; |
| 741 | encode_trampoline(TARGET_NR_rt_sigreturn, tramp + 2); |
| 742 | |
| 743 | unlock_user(tramp, sigtramp_page, 2 * 8); |
| 744 | } |