| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include "qemu/osdep.h" |
| 4 | #include "qemu.h" |
| 5 | #include "loader.h" |
| 6 | #include "target_elf.h" |
| 7 | |
| 8 | |
| 9 | const char *get_elf_cpu_model(uint32_t eflags) |
| 10 | { |
| 11 | return "max"; |
| 12 | } |
| 13 | |
| 14 | void elf_core_copy_fpregs(target_elf_fpregset_t *r, const CPURISCVState *env) |
| 15 | { |
| 16 | for (int i = 0; i < 32; i++) { |
| 17 | r->fpr[i] = tswap64(env->fpr[i]); |
| 18 | } |
| 19 | r->fcsr = tswap32(((uint32_t)env->frm << FSR_RD_SHIFT) | |
| 20 | (riscv_cpu_get_fflags((CPURISCVState *)env) << FSR_AEXC_SHIFT)); |
| 21 | } |
| 22 | |
| 23 | void elf_core_copy_regs(target_elf_gregset_t *r, const CPURISCVState *env) |
| 24 | { |
| 25 | r->pc = tswapal(env->pc); |
| 26 | for (int i = 0; i < 31; i++) { |
| 27 | r->regs[i] = tswapal(env->gpr[i + 1]); |
| 28 | } |
| 29 | } |
| 30 | |
| 31 | abi_ulong get_elf_hwcap(CPUState *cs) |
| 32 | { |
| 33 | #define MISA_BIT(EXT) (1 << (EXT - 'A')) |
| 34 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 35 | uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') |
| 36 | | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C') |
| 37 | | MISA_BIT('V'); |
| 38 | |
| 39 | return cpu->env.misa_ext & mask; |
| 40 | #undef MISA_BIT |
| 41 | } |