| 1 | /* |
| 2 | * RISC-V specific proc functions for linux-user |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 5 | */ |
| 6 | #ifndef RISCV_TARGET_PROC_H |
| 7 | #define RISCV_TARGET_PROC_H |
| 8 | |
| 9 | static int open_cpuinfo(CPUArchState *cpu_env, int fd) |
| 10 | { |
| 11 | int i; |
| 12 | int num_cpus = sysconf(_SC_NPROCESSORS_ONLN); |
| 13 | RISCVCPU *cpu = env_archcpu(cpu_env); |
| 14 | const RISCVCPUConfig *cfg = riscv_cpu_cfg((CPURISCVState *) cpu_env); |
| 15 | char *isa_string = riscv_isa_string(cpu); |
| 16 | const char *mmu; |
| 17 | |
| 18 | if (cfg->mmu) { |
| 19 | mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48"; |
| 20 | } else { |
| 21 | mmu = "none"; |
| 22 | } |
| 23 | |
| 24 | for (i = 0; i < num_cpus; i++) { |
| 25 | dprintf(fd, "processor\t: %d\n", i); |
| 26 | dprintf(fd, "hart\t\t: %d\n", i); |
| 27 | dprintf(fd, "isa\t\t: %s\n", isa_string); |
| 28 | dprintf(fd, "mmu\t\t: %s\n", mmu); |
| 29 | dprintf(fd, "uarch\t\t: qemu\n\n"); |
| 30 | } |
| 31 | |
| 32 | g_free(isa_string); |
| 33 | return 0; |
| 34 | } |
| 35 | #define HAVE_ARCH_PROC_CPUINFO |
| 36 | |
| 37 | #endif /* RISCV_TARGET_PROC_H */ |