| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include "qemu/osdep.h" |
| 4 | #include "qemu.h" |
| 5 | #include "loader.h" |
| 6 | #include "target_elf.h" |
| 7 | |
| 8 | #if TARGET_BIG_ENDIAN |
| 9 | # include "vdso-be.c.inc" |
| 10 | #else |
| 11 | # include "vdso-le.c.inc" |
| 12 | #endif |
| 13 | |
| 14 | const VdsoImageInfo *get_vdso_image_info(uint32_t elf_flags G_GNUC_UNUSED) |
| 15 | { |
| 16 | #if TARGET_BIG_ENDIAN |
| 17 | return &vdso_be_image_info; |
| 18 | #else |
| 19 | return &vdso_le_image_info; |
| 20 | #endif |
| 21 | } |
| 22 | |
| 23 | const char *get_elf_cpu_model(uint32_t eflags) |
| 24 | { |
| 25 | return "sh7785"; |
| 26 | } |
| 27 | |
| 28 | enum { |
| 29 | SH_CPU_HAS_FPU = 0x0001, /* Hardware FPU support */ |
| 30 | SH_CPU_HAS_P2_FLUSH_BUG = 0x0002, /* Need to flush the cache in P2 area */ |
| 31 | SH_CPU_HAS_MMU_PAGE_ASSOC = 0x0004, /* SH3: TLB way selection bit support */ |
| 32 | SH_CPU_HAS_DSP = 0x0008, /* SH-DSP: DSP support */ |
| 33 | SH_CPU_HAS_PERF_COUNTER = 0x0010, /* Hardware performance counters */ |
| 34 | SH_CPU_HAS_PTEA = 0x0020, /* PTEA register */ |
| 35 | SH_CPU_HAS_LLSC = 0x0040, /* movli.l/movco.l */ |
| 36 | SH_CPU_HAS_L2_CACHE = 0x0080, /* Secondary cache / URAM */ |
| 37 | SH_CPU_HAS_OP32 = 0x0100, /* 32-bit instruction support */ |
| 38 | SH_CPU_HAS_PTEAEX = 0x0200, /* PTE ASID Extension support */ |
| 39 | }; |
| 40 | |
| 41 | abi_ulong get_elf_hwcap(CPUState *cs) |
| 42 | { |
| 43 | SuperHCPU *cpu = SUPERH_CPU(cs); |
| 44 | abi_ulong hwcap = 0; |
| 45 | |
| 46 | hwcap |= SH_CPU_HAS_FPU; |
| 47 | |
| 48 | if (cpu->env.features & SH_FEATURE_SH4A) { |
| 49 | hwcap |= SH_CPU_HAS_LLSC; |
| 50 | } |
| 51 | |
| 52 | return hwcap; |
| 53 | } |
| 54 | |
| 55 | void elf_core_copy_fpregs(target_elf_fpregset_t *r, const CPUSH4State *env) |
| 56 | { |
| 57 | for (int i = 0; i < 16; i++) { |
| 58 | r->fpregs[i] = tswap32(env->fregs[i]); |
| 59 | r->xfpregs[i] = tswap32(env->fregs[16 + i]); |
| 60 | } |
| 61 | r->fpscr = tswap32(env->fpscr); |
| 62 | r->fpul = tswap32(env->fpul); |
| 63 | } |
| 64 | |
| 65 | void elf_core_copy_regs(target_elf_gregset_t *r, const CPUSH4State *env) |
| 66 | { |
| 67 | for (int i = 0; i < 16; i++) { |
| 68 | r->pt.regs[i] = tswapal(env->gregs[i]); |
| 69 | } |
| 70 | |
| 71 | r->pt.pc = tswapal(env->pc); |
| 72 | r->pt.pr = tswapal(env->pr); |
| 73 | r->pt.sr = tswapal(env->sr); |
| 74 | r->pt.gbr = tswapal(env->gbr); |
| 75 | r->pt.mach = tswapal(env->mach); |
| 76 | r->pt.macl = tswapal(env->macl); |
| 77 | } |