@samitouri / QOSamiQemu
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1 /*
2 * sh4 linux replacement vdso.
3 *
4 * Copyright 2023 Linaro, Ltd.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #include <asm/unistd.h>
10 #include "vdso-asmoffset.h"
11
12 .text
13
14 .macro endf name
15 .globl \name
16 .type \name, @function
17 .size \name, . - \name
18 .endm
19
20 /*
21 * SH4 syscall convention:
22 * Syscall number in r3 (caller-saved, so no save/restore needed)
23 * Arguments in r4-r7
24 * Return value in r0
25 * Syscall instruction: trapa #0x10
26 */
27
28 .macro vdso_syscall name, nr
29 \name:
30 .cfi_startproc
31 mov.l 1f, r3
32 trapa #0x10
33 rts
34 nop
35 .align 2
36 1: .long \nr
37 .cfi_endproc
38 endf \name
39 .endm
40
41 vdso_syscall __vdso_clock_gettime, __NR_clock_gettime
42 vdso_syscall __vdso_clock_gettime64, __NR_clock_gettime64
43 vdso_syscall __vdso_clock_getres, __NR_clock_getres
44 vdso_syscall __vdso_gettimeofday, __NR_gettimeofday
45
46 /*
47 * Signal return trampolines.
48 *
49 * For sigreturn: r15 points to struct sigframe; sigcontext is at
50 * offset SIGFRAME_SC_OFFSET (0).
51 * For rt_sigreturn: r15 points to struct rt_sigframe; sigcontext is at
52 * offset RT_SIGFRAME_SC_OFFSET (148).
53 *
54 * A single CFI region covers both trampolines. The CFA is set to the
55 * start of the relevant sigcontext; all register offsets are then
56 * identical for both trampolines. Between the two trampolines we use
57 * .cfi_def_cfa_offset to update the CFA base for the different layout.
58 */
59
60 /*
61 * Start the unwind info at least one instruction before the signal
62 * trampoline, because the unwinder will assume we are returning
63 * after a call site.
64 */
65 .cfi_startproc simple
66 .cfi_signal_frame
67 .cfi_return_column 16 /* return column is PC */
68
69 /* CFA = r15 + SIGFRAME_SC_OFFSET = r15 (sigcontext base, sigreturn). */
70 .cfi_def_cfa 15, SIGFRAME_SC_OFFSET
71
72 /* Integer registers r0-r15: sc_gregs[n] at sigcontext + SC_GREGS + n*4. */
73 .cfi_offset 0, SC_GREGS + 0 * 4
74 .cfi_offset 1, SC_GREGS + 1 * 4
75 .cfi_offset 2, SC_GREGS + 2 * 4
76 .cfi_offset 3, SC_GREGS + 3 * 4
77 .cfi_offset 4, SC_GREGS + 4 * 4
78 .cfi_offset 5, SC_GREGS + 5 * 4
79 .cfi_offset 6, SC_GREGS + 6 * 4
80 .cfi_offset 7, SC_GREGS + 7 * 4
81 .cfi_offset 8, SC_GREGS + 8 * 4
82 .cfi_offset 9, SC_GREGS + 9 * 4
83 .cfi_offset 10, SC_GREGS + 10 * 4
84 .cfi_offset 11, SC_GREGS + 11 * 4
85 .cfi_offset 12, SC_GREGS + 12 * 4
86 .cfi_offset 13, SC_GREGS + 13 * 4
87 .cfi_offset 14, SC_GREGS + 14 * 4
88 .cfi_offset 15, SC_GREGS + 15 * 4
89
90 /* PC (return column). */
91 .cfi_offset 16, SC_PC
92
93 /* Control registers. */
94 .cfi_offset 17, SC_PR
95 .cfi_offset 18, SC_GBR
96 .cfi_offset 20, SC_MACH
97 .cfi_offset 21, SC_MACL
98
99 /* FP registers fr0-fr15: sc_fpregs[n] at sigcontext + SC_FPREGS + n*4. */
100 .cfi_offset 25, SC_FPREGS + 0 * 4
101 .cfi_offset 26, SC_FPREGS + 1 * 4
102 .cfi_offset 27, SC_FPREGS + 2 * 4
103 .cfi_offset 28, SC_FPREGS + 3 * 4
104 .cfi_offset 29, SC_FPREGS + 4 * 4
105 .cfi_offset 30, SC_FPREGS + 5 * 4
106 .cfi_offset 31, SC_FPREGS + 6 * 4
107 .cfi_offset 32, SC_FPREGS + 7 * 4
108 .cfi_offset 33, SC_FPREGS + 8 * 4
109 .cfi_offset 34, SC_FPREGS + 9 * 4
110 .cfi_offset 35, SC_FPREGS + 10 * 4
111 .cfi_offset 36, SC_FPREGS + 11 * 4
112 .cfi_offset 37, SC_FPREGS + 12 * 4
113 .cfi_offset 38, SC_FPREGS + 13 * 4
114 .cfi_offset 39, SC_FPREGS + 14 * 4
115 .cfi_offset 40, SC_FPREGS + 15 * 4
116
117 /* FPUL, FPSCR. */
118 .cfi_offset 23, SC_FPUL
119 .cfi_offset 24, SC_FPSCR
120
121 nop
122
123 sigreturn_region_start:
124 __kernel_sigreturn:
125 mov.l 1f, r3
126 trapa #0x10
127 .align 2
128 1: .long __NR_sigreturn
129 endf __kernel_sigreturn
130
131 /* Update CFA base for the rt_sigreturn frame layout. */
132 .cfi_def_cfa_offset RT_SIGFRAME_SC_OFFSET
133
134 __kernel_rt_sigreturn:
135 mov.l 2f, r3
136 trapa #0x10
137 .align 2
138 2: .long __NR_rt_sigreturn
139 endf __kernel_rt_sigreturn
140 sigreturn_region_end:
141
142 .cfi_endproc