| 1 | # -*- Mode: Python -*- |
| 2 | # vim: filetype=python |
| 3 | |
| 4 | ## |
| 5 | # *********** |
| 6 | # CXL devices |
| 7 | # *********** |
| 8 | ## |
| 9 | |
| 10 | ## |
| 11 | # @CxlEventLog: |
| 12 | # |
| 13 | # CXL has a number of separate event logs for different types of |
| 14 | # events. Each such event log is handled and signaled independently. |
| 15 | # |
| 16 | # @informational: Information Event Log |
| 17 | # |
| 18 | # @warning: Warning Event Log |
| 19 | # |
| 20 | # @failure: Failure Event Log |
| 21 | # |
| 22 | # @fatal: Fatal Event Log |
| 23 | # |
| 24 | # Since: 8.1 |
| 25 | ## |
| 26 | { 'enum': 'CxlEventLog', |
| 27 | 'data': ['informational', |
| 28 | 'warning', |
| 29 | 'failure', |
| 30 | 'fatal'] |
| 31 | } |
| 32 | |
| 33 | ## |
| 34 | # @CXLCommonEventBase: |
| 35 | # |
| 36 | # Common event base for a CXL Event (CXL r3.2 8.2.10.2.1 |
| 37 | # Table 8-55 Common Event Record Format). |
| 38 | # |
| 39 | # @path: CXL type 3 device canonical QOM path |
| 40 | # |
| 41 | # @log: event log to add the event to |
| 42 | # |
| 43 | # @flags: Event Record Flags. See CXL r3.2 Table 8-55 Common Event |
| 44 | # Record Format, Event Record Flags for subfield definitions. |
| 45 | # |
| 46 | # @maint-op-class: Maintenance operation class the device requests to |
| 47 | # initiate. |
| 48 | # |
| 49 | # @maint-op-subclass: Maintenance operation subclass the device |
| 50 | # requests to initiate. |
| 51 | # |
| 52 | # @ld-id: Logical Device (LD) ID of LD from where the event |
| 53 | # originated. |
| 54 | # |
| 55 | # @head-id: ID of the device head from where the event originated. |
| 56 | # |
| 57 | # Since: 8.1 |
| 58 | ## |
| 59 | { 'struct': 'CXLCommonEventBase', |
| 60 | 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint32', |
| 61 | '*maint-op-class':'uint8', '*maint-op-subclass':'uint8', |
| 62 | '*ld-id':'uint16', '*head-id':'uint8' } } |
| 63 | |
| 64 | ## |
| 65 | # @CXLGeneralMediaEvent: |
| 66 | # |
| 67 | # Event record for a General Media Event (CXL r3.2 8.2.10.2.1.1). |
| 68 | # |
| 69 | # @dpa: Device Physical Address (relative to @path device). Note |
| 70 | # lower bits include some flags. See CXL r3.2 Table 8-57 General |
| 71 | # Media Event Record, Physical Address. |
| 72 | # |
| 73 | # @descriptor: Memory Event Descriptor with additional memory event |
| 74 | # information. See CXL r3.2 Table 8-57 General Media Event |
| 75 | # Record, Memory Event Descriptor for bit definitions. |
| 76 | # |
| 77 | # @type: Type of memory event that occurred. See CXL r3.2 Table 8-57 |
| 78 | # General Media Event Record, Memory Event Type for possible |
| 79 | # values. |
| 80 | # |
| 81 | # @transaction-type: Type of first transaction that caused the event |
| 82 | # to occur. See CXL r3-2 Table 8-57 General Media Event Record, |
| 83 | # Transaction Type for possible values. |
| 84 | # |
| 85 | # @channel: The channel of the memory event location. A channel is an |
| 86 | # interface that can be independently accessed for a transaction. |
| 87 | # |
| 88 | # @rank: The rank of the memory event location. A rank is a set of |
| 89 | # memory devices on a channel that together execute a transaction. |
| 90 | # |
| 91 | # @device: Bitmask that represents all devices in the rank associated |
| 92 | # with the memory event location. |
| 93 | # |
| 94 | # @component-id: Device specific component identifier for the event. |
| 95 | # May describe a field replaceable sub-component of the device. |
| 96 | # |
| 97 | # @is-comp-id-pldm: This flag specifies whether the device-specific |
| 98 | # component identifier format follows PLDM. |
| 99 | # |
| 100 | # @cme-ev-flags: Advanced programmable corrected memory error |
| 101 | # threshold event flags. |
| 102 | # |
| 103 | # @cme-count: Corrected memory error count at event. |
| 104 | # |
| 105 | # @sub-type: Memory event sub-type. |
| 106 | # |
| 107 | # Since: 8.1 |
| 108 | ## |
| 109 | { 'struct': 'CXLGeneralMediaEvent', |
| 110 | 'base': 'CXLCommonEventBase', |
| 111 | 'data': { 'dpa': 'uint64', 'descriptor': 'uint8', |
| 112 | 'type': 'uint8', 'transaction-type': 'uint8', |
| 113 | '*channel': 'uint8', '*rank': 'uint8', |
| 114 | '*device': 'uint32', '*component-id': 'str', |
| 115 | '*is-comp-id-pldm':'bool', |
| 116 | '*cme-ev-flags':'uint8', '*cme-count':'uint32', |
| 117 | 'sub-type':'uint8' } } |
| 118 | |
| 119 | ## |
| 120 | # @cxl-inject-general-media-event: |
| 121 | # |
| 122 | # Inject an event record for a General Media Event (CXL r3.2 |
| 123 | # 8.2.10.2.1.1). This event type is reported via one of the event |
| 124 | # logs specified via the log parameter. |
| 125 | # |
| 126 | # Since: 8.1 |
| 127 | ## |
| 128 | { 'command': 'cxl-inject-general-media-event', |
| 129 | 'data': 'CXLGeneralMediaEvent' } |
| 130 | |
| 131 | ## |
| 132 | # @CXLDRAMEvent: |
| 133 | # |
| 134 | # Event record for a DRAM Event (CXL r3.2 8.2.10.2.1.2). |
| 135 | # |
| 136 | # @dpa: Device Physical Address (relative to @path device). Note |
| 137 | # lower bits include some flags. See CXL r3.2 Table 8-58 DRAM |
| 138 | # Event Record, Physical Address. |
| 139 | # |
| 140 | # @descriptor: Memory Event Descriptor with additional memory event |
| 141 | # information. See CXL r3.2 Table 8-58 DRAM Event Record, Memory |
| 142 | # Event Descriptor for bit definitions. |
| 143 | # |
| 144 | # @type: Type of memory event that occurred. See CXL r3.2 Table 8-58 |
| 145 | # DRAM Event Record, Memory Event Type for possible values. |
| 146 | # |
| 147 | # @transaction-type: Type of first transaction that caused the event |
| 148 | # to occur. See CXL r3.2 Table 8-58 DRAM Event Record, |
| 149 | # Transaction Type for possible values. |
| 150 | # |
| 151 | # @channel: The channel of the memory event location. A channel is an |
| 152 | # interface that can be independently accessed for a transaction. |
| 153 | # |
| 154 | # @rank: The rank of the memory event location. A rank is a set of |
| 155 | # memory devices on a channel that together execute a transaction. |
| 156 | # |
| 157 | # @nibble-mask: Identifies one or more nibbles that the error affects |
| 158 | # |
| 159 | # @bank-group: Bank group of the memory event location, incorporating |
| 160 | # a number of banks. |
| 161 | # |
| 162 | # @bank: Bank of the memory event location. A single bank is accessed |
| 163 | # per read or write of the memory. |
| 164 | # |
| 165 | # @row: Row address within the DRAM. |
| 166 | # |
| 167 | # @column: Column address within the DRAM. |
| 168 | # |
| 169 | # @correction-mask: Bits within each nibble. Used in order of bits |
| 170 | # set in the nibble-mask. Up to 4 nibbles may be covered. |
| 171 | # |
| 172 | # @component-id: Device specific component identifier for the event. |
| 173 | # May describe a field replaceable sub-component of the device. |
| 174 | # |
| 175 | # @is-comp-id-pldm: This flag specifies whether the device-specific |
| 176 | # component identifier format follows PLDM. |
| 177 | # |
| 178 | # @sub-channel: The sub-channel of the memory event location. |
| 179 | # |
| 180 | # @cme-ev-flags: Advanced programmable corrected memory error |
| 181 | # threshold event flags. |
| 182 | # |
| 183 | # @cvme-count: Corrected volatile memory error count at event. |
| 184 | # |
| 185 | # @sub-type: Memory event sub-type. |
| 186 | # |
| 187 | # Since: 8.1 |
| 188 | ## |
| 189 | { 'struct': 'CXLDRAMEvent', |
| 190 | 'base': 'CXLCommonEventBase', |
| 191 | 'data': { 'dpa': 'uint64', 'descriptor': 'uint8', |
| 192 | 'type': 'uint8', 'transaction-type': 'uint8', |
| 193 | '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32', |
| 194 | '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32', |
| 195 | '*column': 'uint16', '*correction-mask': [ 'uint64' ], |
| 196 | '*component-id': 'str', '*is-comp-id-pldm':'bool', |
| 197 | '*sub-channel':'uint8', |
| 198 | '*cme-ev-flags':'uint8', '*cvme-count':'uint32', |
| 199 | 'sub-type':'uint8' |
| 200 | }} |
| 201 | |
| 202 | ## |
| 203 | # @cxl-inject-dram-event: |
| 204 | # |
| 205 | # Inject an event record for a DRAM Event (CXL r3.2 8.2.10.2.1.2). |
| 206 | # This event type is reported via one of the event logs |
| 207 | # specified via the log parameter. |
| 208 | # |
| 209 | # Since: 8.1 |
| 210 | ## |
| 211 | { 'command': 'cxl-inject-dram-event', |
| 212 | 'data': 'CXLDRAMEvent' } |
| 213 | |
| 214 | ## |
| 215 | # @CXLMemModuleEvent: |
| 216 | # |
| 217 | # Event record for a Memory Module Event (CXL r3.2 8.2.10.2.1.3). |
| 218 | # |
| 219 | # @type: Device Event Type. See CXL r3.2 Table 8-59 Memory Module |
| 220 | # Event Record for bit definitions for bit definiions. |
| 221 | # |
| 222 | # @health-status: Overall health summary bitmap. See CXL r3.2 Table |
| 223 | # 8-148 Get Health Info Output Payload, Health Status for bit |
| 224 | # definitions. |
| 225 | # |
| 226 | # @media-status: Overall media health summary. See CXL r3.2 Table |
| 227 | # 8-148 Get Health Info Output Payload, Media Status for bit |
| 228 | # definitions. |
| 229 | # |
| 230 | # @additional-status: See CXL r3.2 Table 8-148 Get Health Info Output |
| 231 | # Payload, Additional Status for subfield definitions. |
| 232 | # |
| 233 | # @life-used: Percentage (0-100) of factory expected life span. |
| 234 | # |
| 235 | # @temperature: Device temperature in degrees Celsius. |
| 236 | # |
| 237 | # @dirty-shutdown-count: Number of times the device has been unable to |
| 238 | # determine whether data loss may have occurred. |
| 239 | # |
| 240 | # @corrected-volatile-error-count: Total number of correctable errors |
| 241 | # in volatile memory. |
| 242 | # |
| 243 | # @corrected-persistent-error-count: Total number of correctable |
| 244 | # errors in persistent memory |
| 245 | # |
| 246 | # @component-id: Device specific component identifier for the event. |
| 247 | # May describe a field replaceable sub-component of the device. |
| 248 | # |
| 249 | # @is-comp-id-pldm: This flag specifies whether the device-specific |
| 250 | # component identifier format follows PLDM. |
| 251 | # |
| 252 | # @sub-type: Device event sub-type. |
| 253 | # |
| 254 | # Since: 8.1 |
| 255 | ## |
| 256 | { 'struct': 'CXLMemModuleEvent', |
| 257 | 'base': 'CXLCommonEventBase', |
| 258 | 'data': { 'type': 'uint8', 'health-status': 'uint8', |
| 259 | 'media-status': 'uint8', 'additional-status': 'uint8', |
| 260 | 'life-used': 'uint8', 'temperature' : 'int16', |
| 261 | 'dirty-shutdown-count': 'uint32', |
| 262 | 'corrected-volatile-error-count': 'uint32', |
| 263 | 'corrected-persistent-error-count': 'uint32', |
| 264 | '*component-id': 'str', '*is-comp-id-pldm':'bool', |
| 265 | 'sub-type':'uint8' |
| 266 | }} |
| 267 | |
| 268 | ## |
| 269 | # @cxl-inject-memory-module-event: |
| 270 | # |
| 271 | # Inject an event record for a Memory Module Event (CXL r3.2 |
| 272 | # 8.2.10.2.1.3). This event includes a copy of the Device Health info |
| 273 | # at the time of the event. |
| 274 | # |
| 275 | # Since: 8.1 |
| 276 | ## |
| 277 | { 'command': 'cxl-inject-memory-module-event', |
| 278 | 'data': 'CXLMemModuleEvent' } |
| 279 | |
| 280 | ## |
| 281 | # @cxl-inject-poison: |
| 282 | # |
| 283 | # Poison records indicate that a CXL memory device knows that a |
| 284 | # particular memory region may be corrupted. This may be because of |
| 285 | # locally detected errors (e.g. ECC failure) or poisoned writes |
| 286 | # received from other components in the system. This injection |
| 287 | # mechanism enables testing of the OS handling of poison records which |
| 288 | # may be queried via the CXL mailbox. |
| 289 | # |
| 290 | # @path: CXL type 3 device canonical QOM path |
| 291 | # |
| 292 | # @start: Start address; must be 64 byte aligned. |
| 293 | # |
| 294 | # @length: Length of poison to inject; must be a multiple of 64 bytes. |
| 295 | # |
| 296 | # Since: 8.1 |
| 297 | ## |
| 298 | { 'command': 'cxl-inject-poison', |
| 299 | 'data': { 'path': 'str', 'start': 'uint64', 'length': 'size' }} |
| 300 | |
| 301 | ## |
| 302 | # @CxlUncorErrorType: |
| 303 | # |
| 304 | # Type of uncorrectable CXL error to inject. These errors are |
| 305 | # reported via an AER uncorrectable internal error with additional |
| 306 | # information logged at the CXL device. |
| 307 | # |
| 308 | # @cache-data-parity: Data error such as data parity or data ECC error |
| 309 | # CXL.cache |
| 310 | # |
| 311 | # @cache-address-parity: Address parity or other errors associated |
| 312 | # with the address field on CXL.cache |
| 313 | # |
| 314 | # @cache-be-parity: Byte enable parity or other byte enable errors on |
| 315 | # CXL.cache |
| 316 | # |
| 317 | # @cache-data-ecc: ECC error on CXL.cache |
| 318 | # |
| 319 | # @mem-data-parity: Data error such as data parity or data ECC error |
| 320 | # on CXL.mem |
| 321 | # |
| 322 | # @mem-address-parity: Address parity or other errors associated with |
| 323 | # the address field on CXL.mem |
| 324 | # |
| 325 | # @mem-be-parity: Byte enable parity or other byte enable errors on |
| 326 | # CXL.mem. |
| 327 | # |
| 328 | # @mem-data-ecc: Data ECC error on CXL.mem. |
| 329 | # |
| 330 | # @reinit-threshold: REINIT threshold hit. |
| 331 | # |
| 332 | # @rsvd-encoding: Received unrecognized encoding. |
| 333 | # |
| 334 | # @poison-received: Received poison from the peer. |
| 335 | # |
| 336 | # @receiver-overflow: Buffer overflows (first 3 bits of header log |
| 337 | # indicate which) |
| 338 | # |
| 339 | # @internal: Component specific error |
| 340 | # |
| 341 | # @cxl-ide-tx: Integrity and data encryption tx error. |
| 342 | # |
| 343 | # @cxl-ide-rx: Integrity and data encryption rx error. |
| 344 | # |
| 345 | # Since: 8.0 |
| 346 | ## |
| 347 | { 'enum': 'CxlUncorErrorType', |
| 348 | 'data': ['cache-data-parity', |
| 349 | 'cache-address-parity', |
| 350 | 'cache-be-parity', |
| 351 | 'cache-data-ecc', |
| 352 | 'mem-data-parity', |
| 353 | 'mem-address-parity', |
| 354 | 'mem-be-parity', |
| 355 | 'mem-data-ecc', |
| 356 | 'reinit-threshold', |
| 357 | 'rsvd-encoding', |
| 358 | 'poison-received', |
| 359 | 'receiver-overflow', |
| 360 | 'internal', |
| 361 | 'cxl-ide-tx', |
| 362 | 'cxl-ide-rx' |
| 363 | ] |
| 364 | } |
| 365 | |
| 366 | ## |
| 367 | # @CXLUncorErrorRecord: |
| 368 | # |
| 369 | # Record of a single error including header log. |
| 370 | # |
| 371 | # @type: Type of error |
| 372 | # |
| 373 | # @header: 16 DWORD of header. |
| 374 | # |
| 375 | # Since: 8.0 |
| 376 | ## |
| 377 | { 'struct': 'CXLUncorErrorRecord', |
| 378 | 'data': { |
| 379 | 'type': 'CxlUncorErrorType', |
| 380 | 'header': [ 'uint32' ] |
| 381 | } |
| 382 | } |
| 383 | |
| 384 | ## |
| 385 | # @cxl-inject-uncorrectable-errors: |
| 386 | # |
| 387 | # Command to allow injection of multiple errors in one go. This |
| 388 | # allows testing of multiple header log handling in the OS. |
| 389 | # |
| 390 | # @path: CXL Type 3 device canonical QOM path |
| 391 | # |
| 392 | # @errors: Errors to inject |
| 393 | # |
| 394 | # Since: 8.0 |
| 395 | ## |
| 396 | { 'command': 'cxl-inject-uncorrectable-errors', |
| 397 | 'data': { 'path': 'str', |
| 398 | 'errors': [ 'CXLUncorErrorRecord' ] }} |
| 399 | |
| 400 | ## |
| 401 | # @CxlCorErrorType: |
| 402 | # |
| 403 | # Type of CXL correctable error to inject |
| 404 | # |
| 405 | # @cache-data-ecc: Data ECC error on CXL.cache |
| 406 | # |
| 407 | # @mem-data-ecc: Data ECC error on CXL.mem |
| 408 | # |
| 409 | # @crc-threshold: Component specific and applicable to 68 byte Flit |
| 410 | # mode only. |
| 411 | # |
| 412 | # @retry-threshold: Retry threshold hit in the Local Retry State |
| 413 | # Machine, 68B Flits only. |
| 414 | # |
| 415 | # @cache-poison-received: Received poison from a peer on CXL.cache. |
| 416 | # |
| 417 | # @mem-poison-received: Received poison from a peer on CXL.mem |
| 418 | # |
| 419 | # @physical: Received error indication from the physical layer. |
| 420 | # |
| 421 | # Since: 8.0 |
| 422 | ## |
| 423 | { 'enum': 'CxlCorErrorType', |
| 424 | 'data': ['cache-data-ecc', |
| 425 | 'mem-data-ecc', |
| 426 | 'crc-threshold', |
| 427 | 'retry-threshold', |
| 428 | 'cache-poison-received', |
| 429 | 'mem-poison-received', |
| 430 | 'physical'] |
| 431 | } |
| 432 | |
| 433 | ## |
| 434 | # @cxl-inject-correctable-error: |
| 435 | # |
| 436 | # Command to inject a single correctable error. Multiple error |
| 437 | # injection of this error type is not interesting as there is no |
| 438 | # associated header log. These errors are reported via AER as a |
| 439 | # correctable internal error, with additional detail available from |
| 440 | # the CXL device. |
| 441 | # |
| 442 | # @path: CXL Type 3 device canonical QOM path |
| 443 | # |
| 444 | # @type: Type of error. |
| 445 | # |
| 446 | # Since: 8.0 |
| 447 | ## |
| 448 | {'command': 'cxl-inject-correctable-error', |
| 449 | 'data': {'path': 'str', 'type': 'CxlCorErrorType'}} |
| 450 | |
| 451 | ## |
| 452 | # @CxlDynamicCapacityExtent: |
| 453 | # |
| 454 | # A single dynamic capacity extent. This is a contiguous allocation |
| 455 | # of memory by Device Physical Address within a single Dynamic |
| 456 | # Capacity Region on a CXL Type 3 Device. |
| 457 | # |
| 458 | # @offset: The offset (in bytes) to the start of the region where the |
| 459 | # extent belongs to. |
| 460 | # |
| 461 | # @len: The length of the extent in bytes. |
| 462 | # |
| 463 | # Since: 9.1 |
| 464 | ## |
| 465 | { 'struct': 'CxlDynamicCapacityExtent', |
| 466 | 'data': { |
| 467 | 'offset':'uint64', |
| 468 | 'len': 'uint64' |
| 469 | } |
| 470 | } |
| 471 | |
| 472 | ## |
| 473 | # @CxlExtentSelectionPolicy: |
| 474 | # |
| 475 | # The policy to use for selecting which extents comprise the added |
| 476 | # capacity, as defined in Compute Express Link (CXL) Specification, |
| 477 | # Revision 3.1, Table 7-70. |
| 478 | # |
| 479 | # @free: Device is responsible for allocating the requested memory |
| 480 | # capacity and is free to do this using any combination of |
| 481 | # supported extents. |
| 482 | # |
| 483 | # @contiguous: Device is responsible for allocating the requested |
| 484 | # memory capacity but must do so as a single contiguous |
| 485 | # extent. |
| 486 | # |
| 487 | # @prescriptive: The precise set of extents to be allocated is |
| 488 | # specified by the command. Thus allocation is being managed |
| 489 | # by the issuer of the allocation command, not the device. |
| 490 | # |
| 491 | # @enable-shared-access: Capacity has already been allocated to a |
| 492 | # different host using free, contiguous or prescriptive policy |
| 493 | # with a known tag. This policy then instructs the device to make |
| 494 | # the capacity with the specified tag available to an additional |
| 495 | # host. Capacity is implicit as it matches that already |
| 496 | # associated with the tag. Note that the extent list (and hence |
| 497 | # Device Physical Addresses) used are per host, so a device may |
| 498 | # use different representations on each host. The ordering of the |
| 499 | # extents provided to each host is indicated to the host using per |
| 500 | # extent sequence numbers generated by the device. Has a similar |
| 501 | # meaning for temporal sharing, but in that case there may be only |
| 502 | # one host involved. |
| 503 | # |
| 504 | # Since: 9.1 |
| 505 | ## |
| 506 | { 'enum': 'CxlExtentSelectionPolicy', |
| 507 | 'data': ['free', |
| 508 | 'contiguous', |
| 509 | 'prescriptive', |
| 510 | 'enable-shared-access'] |
| 511 | } |
| 512 | |
| 513 | ## |
| 514 | # @cxl-add-dynamic-capacity: |
| 515 | # |
| 516 | # Initiate adding dynamic capacity extents to a host. This simulates |
| 517 | # operations defined in Compute Express Link (CXL) Specification, |
| 518 | # Revision 3.1, Section 7.6.7.6.5. Note that, currently, establishing |
| 519 | # success or failure of the full Add Dynamic Capacity flow requires |
| 520 | # out of band communication with the OS of the CXL host. |
| 521 | # |
| 522 | # @path: path to the CXL Dynamic Capacity Device in the QOM tree. |
| 523 | # |
| 524 | # @host-id: The "Host ID" field as defined in Compute Express Link |
| 525 | # (CXL) Specification, Revision 3.1, Table 7-70. |
| 526 | # |
| 527 | # @selection-policy: The "Selection Policy" bits as defined in |
| 528 | # Compute Express Link (CXL) Specification, Revision 3.1, |
| 529 | # Table 7-70. It specifies the policy to use for selecting |
| 530 | # which extents comprise the added capacity. |
| 531 | # |
| 532 | # @region: The "Region Number" field as defined in Compute Express |
| 533 | # Link (CXL) Specification, Revision 3.1, Table 7-70. Valid |
| 534 | # range is from 0-7. |
| 535 | # |
| 536 | # @tag: The "Tag" field as defined in Compute Express Link (CXL) |
| 537 | # Specification, Revision 3.1, Table 7-70. |
| 538 | # |
| 539 | # @extents: The "Extent List" field as defined in Compute Express Link |
| 540 | # (CXL) Specification, Revision 3.1, Table 7-70. |
| 541 | # |
| 542 | # Features: |
| 543 | # |
| 544 | # @unstable: For now this command is subject to change. |
| 545 | # |
| 546 | # Since: 9.1 |
| 547 | ## |
| 548 | { 'command': 'cxl-add-dynamic-capacity', |
| 549 | 'data': { 'path': 'str', |
| 550 | 'host-id': 'uint16', |
| 551 | 'selection-policy': 'CxlExtentSelectionPolicy', |
| 552 | 'region': 'uint8', |
| 553 | '*tag': 'str', |
| 554 | 'extents': [ 'CxlDynamicCapacityExtent' ] |
| 555 | }, |
| 556 | 'features': [ 'unstable' ] |
| 557 | } |
| 558 | |
| 559 | ## |
| 560 | # @CxlExtentRemovalPolicy: |
| 561 | # |
| 562 | # The policy to use for selecting which extents comprise the released |
| 563 | # capacity, defined in the "Flags" field in Compute Express Link (CXL) |
| 564 | # Specification, Revision 3.1, Table 7-71. |
| 565 | # |
| 566 | # @tag-based: Extents are selected by the device based on tag, with |
| 567 | # no requirement for contiguous extents. |
| 568 | # |
| 569 | # @prescriptive: Extent list of capacity to release is included in |
| 570 | # the request payload. |
| 571 | # |
| 572 | # Since: 9.1 |
| 573 | ## |
| 574 | { 'enum': 'CxlExtentRemovalPolicy', |
| 575 | 'data': ['tag-based', |
| 576 | 'prescriptive'] |
| 577 | } |
| 578 | |
| 579 | ## |
| 580 | # @cxl-release-dynamic-capacity: |
| 581 | # |
| 582 | # Initiate release of dynamic capacity extents from a host. This |
| 583 | # simulates operations defined in Compute Express Link (CXL) |
| 584 | # Specification, Revision 3.1, Section 7.6.7.6.6. Note that, |
| 585 | # currently, success or failure of the full Release Dynamic Capacity |
| 586 | # flow requires out of band communication with the OS of the CXL host. |
| 587 | # |
| 588 | # @path: path to the CXL Dynamic Capacity Device in the QOM tree. |
| 589 | # |
| 590 | # @host-id: The "Host ID" field as defined in Compute Express Link |
| 591 | # (CXL) Specification, Revision 3.1, Table 7-71. |
| 592 | # |
| 593 | # @removal-policy: Bit[3:0] of the "Flags" field as defined in |
| 594 | # Compute Express Link (CXL) Specification, Revision 3.1, |
| 595 | # Table 7-71. |
| 596 | # |
| 597 | # @forced-removal: Bit[4] of the "Flags" field in Compute Express |
| 598 | # Link (CXL) Specification, Revision 3.1, Table 7-71. When set, |
| 599 | # the device does not wait for a Release Dynamic Capacity command |
| 600 | # from the host. Instead, the host immediately looses access to |
| 601 | # the released capacity. |
| 602 | # |
| 603 | # @sanitize-on-release: Bit[5] of the "Flags" field in Compute Express |
| 604 | # Link (CXL) Specification, Revision 3.1, Table 7-71. When set, |
| 605 | # the device should sanitize all released capacity as a result of |
| 606 | # this request. This ensures that all user data and metadata is |
| 607 | # made permanently unavailable by whatever means is appropriate |
| 608 | # for the media type. Note that changing encryption keys is not |
| 609 | # sufficient. |
| 610 | # |
| 611 | # @region: The "Region Number" field as defined in Compute Express |
| 612 | # Link Specification, Revision 3.1, Table 7-71. Valid range |
| 613 | # is from 0-7. |
| 614 | # |
| 615 | # @tag: The "Tag" field as defined in Compute Express Link (CXL) |
| 616 | # Specification, Revision 3.1, Table 7-71. |
| 617 | # |
| 618 | # @extents: The "Extent List" field as defined in Compute Express |
| 619 | # Link (CXL) Specification, Revision 3.1, Table 7-71. |
| 620 | # |
| 621 | # Features: |
| 622 | # |
| 623 | # @unstable: For now this command is subject to change. |
| 624 | # |
| 625 | # Since: 9.1 |
| 626 | ## |
| 627 | { 'command': 'cxl-release-dynamic-capacity', |
| 628 | 'data': { 'path': 'str', |
| 629 | 'host-id': 'uint16', |
| 630 | 'removal-policy': 'CxlExtentRemovalPolicy', |
| 631 | '*forced-removal': 'bool', |
| 632 | '*sanitize-on-release': 'bool', |
| 633 | 'region': 'uint8', |
| 634 | '*tag': 'str', |
| 635 | 'extents': [ 'CxlDynamicCapacityExtent' ] |
| 636 | }, |
| 637 | 'features': [ 'unstable' ] |
| 638 | } |