| 1 | /* |
| 2 | * QEMU Alpha CPU |
| 3 | * |
| 4 | * Copyright (c) 2007 Jocelyn Mayer |
| 5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2.1 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, see |
| 19 | * <http://www.gnu.org/licenses/lgpl-2.1.html> |
| 20 | */ |
| 21 | |
| 22 | #include "qemu/osdep.h" |
| 23 | #include "qapi/error.h" |
| 24 | #include "qemu/qemu-print.h" |
| 25 | #include "cpu.h" |
| 26 | #include "exec/translation-block.h" |
| 27 | #include "exec/target_page.h" |
| 28 | #include "accel/tcg/cpu-ops.h" |
| 29 | #include "fpu/softfloat.h" |
| 30 | |
| 31 | |
| 32 | static void alpha_cpu_set_pc(CPUState *cs, vaddr value) |
| 33 | { |
| 34 | CPUAlphaState *env = cpu_env(cs); |
| 35 | env->pc = value; |
| 36 | } |
| 37 | |
| 38 | static vaddr alpha_cpu_get_pc(CPUState *cs) |
| 39 | { |
| 40 | CPUAlphaState *env = cpu_env(cs); |
| 41 | return env->pc; |
| 42 | } |
| 43 | |
| 44 | static TCGTBCPUState alpha_get_tb_cpu_state(CPUState *cs) |
| 45 | { |
| 46 | CPUAlphaState *env = cpu_env(cs); |
| 47 | uint32_t flags = env->flags & ENV_FLAG_TB_MASK; |
| 48 | |
| 49 | #ifdef CONFIG_USER_ONLY |
| 50 | flags |= TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus; |
| 51 | #endif |
| 52 | |
| 53 | return (TCGTBCPUState){ .pc = env->pc, .flags = flags }; |
| 54 | } |
| 55 | |
| 56 | static void alpha_cpu_synchronize_from_tb(CPUState *cs, |
| 57 | const TranslationBlock *tb) |
| 58 | { |
| 59 | /* The program counter is always up to date with CF_PCREL. */ |
| 60 | if (!(tb_cflags(tb) & CF_PCREL)) { |
| 61 | CPUAlphaState *env = cpu_env(cs); |
| 62 | env->pc = tb->pc; |
| 63 | } |
| 64 | } |
| 65 | |
| 66 | static void alpha_restore_state_to_opc(CPUState *cs, |
| 67 | const TranslationBlock *tb, |
| 68 | const uint64_t *data) |
| 69 | { |
| 70 | CPUAlphaState *env = cpu_env(cs); |
| 71 | |
| 72 | if (tb_cflags(tb) & CF_PCREL) { |
| 73 | env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; |
| 74 | } else { |
| 75 | env->pc = data[0]; |
| 76 | } |
| 77 | } |
| 78 | |
| 79 | #ifndef CONFIG_USER_ONLY |
| 80 | static bool alpha_cpu_has_work(CPUState *cs) |
| 81 | { |
| 82 | /* Here we are checking to see if the CPU should wake up from HALT. |
| 83 | We will have gotten into this state only for WTINT from PALmode. */ |
| 84 | /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU |
| 85 | asleep even if (some) interrupts have been asserted. For now, |
| 86 | assume that if a CPU really wants to stay asleep, it will mask |
| 87 | interrupts at the chipset level, which will prevent these bits |
| 88 | from being set in the first place. */ |
| 89 | return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD |
| 90 | | CPU_INTERRUPT_TIMER |
| 91 | | CPU_INTERRUPT_SMP |
| 92 | | CPU_INTERRUPT_MCHK); |
| 93 | } |
| 94 | #endif /* !CONFIG_USER_ONLY */ |
| 95 | |
| 96 | static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch) |
| 97 | { |
| 98 | return alpha_env_mmu_index(cpu_env(cs)); |
| 99 | } |
| 100 | |
| 101 | static void alpha_cpu_disas_set_info(const CPUState *cpu, |
| 102 | disassemble_info *info) |
| 103 | { |
| 104 | info->endian = BFD_ENDIAN_LITTLE; |
| 105 | info->mach = bfd_mach_alpha_ev6; |
| 106 | info->print_insn = print_insn_alpha; |
| 107 | } |
| 108 | |
| 109 | static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) |
| 110 | { |
| 111 | CPUState *cs = CPU(dev); |
| 112 | AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev); |
| 113 | Error *local_err = NULL; |
| 114 | |
| 115 | #ifndef CONFIG_USER_ONLY |
| 116 | /* Use pc-relative instructions in system-mode */ |
| 117 | cs->tcg_cflags |= CF_PCREL; |
| 118 | #endif |
| 119 | |
| 120 | cpu_common_realize(cs, &local_err); |
| 121 | if (local_err != NULL) { |
| 122 | error_propagate(errp, local_err); |
| 123 | return; |
| 124 | } |
| 125 | |
| 126 | qemu_init_vcpu(cs); |
| 127 | cpu_reset(cs); |
| 128 | |
| 129 | acc->parent_realize(dev, errp); |
| 130 | } |
| 131 | |
| 132 | /* Models */ |
| 133 | typedef struct AlphaCPUAlias { |
| 134 | const char *alias; |
| 135 | const char *typename; |
| 136 | } AlphaCPUAlias; |
| 137 | |
| 138 | static const AlphaCPUAlias alpha_cpu_aliases[] = { |
| 139 | { "21064", ALPHA_CPU_TYPE_NAME("ev4") }, |
| 140 | { "21164", ALPHA_CPU_TYPE_NAME("ev5") }, |
| 141 | { "21164a", ALPHA_CPU_TYPE_NAME("ev56") }, |
| 142 | { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") }, |
| 143 | { "21264", ALPHA_CPU_TYPE_NAME("ev6") }, |
| 144 | { "21264a", ALPHA_CPU_TYPE_NAME("ev67") }, |
| 145 | }; |
| 146 | |
| 147 | static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) |
| 148 | { |
| 149 | ObjectClass *oc; |
| 150 | char *typename; |
| 151 | int i; |
| 152 | |
| 153 | oc = object_class_by_name(cpu_model); |
| 154 | if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL) { |
| 155 | return oc; |
| 156 | } |
| 157 | |
| 158 | for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) { |
| 159 | if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) { |
| 160 | oc = object_class_by_name(alpha_cpu_aliases[i].typename); |
| 161 | assert(oc != NULL && !object_class_is_abstract(oc)); |
| 162 | return oc; |
| 163 | } |
| 164 | } |
| 165 | |
| 166 | typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model); |
| 167 | oc = object_class_by_name(typename); |
| 168 | g_free(typename); |
| 169 | |
| 170 | return oc; |
| 171 | } |
| 172 | |
| 173 | static void ev4_cpu_initfn(Object *obj) |
| 174 | { |
| 175 | cpu_env(CPU(obj))->implver = IMPLVER_2106x; |
| 176 | } |
| 177 | |
| 178 | static void ev5_cpu_initfn(Object *obj) |
| 179 | { |
| 180 | cpu_env(CPU(obj))->implver = IMPLVER_21164; |
| 181 | } |
| 182 | |
| 183 | static void ev56_cpu_initfn(Object *obj) |
| 184 | { |
| 185 | cpu_env(CPU(obj))->amask |= AMASK_BWX; |
| 186 | } |
| 187 | |
| 188 | static void pca56_cpu_initfn(Object *obj) |
| 189 | { |
| 190 | cpu_env(CPU(obj))->amask |= AMASK_MVI; |
| 191 | } |
| 192 | |
| 193 | static void ev6_cpu_initfn(Object *obj) |
| 194 | { |
| 195 | CPUAlphaState *env = cpu_env(CPU(obj)); |
| 196 | |
| 197 | env->implver = IMPLVER_21264; |
| 198 | env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; |
| 199 | } |
| 200 | |
| 201 | static void ev67_cpu_initfn(Object *obj) |
| 202 | { |
| 203 | cpu_env(CPU(obj))->amask |= AMASK_CIX | AMASK_PREFETCH; |
| 204 | } |
| 205 | |
| 206 | static void alpha_cpu_initfn(Object *obj) |
| 207 | { |
| 208 | CPUAlphaState *env = cpu_env(CPU(obj)); |
| 209 | |
| 210 | /* TODO all this should be done in reset, not init */ |
| 211 | |
| 212 | env->lock_addr = -1; |
| 213 | |
| 214 | /* |
| 215 | * TODO: this is incorrect. The Alpha Architecture Handbook version 4 |
| 216 | * describes NaN propagation in section 4.7.10.4. We should prefer |
| 217 | * the operand in Fb (whether it is a QNaN or an SNaN), then the |
| 218 | * operand in Fa. That is float_2nan_prop_ba. |
| 219 | */ |
| 220 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); |
| 221 | /* Default NaN: sign bit clear, msb frac bit set */ |
| 222 | set_float_default_nan_pattern(0b01000000, &env->fp_status); |
| 223 | /* |
| 224 | * TODO: this is incorrect. The Alpha Architecture Handbook version 4 |
| 225 | * section 4.7.7.11 says that we flush to zero for underflow cases, so |
| 226 | * this should be float_ftz_after_rounding to match the |
| 227 | * tininess_after_rounding (which is specified in section 4.7.5). |
| 228 | */ |
| 229 | set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status); |
| 230 | #if defined(CONFIG_USER_ONLY) |
| 231 | env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; |
| 232 | cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD |
| 233 | | FPCR_UNFD | FPCR_INED | FPCR_DNOD |
| 234 | | FPCR_DYN_NORMAL) << 32); |
| 235 | #else |
| 236 | env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN; |
| 237 | #endif |
| 238 | } |
| 239 | |
| 240 | #ifndef CONFIG_USER_ONLY |
| 241 | #include "hw/core/sysemu-cpu-ops.h" |
| 242 | |
| 243 | static const struct SysemuCPUOps alpha_sysemu_ops = { |
| 244 | .has_work = alpha_cpu_has_work, |
| 245 | .get_phys_addr_debug = alpha_cpu_get_phys_addr_debug, |
| 246 | }; |
| 247 | #endif |
| 248 | |
| 249 | static const TCGCPUOps alpha_tcg_ops = { |
| 250 | /* Alpha processors have a weak memory model */ |
| 251 | .guest_default_memory_order = 0, |
| 252 | .mttcg_supported = true, |
| 253 | |
| 254 | .initialize = alpha_translate_init, |
| 255 | .translate_code = alpha_translate_code, |
| 256 | .get_tb_cpu_state = alpha_get_tb_cpu_state, |
| 257 | .synchronize_from_tb = alpha_cpu_synchronize_from_tb, |
| 258 | .restore_state_to_opc = alpha_restore_state_to_opc, |
| 259 | .mmu_index = alpha_cpu_mmu_index, |
| 260 | |
| 261 | #ifdef CONFIG_USER_ONLY |
| 262 | .record_sigsegv = alpha_cpu_record_sigsegv, |
| 263 | .record_sigbus = alpha_cpu_record_sigbus, |
| 264 | #else |
| 265 | .tlb_fill = alpha_cpu_tlb_fill, |
| 266 | .pointer_wrap = cpu_pointer_wrap_notreached, |
| 267 | .cpu_exec_interrupt = alpha_cpu_exec_interrupt, |
| 268 | .cpu_exec_halt = alpha_cpu_has_work, |
| 269 | .cpu_exec_reset = cpu_reset, |
| 270 | .do_interrupt = alpha_cpu_do_interrupt, |
| 271 | .do_transaction_failed = alpha_cpu_do_transaction_failed, |
| 272 | .do_unaligned_access = alpha_cpu_do_unaligned_access, |
| 273 | #endif /* !CONFIG_USER_ONLY */ |
| 274 | }; |
| 275 | |
| 276 | static void alpha_cpu_class_init(ObjectClass *oc, const void *data) |
| 277 | { |
| 278 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 279 | CPUClass *cc = CPU_CLASS(oc); |
| 280 | AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc); |
| 281 | |
| 282 | device_class_set_parent_realize(dc, alpha_cpu_realizefn, |
| 283 | &acc->parent_realize); |
| 284 | |
| 285 | cc->class_by_name = alpha_cpu_class_by_name; |
| 286 | cc->dump_state = alpha_cpu_dump_state; |
| 287 | cc->set_pc = alpha_cpu_set_pc; |
| 288 | cc->get_pc = alpha_cpu_get_pc; |
| 289 | cc->gdb_read_register = alpha_cpu_gdb_read_register; |
| 290 | cc->gdb_write_register = alpha_cpu_gdb_write_register; |
| 291 | cc->gdb_core_xml_file = "alpha-core.xml"; |
| 292 | #ifndef CONFIG_USER_ONLY |
| 293 | dc->vmsd = &vmstate_alpha_cpu; |
| 294 | cc->sysemu_ops = &alpha_sysemu_ops; |
| 295 | #endif |
| 296 | cc->disas_set_info = alpha_cpu_disas_set_info; |
| 297 | |
| 298 | cc->tcg_ops = &alpha_tcg_ops; |
| 299 | } |
| 300 | |
| 301 | #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \ |
| 302 | { \ |
| 303 | .parent = base_type, \ |
| 304 | .instance_init = initfn, \ |
| 305 | .name = ALPHA_CPU_TYPE_NAME(cpu_model), \ |
| 306 | } |
| 307 | |
| 308 | static const TypeInfo alpha_cpu_type_infos[] = { |
| 309 | { |
| 310 | .name = TYPE_ALPHA_CPU, |
| 311 | .parent = TYPE_CPU, |
| 312 | .instance_size = sizeof(AlphaCPU), |
| 313 | .instance_align = __alignof(AlphaCPU), |
| 314 | .instance_init = alpha_cpu_initfn, |
| 315 | .abstract = true, |
| 316 | .class_size = sizeof(AlphaCPUClass), |
| 317 | .class_init = alpha_cpu_class_init, |
| 318 | }, |
| 319 | DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev4", ev4_cpu_initfn), |
| 320 | DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev5", ev5_cpu_initfn), |
| 321 | DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn), |
| 322 | DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56", |
| 323 | pca56_cpu_initfn), |
| 324 | DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev6", ev6_cpu_initfn), |
| 325 | DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn), |
| 326 | DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL), |
| 327 | }; |
| 328 | |
| 329 | DEFINE_TYPES(alpha_cpu_type_infos) |