| 1 | /* |
| 2 | * Alpha emulation cpu definitions for qemu. |
| 3 | * |
| 4 | * Copyright (c) 2007 Jocelyn Mayer |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef ALPHA_CPU_H |
| 21 | #define ALPHA_CPU_H |
| 22 | |
| 23 | #include "cpu-qom.h" |
| 24 | #include "exec/cpu-common.h" |
| 25 | #include "exec/cpu-interrupt.h" |
| 26 | #include "qemu/cpu-float.h" |
| 27 | |
| 28 | #define ICACHE_LINE_SIZE 32 |
| 29 | #define DCACHE_LINE_SIZE 32 |
| 30 | |
| 31 | /* Alpha major type */ |
| 32 | enum { |
| 33 | ALPHA_EV3 = 1, |
| 34 | ALPHA_EV4 = 2, |
| 35 | ALPHA_SIM = 3, |
| 36 | ALPHA_LCA = 4, |
| 37 | ALPHA_EV5 = 5, /* 21164 */ |
| 38 | ALPHA_EV45 = 6, /* 21064A */ |
| 39 | ALPHA_EV56 = 7, /* 21164A */ |
| 40 | }; |
| 41 | |
| 42 | /* EV4 minor type */ |
| 43 | enum { |
| 44 | ALPHA_EV4_2 = 0, |
| 45 | ALPHA_EV4_3 = 1, |
| 46 | }; |
| 47 | |
| 48 | /* LCA minor type */ |
| 49 | enum { |
| 50 | ALPHA_LCA_1 = 1, /* 21066 */ |
| 51 | ALPHA_LCA_2 = 2, /* 20166 */ |
| 52 | ALPHA_LCA_3 = 3, /* 21068 */ |
| 53 | ALPHA_LCA_4 = 4, /* 21068 */ |
| 54 | ALPHA_LCA_5 = 5, /* 21066A */ |
| 55 | ALPHA_LCA_6 = 6, /* 21068A */ |
| 56 | }; |
| 57 | |
| 58 | /* EV5 minor type */ |
| 59 | enum { |
| 60 | ALPHA_EV5_1 = 1, /* Rev BA, CA */ |
| 61 | ALPHA_EV5_2 = 2, /* Rev DA, EA */ |
| 62 | ALPHA_EV5_3 = 3, /* Pass 3 */ |
| 63 | ALPHA_EV5_4 = 4, /* Pass 3.2 */ |
| 64 | ALPHA_EV5_5 = 5, /* Pass 4 */ |
| 65 | }; |
| 66 | |
| 67 | /* EV45 minor type */ |
| 68 | enum { |
| 69 | ALPHA_EV45_1 = 1, /* Pass 1 */ |
| 70 | ALPHA_EV45_2 = 2, /* Pass 1.1 */ |
| 71 | ALPHA_EV45_3 = 3, /* Pass 2 */ |
| 72 | }; |
| 73 | |
| 74 | /* EV56 minor type */ |
| 75 | enum { |
| 76 | ALPHA_EV56_1 = 1, /* Pass 1 */ |
| 77 | ALPHA_EV56_2 = 2, /* Pass 2 */ |
| 78 | }; |
| 79 | |
| 80 | enum { |
| 81 | IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */ |
| 82 | IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */ |
| 83 | IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */ |
| 84 | IMPLVER_21364 = 3, /* EV7 & EV79 */ |
| 85 | }; |
| 86 | |
| 87 | enum { |
| 88 | AMASK_BWX = 0x00000001, |
| 89 | AMASK_FIX = 0x00000002, |
| 90 | AMASK_CIX = 0x00000004, |
| 91 | AMASK_MVI = 0x00000100, |
| 92 | AMASK_TRAP = 0x00000200, |
| 93 | AMASK_PREFETCH = 0x00001000, |
| 94 | }; |
| 95 | |
| 96 | enum { |
| 97 | VAX_ROUND_NORMAL = 0, |
| 98 | VAX_ROUND_CHOPPED, |
| 99 | }; |
| 100 | |
| 101 | enum { |
| 102 | IEEE_ROUND_NORMAL = 0, |
| 103 | IEEE_ROUND_DYNAMIC, |
| 104 | IEEE_ROUND_PLUS, |
| 105 | IEEE_ROUND_MINUS, |
| 106 | IEEE_ROUND_CHOPPED, |
| 107 | }; |
| 108 | |
| 109 | /* IEEE floating-point operations encoding */ |
| 110 | /* Trap mode */ |
| 111 | enum { |
| 112 | FP_TRAP_I = 0x0, |
| 113 | FP_TRAP_U = 0x1, |
| 114 | FP_TRAP_S = 0x4, |
| 115 | FP_TRAP_SU = 0x5, |
| 116 | FP_TRAP_SUI = 0x7, |
| 117 | }; |
| 118 | |
| 119 | /* Rounding mode */ |
| 120 | enum { |
| 121 | FP_ROUND_CHOPPED = 0x0, |
| 122 | FP_ROUND_MINUS = 0x1, |
| 123 | FP_ROUND_NORMAL = 0x2, |
| 124 | FP_ROUND_DYNAMIC = 0x3, |
| 125 | }; |
| 126 | |
| 127 | /* FPCR bits -- right-shifted 32 so we can use a uint32_t. */ |
| 128 | #define FPCR_SUM (1U << (63 - 32)) |
| 129 | #define FPCR_INED (1U << (62 - 32)) |
| 130 | #define FPCR_UNFD (1U << (61 - 32)) |
| 131 | #define FPCR_UNDZ (1U << (60 - 32)) |
| 132 | #define FPCR_DYN_SHIFT (58 - 32) |
| 133 | #define FPCR_DYN_CHOPPED (0U << FPCR_DYN_SHIFT) |
| 134 | #define FPCR_DYN_MINUS (1U << FPCR_DYN_SHIFT) |
| 135 | #define FPCR_DYN_NORMAL (2U << FPCR_DYN_SHIFT) |
| 136 | #define FPCR_DYN_PLUS (3U << FPCR_DYN_SHIFT) |
| 137 | #define FPCR_DYN_MASK (3U << FPCR_DYN_SHIFT) |
| 138 | #define FPCR_IOV (1U << (57 - 32)) |
| 139 | #define FPCR_INE (1U << (56 - 32)) |
| 140 | #define FPCR_UNF (1U << (55 - 32)) |
| 141 | #define FPCR_OVF (1U << (54 - 32)) |
| 142 | #define FPCR_DZE (1U << (53 - 32)) |
| 143 | #define FPCR_INV (1U << (52 - 32)) |
| 144 | #define FPCR_OVFD (1U << (51 - 32)) |
| 145 | #define FPCR_DZED (1U << (50 - 32)) |
| 146 | #define FPCR_INVD (1U << (49 - 32)) |
| 147 | #define FPCR_DNZ (1U << (48 - 32)) |
| 148 | #define FPCR_DNOD (1U << (47 - 32)) |
| 149 | #define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \ |
| 150 | | FPCR_OVF | FPCR_DZE | FPCR_INV) |
| 151 | |
| 152 | /* The silly software trap enables implemented by the kernel emulation. |
| 153 | These are more or less architecturally required, since the real hardware |
| 154 | has read-as-zero bits in the FPCR when the features aren't implemented. |
| 155 | For the purposes of QEMU, we pretend the FPCR can hold everything. */ |
| 156 | #define SWCR_TRAP_ENABLE_INV (1U << 1) |
| 157 | #define SWCR_TRAP_ENABLE_DZE (1U << 2) |
| 158 | #define SWCR_TRAP_ENABLE_OVF (1U << 3) |
| 159 | #define SWCR_TRAP_ENABLE_UNF (1U << 4) |
| 160 | #define SWCR_TRAP_ENABLE_INE (1U << 5) |
| 161 | #define SWCR_TRAP_ENABLE_DNO (1U << 6) |
| 162 | #define SWCR_TRAP_ENABLE_MASK ((1U << 7) - (1U << 1)) |
| 163 | |
| 164 | #define SWCR_MAP_DMZ (1U << 12) |
| 165 | #define SWCR_MAP_UMZ (1U << 13) |
| 166 | #define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ) |
| 167 | |
| 168 | #define SWCR_STATUS_INV (1U << 17) |
| 169 | #define SWCR_STATUS_DZE (1U << 18) |
| 170 | #define SWCR_STATUS_OVF (1U << 19) |
| 171 | #define SWCR_STATUS_UNF (1U << 20) |
| 172 | #define SWCR_STATUS_INE (1U << 21) |
| 173 | #define SWCR_STATUS_DNO (1U << 22) |
| 174 | #define SWCR_STATUS_MASK ((1U << 23) - (1U << 17)) |
| 175 | |
| 176 | #define SWCR_STATUS_TO_EXCSUM_SHIFT 16 |
| 177 | |
| 178 | #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK) |
| 179 | |
| 180 | /* MMU modes definitions */ |
| 181 | |
| 182 | /* Alpha has 5 MMU modes: PALcode, Kernel, Executive, Supervisor, and User. |
| 183 | The Unix PALcode only exposes the kernel and user modes; presumably |
| 184 | executive and supervisor are used by VMS. |
| 185 | |
| 186 | PALcode itself uses physical mode for code and kernel mode for data; |
| 187 | there are PALmode instructions that can access data via physical mode |
| 188 | or via an os-installed "alternate mode", which is one of the 4 above. |
| 189 | |
| 190 | That said, we're only emulating Unix PALcode, and not attempting VMS, |
| 191 | so we don't need to implement Executive and Supervisor. QEMU's own |
| 192 | PALcode cheats and uses the KSEG mapping for its code+data rather than |
| 193 | physical addresses. */ |
| 194 | |
| 195 | #define MMU_KERNEL_IDX 0 |
| 196 | #define MMU_USER_IDX 1 |
| 197 | #define MMU_PHYS_IDX 2 |
| 198 | |
| 199 | typedef struct CPUArchState { |
| 200 | uint64_t ir[31]; |
| 201 | float64 fir[31]; |
| 202 | uint64_t pc; |
| 203 | uint64_t unique; |
| 204 | uint64_t lock_addr; |
| 205 | uint64_t lock_value; |
| 206 | |
| 207 | /* The FPCR, and disassembled portions thereof. */ |
| 208 | uint32_t fpcr; |
| 209 | #ifdef CONFIG_USER_ONLY |
| 210 | uint32_t swcr; |
| 211 | #endif |
| 212 | uint32_t fpcr_exc_enable; |
| 213 | float_status fp_status; |
| 214 | uint8_t fpcr_dyn_round; |
| 215 | uint8_t fpcr_flush_to_zero; |
| 216 | |
| 217 | /* Mask of PALmode, Processor State et al. Most of this gets copied |
| 218 | into the TranslatorBlock flags and controls code generation. */ |
| 219 | uint32_t flags; |
| 220 | |
| 221 | /* The high 32-bits of the processor cycle counter. */ |
| 222 | uint32_t pcc_ofs; |
| 223 | |
| 224 | /* These pass data from the exception logic in the translator and |
| 225 | helpers to the OS entry point. This is used for both system |
| 226 | emulation and user-mode. */ |
| 227 | uint64_t trap_arg0; |
| 228 | uint64_t trap_arg1; |
| 229 | uint64_t trap_arg2; |
| 230 | |
| 231 | #if !defined(CONFIG_USER_ONLY) |
| 232 | /* The internal data required by our emulation of the Unix PALcode. */ |
| 233 | uint64_t exc_addr; |
| 234 | uint64_t palbr; |
| 235 | uint64_t ptbr; |
| 236 | uint64_t vptptr; |
| 237 | uint64_t sysval; |
| 238 | uint64_t usp; |
| 239 | uint64_t shadow[8]; |
| 240 | uint64_t scratch[24]; |
| 241 | #endif |
| 242 | |
| 243 | /* This alarm doesn't exist in real hardware; we wish it did. */ |
| 244 | uint64_t alarm_expire; |
| 245 | |
| 246 | int error_code; |
| 247 | |
| 248 | uint32_t features; |
| 249 | uint32_t amask; |
| 250 | int implver; |
| 251 | } CPUAlphaState; |
| 252 | |
| 253 | /** |
| 254 | * AlphaCPU: |
| 255 | * @env: #CPUAlphaState |
| 256 | * |
| 257 | * An Alpha CPU. |
| 258 | */ |
| 259 | struct ArchCPU { |
| 260 | CPUState parent_obj; |
| 261 | |
| 262 | CPUAlphaState env; |
| 263 | |
| 264 | /* This alarm doesn't exist in real hardware; we wish it did. */ |
| 265 | QEMUTimer *alarm_timer; |
| 266 | }; |
| 267 | |
| 268 | /** |
| 269 | * AlphaCPUClass: |
| 270 | * @parent_realize: The parent class' realize handler. |
| 271 | * |
| 272 | * An Alpha CPU model. |
| 273 | */ |
| 274 | struct AlphaCPUClass { |
| 275 | CPUClass parent_class; |
| 276 | |
| 277 | DeviceRealize parent_realize; |
| 278 | }; |
| 279 | |
| 280 | #ifndef CONFIG_USER_ONLY |
| 281 | extern const VMStateDescription vmstate_alpha_cpu; |
| 282 | |
| 283 | void alpha_cpu_do_interrupt(CPUState *cpu); |
| 284 | bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); |
| 285 | hwaddr alpha_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); |
| 286 | #endif /* !CONFIG_USER_ONLY */ |
| 287 | void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); |
| 288 | int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
| 289 | int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
| 290 | |
| 291 | enum { |
| 292 | FEATURE_ASN = 0x00000001, |
| 293 | FEATURE_SPS = 0x00000002, |
| 294 | FEATURE_VIRBND = 0x00000004, |
| 295 | FEATURE_TBCHK = 0x00000008, |
| 296 | }; |
| 297 | |
| 298 | enum { |
| 299 | EXCP_RESET, |
| 300 | EXCP_MCHK, |
| 301 | EXCP_SMP_INTERRUPT, |
| 302 | EXCP_CLK_INTERRUPT, |
| 303 | EXCP_DEV_INTERRUPT, |
| 304 | EXCP_MMFAULT, |
| 305 | EXCP_UNALIGN, |
| 306 | EXCP_OPCDEC, |
| 307 | EXCP_ARITH, |
| 308 | EXCP_FEN, |
| 309 | EXCP_CALL_PAL, |
| 310 | }; |
| 311 | |
| 312 | /* Alpha-specific interrupt pending bits. */ |
| 313 | #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0 |
| 314 | #define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1 |
| 315 | #define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2 |
| 316 | |
| 317 | /* OSF/1 Page table bits. */ |
| 318 | enum { |
| 319 | PTE_VALID = 0x0001, |
| 320 | PTE_FOR = 0x0002, /* used for page protection (fault on read) */ |
| 321 | PTE_FOW = 0x0004, /* used for page protection (fault on write) */ |
| 322 | PTE_FOE = 0x0008, /* used for page protection (fault on exec) */ |
| 323 | PTE_ASM = 0x0010, |
| 324 | PTE_KRE = 0x0100, |
| 325 | PTE_URE = 0x0200, |
| 326 | PTE_KWE = 0x1000, |
| 327 | PTE_UWE = 0x2000 |
| 328 | }; |
| 329 | |
| 330 | /* Hardware interrupt (entInt) constants. */ |
| 331 | enum { |
| 332 | INT_K_IP, |
| 333 | INT_K_CLK, |
| 334 | INT_K_MCHK, |
| 335 | INT_K_DEV, |
| 336 | INT_K_PERF, |
| 337 | }; |
| 338 | |
| 339 | /* Memory management (entMM) constants. */ |
| 340 | enum { |
| 341 | MM_K_TNV, |
| 342 | MM_K_ACV, |
| 343 | MM_K_FOR, |
| 344 | MM_K_FOE, |
| 345 | MM_K_FOW |
| 346 | }; |
| 347 | |
| 348 | /* Arithmetic exception (entArith) constants. */ |
| 349 | enum { |
| 350 | EXC_M_SWC = 1, /* Software completion */ |
| 351 | EXC_M_INV = 2, /* Invalid operation */ |
| 352 | EXC_M_DZE = 4, /* Division by zero */ |
| 353 | EXC_M_FOV = 8, /* Overflow */ |
| 354 | EXC_M_UNF = 16, /* Underflow */ |
| 355 | EXC_M_INE = 32, /* Inexact result */ |
| 356 | EXC_M_IOV = 64 /* Integer Overflow */ |
| 357 | }; |
| 358 | |
| 359 | /* Processor status constants. */ |
| 360 | /* Low 3 bits are interrupt mask level. */ |
| 361 | #define PS_INT_MASK 7u |
| 362 | |
| 363 | /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes; |
| 364 | The Unix PALcode only uses bit 4. */ |
| 365 | #define PS_USER_MODE 8u |
| 366 | |
| 367 | /* CPUAlphaState->flags constants. These are laid out so that we |
| 368 | can set or reset the pieces individually by assigning to the byte, |
| 369 | or manipulated as a whole. */ |
| 370 | |
| 371 | #define ENV_FLAG_PAL_SHIFT 0 |
| 372 | #define ENV_FLAG_PS_SHIFT 8 |
| 373 | #define ENV_FLAG_RX_SHIFT 16 |
| 374 | #define ENV_FLAG_FEN_SHIFT 24 |
| 375 | |
| 376 | #define ENV_FLAG_PAL_MODE (1u << ENV_FLAG_PAL_SHIFT) |
| 377 | #define ENV_FLAG_PS_USER (PS_USER_MODE << ENV_FLAG_PS_SHIFT) |
| 378 | #define ENV_FLAG_RX_FLAG (1u << ENV_FLAG_RX_SHIFT) |
| 379 | #define ENV_FLAG_FEN (1u << ENV_FLAG_FEN_SHIFT) |
| 380 | |
| 381 | #define ENV_FLAG_TB_MASK \ |
| 382 | (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) |
| 383 | |
| 384 | #define TB_FLAG_UNALIGN (1u << 1) |
| 385 | |
| 386 | static inline int alpha_env_mmu_index(CPUAlphaState *env) |
| 387 | { |
| 388 | int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; |
| 389 | if (env->flags & ENV_FLAG_PAL_MODE) { |
| 390 | ret = MMU_KERNEL_IDX; |
| 391 | } |
| 392 | return ret; |
| 393 | } |
| 394 | |
| 395 | enum { |
| 396 | IR_V0 = 0, |
| 397 | IR_T0 = 1, |
| 398 | IR_T1 = 2, |
| 399 | IR_T2 = 3, |
| 400 | IR_T3 = 4, |
| 401 | IR_T4 = 5, |
| 402 | IR_T5 = 6, |
| 403 | IR_T6 = 7, |
| 404 | IR_T7 = 8, |
| 405 | IR_S0 = 9, |
| 406 | IR_S1 = 10, |
| 407 | IR_S2 = 11, |
| 408 | IR_S3 = 12, |
| 409 | IR_S4 = 13, |
| 410 | IR_S5 = 14, |
| 411 | IR_S6 = 15, |
| 412 | IR_FP = IR_S6, |
| 413 | IR_A0 = 16, |
| 414 | IR_A1 = 17, |
| 415 | IR_A2 = 18, |
| 416 | IR_A3 = 19, |
| 417 | IR_A4 = 20, |
| 418 | IR_A5 = 21, |
| 419 | IR_T8 = 22, |
| 420 | IR_T9 = 23, |
| 421 | IR_T10 = 24, |
| 422 | IR_T11 = 25, |
| 423 | IR_RA = 26, |
| 424 | IR_T12 = 27, |
| 425 | IR_PV = IR_T12, |
| 426 | IR_AT = 28, |
| 427 | IR_GP = 29, |
| 428 | IR_SP = 30, |
| 429 | IR_ZERO = 31, |
| 430 | }; |
| 431 | |
| 432 | void alpha_translate_init(void); |
| 433 | void alpha_translate_code(CPUState *cs, TranslationBlock *tb, |
| 434 | int *max_insns, vaddr pc, void *host_pc); |
| 435 | |
| 436 | #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU |
| 437 | |
| 438 | G_NORETURN void dynamic_excp(CPUAlphaState *, uintptr_t, int, int); |
| 439 | G_NORETURN void arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); |
| 440 | |
| 441 | uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); |
| 442 | void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); |
| 443 | uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); |
| 444 | void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); |
| 445 | |
| 446 | #ifdef CONFIG_USER_ONLY |
| 447 | void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, |
| 448 | MMUAccessType access_type, |
| 449 | bool maperr, uintptr_t retaddr); |
| 450 | void alpha_cpu_record_sigbus(CPUState *cs, vaddr address, |
| 451 | MMUAccessType access_type, uintptr_t retaddr); |
| 452 | #else |
| 453 | bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 454 | MMUAccessType access_type, int mmu_idx, |
| 455 | bool probe, uintptr_t retaddr); |
| 456 | G_NORETURN void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, |
| 457 | MMUAccessType access_type, int mmu_idx, |
| 458 | uintptr_t retaddr); |
| 459 | void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
| 460 | vaddr addr, unsigned size, |
| 461 | MMUAccessType access_type, |
| 462 | int mmu_idx, MemTxAttrs attrs, |
| 463 | MemTxResult response, uintptr_t retaddr); |
| 464 | #endif |
| 465 | |
| 466 | #ifdef CONFIG_USER_ONLY |
| 467 | /* Copied from linux ieee_swcr_to_fpcr. */ |
| 468 | static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr) |
| 469 | { |
| 470 | uint64_t fpcr = 0; |
| 471 | |
| 472 | fpcr |= (swcr & SWCR_STATUS_MASK) << 35; |
| 473 | fpcr |= (swcr & SWCR_MAP_DMZ) << 36; |
| 474 | fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV |
| 475 | | SWCR_TRAP_ENABLE_DZE |
| 476 | | SWCR_TRAP_ENABLE_OVF)) << 48; |
| 477 | fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF |
| 478 | | SWCR_TRAP_ENABLE_INE)) << 57; |
| 479 | fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0); |
| 480 | fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41; |
| 481 | |
| 482 | return fpcr; |
| 483 | } |
| 484 | |
| 485 | /* Copied from linux ieee_fpcr_to_swcr. */ |
| 486 | static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr) |
| 487 | { |
| 488 | uint64_t swcr = 0; |
| 489 | |
| 490 | swcr |= (fpcr >> 35) & SWCR_STATUS_MASK; |
| 491 | swcr |= (fpcr >> 36) & SWCR_MAP_DMZ; |
| 492 | swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV |
| 493 | | SWCR_TRAP_ENABLE_DZE |
| 494 | | SWCR_TRAP_ENABLE_OVF); |
| 495 | swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF | SWCR_TRAP_ENABLE_INE); |
| 496 | swcr |= (fpcr >> 47) & SWCR_MAP_UMZ; |
| 497 | swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO; |
| 498 | |
| 499 | return swcr; |
| 500 | } |
| 501 | #endif /* CONFIG_USER_ONLY */ |
| 502 | |
| 503 | #endif /* ALPHA_CPU_H */ |