| 1 | /* |
| 2 | * QEMU ARM OMAP CP15 register definitions |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 5 | */ |
| 6 | |
| 7 | #include "qemu/osdep.h" |
| 8 | #include "target/arm/cpu.h" |
| 9 | #include "target/arm/cpregs.h" |
| 10 | #include "target/arm/internals.h" |
| 11 | |
| 12 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 13 | uint64_t value) |
| 14 | { |
| 15 | env->cp15.c15_ticonfig = value & 0xe7; |
| 16 | /* The OS_TYPE bit in this register changes the reported CPUID! */ |
| 17 | env->cp15.c0_cpuid = (value & (1 << 5)) ? |
| 18 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; |
| 19 | } |
| 20 | |
| 21 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 22 | uint64_t value) |
| 23 | { |
| 24 | env->cp15.c15_threadid = value & 0xffff; |
| 25 | } |
| 26 | |
| 27 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 28 | uint64_t value) |
| 29 | { |
| 30 | /* Wait-for-interrupt (deprecated) */ |
| 31 | cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); |
| 32 | } |
| 33 | |
| 34 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 35 | uint64_t value) |
| 36 | { |
| 37 | /* |
| 38 | * On OMAP there are registers indicating the max/min index of dcache lines |
| 39 | * containing a dirty line; cache flush operations have to reset these. |
| 40 | */ |
| 41 | env->cp15.c15_i_max = 0x000; |
| 42 | env->cp15.c15_i_min = 0xff0; |
| 43 | } |
| 44 | |
| 45 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
| 46 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, |
| 47 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, |
| 48 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
| 49 | .resetvalue = 0, }, |
| 50 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
| 51 | .access = PL1_RW, .type = ARM_CP_NOP }, |
| 52 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, |
| 53 | .access = PL1_RW, |
| 54 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, |
| 55 | .writefn = omap_ticonfig_write }, |
| 56 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, |
| 57 | .access = PL1_RW, |
| 58 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, |
| 59 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, |
| 60 | .access = PL1_RW, .resetvalue = 0xff0, |
| 61 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, |
| 62 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, |
| 63 | .access = PL1_RW, |
| 64 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, |
| 65 | .writefn = omap_threadid_write }, |
| 66 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, |
| 67 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, |
| 68 | .type = ARM_CP_NO_RAW, |
| 69 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
| 70 | /* |
| 71 | * TODO: Peripheral port remap register: |
| 72 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller |
| 73 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), |
| 74 | * when MMU is off. |
| 75 | */ |
| 76 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
| 77 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
| 78 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
| 79 | .writefn = omap_cachemaint_write }, |
| 80 | { .name = "C9", .cp = 15, .crn = 9, |
| 81 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, |
| 82 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, |
| 83 | }; |
| 84 | |
| 85 | void define_omap_cp_regs(ARMCPU *cpu) |
| 86 | { |
| 87 | define_arm_cp_regs(cpu, omap_cp_reginfo); |
| 88 | } |