| 1 | /* |
| 2 | * QEMU ARM CP Register PMU insns |
| 3 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 4 | */ |
| 5 | |
| 6 | #include "qemu/osdep.h" |
| 7 | #include "qemu/timer.h" |
| 8 | #include "exec/icount.h" |
| 9 | #include "hw/core/irq.h" |
| 10 | #include "cpu.h" |
| 11 | #include "cpu-features.h" |
| 12 | #include "cpregs.h" |
| 13 | #include "internals.h" |
| 14 | |
| 15 | |
| 16 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
| 17 | |
| 18 | /* |
| 19 | * Check for traps to performance monitor registers, which are controlled |
| 20 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. |
| 21 | */ |
| 22 | static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, |
| 23 | bool isread) |
| 24 | { |
| 25 | int el = arm_current_el(env); |
| 26 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
| 27 | |
| 28 | if (el < 2 && (mdcr_el2 & MDCR_TPM)) { |
| 29 | return CP_ACCESS_TRAP_EL2; |
| 30 | } |
| 31 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { |
| 32 | return CP_ACCESS_TRAP_EL3; |
| 33 | } |
| 34 | return CP_ACCESS_OK; |
| 35 | } |
| 36 | |
| 37 | typedef struct pm_event { |
| 38 | uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ |
| 39 | /* If the event is supported on this CPU (used to generate PMCEID[01]) */ |
| 40 | bool (*supported)(CPUARMState *); |
| 41 | /* |
| 42 | * Retrieve the current count of the underlying event. The programmed |
| 43 | * counters hold a difference from the return value from this function |
| 44 | */ |
| 45 | uint64_t (*get_count)(CPUARMState *); |
| 46 | /* |
| 47 | * Return how many nanoseconds it will take (at a minimum) for count events |
| 48 | * to occur. A negative value indicates the counter will never overflow, or |
| 49 | * that the counter has otherwise arranged for the overflow bit to be set |
| 50 | * and the PMU interrupt to be raised on overflow. |
| 51 | */ |
| 52 | int64_t (*ns_per_count)(uint64_t); |
| 53 | } pm_event; |
| 54 | |
| 55 | static bool event_always_supported(CPUARMState *env) |
| 56 | { |
| 57 | return true; |
| 58 | } |
| 59 | |
| 60 | static uint64_t swinc_get_count(CPUARMState *env) |
| 61 | { |
| 62 | /* |
| 63 | * SW_INCR events are written directly to the pmevcntr's by writes to |
| 64 | * PMSWINC, so there is no underlying count maintained by the PMU itself |
| 65 | */ |
| 66 | return 0; |
| 67 | } |
| 68 | |
| 69 | static int64_t swinc_ns_per(uint64_t ignored) |
| 70 | { |
| 71 | return -1; |
| 72 | } |
| 73 | |
| 74 | /* |
| 75 | * Return the underlying cycle count for the PMU cycle counters. If we're in |
| 76 | * usermode, simply return 0. |
| 77 | */ |
| 78 | static uint64_t cycles_get_count(CPUARMState *env) |
| 79 | { |
| 80 | #ifndef CONFIG_USER_ONLY |
| 81 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
| 82 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); |
| 83 | #else |
| 84 | return cpu_get_host_ticks(); |
| 85 | #endif |
| 86 | } |
| 87 | |
| 88 | #ifndef CONFIG_USER_ONLY |
| 89 | static int64_t cycles_ns_per(uint64_t cycles) |
| 90 | { |
| 91 | return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; |
| 92 | } |
| 93 | |
| 94 | static bool instructions_supported(CPUARMState *env) |
| 95 | { |
| 96 | /* Precise instruction counting */ |
| 97 | return icount_enabled() == ICOUNT_PRECISE; |
| 98 | } |
| 99 | |
| 100 | static uint64_t instructions_get_count(CPUARMState *env) |
| 101 | { |
| 102 | assert(icount_enabled() == ICOUNT_PRECISE); |
| 103 | return (uint64_t)icount_get_raw(); |
| 104 | } |
| 105 | |
| 106 | static int64_t instructions_ns_per(uint64_t icount) |
| 107 | { |
| 108 | assert(icount_enabled() == ICOUNT_PRECISE); |
| 109 | return icount_to_ns((int64_t)icount); |
| 110 | } |
| 111 | #endif |
| 112 | |
| 113 | static bool pmuv3p1_events_supported(CPUARMState *env) |
| 114 | { |
| 115 | /* For events which are supported in any v8.1 PMU */ |
| 116 | return cpu_isar_feature(any_pmuv3p1, env_archcpu(env)); |
| 117 | } |
| 118 | |
| 119 | static bool pmuv3p4_events_supported(CPUARMState *env) |
| 120 | { |
| 121 | /* For events which are supported in any v8.1 PMU */ |
| 122 | return cpu_isar_feature(any_pmuv3p4, env_archcpu(env)); |
| 123 | } |
| 124 | |
| 125 | static uint64_t zero_event_get_count(CPUARMState *env) |
| 126 | { |
| 127 | /* For events which on QEMU never fire, so their count is always zero */ |
| 128 | return 0; |
| 129 | } |
| 130 | |
| 131 | static int64_t zero_event_ns_per(uint64_t cycles) |
| 132 | { |
| 133 | /* An event which never fires can never overflow */ |
| 134 | return -1; |
| 135 | } |
| 136 | |
| 137 | static const pm_event pm_events[] = { |
| 138 | { .number = 0x000, /* SW_INCR */ |
| 139 | .supported = event_always_supported, |
| 140 | .get_count = swinc_get_count, |
| 141 | .ns_per_count = swinc_ns_per, |
| 142 | }, |
| 143 | #ifndef CONFIG_USER_ONLY |
| 144 | { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ |
| 145 | .supported = instructions_supported, |
| 146 | .get_count = instructions_get_count, |
| 147 | .ns_per_count = instructions_ns_per, |
| 148 | }, |
| 149 | { .number = 0x011, /* CPU_CYCLES, Cycle */ |
| 150 | .supported = event_always_supported, |
| 151 | .get_count = cycles_get_count, |
| 152 | .ns_per_count = cycles_ns_per, |
| 153 | }, |
| 154 | #endif |
| 155 | { .number = 0x023, /* STALL_FRONTEND */ |
| 156 | .supported = pmuv3p1_events_supported, |
| 157 | .get_count = zero_event_get_count, |
| 158 | .ns_per_count = zero_event_ns_per, |
| 159 | }, |
| 160 | { .number = 0x024, /* STALL_BACKEND */ |
| 161 | .supported = pmuv3p1_events_supported, |
| 162 | .get_count = zero_event_get_count, |
| 163 | .ns_per_count = zero_event_ns_per, |
| 164 | }, |
| 165 | { .number = 0x03c, /* STALL */ |
| 166 | .supported = pmuv3p4_events_supported, |
| 167 | .get_count = zero_event_get_count, |
| 168 | .ns_per_count = zero_event_ns_per, |
| 169 | }, |
| 170 | }; |
| 171 | |
| 172 | /* |
| 173 | * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of |
| 174 | * events (i.e. the statistical profiling extension), this implementation |
| 175 | * should first be updated to something sparse instead of the current |
| 176 | * supported_event_map[] array. |
| 177 | */ |
| 178 | #define MAX_EVENT_ID 0x3c |
| 179 | #define UNSUPPORTED_EVENT UINT16_MAX |
| 180 | static uint16_t supported_event_map[MAX_EVENT_ID + 1]; |
| 181 | |
| 182 | /* |
| 183 | * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map |
| 184 | * of ARM event numbers to indices in our pm_events array. |
| 185 | * |
| 186 | * Note: Events in the 0x40XX range are not currently supported. |
| 187 | */ |
| 188 | void pmu_init(ARMCPU *cpu) |
| 189 | { |
| 190 | unsigned int i; |
| 191 | |
| 192 | /* |
| 193 | * Empty supported_event_map and cpu->pmceid[01] before adding supported |
| 194 | * events to them |
| 195 | */ |
| 196 | for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) { |
| 197 | supported_event_map[i] = UNSUPPORTED_EVENT; |
| 198 | } |
| 199 | cpu->pmceid0 = 0; |
| 200 | cpu->pmceid1 = 0; |
| 201 | |
| 202 | for (i = 0; i < ARRAY_SIZE(pm_events); i++) { |
| 203 | const pm_event *cnt = &pm_events[i]; |
| 204 | assert(cnt->number <= MAX_EVENT_ID); |
| 205 | /* We do not currently support events in the 0x40xx range */ |
| 206 | assert(cnt->number <= 0x3f); |
| 207 | |
| 208 | if (cnt->supported(&cpu->env)) { |
| 209 | supported_event_map[cnt->number] = i; |
| 210 | uint64_t event_mask = 1ULL << (cnt->number & 0x1f); |
| 211 | if (cnt->number & 0x20) { |
| 212 | cpu->pmceid1 |= event_mask; |
| 213 | } else { |
| 214 | cpu->pmceid0 |= event_mask; |
| 215 | } |
| 216 | } |
| 217 | } |
| 218 | } |
| 219 | |
| 220 | /* |
| 221 | * Check at runtime whether a PMU event is supported for the current machine |
| 222 | */ |
| 223 | static bool event_supported(uint16_t number) |
| 224 | { |
| 225 | if (number > MAX_EVENT_ID) { |
| 226 | return false; |
| 227 | } |
| 228 | return supported_event_map[number] != UNSUPPORTED_EVENT; |
| 229 | } |
| 230 | |
| 231 | static CPAccessResult do_pmreg_access(CPUARMState *env, bool is_pmcr) |
| 232 | { |
| 233 | /* |
| 234 | * Performance monitor registers user accessibility is controlled |
| 235 | * by PMUSERENR. MDCR_EL2.TPM/TPMCR and MDCR_EL3.TPM allow configurable |
| 236 | * trapping to EL2 or EL3 for other accesses. |
| 237 | */ |
| 238 | int el = arm_current_el(env); |
| 239 | |
| 240 | if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { |
| 241 | return CP_ACCESS_TRAP_EL1; |
| 242 | } |
| 243 | if (el < 2) { |
| 244 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
| 245 | |
| 246 | if (mdcr_el2 & MDCR_TPM) { |
| 247 | return CP_ACCESS_TRAP_EL2; |
| 248 | } |
| 249 | if (is_pmcr && (mdcr_el2 & MDCR_TPMCR)) { |
| 250 | return CP_ACCESS_TRAP_EL2; |
| 251 | } |
| 252 | } |
| 253 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { |
| 254 | return CP_ACCESS_TRAP_EL3; |
| 255 | } |
| 256 | |
| 257 | return CP_ACCESS_OK; |
| 258 | } |
| 259 | |
| 260 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
| 261 | bool isread) |
| 262 | { |
| 263 | return do_pmreg_access(env, false); |
| 264 | } |
| 265 | |
| 266 | static CPAccessResult pmreg_access_pmcr(CPUARMState *env, |
| 267 | const ARMCPRegInfo *ri, |
| 268 | bool isread) |
| 269 | { |
| 270 | return do_pmreg_access(env, true); |
| 271 | } |
| 272 | |
| 273 | static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, |
| 274 | const ARMCPRegInfo *ri, |
| 275 | bool isread) |
| 276 | { |
| 277 | /* ER: event counter read trap control */ |
| 278 | if (arm_feature(env, ARM_FEATURE_V8) |
| 279 | && arm_current_el(env) == 0 |
| 280 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 |
| 281 | && isread) { |
| 282 | return CP_ACCESS_OK; |
| 283 | } |
| 284 | |
| 285 | return pmreg_access(env, ri, isread); |
| 286 | } |
| 287 | |
| 288 | static CPAccessResult pmreg_access_swinc(CPUARMState *env, |
| 289 | const ARMCPRegInfo *ri, |
| 290 | bool isread) |
| 291 | { |
| 292 | /* SW: software increment write trap control */ |
| 293 | if (arm_feature(env, ARM_FEATURE_V8) |
| 294 | && arm_current_el(env) == 0 |
| 295 | && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 |
| 296 | && !isread) { |
| 297 | return CP_ACCESS_OK; |
| 298 | } |
| 299 | |
| 300 | return pmreg_access(env, ri, isread); |
| 301 | } |
| 302 | |
| 303 | static CPAccessResult pmreg_access_selr(CPUARMState *env, |
| 304 | const ARMCPRegInfo *ri, |
| 305 | bool isread) |
| 306 | { |
| 307 | /* ER: event counter read trap control */ |
| 308 | if (arm_feature(env, ARM_FEATURE_V8) |
| 309 | && arm_current_el(env) == 0 |
| 310 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { |
| 311 | return CP_ACCESS_OK; |
| 312 | } |
| 313 | |
| 314 | return pmreg_access(env, ri, isread); |
| 315 | } |
| 316 | |
| 317 | static CPAccessResult pmreg_access_ccntr(CPUARMState *env, |
| 318 | const ARMCPRegInfo *ri, |
| 319 | bool isread) |
| 320 | { |
| 321 | /* CR: cycle counter read trap control */ |
| 322 | if (arm_feature(env, ARM_FEATURE_V8) |
| 323 | && arm_current_el(env) == 0 |
| 324 | && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 |
| 325 | && isread) { |
| 326 | return CP_ACCESS_OK; |
| 327 | } |
| 328 | |
| 329 | return pmreg_access(env, ri, isread); |
| 330 | } |
| 331 | |
| 332 | /* |
| 333 | * Returns true if the counter (pass 31 for PMCCNTR) should count events using |
| 334 | * the current EL, security state, and register configuration. |
| 335 | */ |
| 336 | static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) |
| 337 | { |
| 338 | uint64_t filter; |
| 339 | bool e, p, u, nsk, nsu, nsh, m; |
| 340 | bool enabled, prohibited = false, filtered; |
| 341 | bool secure = arm_is_secure(env); |
| 342 | int el = arm_current_el(env); |
| 343 | uint64_t mdcr_el2; |
| 344 | uint8_t hpmn; |
| 345 | |
| 346 | /* |
| 347 | * We might be called for M-profile cores where MDCR_EL2 doesn't |
| 348 | * exist and arm_mdcr_el2_eff() will assert, so this early-exit check |
| 349 | * must be before we read that value. |
| 350 | */ |
| 351 | if (!arm_feature(env, ARM_FEATURE_PMU)) { |
| 352 | return false; |
| 353 | } |
| 354 | |
| 355 | mdcr_el2 = arm_mdcr_el2_eff(env); |
| 356 | hpmn = mdcr_el2 & MDCR_HPMN; |
| 357 | |
| 358 | if (!arm_feature(env, ARM_FEATURE_EL2) || |
| 359 | (counter < hpmn || counter == 31)) { |
| 360 | e = env->cp15.c9_pmcr & PMCRE; |
| 361 | } else { |
| 362 | e = mdcr_el2 & MDCR_HPME; |
| 363 | } |
| 364 | enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); |
| 365 | |
| 366 | /* Is event counting prohibited? */ |
| 367 | if (el == 2 && (counter < hpmn || counter == 31)) { |
| 368 | prohibited = mdcr_el2 & MDCR_HPMD; |
| 369 | } |
| 370 | if (secure) { |
| 371 | prohibited = prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); |
| 372 | } |
| 373 | |
| 374 | if (counter == 31) { |
| 375 | /* |
| 376 | * The cycle counter defaults to running. PMCR.DP says "disable |
| 377 | * the cycle counter when event counting is prohibited". |
| 378 | * Some MDCR bits disable the cycle counter specifically. |
| 379 | */ |
| 380 | prohibited = prohibited && env->cp15.c9_pmcr & PMCRDP; |
| 381 | if (cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { |
| 382 | if (secure) { |
| 383 | prohibited = prohibited || (env->cp15.mdcr_el3 & MDCR_SCCD); |
| 384 | } |
| 385 | if (el == 2) { |
| 386 | prohibited = prohibited || (mdcr_el2 & MDCR_HCCD); |
| 387 | } |
| 388 | } |
| 389 | } |
| 390 | |
| 391 | if (counter == 31) { |
| 392 | filter = env->cp15.pmccfiltr_el0; |
| 393 | } else { |
| 394 | filter = env->cp15.c14_pmevtyper[counter]; |
| 395 | } |
| 396 | |
| 397 | p = filter & PMXEVTYPER_P; |
| 398 | u = filter & PMXEVTYPER_U; |
| 399 | nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); |
| 400 | nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); |
| 401 | nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); |
| 402 | m = arm_el_is_aa64(env, 1) && |
| 403 | arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); |
| 404 | |
| 405 | if (el == 0) { |
| 406 | filtered = secure ? u : u != nsu; |
| 407 | } else if (el == 1) { |
| 408 | filtered = secure ? p : p != nsk; |
| 409 | } else if (el == 2) { |
| 410 | filtered = !nsh; |
| 411 | } else { /* EL3 */ |
| 412 | filtered = m != p; |
| 413 | } |
| 414 | |
| 415 | if (counter != 31) { |
| 416 | /* |
| 417 | * If not checking PMCCNTR, ensure the counter is setup to an event we |
| 418 | * support |
| 419 | */ |
| 420 | uint16_t event = filter & PMXEVTYPER_EVTCOUNT; |
| 421 | if (!event_supported(event)) { |
| 422 | return false; |
| 423 | } |
| 424 | } |
| 425 | |
| 426 | return enabled && !prohibited && !filtered; |
| 427 | } |
| 428 | |
| 429 | static void pmu_update_irq(CPUARMState *env) |
| 430 | { |
| 431 | #ifndef CONFIG_USER_ONLY |
| 432 | ARMCPU *cpu = env_archcpu(env); |
| 433 | bool level = (env->cp15.c9_pmcr & PMCRE) && |
| 434 | (env->cp15.c9_pminten & env->cp15.c9_pmovsr); |
| 435 | |
| 436 | gicv5_update_ppi_state(env, GICV5_PPI_PMUIRQ, level); |
| 437 | qemu_set_irq(cpu->pmu_interrupt, level); |
| 438 | #endif |
| 439 | } |
| 440 | |
| 441 | static bool pmccntr_clockdiv_enabled(CPUARMState *env) |
| 442 | { |
| 443 | /* |
| 444 | * Return true if the clock divider is enabled and the cycle counter |
| 445 | * is supposed to tick only once every 64 clock cycles. This is |
| 446 | * controlled by PMCR.D, but if PMCR.LC is set to enable the long |
| 447 | * (64-bit) cycle counter PMCR.D has no effect. |
| 448 | */ |
| 449 | return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) == PMCRD; |
| 450 | } |
| 451 | |
| 452 | static bool pmevcntr_is_64_bit(CPUARMState *env, int counter) |
| 453 | { |
| 454 | /* Return true if the specified event counter is configured to be 64 bit */ |
| 455 | |
| 456 | /* This isn't intended to be used with the cycle counter */ |
| 457 | assert(counter < 31); |
| 458 | |
| 459 | if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { |
| 460 | return false; |
| 461 | } |
| 462 | |
| 463 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
| 464 | /* |
| 465 | * MDCR_EL2.HLP still applies even when EL2 is disabled in the |
| 466 | * current security state, so we don't use arm_mdcr_el2_eff() here. |
| 467 | */ |
| 468 | bool hlp = env->cp15.mdcr_el2 & MDCR_HLP; |
| 469 | int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; |
| 470 | |
| 471 | if (counter >= hpmn) { |
| 472 | return hlp; |
| 473 | } |
| 474 | } |
| 475 | return env->cp15.c9_pmcr & PMCRLP; |
| 476 | } |
| 477 | |
| 478 | /* |
| 479 | * Ensure c15_ccnt is the guest-visible count so that operations such as |
| 480 | * enabling/disabling the counter or filtering, modifying the count itself, |
| 481 | * etc. can be done logically. This is essentially a no-op if the counter is |
| 482 | * not enabled at the time of the call. |
| 483 | */ |
| 484 | static void pmccntr_op_start(CPUARMState *env) |
| 485 | { |
| 486 | uint64_t cycles = cycles_get_count(env); |
| 487 | |
| 488 | if (pmu_counter_enabled(env, 31)) { |
| 489 | uint64_t eff_cycles = cycles; |
| 490 | if (pmccntr_clockdiv_enabled(env)) { |
| 491 | eff_cycles /= 64; |
| 492 | } |
| 493 | |
| 494 | uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; |
| 495 | |
| 496 | uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ |
| 497 | 1ull << 63 : 1ull << 31; |
| 498 | if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { |
| 499 | env->cp15.c9_pmovsr |= (1ULL << 31); |
| 500 | pmu_update_irq(env); |
| 501 | } |
| 502 | |
| 503 | env->cp15.c15_ccnt = new_pmccntr; |
| 504 | } |
| 505 | env->cp15.c15_ccnt_delta = cycles; |
| 506 | } |
| 507 | |
| 508 | /* |
| 509 | * If PMCCNTR is enabled, recalculate the delta between the clock and the |
| 510 | * guest-visible count. A call to pmccntr_op_finish should follow every call to |
| 511 | * pmccntr_op_start. |
| 512 | */ |
| 513 | static void pmccntr_op_finish(CPUARMState *env) |
| 514 | { |
| 515 | if (pmu_counter_enabled(env, 31)) { |
| 516 | #ifndef CONFIG_USER_ONLY |
| 517 | /* Calculate when the counter will next overflow */ |
| 518 | uint64_t remaining_cycles = -env->cp15.c15_ccnt; |
| 519 | if (!(env->cp15.c9_pmcr & PMCRLC)) { |
| 520 | remaining_cycles = (uint32_t)remaining_cycles; |
| 521 | } |
| 522 | int64_t overflow_in = cycles_ns_per(remaining_cycles); |
| 523 | |
| 524 | if (overflow_in > 0) { |
| 525 | int64_t overflow_at; |
| 526 | |
| 527 | if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
| 528 | overflow_in, &overflow_at)) { |
| 529 | ARMCPU *cpu = env_archcpu(env); |
| 530 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
| 531 | } |
| 532 | } |
| 533 | #endif |
| 534 | |
| 535 | uint64_t prev_cycles = env->cp15.c15_ccnt_delta; |
| 536 | if (pmccntr_clockdiv_enabled(env)) { |
| 537 | prev_cycles /= 64; |
| 538 | } |
| 539 | env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; |
| 540 | } |
| 541 | } |
| 542 | |
| 543 | static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) |
| 544 | { |
| 545 | |
| 546 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; |
| 547 | uint64_t count = 0; |
| 548 | if (event_supported(event)) { |
| 549 | uint16_t event_idx = supported_event_map[event]; |
| 550 | count = pm_events[event_idx].get_count(env); |
| 551 | } |
| 552 | |
| 553 | if (pmu_counter_enabled(env, counter)) { |
| 554 | uint64_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; |
| 555 | uint64_t overflow_mask = pmevcntr_is_64_bit(env, counter) ? |
| 556 | 1ULL << 63 : 1ULL << 31; |
| 557 | |
| 558 | if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & overflow_mask) { |
| 559 | env->cp15.c9_pmovsr |= (1 << counter); |
| 560 | pmu_update_irq(env); |
| 561 | } |
| 562 | env->cp15.c14_pmevcntr[counter] = new_pmevcntr; |
| 563 | } |
| 564 | env->cp15.c14_pmevcntr_delta[counter] = count; |
| 565 | } |
| 566 | |
| 567 | static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) |
| 568 | { |
| 569 | if (pmu_counter_enabled(env, counter)) { |
| 570 | #ifndef CONFIG_USER_ONLY |
| 571 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; |
| 572 | uint16_t event_idx = supported_event_map[event]; |
| 573 | uint64_t delta = -(env->cp15.c14_pmevcntr[counter] + 1); |
| 574 | int64_t overflow_in; |
| 575 | |
| 576 | if (!pmevcntr_is_64_bit(env, counter)) { |
| 577 | delta = (uint32_t)delta; |
| 578 | } |
| 579 | overflow_in = pm_events[event_idx].ns_per_count(delta); |
| 580 | |
| 581 | if (overflow_in > 0) { |
| 582 | int64_t overflow_at; |
| 583 | |
| 584 | if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
| 585 | overflow_in, &overflow_at)) { |
| 586 | ARMCPU *cpu = env_archcpu(env); |
| 587 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
| 588 | } |
| 589 | } |
| 590 | #endif |
| 591 | |
| 592 | env->cp15.c14_pmevcntr_delta[counter] -= |
| 593 | env->cp15.c14_pmevcntr[counter]; |
| 594 | } |
| 595 | } |
| 596 | |
| 597 | void pmu_op_start(CPUARMState *env) |
| 598 | { |
| 599 | unsigned int i; |
| 600 | pmccntr_op_start(env); |
| 601 | for (i = 0; i < pmu_num_counters(env); i++) { |
| 602 | pmevcntr_op_start(env, i); |
| 603 | } |
| 604 | } |
| 605 | |
| 606 | void pmu_op_finish(CPUARMState *env) |
| 607 | { |
| 608 | unsigned int i; |
| 609 | pmccntr_op_finish(env); |
| 610 | for (i = 0; i < pmu_num_counters(env); i++) { |
| 611 | pmevcntr_op_finish(env, i); |
| 612 | } |
| 613 | } |
| 614 | |
| 615 | void pmu_pre_el_change(ARMCPU *cpu, void *ignored) |
| 616 | { |
| 617 | pmu_op_start(&cpu->env); |
| 618 | } |
| 619 | |
| 620 | void pmu_post_el_change(ARMCPU *cpu, void *ignored) |
| 621 | { |
| 622 | pmu_op_finish(&cpu->env); |
| 623 | } |
| 624 | |
| 625 | void arm_pmu_timer_cb(void *opaque) |
| 626 | { |
| 627 | ARMCPU *cpu = opaque; |
| 628 | |
| 629 | /* |
| 630 | * Update all the counter values based on the current underlying counts, |
| 631 | * triggering interrupts to be raised, if necessary. pmu_op_finish() also |
| 632 | * has the effect of setting the cpu->pmu_timer to the next earliest time a |
| 633 | * counter may expire. |
| 634 | */ |
| 635 | pmu_op_start(&cpu->env); |
| 636 | pmu_op_finish(&cpu->env); |
| 637 | } |
| 638 | |
| 639 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 640 | uint64_t value) |
| 641 | { |
| 642 | pmu_op_start(env); |
| 643 | |
| 644 | if (value & PMCRC) { |
| 645 | /* The counter has been reset */ |
| 646 | env->cp15.c15_ccnt = 0; |
| 647 | } |
| 648 | |
| 649 | if (value & PMCRP) { |
| 650 | unsigned int i; |
| 651 | for (i = 0; i < pmu_num_counters(env); i++) { |
| 652 | env->cp15.c14_pmevcntr[i] = 0; |
| 653 | } |
| 654 | } |
| 655 | |
| 656 | env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; |
| 657 | env->cp15.c9_pmcr |= (value & PMCR_WRITABLE_MASK); |
| 658 | |
| 659 | pmu_op_finish(env); |
| 660 | } |
| 661 | |
| 662 | static uint64_t pmcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
| 663 | { |
| 664 | uint64_t pmcr = env->cp15.c9_pmcr; |
| 665 | |
| 666 | /* |
| 667 | * If EL2 is implemented and enabled for the current security state, reads |
| 668 | * of PMCR.N from EL1 or EL0 return the value of MDCR_EL2.HPMN or HDCR.HPMN. |
| 669 | */ |
| 670 | if (arm_current_el(env) <= 1 && arm_is_el2_enabled(env)) { |
| 671 | pmcr &= ~PMCRN_MASK; |
| 672 | pmcr |= (env->cp15.mdcr_el2 & MDCR_HPMN) << PMCRN_SHIFT; |
| 673 | } |
| 674 | |
| 675 | return pmcr; |
| 676 | } |
| 677 | |
| 678 | static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 679 | uint64_t value) |
| 680 | { |
| 681 | unsigned int i; |
| 682 | uint64_t overflow_mask, new_pmswinc; |
| 683 | |
| 684 | for (i = 0; i < pmu_num_counters(env); i++) { |
| 685 | /* Increment a counter's count iff: */ |
| 686 | if ((value & (1 << i)) && /* counter's bit is set */ |
| 687 | /* counter is enabled and not filtered */ |
| 688 | pmu_counter_enabled(env, i) && |
| 689 | /* counter is SW_INCR */ |
| 690 | (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { |
| 691 | pmevcntr_op_start(env, i); |
| 692 | |
| 693 | /* |
| 694 | * Detect if this write causes an overflow since we can't predict |
| 695 | * PMSWINC overflows like we can for other events |
| 696 | */ |
| 697 | new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; |
| 698 | |
| 699 | overflow_mask = pmevcntr_is_64_bit(env, i) ? |
| 700 | 1ULL << 63 : 1ULL << 31; |
| 701 | |
| 702 | if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & overflow_mask) { |
| 703 | env->cp15.c9_pmovsr |= (1 << i); |
| 704 | pmu_update_irq(env); |
| 705 | } |
| 706 | |
| 707 | env->cp15.c14_pmevcntr[i] = new_pmswinc; |
| 708 | |
| 709 | pmevcntr_op_finish(env, i); |
| 710 | } |
| 711 | } |
| 712 | } |
| 713 | |
| 714 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
| 715 | { |
| 716 | uint64_t ret; |
| 717 | pmccntr_op_start(env); |
| 718 | ret = env->cp15.c15_ccnt; |
| 719 | pmccntr_op_finish(env); |
| 720 | return ret; |
| 721 | } |
| 722 | |
| 723 | static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 724 | uint64_t value) |
| 725 | { |
| 726 | /* |
| 727 | * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and |
| 728 | * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the |
| 729 | * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are |
| 730 | * accessed. |
| 731 | */ |
| 732 | env->cp15.c9_pmselr = value & 0x1f; |
| 733 | } |
| 734 | |
| 735 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 736 | uint64_t value) |
| 737 | { |
| 738 | pmccntr_op_start(env); |
| 739 | env->cp15.c15_ccnt = value; |
| 740 | pmccntr_op_finish(env); |
| 741 | } |
| 742 | |
| 743 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, |
| 744 | uint64_t value) |
| 745 | { |
| 746 | uint64_t cur_val = pmccntr_read(env, NULL); |
| 747 | |
| 748 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); |
| 749 | } |
| 750 | |
| 751 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 752 | uint64_t value) |
| 753 | { |
| 754 | pmccntr_op_start(env); |
| 755 | env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; |
| 756 | pmccntr_op_finish(env); |
| 757 | } |
| 758 | |
| 759 | static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, |
| 760 | uint64_t value) |
| 761 | { |
| 762 | pmccntr_op_start(env); |
| 763 | /* M is not accessible from AArch32 */ |
| 764 | env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | |
| 765 | (value & PMCCFILTR); |
| 766 | pmccntr_op_finish(env); |
| 767 | } |
| 768 | |
| 769 | static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) |
| 770 | { |
| 771 | /* M is not visible in AArch32 */ |
| 772 | return env->cp15.pmccfiltr_el0 & PMCCFILTR; |
| 773 | } |
| 774 | |
| 775 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 776 | uint64_t value) |
| 777 | { |
| 778 | pmu_op_start(env); |
| 779 | value &= pmu_counter_mask(env); |
| 780 | env->cp15.c9_pmcnten |= value; |
| 781 | pmu_op_finish(env); |
| 782 | } |
| 783 | |
| 784 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 785 | uint64_t value) |
| 786 | { |
| 787 | pmu_op_start(env); |
| 788 | value &= pmu_counter_mask(env); |
| 789 | env->cp15.c9_pmcnten &= ~value; |
| 790 | pmu_op_finish(env); |
| 791 | } |
| 792 | |
| 793 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 794 | uint64_t value) |
| 795 | { |
| 796 | value &= pmu_counter_mask(env); |
| 797 | env->cp15.c9_pmovsr &= ~value; |
| 798 | pmu_update_irq(env); |
| 799 | } |
| 800 | |
| 801 | static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 802 | uint64_t value) |
| 803 | { |
| 804 | value &= pmu_counter_mask(env); |
| 805 | env->cp15.c9_pmovsr |= value; |
| 806 | pmu_update_irq(env); |
| 807 | } |
| 808 | |
| 809 | static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 810 | uint64_t value, const uint8_t counter) |
| 811 | { |
| 812 | if (counter == 31) { |
| 813 | pmccfiltr_write(env, ri, value); |
| 814 | } else if (counter < pmu_num_counters(env)) { |
| 815 | pmevcntr_op_start(env, counter); |
| 816 | |
| 817 | /* |
| 818 | * If this counter's event type is changing, store the current |
| 819 | * underlying count for the new type in c14_pmevcntr_delta[counter] so |
| 820 | * pmevcntr_op_finish has the correct baseline when it converts back to |
| 821 | * a delta. |
| 822 | */ |
| 823 | uint16_t old_event = env->cp15.c14_pmevtyper[counter] & |
| 824 | PMXEVTYPER_EVTCOUNT; |
| 825 | uint16_t new_event = value & PMXEVTYPER_EVTCOUNT; |
| 826 | if (old_event != new_event) { |
| 827 | uint64_t count = 0; |
| 828 | if (event_supported(new_event)) { |
| 829 | uint16_t event_idx = supported_event_map[new_event]; |
| 830 | count = pm_events[event_idx].get_count(env); |
| 831 | } |
| 832 | env->cp15.c14_pmevcntr_delta[counter] = count; |
| 833 | } |
| 834 | |
| 835 | env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; |
| 836 | pmevcntr_op_finish(env, counter); |
| 837 | } |
| 838 | /* |
| 839 | * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when |
| 840 | * PMSELR value is equal to or greater than the number of implemented |
| 841 | * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. |
| 842 | */ |
| 843 | } |
| 844 | |
| 845 | static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, |
| 846 | const uint8_t counter) |
| 847 | { |
| 848 | if (counter == 31) { |
| 849 | return env->cp15.pmccfiltr_el0; |
| 850 | } else if (counter < pmu_num_counters(env)) { |
| 851 | return env->cp15.c14_pmevtyper[counter]; |
| 852 | } else { |
| 853 | /* |
| 854 | * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER |
| 855 | * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). |
| 856 | */ |
| 857 | return 0; |
| 858 | } |
| 859 | } |
| 860 | |
| 861 | static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, |
| 862 | uint64_t value) |
| 863 | { |
| 864 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); |
| 865 | pmevtyper_write(env, ri, value, counter); |
| 866 | } |
| 867 | |
| 868 | static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, |
| 869 | uint64_t value) |
| 870 | { |
| 871 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); |
| 872 | env->cp15.c14_pmevtyper[counter] = value; |
| 873 | |
| 874 | /* |
| 875 | * pmevtyper_rawwrite is called between a pair of pmu_op_start and |
| 876 | * pmu_op_finish calls when loading saved state for a migration. Because |
| 877 | * we're potentially updating the type of event here, the value written to |
| 878 | * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a |
| 879 | * different counter type. Therefore, we need to set this value to the |
| 880 | * current count for the counter type we're writing so that pmu_op_finish |
| 881 | * has the correct count for its calculation. |
| 882 | */ |
| 883 | uint16_t event = value & PMXEVTYPER_EVTCOUNT; |
| 884 | if (event_supported(event)) { |
| 885 | uint16_t event_idx = supported_event_map[event]; |
| 886 | env->cp15.c14_pmevcntr_delta[counter] = |
| 887 | pm_events[event_idx].get_count(env); |
| 888 | } |
| 889 | } |
| 890 | |
| 891 | static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
| 892 | { |
| 893 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); |
| 894 | return pmevtyper_read(env, ri, counter); |
| 895 | } |
| 896 | |
| 897 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 898 | uint64_t value) |
| 899 | { |
| 900 | pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); |
| 901 | } |
| 902 | |
| 903 | static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) |
| 904 | { |
| 905 | return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); |
| 906 | } |
| 907 | |
| 908 | static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 909 | uint64_t value, uint8_t counter) |
| 910 | { |
| 911 | if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { |
| 912 | /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */ |
| 913 | value &= MAKE_64BIT_MASK(0, 32); |
| 914 | } |
| 915 | if (counter < pmu_num_counters(env)) { |
| 916 | pmevcntr_op_start(env, counter); |
| 917 | env->cp15.c14_pmevcntr[counter] = value; |
| 918 | pmevcntr_op_finish(env, counter); |
| 919 | } |
| 920 | /* |
| 921 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR |
| 922 | * are CONSTRAINED UNPREDICTABLE. |
| 923 | */ |
| 924 | } |
| 925 | |
| 926 | static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, |
| 927 | uint8_t counter) |
| 928 | { |
| 929 | if (counter < pmu_num_counters(env)) { |
| 930 | uint64_t ret; |
| 931 | pmevcntr_op_start(env, counter); |
| 932 | ret = env->cp15.c14_pmevcntr[counter]; |
| 933 | pmevcntr_op_finish(env, counter); |
| 934 | if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { |
| 935 | /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */ |
| 936 | ret &= MAKE_64BIT_MASK(0, 32); |
| 937 | } |
| 938 | return ret; |
| 939 | } else { |
| 940 | /* |
| 941 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR |
| 942 | * are CONSTRAINED UNPREDICTABLE. |
| 943 | */ |
| 944 | return 0; |
| 945 | } |
| 946 | } |
| 947 | |
| 948 | static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, |
| 949 | uint64_t value) |
| 950 | { |
| 951 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); |
| 952 | pmevcntr_write(env, ri, value, counter); |
| 953 | } |
| 954 | |
| 955 | static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
| 956 | { |
| 957 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); |
| 958 | return pmevcntr_read(env, ri, counter); |
| 959 | } |
| 960 | |
| 961 | static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, |
| 962 | uint64_t value) |
| 963 | { |
| 964 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); |
| 965 | assert(counter < pmu_num_counters(env)); |
| 966 | env->cp15.c14_pmevcntr[counter] = value; |
| 967 | pmevcntr_write(env, ri, value, counter); |
| 968 | } |
| 969 | |
| 970 | static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) |
| 971 | { |
| 972 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); |
| 973 | assert(counter < pmu_num_counters(env)); |
| 974 | return env->cp15.c14_pmevcntr[counter]; |
| 975 | } |
| 976 | |
| 977 | static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 978 | uint64_t value) |
| 979 | { |
| 980 | pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); |
| 981 | } |
| 982 | |
| 983 | static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
| 984 | { |
| 985 | return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); |
| 986 | } |
| 987 | |
| 988 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 989 | uint64_t value) |
| 990 | { |
| 991 | if (arm_feature(env, ARM_FEATURE_V8)) { |
| 992 | env->cp15.c9_pmuserenr = value & 0xf; |
| 993 | } else { |
| 994 | env->cp15.c9_pmuserenr = value & 1; |
| 995 | } |
| 996 | } |
| 997 | |
| 998 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 999 | uint64_t value) |
| 1000 | { |
| 1001 | /* We have no event counters so only the C bit can be changed */ |
| 1002 | value &= pmu_counter_mask(env); |
| 1003 | env->cp15.c9_pminten |= value; |
| 1004 | pmu_update_irq(env); |
| 1005 | } |
| 1006 | |
| 1007 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 1008 | uint64_t value) |
| 1009 | { |
| 1010 | value &= pmu_counter_mask(env); |
| 1011 | env->cp15.c9_pminten &= ~value; |
| 1012 | pmu_update_irq(env); |
| 1013 | } |
| 1014 | |
| 1015 | static const ARMCPRegInfo v7_pm_reginfo[] = { |
| 1016 | /* |
| 1017 | * Performance monitors are implementation defined in v7, |
| 1018 | * but with an ARM recommended set of registers, which we |
| 1019 | * follow. |
| 1020 | * |
| 1021 | * Performance registers fall into three categories: |
| 1022 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) |
| 1023 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) |
| 1024 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) |
| 1025 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW |
| 1026 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. |
| 1027 | */ |
| 1028 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, |
| 1029 | .access = PL0_RW, .type = ARM_CP_ALIAS | ARM_CP_IO, |
| 1030 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
| 1031 | .writefn = pmcntenset_write, |
| 1032 | .accessfn = pmreg_access, |
| 1033 | .fgt = FGT_PMCNTEN, |
| 1034 | .raw_writefn = raw_write }, |
| 1035 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO, |
| 1036 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, |
| 1037 | .access = PL0_RW, .accessfn = pmreg_access, |
| 1038 | .fgt = FGT_PMCNTEN, |
| 1039 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, |
| 1040 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, |
| 1041 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
| 1042 | .access = PL0_RW, |
| 1043 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
| 1044 | .accessfn = pmreg_access, |
| 1045 | .fgt = FGT_PMCNTEN, |
| 1046 | .writefn = pmcntenclr_write, .raw_writefn = raw_write, |
| 1047 | .type = ARM_CP_ALIAS | ARM_CP_IO }, |
| 1048 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
| 1049 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, |
| 1050 | .access = PL0_RW, .accessfn = pmreg_access, |
| 1051 | .fgt = FGT_PMCNTEN, |
| 1052 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
| 1053 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
| 1054 | .writefn = pmcntenclr_write, .raw_writefn = raw_write }, |
| 1055 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
| 1056 | .access = PL0_RW, .type = ARM_CP_IO, |
| 1057 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
| 1058 | .accessfn = pmreg_access, |
| 1059 | .fgt = FGT_PMOVS, |
| 1060 | .writefn = pmovsr_write, |
| 1061 | .raw_writefn = raw_write }, |
| 1062 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
| 1063 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, |
| 1064 | .access = PL0_RW, .accessfn = pmreg_access, |
| 1065 | .fgt = FGT_PMOVS, |
| 1066 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
| 1067 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
| 1068 | .writefn = pmovsr_write, |
| 1069 | .raw_writefn = raw_write }, |
| 1070 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
| 1071 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
| 1072 | .fgt = FGT_PMSWINC_EL0, |
| 1073 | .type = ARM_CP_NO_RAW | ARM_CP_IO, |
| 1074 | .writefn = pmswinc_write }, |
| 1075 | { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, |
| 1076 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, |
| 1077 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
| 1078 | .fgt = FGT_PMSWINC_EL0, |
| 1079 | .type = ARM_CP_NO_RAW | ARM_CP_IO, |
| 1080 | .writefn = pmswinc_write }, |
| 1081 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
| 1082 | .access = PL0_RW, .type = ARM_CP_ALIAS, |
| 1083 | .fgt = FGT_PMSELR_EL0, |
| 1084 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), |
| 1085 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, |
| 1086 | .raw_writefn = raw_write}, |
| 1087 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, |
| 1088 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, |
| 1089 | .access = PL0_RW, .accessfn = pmreg_access_selr, |
| 1090 | .fgt = FGT_PMSELR_EL0, |
| 1091 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), |
| 1092 | .writefn = pmselr_write, .raw_writefn = raw_write, }, |
| 1093 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
| 1094 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, |
| 1095 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
| 1096 | .fgt = FGT_PMCCNTR_EL0, |
| 1097 | .type = ARM_CP_IO, |
| 1098 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), |
| 1099 | .readfn = pmccntr_read, .writefn = pmccntr_write, |
| 1100 | .raw_readfn = raw_read, .raw_writefn = raw_write, }, |
| 1101 | { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, |
| 1102 | .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, |
| 1103 | .access = PL0_RW, .accessfn = pmreg_access, |
| 1104 | .fgt = FGT_PMCCFILTR_EL0, |
| 1105 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
| 1106 | .resetvalue = 0, }, |
| 1107 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
| 1108 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, |
| 1109 | .writefn = pmccfiltr_write, .raw_writefn = raw_write, |
| 1110 | .access = PL0_RW, .accessfn = pmreg_access, |
| 1111 | .fgt = FGT_PMCCFILTR_EL0, |
| 1112 | .type = ARM_CP_IO, |
| 1113 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), |
| 1114 | .resetvalue = 0, }, |
| 1115 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
| 1116 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
| 1117 | .accessfn = pmreg_access, |
| 1118 | .fgt = FGT_PMEVTYPERN_EL0, |
| 1119 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
| 1120 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, |
| 1121 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, |
| 1122 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
| 1123 | .accessfn = pmreg_access, |
| 1124 | .fgt = FGT_PMEVTYPERN_EL0, |
| 1125 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
| 1126 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
| 1127 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
| 1128 | .accessfn = pmreg_access_xevcntr, |
| 1129 | .fgt = FGT_PMEVCNTRN_EL0, |
| 1130 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, |
| 1131 | { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, |
| 1132 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, |
| 1133 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
| 1134 | .accessfn = pmreg_access_xevcntr, |
| 1135 | .fgt = FGT_PMEVCNTRN_EL0, |
| 1136 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, |
| 1137 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
| 1138 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, |
| 1139 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr), |
| 1140 | .resetvalue = 0, |
| 1141 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
| 1142 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
| 1143 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, |
| 1144 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
| 1145 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
| 1146 | .resetvalue = 0, |
| 1147 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
| 1148 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
| 1149 | .access = PL1_RW, .accessfn = access_tpm, |
| 1150 | .fgt = FGT_PMINTEN, |
| 1151 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
| 1152 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), |
| 1153 | .resetvalue = 0, |
| 1154 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
| 1155 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, |
| 1156 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, |
| 1157 | .access = PL1_RW, .accessfn = access_tpm, |
| 1158 | .fgt = FGT_PMINTEN, |
| 1159 | .type = ARM_CP_IO, |
| 1160 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
| 1161 | .writefn = pmintenset_write, .raw_writefn = raw_write, |
| 1162 | .resetvalue = 0x0 }, |
| 1163 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
| 1164 | .access = PL1_RW, .accessfn = access_tpm, |
| 1165 | .fgt = FGT_PMINTEN, |
| 1166 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
| 1167 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
| 1168 | .writefn = pmintenclr_write, .raw_writefn = raw_write }, |
| 1169 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
| 1170 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, |
| 1171 | .access = PL1_RW, .accessfn = access_tpm, |
| 1172 | .fgt = FGT_PMINTEN, |
| 1173 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
| 1174 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
| 1175 | .writefn = pmintenclr_write, .raw_writefn = raw_write }, |
| 1176 | }; |
| 1177 | |
| 1178 | static const ARMCPRegInfo pmovsset_cp_reginfo[] = { |
| 1179 | /* PMOVSSET is not implemented in v7 before v7ve */ |
| 1180 | { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, |
| 1181 | .access = PL0_RW, .accessfn = pmreg_access, |
| 1182 | .fgt = FGT_PMOVS, |
| 1183 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
| 1184 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
| 1185 | .writefn = pmovsset_write, |
| 1186 | .raw_writefn = raw_write }, |
| 1187 | { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, |
| 1188 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, |
| 1189 | .access = PL0_RW, .accessfn = pmreg_access, |
| 1190 | .fgt = FGT_PMOVS, |
| 1191 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
| 1192 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
| 1193 | .writefn = pmovsset_write, |
| 1194 | .raw_writefn = raw_write }, |
| 1195 | }; |
| 1196 | |
| 1197 | void define_pm_cpregs(ARMCPU *cpu) |
| 1198 | { |
| 1199 | CPUARMState *env = &cpu->env; |
| 1200 | |
| 1201 | if (arm_feature(env, ARM_FEATURE_V7)) { |
| 1202 | /* |
| 1203 | * v7 performance monitor control register: same implementor |
| 1204 | * field as main ID register, and we implement four counters in |
| 1205 | * addition to the cycle count register. |
| 1206 | */ |
| 1207 | static const ARMCPRegInfo pmcr = { |
| 1208 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, |
| 1209 | .access = PL0_RW, |
| 1210 | .fgt = FGT_PMCR_EL0, |
| 1211 | .type = ARM_CP_IO | ARM_CP_ALIAS, |
| 1212 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), |
| 1213 | .accessfn = pmreg_access_pmcr, |
| 1214 | .readfn = pmcr_read, .raw_readfn = raw_read, |
| 1215 | .writefn = pmcr_write, .raw_writefn = raw_write, |
| 1216 | }; |
| 1217 | const ARMCPRegInfo pmcr64 = { |
| 1218 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, |
| 1219 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, |
| 1220 | .access = PL0_RW, .accessfn = pmreg_access_pmcr, |
| 1221 | .fgt = FGT_PMCR_EL0, |
| 1222 | .type = ARM_CP_IO, |
| 1223 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), |
| 1224 | .resetvalue = cpu->isar.reset_pmcr_el0, |
| 1225 | .readfn = pmcr_read, .raw_readfn = raw_read, |
| 1226 | .writefn = pmcr_write, .raw_writefn = raw_write, |
| 1227 | }; |
| 1228 | |
| 1229 | define_one_arm_cp_reg(cpu, &pmcr); |
| 1230 | define_one_arm_cp_reg(cpu, &pmcr64); |
| 1231 | define_arm_cp_regs(cpu, v7_pm_reginfo); |
| 1232 | /* |
| 1233 | * 32-bit AArch32 PMCCNTR. We don't expose this to GDB if the |
| 1234 | * new-in-v8 PMUv3 64-bit AArch32 PMCCNTR register is implemented |
| 1235 | * (as that will provide the GDB user's view of "PMCCNTR"). |
| 1236 | */ |
| 1237 | ARMCPRegInfo pmccntr = { |
| 1238 | .name = "PMCCNTR", |
| 1239 | .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
| 1240 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
| 1241 | .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, |
| 1242 | .fgt = FGT_PMCCNTR_EL0, |
| 1243 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
| 1244 | }; |
| 1245 | if (arm_feature(env, ARM_FEATURE_V8)) { |
| 1246 | pmccntr.type |= ARM_CP_NO_GDB; |
| 1247 | } |
| 1248 | define_one_arm_cp_reg(cpu, &pmccntr); |
| 1249 | |
| 1250 | for (unsigned i = 0, pmcrn = pmu_num_counters(env); i < pmcrn; i++) { |
| 1251 | g_autofree char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); |
| 1252 | g_autofree char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); |
| 1253 | g_autofree char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); |
| 1254 | g_autofree char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); |
| 1255 | |
| 1256 | ARMCPRegInfo pmev_regs[] = { |
| 1257 | { .name = pmevcntr_name, .cp = 15, .crn = 14, |
| 1258 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, |
| 1259 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, |
| 1260 | .fgt = FGT_PMEVCNTRN_EL0, |
| 1261 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, |
| 1262 | .accessfn = pmreg_access_xevcntr }, |
| 1263 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, |
| 1264 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), |
| 1265 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr, |
| 1266 | .type = ARM_CP_IO, |
| 1267 | .fgt = FGT_PMEVCNTRN_EL0, |
| 1268 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, |
| 1269 | .raw_readfn = pmevcntr_rawread, |
| 1270 | .raw_writefn = pmevcntr_rawwrite }, |
| 1271 | { .name = pmevtyper_name, .cp = 15, .crn = 14, |
| 1272 | .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, |
| 1273 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, |
| 1274 | .fgt = FGT_PMEVTYPERN_EL0, |
| 1275 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, |
| 1276 | .accessfn = pmreg_access }, |
| 1277 | { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, |
| 1278 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), |
| 1279 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, |
| 1280 | .fgt = FGT_PMEVTYPERN_EL0, |
| 1281 | .type = ARM_CP_IO, |
| 1282 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, |
| 1283 | .raw_writefn = pmevtyper_rawwrite }, |
| 1284 | }; |
| 1285 | define_arm_cp_regs(cpu, pmev_regs); |
| 1286 | } |
| 1287 | } |
| 1288 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
| 1289 | define_arm_cp_regs(cpu, pmovsset_cp_reginfo); |
| 1290 | } |
| 1291 | |
| 1292 | if (arm_feature(env, ARM_FEATURE_V8)) { |
| 1293 | const ARMCPRegInfo v8_pm_reginfo[] = { |
| 1294 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
| 1295 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, |
| 1296 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, |
| 1297 | .fgt = FGT_PMCEIDN_EL0, |
| 1298 | .resetvalue = extract64(cpu->pmceid0, 0, 32) }, |
| 1299 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, |
| 1300 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, |
| 1301 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, |
| 1302 | .fgt = FGT_PMCEIDN_EL0, |
| 1303 | .resetvalue = cpu->pmceid0 }, |
| 1304 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, |
| 1305 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, |
| 1306 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, |
| 1307 | .fgt = FGT_PMCEIDN_EL0, |
| 1308 | .resetvalue = extract64(cpu->pmceid1, 0, 32) }, |
| 1309 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, |
| 1310 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, |
| 1311 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, |
| 1312 | .fgt = FGT_PMCEIDN_EL0, |
| 1313 | .resetvalue = cpu->pmceid1 }, |
| 1314 | /* AArch32 64-bit PMCCNTR view: added in PMUv3 with Armv8 */ |
| 1315 | { .name = "PMCCNTR", .state = ARM_CP_STATE_AA32, |
| 1316 | .cp = 15, .crm = 9, .opc1 = 0, |
| 1317 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, .resetvalue = 0, |
| 1318 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_64BIT, |
| 1319 | .fgt = FGT_PMCCNTR_EL0, .readfn = pmccntr_read, |
| 1320 | .writefn = pmccntr_write, }, |
| 1321 | }; |
| 1322 | define_arm_cp_regs(cpu, v8_pm_reginfo); |
| 1323 | } |
| 1324 | |
| 1325 | if (cpu_isar_feature(aa32_pmuv3p1, cpu)) { |
| 1326 | ARMCPRegInfo v81_pmu_regs[] = { |
| 1327 | { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, |
| 1328 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, |
| 1329 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, |
| 1330 | .fgt = FGT_PMCEIDN_EL0, |
| 1331 | .resetvalue = extract64(cpu->pmceid0, 32, 32) }, |
| 1332 | { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, |
| 1333 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, |
| 1334 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, |
| 1335 | .fgt = FGT_PMCEIDN_EL0, |
| 1336 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, |
| 1337 | }; |
| 1338 | define_arm_cp_regs(cpu, v81_pmu_regs); |
| 1339 | } |
| 1340 | |
| 1341 | if (cpu_isar_feature(any_pmuv3p4, cpu)) { |
| 1342 | static const ARMCPRegInfo v84_pmmir = { |
| 1343 | .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH, |
| 1344 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6, |
| 1345 | .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, |
| 1346 | .fgt = FGT_PMMIR_EL1, |
| 1347 | .resetvalue = 0 |
| 1348 | }; |
| 1349 | define_one_arm_cp_reg(cpu, &v84_pmmir); |
| 1350 | } |
| 1351 | } |