| 1 | /* |
| 2 | * QEMU ARM CP Register access and descriptions |
| 3 | * |
| 4 | * Copyright (c) 2022 Linaro Ltd |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, see |
| 18 | * <http://www.gnu.org/licenses/gpl-2.0.html> |
| 19 | */ |
| 20 | |
| 21 | #ifndef TARGET_ARM_CPREGS_H |
| 22 | #define TARGET_ARM_CPREGS_H |
| 23 | |
| 24 | #include "hw/core/registerfields.h" |
| 25 | #include "exec/memop.h" |
| 26 | #include "target/arm/kvm-consts.h" |
| 27 | #include "cpu.h" |
| 28 | |
| 29 | /* |
| 30 | * ARMCPRegInfo type field bits: |
| 31 | */ |
| 32 | enum { |
| 33 | /* |
| 34 | * Register must be handled specially during translation. |
| 35 | * The method is one of the values below: |
| 36 | */ |
| 37 | ARM_CP_SPECIAL_MASK = 0x000f, |
| 38 | /* Special: no change to PE state: writes ignored, reads ignored. */ |
| 39 | ARM_CP_NOP = 0x0001, |
| 40 | /* Special: sysreg is WFI, for v5 and v6. */ |
| 41 | ARM_CP_WFI = 0x0002, |
| 42 | /* Special: sysreg is NZCV. */ |
| 43 | ARM_CP_NZCV = 0x0003, |
| 44 | /* Special: sysreg is CURRENTEL. */ |
| 45 | ARM_CP_CURRENTEL = 0x0004, |
| 46 | /* Special: sysreg is DC ZVA or similar. */ |
| 47 | ARM_CP_DC_ZVA = 0x0005, |
| 48 | ARM_CP_DC_GVA = 0x0006, |
| 49 | ARM_CP_DC_GZVA = 0x0007, |
| 50 | /* Special: gcs instructions */ |
| 51 | ARM_CP_GCSPUSHM = 0x0008, |
| 52 | ARM_CP_GCSPOPM = 0x0009, |
| 53 | ARM_CP_GCSPUSHX = 0x000a, |
| 54 | ARM_CP_GCSPOPX = 0x000b, |
| 55 | ARM_CP_GCSPOPCX = 0x000c, |
| 56 | ARM_CP_GCSSS1 = 0x000d, |
| 57 | ARM_CP_GCSSS2 = 0x000e, |
| 58 | |
| 59 | /* Flag: reads produce resetvalue; writes ignored. */ |
| 60 | ARM_CP_CONST = 1 << 4, |
| 61 | /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */ |
| 62 | ARM_CP_64BIT = 1 << 5, |
| 63 | /* |
| 64 | * Flag: TB should not be ended after a write to this register |
| 65 | * (the default is that the TB ends after cp writes). |
| 66 | */ |
| 67 | ARM_CP_SUPPRESS_TB_END = 1 << 6, |
| 68 | /* |
| 69 | * Flag: Permit a register definition to override a previous definition |
| 70 | * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new |
| 71 | * or the old must have the ARM_CP_OVERRIDE bit set. |
| 72 | */ |
| 73 | ARM_CP_OVERRIDE = 1 << 7, |
| 74 | /* |
| 75 | * Flag: Register is an alias view of some underlying state which is also |
| 76 | * visible via another register, and that the other register is handling |
| 77 | * migration and reset; registers marked ARM_CP_ALIAS will not be migrated |
| 78 | * but may have their state set by syncing of register state from KVM. |
| 79 | */ |
| 80 | ARM_CP_ALIAS = 1 << 8, |
| 81 | /* |
| 82 | * Flag: Register does I/O and therefore its accesses need to be marked |
| 83 | * with translator_io_start() and also end the TB. In particular, |
| 84 | * registers which implement clocks or timers require this. |
| 85 | */ |
| 86 | ARM_CP_IO = 1 << 9, |
| 87 | /* |
| 88 | * Flag: Register has no underlying state and does not support raw access |
| 89 | * for state saving/loading; it will not be used for either migration or |
| 90 | * KVM state synchronization. Typically this is for "registers" which are |
| 91 | * actually used as instructions for cache maintenance and so on. |
| 92 | */ |
| 93 | ARM_CP_NO_RAW = 1 << 10, |
| 94 | /* |
| 95 | * Flag: The read or write hook might raise an exception; the generated |
| 96 | * code will synchronize the CPU state before calling the hook so that it |
| 97 | * is safe for the hook to call raise_exception(). |
| 98 | */ |
| 99 | ARM_CP_RAISES_EXC = 1 << 11, |
| 100 | /* |
| 101 | * Flag: Writes to the sysreg might change the exception level - typically |
| 102 | * on older ARM chips. For those cases we need to re-read the new el when |
| 103 | * recomputing the translation flags. |
| 104 | */ |
| 105 | ARM_CP_NEWEL = 1 << 12, |
| 106 | /* |
| 107 | * Flag: Access check for this sysreg is identical to accessing FPU state |
| 108 | * from an instruction: use translation fp_access_check(). |
| 109 | */ |
| 110 | ARM_CP_FPU = 1 << 13, |
| 111 | /* |
| 112 | * Flag: Access check for this sysreg is identical to accessing SVE state |
| 113 | * from an instruction: use translation sve_access_check(). |
| 114 | */ |
| 115 | ARM_CP_SVE = 1 << 14, |
| 116 | /* Flag: Do not expose in gdb sysreg xml. */ |
| 117 | ARM_CP_NO_GDB = 1 << 15, |
| 118 | /* |
| 119 | * Flags: If EL3 but not EL2... |
| 120 | * - UNDEF: discard the cpreg, |
| 121 | * - KEEP: retain the cpreg as is, |
| 122 | * - C_NZ: set const on the cpreg, but retain resetvalue, |
| 123 | * - else: set const on the cpreg, zero resetvalue, aka RES0. |
| 124 | * See rule RJFFP in section D1.1.3 of DDI0487H.a. |
| 125 | */ |
| 126 | ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16, |
| 127 | ARM_CP_EL3_NO_EL2_KEEP = 1 << 17, |
| 128 | ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18, |
| 129 | /* |
| 130 | * Flag: Access check for this sysreg is constrained by the |
| 131 | * ARM pseudocode function CheckSMEAccess(). |
| 132 | */ |
| 133 | ARM_CP_SME = 1 << 19, |
| 134 | /* |
| 135 | * Flag: one of the four EL2 registers which redirect to the |
| 136 | * equivalent EL1 register when FEAT_NV2 is enabled. |
| 137 | */ |
| 138 | ARM_CP_NV2_REDIRECT = 1 << 20, |
| 139 | /* |
| 140 | * Flag: this is a TLBI insn which (when FEAT_XS is present) also has |
| 141 | * an NXS variant at the same encoding except that crn is 1 greater, |
| 142 | * so when registering this cpreg automatically also register one |
| 143 | * for the TLBI NXS variant. (For QEMU the NXS variant behaves |
| 144 | * identically to the normal one, other than FGT trapping handling.) |
| 145 | */ |
| 146 | ARM_CP_ADD_TLBI_NXS = 1 << 21, |
| 147 | /* |
| 148 | * Flag: even though this sysreg has opc1 == 4 or 5, it |
| 149 | * should not trap to EL2 when HCR_EL2.NV is set. |
| 150 | */ |
| 151 | ARM_CP_NV_NO_TRAP = 1 << 22, |
| 152 | /* |
| 153 | * Flag: Access check for this sysreg is constrained by the |
| 154 | * ARM pseudocode function CheckFPMREnabled(). |
| 155 | */ |
| 156 | ARM_CP_FPMR = 1 << 23, |
| 157 | }; |
| 158 | |
| 159 | /* |
| 160 | * Interface for defining coprocessor registers. |
| 161 | * Registers are defined in tables of arm_cp_reginfo structs |
| 162 | * which are passed to define_arm_cp_regs(). |
| 163 | */ |
| 164 | |
| 165 | /* |
| 166 | * When looking up a coprocessor register we look for it |
| 167 | * via an integer which encodes all of: |
| 168 | * coprocessor number |
| 169 | * Crn, Crm, opc1, opc2 fields |
| 170 | * 32 or 64 bit register (ie is it accessed via MRC/MCR |
| 171 | * or via MRRC/MCRR?) |
| 172 | * non-secure/secure bank (AArch32 only) |
| 173 | * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. |
| 174 | * (In this case crn and opc2 should be zero.) |
| 175 | * For AArch64, there is no 32/64 bit size distinction; |
| 176 | * instead all registers have a 2 bit op0, 3 bit op1 and op2, |
| 177 | * and 4 bit CRn and CRm. The encoding patterns are chosen |
| 178 | * to be easy to convert to and from the KVM encodings, and also |
| 179 | * so that the hashtable can contain both AArch32 and AArch64 |
| 180 | * registers (to allow for interprocessing where we might run |
| 181 | * 32 bit code on a 64 bit core). |
| 182 | */ |
| 183 | /* |
| 184 | * This bit is private to our hashtable cpreg; in KVM register |
| 185 | * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 |
| 186 | * in the upper bits of the 64 bit ID. |
| 187 | */ |
| 188 | #define CP_REG_AA64_SHIFT 28 |
| 189 | #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) |
| 190 | |
| 191 | /* |
| 192 | * To enable banking of coprocessor registers depending on ns-bit we |
| 193 | * add a bit to distinguish between secure and non-secure cpregs in the |
| 194 | * hashtable. |
| 195 | */ |
| 196 | #define CP_REG_AA32_NS_SHIFT 29 |
| 197 | #define CP_REG_AA32_NS_MASK (1 << CP_REG_AA32_NS_SHIFT) |
| 198 | |
| 199 | /* Distinguish 32-bit and 64-bit views of AArch32 system registers. */ |
| 200 | #define CP_REG_AA32_64BIT_SHIFT 15 |
| 201 | #define CP_REG_AA32_64BIT_MASK (1 << CP_REG_AA32_64BIT_SHIFT) |
| 202 | |
| 203 | #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ |
| 204 | (((ns) << CP_REG_AA32_NS_SHIFT) | \ |
| 205 | ((is64) << CP_REG_AA32_64BIT_SHIFT) | \ |
| 206 | ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) |
| 207 | |
| 208 | #define ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) \ |
| 209 | (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \ |
| 210 | ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ |
| 211 | ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ |
| 212 | ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ |
| 213 | ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ |
| 214 | ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) |
| 215 | |
| 216 | /* |
| 217 | * Convert a full 64 bit KVM register ID to the truncated 32 bit |
| 218 | * version used as a key for the coprocessor register hashtable |
| 219 | */ |
| 220 | static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) |
| 221 | { |
| 222 | uint32_t cpregid = kvmid; |
| 223 | if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { |
| 224 | cpregid |= CP_REG_AA64_MASK; |
| 225 | } else { |
| 226 | if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { |
| 227 | cpregid |= CP_REG_AA32_64BIT_MASK; |
| 228 | } |
| 229 | |
| 230 | /* |
| 231 | * KVM is always non-secure so add the NS flag on AArch32 register |
| 232 | * entries. |
| 233 | */ |
| 234 | cpregid |= CP_REG_AA32_NS_MASK; |
| 235 | } |
| 236 | return cpregid; |
| 237 | } |
| 238 | |
| 239 | /* |
| 240 | * Convert a truncated 32 bit hashtable key into the full |
| 241 | * 64 bit KVM register ID. |
| 242 | */ |
| 243 | static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) |
| 244 | { |
| 245 | uint64_t kvmid; |
| 246 | |
| 247 | if (cpregid & CP_REG_AA64_MASK) { |
| 248 | kvmid = cpregid & ~CP_REG_AA64_MASK; |
| 249 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; |
| 250 | } else { |
| 251 | kvmid = cpregid & ~CP_REG_AA32_64BIT_MASK; |
| 252 | if (cpregid & CP_REG_AA32_64BIT_MASK) { |
| 253 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; |
| 254 | } else { |
| 255 | kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; |
| 256 | } |
| 257 | } |
| 258 | return kvmid; |
| 259 | } |
| 260 | |
| 261 | /* |
| 262 | * Valid values for ARMCPRegInfo state field, indicating which of |
| 263 | * the AArch32 and AArch64 execution states this register is visible in. |
| 264 | * If the reginfo doesn't explicitly specify then it is AArch32 only. |
| 265 | * If the reginfo is declared to be visible in both states then a second |
| 266 | * reginfo is synthesised for the AArch32 view of the AArch64 register, |
| 267 | * such that the AArch32 view is the lower 32 bits of the AArch64 one. |
| 268 | * Note that we rely on the values of these enums as we iterate through |
| 269 | * the various states in some places. |
| 270 | */ |
| 271 | typedef enum { |
| 272 | ARM_CP_STATE_AA32 = 0, |
| 273 | ARM_CP_STATE_AA64 = 1, |
| 274 | ARM_CP_STATE_BOTH = 2, |
| 275 | } CPState; |
| 276 | |
| 277 | /* |
| 278 | * ARM CP register secure state flags. These flags identify security state |
| 279 | * attributes for a given CP register entry. |
| 280 | * The existence of both or neither secure and non-secure flags indicates that |
| 281 | * the register has both a secure and non-secure hash entry. A single one of |
| 282 | * these flags causes the register to only be hashed for the specified |
| 283 | * security state. |
| 284 | * Although definitions may have any combination of the S/NS bits, each |
| 285 | * registered entry will only have one to identify whether the entry is secure |
| 286 | * or non-secure. |
| 287 | */ |
| 288 | typedef enum { |
| 289 | ARM_CP_SECSTATE_BOTH = 0, /* define one cpreg for each secstate */ |
| 290 | ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ |
| 291 | ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ |
| 292 | } CPSecureState; |
| 293 | |
| 294 | /* |
| 295 | * Access rights: |
| 296 | * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM |
| 297 | * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and |
| 298 | * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 |
| 299 | * (ie any of the privileged modes in Secure state, or Monitor mode). |
| 300 | * If a register is accessible in one privilege level it's always accessible |
| 301 | * in higher privilege levels too. Since "Secure PL1" also follows this rule |
| 302 | * (ie anything visible in PL2 is visible in S-PL1, some things are only |
| 303 | * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the |
| 304 | * terminology a little and call this PL3. |
| 305 | * In AArch64 things are somewhat simpler as the PLx bits line up exactly |
| 306 | * with the ELx exception levels. |
| 307 | * |
| 308 | * If access permissions for a register are more complex than can be |
| 309 | * described with these bits, then use a laxer set of restrictions, and |
| 310 | * do the more restrictive/complex check inside a helper function. |
| 311 | */ |
| 312 | typedef enum { |
| 313 | PL3_R = 0x80, |
| 314 | PL3_W = 0x40, |
| 315 | PL2_R = 0x20 | PL3_R, |
| 316 | PL2_W = 0x10 | PL3_W, |
| 317 | PL1_R = 0x08 | PL2_R, |
| 318 | PL1_W = 0x04 | PL2_W, |
| 319 | PL0_R = 0x02 | PL1_R, |
| 320 | PL0_W = 0x01 | PL1_W, |
| 321 | |
| 322 | /* |
| 323 | * For user-mode some registers are accessible to EL0 via a kernel |
| 324 | * trap-and-emulate ABI. In this case we define the read permissions |
| 325 | * as actually being PL0_R. However some bits of any given register |
| 326 | * may still be masked. |
| 327 | */ |
| 328 | #ifdef CONFIG_USER_ONLY |
| 329 | PL0U_R = PL0_R, |
| 330 | #else |
| 331 | PL0U_R = PL1_R, |
| 332 | #endif |
| 333 | |
| 334 | PL3_RW = PL3_R | PL3_W, |
| 335 | PL2_RW = PL2_R | PL2_W, |
| 336 | PL1_RW = PL1_R | PL1_W, |
| 337 | PL0_RW = PL0_R | PL0_W, |
| 338 | } CPAccessRights; |
| 339 | |
| 340 | typedef enum CPAccessResult { |
| 341 | /* Access is permitted */ |
| 342 | CP_ACCESS_OK = 0, |
| 343 | |
| 344 | /* |
| 345 | * Combined with one of the following, the low 2 bits indicate the |
| 346 | * target exception level. If 0, the exception is taken to the usual |
| 347 | * target EL (EL1 or PL1 if in EL0, otherwise to the current EL). |
| 348 | */ |
| 349 | CP_ACCESS_EL_MASK = 3, |
| 350 | |
| 351 | /* |
| 352 | * Access fails due to a configurable trap or enable which would |
| 353 | * result in a categorized exception syndrome giving information about |
| 354 | * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, |
| 355 | * 0xc or 0x18). These traps are always to a specified target EL, |
| 356 | * never to the usual target EL. |
| 357 | */ |
| 358 | CP_ACCESS_TRAP_BIT = (1 << 2), |
| 359 | CP_ACCESS_TRAP_EL1 = CP_ACCESS_TRAP_BIT | 1, |
| 360 | CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP_BIT | 2, |
| 361 | CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP_BIT | 3, |
| 362 | |
| 363 | /* |
| 364 | * Access fails with UNDEFINED, i.e. an exception syndrome 0x0 |
| 365 | * ("uncategorized"), which is what an undefined insn produces. |
| 366 | * Note that this is not a catch-all case -- the set of cases which may |
| 367 | * result in this failure is specifically defined by the architecture. |
| 368 | * This trap is always to the usual target EL, never directly to a |
| 369 | * specified target EL. |
| 370 | */ |
| 371 | CP_ACCESS_UNDEFINED = (2 << 2), |
| 372 | |
| 373 | /* |
| 374 | * Access fails with EXLOCK, a GCS exception syndrome. |
| 375 | * These traps are always to the current execution EL, |
| 376 | * which is the same as the usual target EL because |
| 377 | * they cannot occur from EL0. |
| 378 | */ |
| 379 | CP_ACCESS_EXLOCK = (3 << 2), |
| 380 | } CPAccessResult; |
| 381 | |
| 382 | /* Indexes into fgt_read[] */ |
| 383 | #define FGTREG_HFGRTR 0 |
| 384 | #define FGTREG_HDFGRTR 1 |
| 385 | /* Indexes into fgt_write[] */ |
| 386 | #define FGTREG_HFGWTR 0 |
| 387 | #define FGTREG_HDFGWTR 1 |
| 388 | #define FGTREG_FGWTE3 2 |
| 389 | /* Indexes into fgt_exec[] */ |
| 390 | #define FGTREG_HFGITR 0 |
| 391 | |
| 392 | FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1) |
| 393 | FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1) |
| 394 | FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1) |
| 395 | FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1) |
| 396 | FIELD(HFGRTR_EL2, APDAKEY, 4, 1) |
| 397 | FIELD(HFGRTR_EL2, APDBKEY, 5, 1) |
| 398 | FIELD(HFGRTR_EL2, APGAKEY, 6, 1) |
| 399 | FIELD(HFGRTR_EL2, APIAKEY, 7, 1) |
| 400 | FIELD(HFGRTR_EL2, APIBKEY, 8, 1) |
| 401 | FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1) |
| 402 | FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1) |
| 403 | FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1) |
| 404 | FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1) |
| 405 | FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1) |
| 406 | FIELD(HFGRTR_EL2, CTR_EL0, 14, 1) |
| 407 | FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1) |
| 408 | FIELD(HFGRTR_EL2, ESR_EL1, 16, 1) |
| 409 | FIELD(HFGRTR_EL2, FAR_EL1, 17, 1) |
| 410 | FIELD(HFGRTR_EL2, ISR_EL1, 18, 1) |
| 411 | FIELD(HFGRTR_EL2, LORC_EL1, 19, 1) |
| 412 | FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1) |
| 413 | FIELD(HFGRTR_EL2, LORID_EL1, 21, 1) |
| 414 | FIELD(HFGRTR_EL2, LORN_EL1, 22, 1) |
| 415 | FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1) |
| 416 | FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1) |
| 417 | FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1) |
| 418 | FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1) |
| 419 | FIELD(HFGRTR_EL2, PAR_EL1, 27, 1) |
| 420 | FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1) |
| 421 | FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1) |
| 422 | FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1) |
| 423 | FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1) |
| 424 | FIELD(HFGRTR_EL2, TCR_EL1, 32, 1) |
| 425 | FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1) |
| 426 | FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1) |
| 427 | FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1) |
| 428 | FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1) |
| 429 | FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1) |
| 430 | FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1) |
| 431 | FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1) |
| 432 | FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1) |
| 433 | FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1) |
| 434 | FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1) |
| 435 | FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1) |
| 436 | FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1) |
| 437 | FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1) |
| 438 | FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1) |
| 439 | FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1) |
| 440 | FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1) |
| 441 | FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1) |
| 442 | FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1) |
| 443 | /* 51: RES0 */ |
| 444 | FIELD(HFGRTR_EL2, NGCS_EL0, 52, 1) |
| 445 | FIELD(HFGRTR_EL2, NGCS_EL1, 53, 1) |
| 446 | FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1) |
| 447 | FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1) |
| 448 | FIELD(HFGRTR_EL2, NRCWMASK_EL1, 56, 1) |
| 449 | FIELD(HFGRTR_EL2, NPIRE0_EL1, 57, 1) |
| 450 | FIELD(HFGRTR_EL2, NPIR_EL1, 58, 1) |
| 451 | FIELD(HFGRTR_EL2, NPOR_EL0, 59, 1) |
| 452 | FIELD(HFGRTR_EL2, NPOR_EL1, 60, 1) |
| 453 | FIELD(HFGRTR_EL2, NS2POR_EL1, 61, 1) |
| 454 | FIELD(HFGRTR_EL2, NMAIR2_EL1, 62, 1) |
| 455 | FIELD(HFGRTR_EL2, NAMAIR2_EL1, 63, 1) |
| 456 | |
| 457 | /* These match HFGRTR but bits for RO registers are RES0 */ |
| 458 | FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1) |
| 459 | FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1) |
| 460 | FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1) |
| 461 | FIELD(HFGWTR_EL2, APDAKEY, 4, 1) |
| 462 | FIELD(HFGWTR_EL2, APDBKEY, 5, 1) |
| 463 | FIELD(HFGWTR_EL2, APGAKEY, 6, 1) |
| 464 | FIELD(HFGWTR_EL2, APIAKEY, 7, 1) |
| 465 | FIELD(HFGWTR_EL2, APIBKEY, 8, 1) |
| 466 | FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1) |
| 467 | FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1) |
| 468 | FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1) |
| 469 | FIELD(HFGWTR_EL2, ESR_EL1, 16, 1) |
| 470 | FIELD(HFGWTR_EL2, FAR_EL1, 17, 1) |
| 471 | FIELD(HFGWTR_EL2, LORC_EL1, 19, 1) |
| 472 | FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1) |
| 473 | FIELD(HFGWTR_EL2, LORN_EL1, 22, 1) |
| 474 | FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1) |
| 475 | FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1) |
| 476 | FIELD(HFGWTR_EL2, PAR_EL1, 27, 1) |
| 477 | FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1) |
| 478 | FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1) |
| 479 | FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1) |
| 480 | FIELD(HFGWTR_EL2, TCR_EL1, 32, 1) |
| 481 | FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1) |
| 482 | FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1) |
| 483 | FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1) |
| 484 | FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1) |
| 485 | FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1) |
| 486 | FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1) |
| 487 | FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1) |
| 488 | FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1) |
| 489 | FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1) |
| 490 | FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1) |
| 491 | FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1) |
| 492 | FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1) |
| 493 | FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1) |
| 494 | FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1) |
| 495 | FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1) |
| 496 | FIELD(HFGWTR_EL2, NGCS_EL0, 52, 1) |
| 497 | FIELD(HFGWTR_EL2, NGCS_EL1, 53, 1) |
| 498 | FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1) |
| 499 | FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1) |
| 500 | FIELD(HFGWTR_EL2, NRCWMASK_EL1, 56, 1) |
| 501 | FIELD(HFGWTR_EL2, NPIRE0_EL1, 57, 1) |
| 502 | FIELD(HFGWTR_EL2, NPIR_EL1, 58, 1) |
| 503 | FIELD(HFGWTR_EL2, NPOR_EL0, 59, 1) |
| 504 | FIELD(HFGWTR_EL2, NPOR_EL1, 60, 1) |
| 505 | FIELD(HFGWTR_EL2, NS2POR_EL1, 61, 1) |
| 506 | FIELD(HFGWTR_EL2, NMAIR2_EL1, 62, 1) |
| 507 | FIELD(HFGWTR_EL2, NAMAIR2_EL1, 63, 1) |
| 508 | |
| 509 | FIELD(HFGITR_EL2, ICIALLUIS, 0, 1) |
| 510 | FIELD(HFGITR_EL2, ICIALLU, 1, 1) |
| 511 | FIELD(HFGITR_EL2, ICIVAU, 2, 1) |
| 512 | FIELD(HFGITR_EL2, DCIVAC, 3, 1) |
| 513 | FIELD(HFGITR_EL2, DCISW, 4, 1) |
| 514 | FIELD(HFGITR_EL2, DCCSW, 5, 1) |
| 515 | FIELD(HFGITR_EL2, DCCISW, 6, 1) |
| 516 | FIELD(HFGITR_EL2, DCCVAU, 7, 1) |
| 517 | FIELD(HFGITR_EL2, DCCVAP, 8, 1) |
| 518 | FIELD(HFGITR_EL2, DCCVADP, 9, 1) |
| 519 | FIELD(HFGITR_EL2, DCCIVAC, 10, 1) |
| 520 | FIELD(HFGITR_EL2, DCZVA, 11, 1) |
| 521 | FIELD(HFGITR_EL2, ATS1E1R, 12, 1) |
| 522 | FIELD(HFGITR_EL2, ATS1E1W, 13, 1) |
| 523 | FIELD(HFGITR_EL2, ATS1E0R, 14, 1) |
| 524 | FIELD(HFGITR_EL2, ATS1E0W, 15, 1) |
| 525 | FIELD(HFGITR_EL2, ATS1E1RP, 16, 1) |
| 526 | FIELD(HFGITR_EL2, ATS1E1WP, 17, 1) |
| 527 | FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1) |
| 528 | FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1) |
| 529 | FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1) |
| 530 | FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1) |
| 531 | FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1) |
| 532 | FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1) |
| 533 | FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1) |
| 534 | FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1) |
| 535 | FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1) |
| 536 | FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1) |
| 537 | FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1) |
| 538 | FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1) |
| 539 | FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1) |
| 540 | FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1) |
| 541 | FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1) |
| 542 | FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1) |
| 543 | FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1) |
| 544 | FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1) |
| 545 | FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1) |
| 546 | FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1) |
| 547 | FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1) |
| 548 | FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1) |
| 549 | FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1) |
| 550 | FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1) |
| 551 | FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1) |
| 552 | FIELD(HFGITR_EL2, TLBIVAE1, 43, 1) |
| 553 | FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1) |
| 554 | FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1) |
| 555 | FIELD(HFGITR_EL2, TLBIVALE1, 46, 1) |
| 556 | FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1) |
| 557 | FIELD(HFGITR_EL2, CFPRCTX, 48, 1) |
| 558 | FIELD(HFGITR_EL2, DVPRCTX, 49, 1) |
| 559 | FIELD(HFGITR_EL2, CPPRCTX, 50, 1) |
| 560 | FIELD(HFGITR_EL2, ERET, 51, 1) |
| 561 | FIELD(HFGITR_EL2, SVC_EL0, 52, 1) |
| 562 | FIELD(HFGITR_EL2, SVC_EL1, 53, 1) |
| 563 | FIELD(HFGITR_EL2, DCCVAC, 54, 1) |
| 564 | FIELD(HFGITR_EL2, NBRBINJ, 55, 1) |
| 565 | FIELD(HFGITR_EL2, NBRBIALL, 56, 1) |
| 566 | FIELD(HFGITR_EL2, NGCSPUSHM_EL1, 57, 1) |
| 567 | FIELD(HFGITR_EL2, NGCSSTR_EL1, 58, 1) |
| 568 | FIELD(HFGITR_EL2, NGCSEPP, 59, 1) |
| 569 | FIELD(HFGITR_EL2, COSPRCTX, 60, 1) |
| 570 | FIELD(HFGITR_EL2, ATS1E1A, 62, 1) |
| 571 | |
| 572 | FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1) |
| 573 | FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1) |
| 574 | FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1) |
| 575 | FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1) |
| 576 | FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1) |
| 577 | FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1) |
| 578 | FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1) |
| 579 | FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1) |
| 580 | /* 8: RES0: OSLAR_EL1 is WO */ |
| 581 | FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1) |
| 582 | FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1) |
| 583 | FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1) |
| 584 | FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1) |
| 585 | FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1) |
| 586 | FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1) |
| 587 | FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1) |
| 588 | FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1) |
| 589 | FIELD(HDFGRTR_EL2, PMINTEN, 17, 1) |
| 590 | FIELD(HDFGRTR_EL2, PMOVS, 18, 1) |
| 591 | FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1) |
| 592 | /* 20: RES0: PMSWINC_EL0 is WO */ |
| 593 | /* 21: RES0: PMCR_EL0 is WO */ |
| 594 | FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1) |
| 595 | FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1) |
| 596 | FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1) |
| 597 | FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1) |
| 598 | FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1) |
| 599 | FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1) |
| 600 | FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1) |
| 601 | FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1) |
| 602 | FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1) |
| 603 | FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1) |
| 604 | FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1) |
| 605 | FIELD(HDFGRTR_EL2, TRC, 33, 1) |
| 606 | FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1) |
| 607 | FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1) |
| 608 | FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1) |
| 609 | FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1) |
| 610 | /* 38, 39: RES0 */ |
| 611 | FIELD(HDFGRTR_EL2, TRCID, 40, 1) |
| 612 | FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1) |
| 613 | /* 42: RES0: TRCOSLAR is WO */ |
| 614 | FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1) |
| 615 | FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1) |
| 616 | FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1) |
| 617 | FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1) |
| 618 | FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1) |
| 619 | FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1) |
| 620 | /* 49: RES0: TRFCR_EL1 is WO */ |
| 621 | FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1) |
| 622 | FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1) |
| 623 | FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1) |
| 624 | FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1) |
| 625 | FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1) |
| 626 | FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1) |
| 627 | FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1) |
| 628 | FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1) |
| 629 | FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1) |
| 630 | FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1) |
| 631 | FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1) |
| 632 | FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1) |
| 633 | FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1) |
| 634 | FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1) |
| 635 | |
| 636 | /* |
| 637 | * These match HDFGRTR_EL2, but bits for RO registers are RES0. |
| 638 | * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0. |
| 639 | */ |
| 640 | FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1) |
| 641 | FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1) |
| 642 | FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1) |
| 643 | FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1) |
| 644 | FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1) |
| 645 | FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1) |
| 646 | FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1) |
| 647 | FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1) |
| 648 | FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1) |
| 649 | FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1) |
| 650 | FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1) |
| 651 | FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1) |
| 652 | FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1) |
| 653 | FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1) |
| 654 | FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1) |
| 655 | FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1) |
| 656 | FIELD(HDFGWTR_EL2, PMINTEN, 17, 1) |
| 657 | FIELD(HDFGWTR_EL2, PMOVS, 18, 1) |
| 658 | FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1) |
| 659 | FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1) |
| 660 | FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1) |
| 661 | FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1) |
| 662 | FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1) |
| 663 | FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1) |
| 664 | FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1) |
| 665 | FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1) |
| 666 | FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1) |
| 667 | FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1) |
| 668 | FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1) |
| 669 | FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1) |
| 670 | FIELD(HDFGWTR_EL2, TRC, 33, 1) |
| 671 | FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1) |
| 672 | FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1) |
| 673 | FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1) |
| 674 | FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1) |
| 675 | FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1) |
| 676 | FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1) |
| 677 | FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1) |
| 678 | FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1) |
| 679 | FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1) |
| 680 | FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1) |
| 681 | FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1) |
| 682 | FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1) |
| 683 | FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1) |
| 684 | FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1) |
| 685 | FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1) |
| 686 | FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1) |
| 687 | FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1) |
| 688 | FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) |
| 689 | FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) |
| 690 | FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) |
| 691 | |
| 692 | FIELD(FGWTE3_EL3, ACTLR_EL3, 0, 1) |
| 693 | FIELD(FGWTE3_EL3, AFSR0_EL3, 1, 1) |
| 694 | FIELD(FGWTE3_EL3, AFSR1_EL3, 2, 1) |
| 695 | FIELD(FGWTE3_EL3, AMAIR_EL3, 3, 1) |
| 696 | FIELD(FGWTE3_EL3, AMAIR2_EL3, 4, 1) |
| 697 | FIELD(FGWTE3_EL3, GCSCR_EL3, 5, 1) |
| 698 | FIELD(FGWTE3_EL3, GCSPR_EL3, 6, 1) |
| 699 | FIELD(FGWTE3_EL3, GPCCR_EL3, 7, 1) |
| 700 | FIELD(FGWTE3_EL3, GPTBR_EL3, 8, 1) |
| 701 | FIELD(FGWTE3_EL3, MAIR_EL3, 9, 1) |
| 702 | FIELD(FGWTE3_EL3, MAIR2_EL3, 10, 1) |
| 703 | FIELD(FGWTE3_EL3, MDCR_EL3, 11, 1) |
| 704 | FIELD(FGWTE3_EL3, MECID_RL_A_EL3, 12, 1) |
| 705 | FIELD(FGWTE3_EL3, MPAM3_EL3, 13, 1) |
| 706 | FIELD(FGWTE3_EL3, PIR_EL3, 14, 1) |
| 707 | FIELD(FGWTE3_EL3, SCTLR_EL3, 15, 1) |
| 708 | FIELD(FGWTE3_EL3, SCTLR2_EL3, 16, 1) |
| 709 | FIELD(FGWTE3_EL3, SPMROOTCR_EL3, 17, 1) |
| 710 | FIELD(FGWTE3_EL3, TCR_EL3, 18, 1) |
| 711 | FIELD(FGWTE3_EL3, TPIDR_EL3, 19, 1) |
| 712 | FIELD(FGWTE3_EL3, TTBR0_EL3, 20, 1) |
| 713 | FIELD(FGWTE3_EL3, VBAR_EL3, 21, 1) |
| 714 | FIELD(FGWTE3_EL3, GPCBW_EL3, 22, 1) |
| 715 | |
| 716 | FIELD(FGT, NXS, 13, 1) /* Honour HCR_EL2.FGTnXS to suppress FGT */ |
| 717 | /* Which fine-grained trap bit register to check, if any */ |
| 718 | FIELD(FGT, TYPE, 10, 3) |
| 719 | FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */ |
| 720 | FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */ |
| 721 | FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */ |
| 722 | |
| 723 | /* |
| 724 | * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::fgt |
| 725 | * fields. We assume for brevity's sake that there are no duplicated |
| 726 | * bit names across the various FGT registers. |
| 727 | */ |
| 728 | #define DO_BIT(REG, BITNAME) \ |
| 729 | FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT |
| 730 | |
| 731 | #define DO_EL3_BIT(REG, BITNAME) \ |
| 732 | FGT_##BITNAME = FGT_##REG | R_##REG##_EL3_##BITNAME##_SHIFT |
| 733 | |
| 734 | /* Some bits have reversed sense, so 0 means trap and 1 means not */ |
| 735 | #define DO_REV_BIT(REG, BITNAME) \ |
| 736 | FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT |
| 737 | |
| 738 | /* |
| 739 | * The FGT bits for TLBI maintenance instructions accessible at EL1 always |
| 740 | * affect the "normal" TLBI insns; they affect the corresponding TLBI insns |
| 741 | * with the nXS qualifier only if HCRX_EL2.FGTnXS is 0. We define e.g. |
| 742 | * FGT_TLBIVAE1 to use for the normal insn, and FGT_TLBIVAE1NXS to use |
| 743 | * for the nXS qualified insn. |
| 744 | */ |
| 745 | #define DO_TLBINXS_BIT(REG, BITNAME) \ |
| 746 | FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT, \ |
| 747 | FGT_##BITNAME##NXS = FGT_##BITNAME | R_FGT_NXS_MASK |
| 748 | |
| 749 | typedef enum FGTBit { |
| 750 | /* |
| 751 | * These bits tell us which register arrays to use: |
| 752 | * if FGT_R is set then reads are checked against fgt_read[]; |
| 753 | * if FGT_W is set then writes are checked against fgt_write[]; |
| 754 | * if FGT_EXEC is set then all accesses are checked against fgt_exec[]. |
| 755 | * |
| 756 | * For almost all bits in the R/W register pairs, the bit exists in |
| 757 | * both registers for a RW register, in HFGRTR/HDFGRTR for a RO register |
| 758 | * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa |
| 759 | * for a WO register. There are unfortunately a couple of exceptions |
| 760 | * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but |
| 761 | * the FGT system only allows trapping of writes, not reads. |
| 762 | * |
| 763 | * Note that we arrange these bits so that a 0 FGTBit means "no trap". |
| 764 | */ |
| 765 | FGT_R = 1 << R_FGT_TYPE_SHIFT, |
| 766 | FGT_W = 2 << R_FGT_TYPE_SHIFT, |
| 767 | FGT_EXEC = 4 << R_FGT_TYPE_SHIFT, |
| 768 | FGT_RW = FGT_R | FGT_W, |
| 769 | /* Bit to identify whether trap bit is reversed sense */ |
| 770 | FGT_REV = R_FGT_REV_MASK, |
| 771 | |
| 772 | /* |
| 773 | * If a bit exists in HFGRTR/HDFGRTR then either the register being |
| 774 | * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either |
| 775 | * want to trap for both reads and writes or else it's harmless to mark |
| 776 | * it as trap-on-writes. |
| 777 | * If a bit exists only in HFGWTR/HDFGWTR then either the register being |
| 778 | * trapped is WO, or else it is one of the two oddball special cases |
| 779 | * which are RW but have only a write trap. We mark these as only |
| 780 | * FGT_W so we get the right behaviour for those special cases. |
| 781 | * (If a bit was added in future that provided only a read trap for an |
| 782 | * RW register we'd need to do something special to get the FGT_R bit |
| 783 | * only. But this seems unlikely to happen.) |
| 784 | * |
| 785 | * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if |
| 786 | * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGWTR. |
| 787 | */ |
| 788 | FGT_HFGRTR = FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT), |
| 789 | FGT_HFGWTR = FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT), |
| 790 | FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), |
| 791 | FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), |
| 792 | FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), |
| 793 | FGT_FGWTE3 = FGT_W | (FGTREG_FGWTE3 << R_FGT_IDX_SHIFT), |
| 794 | |
| 795 | /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */ |
| 796 | DO_BIT(HFGRTR, AFSR0_EL1), |
| 797 | DO_BIT(HFGRTR, AFSR1_EL1), |
| 798 | DO_BIT(HFGRTR, AIDR_EL1), |
| 799 | DO_BIT(HFGRTR, AMAIR_EL1), |
| 800 | DO_BIT(HFGRTR, APDAKEY), |
| 801 | DO_BIT(HFGRTR, APDBKEY), |
| 802 | DO_BIT(HFGRTR, APGAKEY), |
| 803 | DO_BIT(HFGRTR, APIAKEY), |
| 804 | DO_BIT(HFGRTR, APIBKEY), |
| 805 | DO_BIT(HFGRTR, CCSIDR_EL1), |
| 806 | DO_BIT(HFGRTR, CLIDR_EL1), |
| 807 | DO_BIT(HFGRTR, CONTEXTIDR_EL1), |
| 808 | DO_BIT(HFGRTR, CPACR_EL1), |
| 809 | DO_BIT(HFGRTR, CSSELR_EL1), |
| 810 | DO_BIT(HFGRTR, CTR_EL0), |
| 811 | DO_BIT(HFGRTR, DCZID_EL0), |
| 812 | DO_BIT(HFGRTR, ESR_EL1), |
| 813 | DO_BIT(HFGRTR, FAR_EL1), |
| 814 | DO_BIT(HFGRTR, ISR_EL1), |
| 815 | DO_BIT(HFGRTR, LORC_EL1), |
| 816 | DO_BIT(HFGRTR, LOREA_EL1), |
| 817 | DO_BIT(HFGRTR, LORID_EL1), |
| 818 | DO_BIT(HFGRTR, LORN_EL1), |
| 819 | DO_BIT(HFGRTR, LORSA_EL1), |
| 820 | DO_BIT(HFGRTR, MAIR_EL1), |
| 821 | DO_BIT(HFGRTR, MIDR_EL1), |
| 822 | DO_BIT(HFGRTR, MPIDR_EL1), |
| 823 | DO_BIT(HFGRTR, PAR_EL1), |
| 824 | DO_BIT(HFGRTR, REVIDR_EL1), |
| 825 | DO_BIT(HFGRTR, SCTLR_EL1), |
| 826 | DO_BIT(HFGRTR, SCXTNUM_EL1), |
| 827 | DO_BIT(HFGRTR, SCXTNUM_EL0), |
| 828 | DO_BIT(HFGRTR, TCR_EL1), |
| 829 | DO_BIT(HFGRTR, TPIDR_EL1), |
| 830 | DO_BIT(HFGRTR, TPIDRRO_EL0), |
| 831 | DO_BIT(HFGRTR, TPIDR_EL0), |
| 832 | DO_BIT(HFGRTR, TTBR0_EL1), |
| 833 | DO_BIT(HFGRTR, TTBR1_EL1), |
| 834 | DO_BIT(HFGRTR, VBAR_EL1), |
| 835 | DO_BIT(HFGRTR, ICC_IGRPENN_EL1), |
| 836 | DO_BIT(HFGRTR, ERRIDR_EL1), |
| 837 | DO_REV_BIT(HFGRTR, NGCS_EL0), |
| 838 | DO_REV_BIT(HFGRTR, NGCS_EL1), |
| 839 | DO_REV_BIT(HFGRTR, NSMPRI_EL1), |
| 840 | DO_REV_BIT(HFGRTR, NTPIDR2_EL0), |
| 841 | DO_REV_BIT(HFGRTR, NPIRE0_EL1), |
| 842 | DO_REV_BIT(HFGRTR, NPIR_EL1), |
| 843 | DO_REV_BIT(HFGRTR, NMAIR2_EL1), |
| 844 | DO_REV_BIT(HFGRTR, NAMAIR2_EL1), |
| 845 | |
| 846 | /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */ |
| 847 | DO_BIT(HDFGRTR, DBGBCRN_EL1), |
| 848 | DO_BIT(HDFGRTR, DBGBVRN_EL1), |
| 849 | DO_BIT(HDFGRTR, DBGWCRN_EL1), |
| 850 | DO_BIT(HDFGRTR, DBGWVRN_EL1), |
| 851 | DO_BIT(HDFGRTR, MDSCR_EL1), |
| 852 | DO_BIT(HDFGRTR, DBGCLAIM), |
| 853 | DO_BIT(HDFGWTR, OSLAR_EL1), |
| 854 | DO_BIT(HDFGRTR, OSLSR_EL1), |
| 855 | DO_BIT(HDFGRTR, OSECCR_EL1), |
| 856 | DO_BIT(HDFGRTR, OSDLR_EL1), |
| 857 | DO_BIT(HDFGRTR, PMEVCNTRN_EL0), |
| 858 | DO_BIT(HDFGRTR, PMEVTYPERN_EL0), |
| 859 | DO_BIT(HDFGRTR, PMCCFILTR_EL0), |
| 860 | DO_BIT(HDFGRTR, PMCCNTR_EL0), |
| 861 | DO_BIT(HDFGRTR, PMCNTEN), |
| 862 | DO_BIT(HDFGRTR, PMINTEN), |
| 863 | DO_BIT(HDFGRTR, PMOVS), |
| 864 | DO_BIT(HDFGRTR, PMSELR_EL0), |
| 865 | DO_BIT(HDFGWTR, PMSWINC_EL0), |
| 866 | DO_BIT(HDFGWTR, PMCR_EL0), |
| 867 | DO_BIT(HDFGRTR, PMMIR_EL1), |
| 868 | DO_BIT(HDFGRTR, PMCEIDN_EL0), |
| 869 | |
| 870 | /* Trap bits in HFGITR_EL2, starting from bit 0 */ |
| 871 | DO_BIT(HFGITR, ICIALLUIS), |
| 872 | DO_BIT(HFGITR, ICIALLU), |
| 873 | DO_BIT(HFGITR, ICIVAU), |
| 874 | DO_BIT(HFGITR, DCIVAC), |
| 875 | DO_BIT(HFGITR, DCISW), |
| 876 | DO_BIT(HFGITR, DCCSW), |
| 877 | DO_BIT(HFGITR, DCCISW), |
| 878 | DO_BIT(HFGITR, DCCVAU), |
| 879 | DO_BIT(HFGITR, DCCVAP), |
| 880 | DO_BIT(HFGITR, DCCVADP), |
| 881 | DO_BIT(HFGITR, DCCIVAC), |
| 882 | DO_BIT(HFGITR, DCZVA), |
| 883 | DO_BIT(HFGITR, ATS1E1R), |
| 884 | DO_BIT(HFGITR, ATS1E1W), |
| 885 | DO_BIT(HFGITR, ATS1E0R), |
| 886 | DO_BIT(HFGITR, ATS1E0W), |
| 887 | DO_BIT(HFGITR, ATS1E1RP), |
| 888 | DO_BIT(HFGITR, ATS1E1WP), |
| 889 | DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1OS), |
| 890 | DO_TLBINXS_BIT(HFGITR, TLBIVAE1OS), |
| 891 | DO_TLBINXS_BIT(HFGITR, TLBIASIDE1OS), |
| 892 | DO_TLBINXS_BIT(HFGITR, TLBIVAAE1OS), |
| 893 | DO_TLBINXS_BIT(HFGITR, TLBIVALE1OS), |
| 894 | DO_TLBINXS_BIT(HFGITR, TLBIVAALE1OS), |
| 895 | DO_TLBINXS_BIT(HFGITR, TLBIRVAE1OS), |
| 896 | DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1OS), |
| 897 | DO_TLBINXS_BIT(HFGITR, TLBIRVALE1OS), |
| 898 | DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1OS), |
| 899 | DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1IS), |
| 900 | DO_TLBINXS_BIT(HFGITR, TLBIVAE1IS), |
| 901 | DO_TLBINXS_BIT(HFGITR, TLBIASIDE1IS), |
| 902 | DO_TLBINXS_BIT(HFGITR, TLBIVAAE1IS), |
| 903 | DO_TLBINXS_BIT(HFGITR, TLBIVALE1IS), |
| 904 | DO_TLBINXS_BIT(HFGITR, TLBIVAALE1IS), |
| 905 | DO_TLBINXS_BIT(HFGITR, TLBIRVAE1IS), |
| 906 | DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1IS), |
| 907 | DO_TLBINXS_BIT(HFGITR, TLBIRVALE1IS), |
| 908 | DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1IS), |
| 909 | DO_TLBINXS_BIT(HFGITR, TLBIRVAE1), |
| 910 | DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1), |
| 911 | DO_TLBINXS_BIT(HFGITR, TLBIRVALE1), |
| 912 | DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1), |
| 913 | DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1), |
| 914 | DO_TLBINXS_BIT(HFGITR, TLBIVAE1), |
| 915 | DO_TLBINXS_BIT(HFGITR, TLBIASIDE1), |
| 916 | DO_TLBINXS_BIT(HFGITR, TLBIVAAE1), |
| 917 | DO_TLBINXS_BIT(HFGITR, TLBIVALE1), |
| 918 | DO_TLBINXS_BIT(HFGITR, TLBIVAALE1), |
| 919 | DO_BIT(HFGITR, CFPRCTX), |
| 920 | DO_BIT(HFGITR, DVPRCTX), |
| 921 | DO_BIT(HFGITR, CPPRCTX), |
| 922 | DO_BIT(HFGITR, DCCVAC), |
| 923 | DO_REV_BIT(HFGITR, NGCSPUSHM_EL1), |
| 924 | DO_REV_BIT(HFGITR, NGCSEPP), |
| 925 | DO_BIT(HFGITR, ATS1E1A), |
| 926 | |
| 927 | /* Trap bits in FGWTE3_EL3, starting from bit 0 */ |
| 928 | DO_EL3_BIT(FGWTE3, ACTLR_EL3), |
| 929 | DO_EL3_BIT(FGWTE3, AFSR0_EL3), |
| 930 | DO_EL3_BIT(FGWTE3, AFSR1_EL3), |
| 931 | DO_EL3_BIT(FGWTE3, AMAIR_EL3), |
| 932 | DO_EL3_BIT(FGWTE3, AMAIR2_EL3), |
| 933 | DO_EL3_BIT(FGWTE3, GCSCR_EL3), |
| 934 | DO_EL3_BIT(FGWTE3, GCSPR_EL3), |
| 935 | DO_EL3_BIT(FGWTE3, GPCCR_EL3), |
| 936 | DO_EL3_BIT(FGWTE3, GPTBR_EL3), |
| 937 | DO_EL3_BIT(FGWTE3, MAIR_EL3), |
| 938 | DO_EL3_BIT(FGWTE3, MAIR2_EL3), |
| 939 | DO_EL3_BIT(FGWTE3, MDCR_EL3), |
| 940 | DO_EL3_BIT(FGWTE3, MECID_RL_A_EL3), |
| 941 | DO_EL3_BIT(FGWTE3, MPAM3_EL3), |
| 942 | DO_EL3_BIT(FGWTE3, PIR_EL3), |
| 943 | DO_EL3_BIT(FGWTE3, SCTLR_EL3), |
| 944 | DO_EL3_BIT(FGWTE3, SCTLR2_EL3), |
| 945 | DO_EL3_BIT(FGWTE3, SPMROOTCR_EL3), |
| 946 | DO_EL3_BIT(FGWTE3, TCR_EL3), |
| 947 | DO_EL3_BIT(FGWTE3, TPIDR_EL3), |
| 948 | DO_EL3_BIT(FGWTE3, TTBR0_EL3), |
| 949 | DO_EL3_BIT(FGWTE3, VBAR_EL3), |
| 950 | DO_EL3_BIT(FGWTE3, GPCBW_EL3), |
| 951 | } FGTBit; |
| 952 | |
| 953 | #undef DO_BIT |
| 954 | #undef DO_EL3_BIT |
| 955 | #undef DO_REV_BIT |
| 956 | #undef DO_TLBINXS_BIT |
| 957 | |
| 958 | typedef struct ARMCPRegInfo ARMCPRegInfo; |
| 959 | |
| 960 | /* |
| 961 | * Access functions for coprocessor registers. These cannot fail and |
| 962 | * may not raise exceptions. |
| 963 | */ |
| 964 | typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *ri); |
| 965 | typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *ri, |
| 966 | uint64_t value); |
| 967 | /* Access permission check functions for coprocessor registers. */ |
| 968 | typedef CPAccessResult CPAccessFn(CPUARMState *env, |
| 969 | const ARMCPRegInfo *ri, |
| 970 | bool isread); |
| 971 | /* Hook function for register reset */ |
| 972 | typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *ri); |
| 973 | |
| 974 | #define CP_ANY 0xff |
| 975 | |
| 976 | /* Flags in the high bits of nv2_redirect_offset */ |
| 977 | #define NV2_REDIR_NV1 0x4000 /* Only redirect when HCR_EL2.NV1 == 1 */ |
| 978 | #define NV2_REDIR_NO_NV1 0x8000 /* Only redirect when HCR_EL2.NV1 == 0 */ |
| 979 | #define NV2_REDIR_FLAG_MASK 0xc000 |
| 980 | |
| 981 | /* Definition of an ARM coprocessor register */ |
| 982 | struct ARMCPRegInfo { |
| 983 | /* Name of register (useful mainly for debugging, need not be unique) */ |
| 984 | const char *name; |
| 985 | /* |
| 986 | * Location of register: coprocessor number and (crn,crm,opc1,opc2) |
| 987 | * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a |
| 988 | * 'wildcard' field -- any value of that field in the MRC/MCR insn |
| 989 | * will be decoded to this register. The register read and write |
| 990 | * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 |
| 991 | * used by the program, so it is possible to register a wildcard and |
| 992 | * then behave differently on read/write if necessary. |
| 993 | * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 |
| 994 | * must both be zero. |
| 995 | * For AArch64-visible registers, opc0 is also used. |
| 996 | * Since there are no "coprocessors" in AArch64, cp is purely used as a |
| 997 | * way to distinguish (for KVM's benefit) guest-visible system registers |
| 998 | * from demuxed ones provided to preserve the "no side effects on |
| 999 | * KVM register read/write from QEMU" semantics. cp==0x13 is guest |
| 1000 | * visible (to match KVM's encoding); cp==0 will be converted to |
| 1001 | * cp==0x13 when the ARMCPRegInfo is registered, for convenience. |
| 1002 | */ |
| 1003 | uint8_t cp; |
| 1004 | uint8_t crn; |
| 1005 | uint8_t crm; |
| 1006 | uint8_t opc0; |
| 1007 | uint8_t opc1; |
| 1008 | uint8_t opc2; |
| 1009 | /* Execution state in which this register is visible: ARM_CP_STATE_* */ |
| 1010 | CPState state; |
| 1011 | /* Register type: ARM_CP_* bits/values */ |
| 1012 | int type; |
| 1013 | /* Access rights: PL*_[RW] */ |
| 1014 | CPAccessRights access; |
| 1015 | /* Security state: ARM_CP_SECSTATE_* bits/values */ |
| 1016 | CPSecureState secure; |
| 1017 | /* |
| 1018 | * Which fine-grained trap register bit to check, if any. This |
| 1019 | * value encodes both the trap register and bit within it. |
| 1020 | */ |
| 1021 | FGTBit fgt; |
| 1022 | |
| 1023 | /* |
| 1024 | * Offset from VNCR_EL2 when FEAT_NV2 redirects access to memory; |
| 1025 | * may include an NV2_REDIR_* flag. |
| 1026 | */ |
| 1027 | uint32_t nv2_redirect_offset; |
| 1028 | |
| 1029 | /* |
| 1030 | * With VHE, with E2H, at EL2, access to this EL0/EL1 reg redirects |
| 1031 | * to the EL2 reg with the specified key. |
| 1032 | */ |
| 1033 | uint32_t vhe_redir_to_el2; |
| 1034 | |
| 1035 | /* |
| 1036 | * For VHE. Before registration, this field holds the key for an |
| 1037 | * EL02/EL12 reg to be created to point back to this EL0/EL1 reg. |
| 1038 | * After registration, this field is set only on the EL02/EL12 reg |
| 1039 | * and points back to the EL02/EL12 reg for redirection with E2H. |
| 1040 | */ |
| 1041 | uint32_t vhe_redir_to_el01; |
| 1042 | |
| 1043 | /* |
| 1044 | * Value of this register, if it is ARM_CP_CONST. Otherwise, if |
| 1045 | * fieldoffset is non-zero, the reset value of the register. |
| 1046 | */ |
| 1047 | uint64_t resetvalue; |
| 1048 | /* |
| 1049 | * Offset of the field in CPUARMState for this register. |
| 1050 | * This is not needed if either: |
| 1051 | * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs |
| 1052 | * 2. both readfn and writefn are specified |
| 1053 | */ |
| 1054 | ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ |
| 1055 | |
| 1056 | /* |
| 1057 | * Offsets of the secure and non-secure fields in CPUARMState for the |
| 1058 | * register if it is banked. These fields are only used during the static |
| 1059 | * registration of a register. During hashing the bank associated |
| 1060 | * with a given security state is copied to fieldoffset which is used from |
| 1061 | * there on out. |
| 1062 | * |
| 1063 | * It is expected that register definitions use either fieldoffset or |
| 1064 | * bank_fieldoffsets in the definition but not both. It is also expected |
| 1065 | * that both bank offsets are set when defining a banked register. This |
| 1066 | * use indicates that a register is banked. |
| 1067 | */ |
| 1068 | ptrdiff_t bank_fieldoffsets[2]; |
| 1069 | |
| 1070 | /* |
| 1071 | * Function for making any access checks for this register in addition to |
| 1072 | * those specified by the 'access' permissions bits. If NULL, no extra |
| 1073 | * checks required. The access check is performed at runtime, not at |
| 1074 | * translate time. |
| 1075 | */ |
| 1076 | CPAccessFn *accessfn; |
| 1077 | /* |
| 1078 | * Function for handling reads of this register. If NULL, then reads |
| 1079 | * will be done by loading from the offset into CPUARMState specified |
| 1080 | * by fieldoffset. |
| 1081 | */ |
| 1082 | CPReadFn *readfn; |
| 1083 | /* |
| 1084 | * Function for handling writes of this register. If NULL, then writes |
| 1085 | * will be done by writing to the offset into CPUARMState specified |
| 1086 | * by fieldoffset. |
| 1087 | */ |
| 1088 | CPWriteFn *writefn; |
| 1089 | /* |
| 1090 | * Function for doing a "raw" read; used when we need to copy |
| 1091 | * coprocessor state to the kernel for KVM or out for |
| 1092 | * migration. This only needs to be provided if there is also a |
| 1093 | * readfn and it has side effects (for instance clear-on-read bits). |
| 1094 | */ |
| 1095 | CPReadFn *raw_readfn; |
| 1096 | /* |
| 1097 | * Function for doing a "raw" write; used when we need to copy KVM |
| 1098 | * kernel coprocessor state into userspace, or for inbound |
| 1099 | * migration. This only needs to be provided if there is also a |
| 1100 | * writefn and it masks out "unwritable" bits or has write-one-to-clear |
| 1101 | * or similar behaviour. |
| 1102 | */ |
| 1103 | CPWriteFn *raw_writefn; |
| 1104 | /* |
| 1105 | * Function for resetting the register. If NULL, then reset will be done |
| 1106 | * by writing resetvalue to the field specified in fieldoffset. If |
| 1107 | * fieldoffset is 0 then no reset will be done. |
| 1108 | */ |
| 1109 | CPResetFn *resetfn; |
| 1110 | }; |
| 1111 | |
| 1112 | void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs); |
| 1113 | void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t len); |
| 1114 | |
| 1115 | #define define_arm_cp_regs(CPU, REGS) \ |
| 1116 | do { \ |
| 1117 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ |
| 1118 | define_arm_cp_regs_len(CPU, REGS, ARRAY_SIZE(REGS)); \ |
| 1119 | } while (0) |
| 1120 | |
| 1121 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); |
| 1122 | |
| 1123 | /* |
| 1124 | * Definition of an ARM co-processor register as viewed from |
| 1125 | * userspace. This is used for presenting sanitised versions of |
| 1126 | * registers to userspace when emulating the Linux AArch64 CPU |
| 1127 | * ID/feature ABI (advertised as HWCAP_CPUID). |
| 1128 | */ |
| 1129 | typedef struct ARMCPRegUserSpaceInfo { |
| 1130 | /* Name of register */ |
| 1131 | const char *name; |
| 1132 | |
| 1133 | /* Is the name actually a glob pattern */ |
| 1134 | bool is_glob; |
| 1135 | |
| 1136 | /* Only some bits are exported to user space */ |
| 1137 | uint64_t exported_bits; |
| 1138 | |
| 1139 | /* Fixed bits are applied after the mask */ |
| 1140 | uint64_t fixed_bits; |
| 1141 | } ARMCPRegUserSpaceInfo; |
| 1142 | |
| 1143 | void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, |
| 1144 | const ARMCPRegUserSpaceInfo *mods, |
| 1145 | size_t mods_len); |
| 1146 | |
| 1147 | #define modify_arm_cp_regs(REGS, MODS) \ |
| 1148 | do { \ |
| 1149 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ |
| 1150 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0); \ |
| 1151 | modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \ |
| 1152 | MODS, ARRAY_SIZE(MODS)); \ |
| 1153 | } while (0) |
| 1154 | |
| 1155 | /* CPWriteFn that can be used to implement writes-ignored behaviour */ |
| 1156 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
| 1157 | uint64_t value); |
| 1158 | /* CPReadFn that can be used for read-as-zero behaviour */ |
| 1159 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); |
| 1160 | |
| 1161 | /* CPReadFn that just reads the value from ri->fieldoffset */ |
| 1162 | uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri); |
| 1163 | |
| 1164 | /* CPWriteFn that just writes the value to ri->fieldoffset */ |
| 1165 | void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); |
| 1166 | |
| 1167 | /* |
| 1168 | * CPResetFn that does nothing, for use if no reset is required even |
| 1169 | * if fieldoffset is non zero. |
| 1170 | */ |
| 1171 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri); |
| 1172 | |
| 1173 | /* |
| 1174 | * Return MO_32 if the field in CPUARMState is uint32_t or |
| 1175 | * MO_64 if the field in CPUARMState is uint64_t. |
| 1176 | */ |
| 1177 | static inline MemOp cpreg_field_type(const ARMCPRegInfo *ri) |
| 1178 | { |
| 1179 | return (ri->state == ARM_CP_STATE_AA64 || (ri->type & ARM_CP_64BIT) |
| 1180 | ? MO_64 : MO_32); |
| 1181 | } |
| 1182 | |
| 1183 | static inline bool cp_access_ok(int current_el, |
| 1184 | const ARMCPRegInfo *ri, int isread) |
| 1185 | { |
| 1186 | return (ri->access >> ((current_el * 2) + isread)) & 1; |
| 1187 | } |
| 1188 | |
| 1189 | /* Raw read of a coprocessor register (as needed for migration, etc) */ |
| 1190 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); |
| 1191 | |
| 1192 | /* |
| 1193 | * Return true if the cp register encoding is in the "feature ID space" as |
| 1194 | * defined by FEAT_IDST (and thus should be reported with ER_ELx.EC |
| 1195 | * as EC_SYSTEMREGISTERTRAP rather than EC_UNCATEGORIZED). |
| 1196 | */ |
| 1197 | static inline bool arm_cpreg_encoding_in_idspace(uint8_t opc0, uint8_t opc1, |
| 1198 | uint8_t opc2, |
| 1199 | uint8_t crn, uint8_t crm) |
| 1200 | { |
| 1201 | return opc0 == 3 && (opc1 == 0 || opc1 == 1 || opc1 == 3) && |
| 1202 | crn == 0 && crm < 8; |
| 1203 | } |
| 1204 | |
| 1205 | /* |
| 1206 | * As arm_cpreg_encoding_in_idspace(), but take the encoding from an |
| 1207 | * ARMCPRegInfo. |
| 1208 | */ |
| 1209 | static inline bool arm_cpreg_in_idspace(const ARMCPRegInfo *ri) |
| 1210 | { |
| 1211 | return ri->state == ARM_CP_STATE_AA64 && |
| 1212 | arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2, |
| 1213 | ri->crn, ri->crm); |
| 1214 | } |
| 1215 | |
| 1216 | #ifdef CONFIG_USER_ONLY |
| 1217 | static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } |
| 1218 | #else |
| 1219 | void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); |
| 1220 | #endif |
| 1221 | |
| 1222 | CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool); |
| 1223 | |
| 1224 | /** |
| 1225 | * arm_cpreg_trap_in_nv: Return true if cpreg traps in nested virtualization |
| 1226 | * |
| 1227 | * Return true if this cpreg is one which should be trapped to EL2 if |
| 1228 | * it is executed at EL1 when nested virtualization is enabled via HCR_EL2.NV. |
| 1229 | */ |
| 1230 | static inline bool arm_cpreg_traps_in_nv(const ARMCPRegInfo *ri) |
| 1231 | { |
| 1232 | /* |
| 1233 | * The Arm ARM defines the registers to be trapped in terms of |
| 1234 | * their names (I_TZTZL). However the underlying principle is "if |
| 1235 | * it would UNDEF at EL1 but work at EL2 then it should trap", and |
| 1236 | * the way the encoding of sysregs and system instructions is done |
| 1237 | * means that the right set of registers is exactly those where |
| 1238 | * the opc1 field is 4 or 5. (You can see this also in the assert |
| 1239 | * we do that the opc1 field and the permissions mask line up in |
| 1240 | * define_one_arm_cp_reg().) |
| 1241 | * Checking the opc1 field is easier for us and avoids the problem |
| 1242 | * that we do not consistently use the right architectural names |
| 1243 | * for all sysregs, since we treat the name field as largely for debug. |
| 1244 | * |
| 1245 | * However we do this check, it is going to be at least potentially |
| 1246 | * fragile to future new sysregs, but this seems the least likely |
| 1247 | * to break. |
| 1248 | * |
| 1249 | * In particular, note that the FEAT_MEC sysregs and instructions |
| 1250 | * are exceptions to this trapping rule, so they are marked as |
| 1251 | * ARM_CP_NV_NO_TRAP to indicate that they should not be trapped |
| 1252 | * to EL2. (They are an exception because the FEAT_MEC sysregs UNDEF |
| 1253 | * unless in Realm, and Realm is not expected to be virtualized.) |
| 1254 | */ |
| 1255 | |
| 1256 | if (ri->type & ARM_CP_NV_NO_TRAP) { |
| 1257 | return false; |
| 1258 | } |
| 1259 | |
| 1260 | return ri->opc1 == 4 || ri->opc1 == 5; |
| 1261 | } |
| 1262 | |
| 1263 | /* Macros for accessing a specified CP register bank */ |
| 1264 | #define A32_BANKED_REG_GET(_env, _regname, _secure) \ |
| 1265 | ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) |
| 1266 | |
| 1267 | #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ |
| 1268 | do { \ |
| 1269 | if (_secure) { \ |
| 1270 | (_env)->cp15._regname##_s = (_val); \ |
| 1271 | } else { \ |
| 1272 | (_env)->cp15._regname##_ns = (_val); \ |
| 1273 | } \ |
| 1274 | } while (0) |
| 1275 | |
| 1276 | /* |
| 1277 | * Macros for automatically accessing a specific CP register bank depending on |
| 1278 | * the current secure state of the system. These macros are not intended for |
| 1279 | * supporting instruction translation reads/writes as these are dependent |
| 1280 | * solely on the SCR.NS bit and not the mode. |
| 1281 | */ |
| 1282 | #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ |
| 1283 | A32_BANKED_REG_GET((_env), _regname, \ |
| 1284 | (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) |
| 1285 | |
| 1286 | #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ |
| 1287 | A32_BANKED_REG_SET((_env), _regname, \ |
| 1288 | (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ |
| 1289 | (_val)) |
| 1290 | |
| 1291 | #endif /* TARGET_ARM_CPREGS_H */ |