| 1 | /* |
| 2 | * QEMU Arm CPU -- feature test functions |
| 3 | * |
| 4 | * Copyright (c) 2023 Linaro Ltd |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef TARGET_ARM_FEATURES_H |
| 21 | #define TARGET_ARM_FEATURES_H |
| 22 | |
| 23 | #include "hw/core/registerfields.h" |
| 24 | #include "qemu/host-utils.h" |
| 25 | #include "cpu.h" |
| 26 | #include "cpu-sysregs.h" |
| 27 | |
| 28 | /* |
| 29 | * System register ID fields. |
| 30 | */ |
| 31 | FIELD(CLIDR_EL1, CTYPE1, 0, 3) |
| 32 | FIELD(CLIDR_EL1, CTYPE2, 3, 3) |
| 33 | FIELD(CLIDR_EL1, CTYPE3, 6, 3) |
| 34 | FIELD(CLIDR_EL1, CTYPE4, 9, 3) |
| 35 | FIELD(CLIDR_EL1, CTYPE5, 12, 3) |
| 36 | FIELD(CLIDR_EL1, CTYPE6, 15, 3) |
| 37 | FIELD(CLIDR_EL1, CTYPE7, 18, 3) |
| 38 | FIELD(CLIDR_EL1, LOUIS, 21, 3) |
| 39 | FIELD(CLIDR_EL1, LOC, 24, 3) |
| 40 | FIELD(CLIDR_EL1, LOUU, 27, 3) |
| 41 | FIELD(CLIDR_EL1, ICB, 30, 3) |
| 42 | |
| 43 | /* When FEAT_CCIDX is implemented */ |
| 44 | FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) |
| 45 | FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) |
| 46 | FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) |
| 47 | |
| 48 | /* When FEAT_CCIDX is not implemented */ |
| 49 | FIELD(CCSIDR_EL1, LINESIZE, 0, 3) |
| 50 | FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) |
| 51 | FIELD(CCSIDR_EL1, NUMSETS, 13, 15) |
| 52 | |
| 53 | FIELD(CTR_EL0, IMINLINE, 0, 4) |
| 54 | FIELD(CTR_EL0, L1IP, 14, 2) |
| 55 | FIELD(CTR_EL0, DMINLINE, 16, 4) |
| 56 | FIELD(CTR_EL0, ERG, 20, 4) |
| 57 | FIELD(CTR_EL0, CWG, 24, 4) |
| 58 | FIELD(CTR_EL0, IDC, 28, 1) |
| 59 | FIELD(CTR_EL0, DIC, 29, 1) |
| 60 | FIELD(CTR_EL0, TMINLINE, 32, 6) |
| 61 | |
| 62 | FIELD(MIDR_EL1, REVISION, 0, 4) |
| 63 | FIELD(MIDR_EL1, PARTNUM, 4, 12) |
| 64 | FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) |
| 65 | FIELD(MIDR_EL1, VARIANT, 20, 4) |
| 66 | FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) |
| 67 | |
| 68 | FIELD(ID_ISAR0, SWAP, 0, 4) |
| 69 | FIELD(ID_ISAR0, BITCOUNT, 4, 4) |
| 70 | FIELD(ID_ISAR0, BITFIELD, 8, 4) |
| 71 | FIELD(ID_ISAR0, CMPBRANCH, 12, 4) |
| 72 | FIELD(ID_ISAR0, COPROC, 16, 4) |
| 73 | FIELD(ID_ISAR0, DEBUG, 20, 4) |
| 74 | FIELD(ID_ISAR0, DIVIDE, 24, 4) |
| 75 | |
| 76 | FIELD(ID_ISAR1, ENDIAN, 0, 4) |
| 77 | FIELD(ID_ISAR1, EXCEPT, 4, 4) |
| 78 | FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) |
| 79 | FIELD(ID_ISAR1, EXTEND, 12, 4) |
| 80 | FIELD(ID_ISAR1, IFTHEN, 16, 4) |
| 81 | FIELD(ID_ISAR1, IMMEDIATE, 20, 4) |
| 82 | FIELD(ID_ISAR1, INTERWORK, 24, 4) |
| 83 | FIELD(ID_ISAR1, JAZELLE, 28, 4) |
| 84 | |
| 85 | FIELD(ID_ISAR2, LOADSTORE, 0, 4) |
| 86 | FIELD(ID_ISAR2, MEMHINT, 4, 4) |
| 87 | FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) |
| 88 | FIELD(ID_ISAR2, MULT, 12, 4) |
| 89 | FIELD(ID_ISAR2, MULTS, 16, 4) |
| 90 | FIELD(ID_ISAR2, MULTU, 20, 4) |
| 91 | FIELD(ID_ISAR2, PSR_AR, 24, 4) |
| 92 | FIELD(ID_ISAR2, REVERSAL, 28, 4) |
| 93 | |
| 94 | FIELD(ID_ISAR3, SATURATE, 0, 4) |
| 95 | FIELD(ID_ISAR3, SIMD, 4, 4) |
| 96 | FIELD(ID_ISAR3, SVC, 8, 4) |
| 97 | FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) |
| 98 | FIELD(ID_ISAR3, TABBRANCH, 16, 4) |
| 99 | FIELD(ID_ISAR3, T32COPY, 20, 4) |
| 100 | FIELD(ID_ISAR3, TRUENOP, 24, 4) |
| 101 | FIELD(ID_ISAR3, T32EE, 28, 4) |
| 102 | |
| 103 | FIELD(ID_ISAR4, UNPRIV, 0, 4) |
| 104 | FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) |
| 105 | FIELD(ID_ISAR4, WRITEBACK, 8, 4) |
| 106 | FIELD(ID_ISAR4, SMC, 12, 4) |
| 107 | FIELD(ID_ISAR4, BARRIER, 16, 4) |
| 108 | FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) |
| 109 | FIELD(ID_ISAR4, PSR_M, 24, 4) |
| 110 | FIELD(ID_ISAR4, SWP_FRAC, 28, 4) |
| 111 | |
| 112 | FIELD(ID_ISAR5, SEVL, 0, 4) |
| 113 | FIELD(ID_ISAR5, AES, 4, 4) |
| 114 | FIELD(ID_ISAR5, SHA1, 8, 4) |
| 115 | FIELD(ID_ISAR5, SHA2, 12, 4) |
| 116 | FIELD(ID_ISAR5, CRC32, 16, 4) |
| 117 | FIELD(ID_ISAR5, RDM, 24, 4) |
| 118 | FIELD(ID_ISAR5, VCMA, 28, 4) |
| 119 | |
| 120 | FIELD(ID_ISAR6, JSCVT, 0, 4) |
| 121 | FIELD(ID_ISAR6, DP, 4, 4) |
| 122 | FIELD(ID_ISAR6, FHM, 8, 4) |
| 123 | FIELD(ID_ISAR6, SB, 12, 4) |
| 124 | FIELD(ID_ISAR6, SPECRES, 16, 4) |
| 125 | FIELD(ID_ISAR6, BF16, 20, 4) |
| 126 | FIELD(ID_ISAR6, I8MM, 24, 4) |
| 127 | |
| 128 | FIELD(ID_MMFR0, VMSA, 0, 4) |
| 129 | FIELD(ID_MMFR0, PMSA, 4, 4) |
| 130 | FIELD(ID_MMFR0, OUTERSHR, 8, 4) |
| 131 | FIELD(ID_MMFR0, SHARELVL, 12, 4) |
| 132 | FIELD(ID_MMFR0, TCM, 16, 4) |
| 133 | FIELD(ID_MMFR0, AUXREG, 20, 4) |
| 134 | FIELD(ID_MMFR0, FCSE, 24, 4) |
| 135 | FIELD(ID_MMFR0, INNERSHR, 28, 4) |
| 136 | |
| 137 | FIELD(ID_MMFR1, L1HVDVA, 0, 4) |
| 138 | FIELD(ID_MMFR1, L1UNIVA, 4, 4) |
| 139 | FIELD(ID_MMFR1, L1HVDSW, 8, 4) |
| 140 | FIELD(ID_MMFR1, L1UNISW, 12, 4) |
| 141 | FIELD(ID_MMFR1, L1HVD, 16, 4) |
| 142 | FIELD(ID_MMFR1, L1UNI, 20, 4) |
| 143 | FIELD(ID_MMFR1, L1TSTCLN, 24, 4) |
| 144 | FIELD(ID_MMFR1, BPRED, 28, 4) |
| 145 | |
| 146 | FIELD(ID_MMFR2, L1HVDFG, 0, 4) |
| 147 | FIELD(ID_MMFR2, L1HVDBG, 4, 4) |
| 148 | FIELD(ID_MMFR2, L1HVDRNG, 8, 4) |
| 149 | FIELD(ID_MMFR2, HVDTLB, 12, 4) |
| 150 | FIELD(ID_MMFR2, UNITLB, 16, 4) |
| 151 | FIELD(ID_MMFR2, MEMBARR, 20, 4) |
| 152 | FIELD(ID_MMFR2, WFISTALL, 24, 4) |
| 153 | FIELD(ID_MMFR2, HWACCFLG, 28, 4) |
| 154 | |
| 155 | FIELD(ID_MMFR3, CMAINTVA, 0, 4) |
| 156 | FIELD(ID_MMFR3, CMAINTSW, 4, 4) |
| 157 | FIELD(ID_MMFR3, BPMAINT, 8, 4) |
| 158 | FIELD(ID_MMFR3, MAINTBCST, 12, 4) |
| 159 | FIELD(ID_MMFR3, PAN, 16, 4) |
| 160 | FIELD(ID_MMFR3, COHWALK, 20, 4) |
| 161 | FIELD(ID_MMFR3, CMEMSZ, 24, 4) |
| 162 | FIELD(ID_MMFR3, SUPERSEC, 28, 4) |
| 163 | |
| 164 | FIELD(ID_MMFR4, SPECSEI, 0, 4) |
| 165 | FIELD(ID_MMFR4, AC2, 4, 4) |
| 166 | FIELD(ID_MMFR4, XNX, 8, 4) |
| 167 | FIELD(ID_MMFR4, CNP, 12, 4) |
| 168 | FIELD(ID_MMFR4, HPDS, 16, 4) |
| 169 | FIELD(ID_MMFR4, LSM, 20, 4) |
| 170 | FIELD(ID_MMFR4, CCIDX, 24, 4) |
| 171 | FIELD(ID_MMFR4, EVT, 28, 4) |
| 172 | |
| 173 | FIELD(ID_MMFR5, ETS, 0, 4) |
| 174 | FIELD(ID_MMFR5, NTLBPA, 4, 4) |
| 175 | |
| 176 | FIELD(ID_PFR0, STATE0, 0, 4) |
| 177 | FIELD(ID_PFR0, STATE1, 4, 4) |
| 178 | FIELD(ID_PFR0, STATE2, 8, 4) |
| 179 | FIELD(ID_PFR0, STATE3, 12, 4) |
| 180 | FIELD(ID_PFR0, CSV2, 16, 4) |
| 181 | FIELD(ID_PFR0, AMU, 20, 4) |
| 182 | FIELD(ID_PFR0, DIT, 24, 4) |
| 183 | FIELD(ID_PFR0, RAS, 28, 4) |
| 184 | |
| 185 | FIELD(ID_PFR1, PROGMOD, 0, 4) |
| 186 | FIELD(ID_PFR1, SECURITY, 4, 4) |
| 187 | FIELD(ID_PFR1, MPROGMOD, 8, 4) |
| 188 | FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) |
| 189 | FIELD(ID_PFR1, GENTIMER, 16, 4) |
| 190 | FIELD(ID_PFR1, SEC_FRAC, 20, 4) |
| 191 | FIELD(ID_PFR1, VIRT_FRAC, 24, 4) |
| 192 | FIELD(ID_PFR1, GIC, 28, 4) |
| 193 | |
| 194 | FIELD(ID_PFR2, CSV3, 0, 4) |
| 195 | FIELD(ID_PFR2, SSBS, 4, 4) |
| 196 | FIELD(ID_PFR2, RAS_FRAC, 8, 4) |
| 197 | |
| 198 | FIELD(ID_AA64ISAR0, AES, 4, 4) |
| 199 | FIELD(ID_AA64ISAR0, SHA1, 8, 4) |
| 200 | FIELD(ID_AA64ISAR0, SHA2, 12, 4) |
| 201 | FIELD(ID_AA64ISAR0, CRC32, 16, 4) |
| 202 | FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) |
| 203 | FIELD(ID_AA64ISAR0, TME, 24, 4) |
| 204 | FIELD(ID_AA64ISAR0, RDM, 28, 4) |
| 205 | FIELD(ID_AA64ISAR0, SHA3, 32, 4) |
| 206 | FIELD(ID_AA64ISAR0, SM3, 36, 4) |
| 207 | FIELD(ID_AA64ISAR0, SM4, 40, 4) |
| 208 | FIELD(ID_AA64ISAR0, DP, 44, 4) |
| 209 | FIELD(ID_AA64ISAR0, FHM, 48, 4) |
| 210 | FIELD(ID_AA64ISAR0, TS, 52, 4) |
| 211 | FIELD(ID_AA64ISAR0, TLB, 56, 4) |
| 212 | FIELD(ID_AA64ISAR0, RNDR, 60, 4) |
| 213 | |
| 214 | FIELD(ID_AA64ISAR1, DPB, 0, 4) |
| 215 | FIELD(ID_AA64ISAR1, APA, 4, 4) |
| 216 | FIELD(ID_AA64ISAR1, API, 8, 4) |
| 217 | FIELD(ID_AA64ISAR1, JSCVT, 12, 4) |
| 218 | FIELD(ID_AA64ISAR1, FCMA, 16, 4) |
| 219 | FIELD(ID_AA64ISAR1, LRCPC, 20, 4) |
| 220 | FIELD(ID_AA64ISAR1, GPA, 24, 4) |
| 221 | FIELD(ID_AA64ISAR1, GPI, 28, 4) |
| 222 | FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) |
| 223 | FIELD(ID_AA64ISAR1, SB, 36, 4) |
| 224 | FIELD(ID_AA64ISAR1, SPECRES, 40, 4) |
| 225 | FIELD(ID_AA64ISAR1, BF16, 44, 4) |
| 226 | FIELD(ID_AA64ISAR1, DGH, 48, 4) |
| 227 | FIELD(ID_AA64ISAR1, I8MM, 52, 4) |
| 228 | FIELD(ID_AA64ISAR1, XS, 56, 4) |
| 229 | FIELD(ID_AA64ISAR1, LS64, 60, 4) |
| 230 | |
| 231 | FIELD(ID_AA64ISAR2, WFXT, 0, 4) |
| 232 | FIELD(ID_AA64ISAR2, RPRES, 4, 4) |
| 233 | FIELD(ID_AA64ISAR2, GPA3, 8, 4) |
| 234 | FIELD(ID_AA64ISAR2, APA3, 12, 4) |
| 235 | FIELD(ID_AA64ISAR2, MOPS, 16, 4) |
| 236 | FIELD(ID_AA64ISAR2, BC, 20, 4) |
| 237 | FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) |
| 238 | FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) |
| 239 | FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) |
| 240 | FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) |
| 241 | FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) |
| 242 | FIELD(ID_AA64ISAR2, RPRFM, 48, 4) |
| 243 | FIELD(ID_AA64ISAR2, CSSC, 52, 4) |
| 244 | FIELD(ID_AA64ISAR2, LUT, 56, 4) |
| 245 | FIELD(ID_AA64ISAR2, ATS1A, 60, 4) |
| 246 | |
| 247 | FIELD(ID_AA64ISAR3, CPA, 0, 4) |
| 248 | FIELD(ID_AA64ISAR3, FAMINMAX, 4, 4) |
| 249 | FIELD(ID_AA64ISAR3, TLBIW, 8, 4) |
| 250 | FIELD(ID_AA64ISAR3, PACM, 12, 4) |
| 251 | FIELD(ID_AA64ISAR3, LSFE, 16, 4) |
| 252 | FIELD(ID_AA64ISAR3, OCCMO, 20, 4) |
| 253 | FIELD(ID_AA64ISAR3, LSUI, 24, 4) |
| 254 | FIELD(ID_AA64ISAR3, FPRCVT, 28, 4) |
| 255 | |
| 256 | FIELD(ID_AA64PFR0, EL0, 0, 4) |
| 257 | FIELD(ID_AA64PFR0, EL1, 4, 4) |
| 258 | FIELD(ID_AA64PFR0, EL2, 8, 4) |
| 259 | FIELD(ID_AA64PFR0, EL3, 12, 4) |
| 260 | FIELD(ID_AA64PFR0, FP, 16, 4) |
| 261 | FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) |
| 262 | FIELD(ID_AA64PFR0, GIC, 24, 4) |
| 263 | FIELD(ID_AA64PFR0, RAS, 28, 4) |
| 264 | FIELD(ID_AA64PFR0, SVE, 32, 4) |
| 265 | FIELD(ID_AA64PFR0, SEL2, 36, 4) |
| 266 | FIELD(ID_AA64PFR0, MPAM, 40, 4) |
| 267 | FIELD(ID_AA64PFR0, AMU, 44, 4) |
| 268 | FIELD(ID_AA64PFR0, DIT, 48, 4) |
| 269 | FIELD(ID_AA64PFR0, RME, 52, 4) |
| 270 | FIELD(ID_AA64PFR0, CSV2, 56, 4) |
| 271 | FIELD(ID_AA64PFR0, CSV3, 60, 4) |
| 272 | |
| 273 | FIELD(ID_AA64PFR1, BT, 0, 4) |
| 274 | FIELD(ID_AA64PFR1, SSBS, 4, 4) |
| 275 | FIELD(ID_AA64PFR1, MTE, 8, 4) |
| 276 | FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) |
| 277 | FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) |
| 278 | FIELD(ID_AA64PFR1, SME, 24, 4) |
| 279 | FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) |
| 280 | FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) |
| 281 | FIELD(ID_AA64PFR1, NMI, 36, 4) |
| 282 | FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) |
| 283 | FIELD(ID_AA64PFR1, GCS, 44, 4) |
| 284 | FIELD(ID_AA64PFR1, THE, 48, 4) |
| 285 | FIELD(ID_AA64PFR1, MTEX, 52, 4) |
| 286 | FIELD(ID_AA64PFR1, DF2, 56, 4) |
| 287 | FIELD(ID_AA64PFR1, PFAR, 60, 4) |
| 288 | |
| 289 | FIELD(ID_AA64PFR2, MTEPERM, 0, 4) |
| 290 | FIELD(ID_AA64PFR2, MTESTOREONLY, 4, 4) |
| 291 | FIELD(ID_AA64PFR2, MTEFAR, 8, 4) |
| 292 | FIELD(ID_AA64PFR2, GCIE, 12, 4) |
| 293 | FIELD(ID_AA64PFR2, FPMR, 32, 4) |
| 294 | |
| 295 | FIELD(ID_AA64MMFR0, PARANGE, 0, 4) |
| 296 | FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) |
| 297 | FIELD(ID_AA64MMFR0, BIGEND, 8, 4) |
| 298 | FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) |
| 299 | FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) |
| 300 | FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) |
| 301 | FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) |
| 302 | FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) |
| 303 | FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) |
| 304 | FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) |
| 305 | FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) |
| 306 | FIELD(ID_AA64MMFR0, EXS, 44, 4) |
| 307 | FIELD(ID_AA64MMFR0, FGT, 56, 4) |
| 308 | FIELD(ID_AA64MMFR0, ECV, 60, 4) |
| 309 | |
| 310 | FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) |
| 311 | FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) |
| 312 | FIELD(ID_AA64MMFR1, VH, 8, 4) |
| 313 | FIELD(ID_AA64MMFR1, HPDS, 12, 4) |
| 314 | FIELD(ID_AA64MMFR1, LO, 16, 4) |
| 315 | FIELD(ID_AA64MMFR1, PAN, 20, 4) |
| 316 | FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) |
| 317 | FIELD(ID_AA64MMFR1, XNX, 28, 4) |
| 318 | FIELD(ID_AA64MMFR1, TWED, 32, 4) |
| 319 | FIELD(ID_AA64MMFR1, ETS, 36, 4) |
| 320 | FIELD(ID_AA64MMFR1, HCX, 40, 4) |
| 321 | FIELD(ID_AA64MMFR1, AFP, 44, 4) |
| 322 | FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) |
| 323 | FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) |
| 324 | FIELD(ID_AA64MMFR1, CMOW, 56, 4) |
| 325 | FIELD(ID_AA64MMFR1, ECBHB, 60, 4) |
| 326 | |
| 327 | FIELD(ID_AA64MMFR2, CNP, 0, 4) |
| 328 | FIELD(ID_AA64MMFR2, UAO, 4, 4) |
| 329 | FIELD(ID_AA64MMFR2, LSM, 8, 4) |
| 330 | FIELD(ID_AA64MMFR2, IESB, 12, 4) |
| 331 | FIELD(ID_AA64MMFR2, VARANGE, 16, 4) |
| 332 | FIELD(ID_AA64MMFR2, CCIDX, 20, 4) |
| 333 | FIELD(ID_AA64MMFR2, NV, 24, 4) |
| 334 | FIELD(ID_AA64MMFR2, ST, 28, 4) |
| 335 | FIELD(ID_AA64MMFR2, AT, 32, 4) |
| 336 | FIELD(ID_AA64MMFR2, IDS, 36, 4) |
| 337 | FIELD(ID_AA64MMFR2, FWB, 40, 4) |
| 338 | FIELD(ID_AA64MMFR2, TTL, 48, 4) |
| 339 | FIELD(ID_AA64MMFR2, BBM, 52, 4) |
| 340 | FIELD(ID_AA64MMFR2, EVT, 56, 4) |
| 341 | FIELD(ID_AA64MMFR2, E0PD, 60, 4) |
| 342 | |
| 343 | FIELD(ID_AA64MMFR3, TCRX, 0, 4) |
| 344 | FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) |
| 345 | FIELD(ID_AA64MMFR3, S1PIE, 8, 4) |
| 346 | FIELD(ID_AA64MMFR3, S2PIE, 12, 4) |
| 347 | FIELD(ID_AA64MMFR3, S1POE, 16, 4) |
| 348 | FIELD(ID_AA64MMFR3, S2POE, 20, 4) |
| 349 | FIELD(ID_AA64MMFR3, AIE, 24, 4) |
| 350 | FIELD(ID_AA64MMFR3, MEC, 28, 4) |
| 351 | FIELD(ID_AA64MMFR3, D128, 32, 4) |
| 352 | FIELD(ID_AA64MMFR3, D128_2, 36, 4) |
| 353 | FIELD(ID_AA64MMFR3, SNERR, 40, 4) |
| 354 | FIELD(ID_AA64MMFR3, ANERR, 44, 4) |
| 355 | FIELD(ID_AA64MMFR3, SDERR, 52, 4) |
| 356 | FIELD(ID_AA64MMFR3, ADERR, 56, 4) |
| 357 | FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) |
| 358 | |
| 359 | FIELD(ID_AA64MMFR4, POPS, 0, 4) |
| 360 | FIELD(ID_AA64MMFR4, EIESB, 4, 4) |
| 361 | FIELD(ID_AA64MMFR4, ASID2, 8, 4) |
| 362 | FIELD(ID_AA64MMFR4, HACDBS, 12, 4) |
| 363 | FIELD(ID_AA64MMFR4, FGWTE3, 16, 4) |
| 364 | FIELD(ID_AA64MMFR4, NV_FRAC, 20, 4) |
| 365 | FIELD(ID_AA64MMFR4, E2H0, 24, 4) |
| 366 | FIELD(ID_AA64MMFR4, RMEGDI, 28, 4) |
| 367 | FIELD(ID_AA64MMFR4, E3DSE, 36, 4) |
| 368 | FIELD(ID_AA64MMFR4, SRMASK, 44, 4) |
| 369 | |
| 370 | FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) |
| 371 | FIELD(ID_AA64DFR0, TRACEVER, 4, 4) |
| 372 | FIELD(ID_AA64DFR0, PMUVER, 8, 4) |
| 373 | FIELD(ID_AA64DFR0, BRPS, 12, 4) |
| 374 | FIELD(ID_AA64DFR0, PMSS, 16, 4) |
| 375 | FIELD(ID_AA64DFR0, WRPS, 20, 4) |
| 376 | FIELD(ID_AA64DFR0, SEBEP, 24, 4) |
| 377 | FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) |
| 378 | FIELD(ID_AA64DFR0, PMSVER, 32, 4) |
| 379 | FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) |
| 380 | FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) |
| 381 | FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) |
| 382 | FIELD(ID_AA64DFR0, MTPMU, 48, 4) |
| 383 | FIELD(ID_AA64DFR0, BRBE, 52, 4) |
| 384 | FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) |
| 385 | FIELD(ID_AA64DFR0, HPMN0, 60, 4) |
| 386 | |
| 387 | FIELD(ID_AA64ZFR0, SVEVER, 0, 4) |
| 388 | FIELD(ID_AA64ZFR0, AES, 4, 4) |
| 389 | FIELD(ID_AA64ZFR0, ELTPERM, 12, 4) |
| 390 | FIELD(ID_AA64ZFR0, BITPERM, 16, 4) |
| 391 | FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) |
| 392 | FIELD(ID_AA64ZFR0, B16B16, 24, 4) |
| 393 | FIELD(ID_AA64ZFR0, SHA3, 32, 4) |
| 394 | FIELD(ID_AA64ZFR0, SM4, 40, 4) |
| 395 | FIELD(ID_AA64ZFR0, I8MM, 44, 4) |
| 396 | FIELD(ID_AA64ZFR0, F16MM, 48, 4) |
| 397 | FIELD(ID_AA64ZFR0, F32MM, 52, 4) |
| 398 | FIELD(ID_AA64ZFR0, F64MM, 56, 4) |
| 399 | |
| 400 | FIELD(ID_AA64SMFR0, SMOP4, 0, 1) |
| 401 | FIELD(ID_AA64SMFR0, STMOP, 16, 1) |
| 402 | FIELD(ID_AA64SMFR0, SFEXPA, 23, 1) |
| 403 | FIELD(ID_AA64SMFR0, AES, 24, 1) |
| 404 | FIELD(ID_AA64SMFR0, SBITPERM, 25, 1) |
| 405 | FIELD(ID_AA64SMFR0, SF8DP2, 28, 1) |
| 406 | FIELD(ID_AA64SMFR0, SF8DP4, 29, 1) |
| 407 | FIELD(ID_AA64SMFR0, SF8FMA, 30, 1) |
| 408 | FIELD(ID_AA64SMFR0, F32F32, 32, 1) |
| 409 | FIELD(ID_AA64SMFR0, BI32I32, 33, 1) |
| 410 | FIELD(ID_AA64SMFR0, B16F32, 34, 1) |
| 411 | FIELD(ID_AA64SMFR0, F16F32, 35, 1) |
| 412 | FIELD(ID_AA64SMFR0, I8I32, 36, 4) |
| 413 | FIELD(ID_AA64SMFR0, F8F32, 40, 1) |
| 414 | FIELD(ID_AA64SMFR0, F8F16, 41, 1) |
| 415 | FIELD(ID_AA64SMFR0, F16F16, 42, 1) |
| 416 | FIELD(ID_AA64SMFR0, B16B16, 43, 1) |
| 417 | FIELD(ID_AA64SMFR0, I16I32, 44, 4) |
| 418 | FIELD(ID_AA64SMFR0, F64F64, 48, 1) |
| 419 | FIELD(ID_AA64SMFR0, I16I64, 52, 4) |
| 420 | FIELD(ID_AA64SMFR0, SMEVER, 56, 4) |
| 421 | FIELD(ID_AA64SMFR0, LUTv2, 60, 1) |
| 422 | FIELD(ID_AA64SMFR0, FA64, 63, 1) |
| 423 | |
| 424 | FIELD(ID_AA64FPFR0, F8E5M2, 0, 1) |
| 425 | FIELD(ID_AA64FPFR0, F8E4M3, 1, 1) |
| 426 | FIELD(ID_AA64FPFR0, F8MM4, 26, 1) |
| 427 | FIELD(ID_AA64FPFR0, F8MM8, 27, 1) |
| 428 | FIELD(ID_AA64FPFR0, F8DP2, 28, 1) |
| 429 | FIELD(ID_AA64FPFR0, F8DP4, 29, 1) |
| 430 | FIELD(ID_AA64FPFR0, F8FMA, 30, 1) |
| 431 | FIELD(ID_AA64FPFR0, F8CVT, 31, 1) |
| 432 | |
| 433 | FIELD(ID_DFR0, COPDBG, 0, 4) |
| 434 | FIELD(ID_DFR0, COPSDBG, 4, 4) |
| 435 | FIELD(ID_DFR0, MMAPDBG, 8, 4) |
| 436 | FIELD(ID_DFR0, COPTRC, 12, 4) |
| 437 | FIELD(ID_DFR0, MMAPTRC, 16, 4) |
| 438 | FIELD(ID_DFR0, MPROFDBG, 20, 4) |
| 439 | FIELD(ID_DFR0, PERFMON, 24, 4) |
| 440 | FIELD(ID_DFR0, TRACEFILT, 28, 4) |
| 441 | |
| 442 | FIELD(ID_DFR1, MTPMU, 0, 4) |
| 443 | FIELD(ID_DFR1, HPMN0, 4, 4) |
| 444 | |
| 445 | FIELD(DBGDIDR, SE_IMP, 12, 1) |
| 446 | FIELD(DBGDIDR, NSUHD_IMP, 14, 1) |
| 447 | FIELD(DBGDIDR, VERSION, 16, 4) |
| 448 | FIELD(DBGDIDR, CTX_CMPS, 20, 4) |
| 449 | FIELD(DBGDIDR, BRPS, 24, 4) |
| 450 | FIELD(DBGDIDR, WRPS, 28, 4) |
| 451 | |
| 452 | FIELD(DBGDEVID, PCSAMPLE, 0, 4) |
| 453 | FIELD(DBGDEVID, WPADDRMASK, 4, 4) |
| 454 | FIELD(DBGDEVID, BPADDRMASK, 8, 4) |
| 455 | FIELD(DBGDEVID, VECTORCATCH, 12, 4) |
| 456 | FIELD(DBGDEVID, VIRTEXTNS, 16, 4) |
| 457 | FIELD(DBGDEVID, DOUBLELOCK, 20, 4) |
| 458 | FIELD(DBGDEVID, AUXREGS, 24, 4) |
| 459 | FIELD(DBGDEVID, CIDMASK, 28, 4) |
| 460 | |
| 461 | FIELD(DBGDEVID1, PCSROFFSET, 0, 4) |
| 462 | |
| 463 | FIELD(MVFR0, SIMDREG, 0, 4) |
| 464 | FIELD(MVFR0, FPSP, 4, 4) |
| 465 | FIELD(MVFR0, FPDP, 8, 4) |
| 466 | FIELD(MVFR0, FPTRAP, 12, 4) |
| 467 | FIELD(MVFR0, FPDIVIDE, 16, 4) |
| 468 | FIELD(MVFR0, FPSQRT, 20, 4) |
| 469 | FIELD(MVFR0, FPSHVEC, 24, 4) |
| 470 | FIELD(MVFR0, FPROUND, 28, 4) |
| 471 | |
| 472 | FIELD(MVFR1, FPFTZ, 0, 4) |
| 473 | FIELD(MVFR1, FPDNAN, 4, 4) |
| 474 | FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ |
| 475 | FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ |
| 476 | FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ |
| 477 | FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ |
| 478 | FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ |
| 479 | FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ |
| 480 | FIELD(MVFR1, FPHP, 24, 4) |
| 481 | FIELD(MVFR1, SIMDFMAC, 28, 4) |
| 482 | |
| 483 | FIELD(MVFR2, SIMDMISC, 0, 4) |
| 484 | FIELD(MVFR2, FPMISC, 4, 4) |
| 485 | |
| 486 | /* |
| 487 | * Naming convention for isar_feature functions: |
| 488 | * Functions which test 32-bit ID registers should have _aa32_ in |
| 489 | * their name. Functions which test 64-bit ID registers should have |
| 490 | * _aa64_ in their name. These must only be used in code where we |
| 491 | * know for certain that the CPU has AArch32 or AArch64 respectively |
| 492 | * or where the correct answer for a CPU which doesn't implement that |
| 493 | * CPU state is "false" (eg when generating A32 or A64 code, if adding |
| 494 | * system registers that are specific to that CPU state, for "should |
| 495 | * we let this system register bit be set" tests where the 32-bit |
| 496 | * flavour of the register doesn't have the bit, and so on). |
| 497 | * Functions which simply ask "does this feature exist at all" have |
| 498 | * _any_ in their name, and always return the logical OR of the _aa64_ |
| 499 | * and the _aa32_ function. |
| 500 | */ |
| 501 | |
| 502 | /* |
| 503 | * 32-bit feature tests via id registers. |
| 504 | */ |
| 505 | static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) |
| 506 | { |
| 507 | return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) != 0; |
| 508 | } |
| 509 | |
| 510 | static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) |
| 511 | { |
| 512 | return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) > 1; |
| 513 | } |
| 514 | |
| 515 | static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) |
| 516 | { |
| 517 | /* (M-profile) low-overhead loops and branch future */ |
| 518 | return FIELD_EX32_IDREG(id, ID_ISAR0, CMPBRANCH) >= 3; |
| 519 | } |
| 520 | |
| 521 | static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) |
| 522 | { |
| 523 | return FIELD_EX32_IDREG(id, ID_ISAR1, JAZELLE) != 0; |
| 524 | } |
| 525 | |
| 526 | static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) |
| 527 | { |
| 528 | return FIELD_EX32_IDREG(id, ID_ISAR5, AES) != 0; |
| 529 | } |
| 530 | |
| 531 | static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) |
| 532 | { |
| 533 | return FIELD_EX32_IDREG(id, ID_ISAR5, AES) > 1; |
| 534 | } |
| 535 | |
| 536 | static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) |
| 537 | { |
| 538 | return FIELD_EX32_IDREG(id, ID_ISAR5, SHA1) != 0; |
| 539 | } |
| 540 | |
| 541 | static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) |
| 542 | { |
| 543 | return FIELD_EX32_IDREG(id, ID_ISAR5, SHA2) != 0; |
| 544 | } |
| 545 | |
| 546 | static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) |
| 547 | { |
| 548 | return FIELD_EX32_IDREG(id, ID_ISAR5, CRC32) != 0; |
| 549 | } |
| 550 | |
| 551 | static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) |
| 552 | { |
| 553 | return FIELD_EX32_IDREG(id, ID_ISAR5, RDM) != 0; |
| 554 | } |
| 555 | |
| 556 | static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) |
| 557 | { |
| 558 | return FIELD_EX32_IDREG(id, ID_ISAR5, VCMA) != 0; |
| 559 | } |
| 560 | |
| 561 | static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) |
| 562 | { |
| 563 | return FIELD_EX32_IDREG(id, ID_ISAR6, JSCVT) != 0; |
| 564 | } |
| 565 | |
| 566 | static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) |
| 567 | { |
| 568 | return FIELD_EX32_IDREG(id, ID_ISAR6, DP) != 0; |
| 569 | } |
| 570 | |
| 571 | static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) |
| 572 | { |
| 573 | return FIELD_EX32_IDREG(id, ID_ISAR6, FHM) != 0; |
| 574 | } |
| 575 | |
| 576 | static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) |
| 577 | { |
| 578 | return FIELD_EX32_IDREG(id, ID_ISAR6, SB) != 0; |
| 579 | } |
| 580 | |
| 581 | static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) |
| 582 | { |
| 583 | return FIELD_EX32_IDREG(id, ID_ISAR6, SPECRES) != 0; |
| 584 | } |
| 585 | |
| 586 | static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) |
| 587 | { |
| 588 | return FIELD_EX32_IDREG(id, ID_ISAR6, BF16) != 0; |
| 589 | } |
| 590 | |
| 591 | static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) |
| 592 | { |
| 593 | return FIELD_EX32_IDREG(id, ID_ISAR6, I8MM) != 0; |
| 594 | } |
| 595 | |
| 596 | static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) |
| 597 | { |
| 598 | return FIELD_EX32_IDREG(id, ID_PFR0, RAS) != 0; |
| 599 | } |
| 600 | |
| 601 | static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) |
| 602 | { |
| 603 | return FIELD_EX32_IDREG(id, ID_PFR1, MPROGMOD) != 0; |
| 604 | } |
| 605 | |
| 606 | static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) |
| 607 | { |
| 608 | /* |
| 609 | * Return true if M-profile state handling insns |
| 610 | * (VSCCLRM, CLRM, FPCTX access insns) are implemented |
| 611 | */ |
| 612 | return FIELD_EX32_IDREG(id, ID_PFR1, SECURITY) >= 3; |
| 613 | } |
| 614 | |
| 615 | static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) |
| 616 | { |
| 617 | /* Sadly this is encoded differently for A-profile and M-profile */ |
| 618 | if (isar_feature_aa32_mprofile(id)) { |
| 619 | return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; |
| 620 | } else { |
| 621 | return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; |
| 622 | } |
| 623 | } |
| 624 | |
| 625 | static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) |
| 626 | { |
| 627 | /* |
| 628 | * Return true if MVE is supported (either integer or floating point). |
| 629 | * We must check for M-profile as the MVFR1 field means something |
| 630 | * else for A-profile. |
| 631 | */ |
| 632 | return isar_feature_aa32_mprofile(id) && |
| 633 | FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; |
| 634 | } |
| 635 | |
| 636 | static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) |
| 637 | { |
| 638 | /* |
| 639 | * Return true if MVE is supported (either integer or floating point). |
| 640 | * We must check for M-profile as the MVFR1 field means something |
| 641 | * else for A-profile. |
| 642 | */ |
| 643 | return isar_feature_aa32_mprofile(id) && |
| 644 | FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; |
| 645 | } |
| 646 | |
| 647 | static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) |
| 648 | { |
| 649 | /* |
| 650 | * Return true if either VFP or SIMD is implemented. |
| 651 | * In this case, a minimum of VFP w/ D0-D15. |
| 652 | */ |
| 653 | return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; |
| 654 | } |
| 655 | |
| 656 | static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) |
| 657 | { |
| 658 | /* Return true if D16-D31 are implemented */ |
| 659 | return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; |
| 660 | } |
| 661 | |
| 662 | static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) |
| 663 | { |
| 664 | return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; |
| 665 | } |
| 666 | |
| 667 | static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) |
| 668 | { |
| 669 | /* Return true if CPU supports single precision floating point, VFPv2 */ |
| 670 | return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; |
| 671 | } |
| 672 | |
| 673 | static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) |
| 674 | { |
| 675 | /* Return true if CPU supports single precision floating point, VFPv3 */ |
| 676 | return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; |
| 677 | } |
| 678 | |
| 679 | static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) |
| 680 | { |
| 681 | /* Return true if CPU supports double precision floating point, VFPv2 */ |
| 682 | return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; |
| 683 | } |
| 684 | |
| 685 | static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) |
| 686 | { |
| 687 | /* Return true if CPU supports double precision floating point, VFPv3 */ |
| 688 | return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; |
| 689 | } |
| 690 | |
| 691 | static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) |
| 692 | { |
| 693 | return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); |
| 694 | } |
| 695 | |
| 696 | /* |
| 697 | * We always set the FP and SIMD FP16 fields to indicate identical |
| 698 | * levels of support (assuming SIMD is implemented at all), so |
| 699 | * we only need one set of accessors. |
| 700 | */ |
| 701 | static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) |
| 702 | { |
| 703 | return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; |
| 704 | } |
| 705 | |
| 706 | static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) |
| 707 | { |
| 708 | return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; |
| 709 | } |
| 710 | |
| 711 | /* |
| 712 | * Note that this ID register field covers both VFP and Neon FMAC, |
| 713 | * so should usually be tested in combination with some other |
| 714 | * check that confirms the presence of whichever of VFP or Neon is |
| 715 | * relevant, to avoid accidentally enabling a Neon feature on |
| 716 | * a VFP-no-Neon core or vice-versa. |
| 717 | */ |
| 718 | static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) |
| 719 | { |
| 720 | return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; |
| 721 | } |
| 722 | |
| 723 | static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) |
| 724 | { |
| 725 | return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; |
| 726 | } |
| 727 | |
| 728 | static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) |
| 729 | { |
| 730 | return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; |
| 731 | } |
| 732 | |
| 733 | static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) |
| 734 | { |
| 735 | return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; |
| 736 | } |
| 737 | |
| 738 | static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) |
| 739 | { |
| 740 | return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; |
| 741 | } |
| 742 | |
| 743 | static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) |
| 744 | { |
| 745 | return FIELD_EX32_IDREG(id, ID_MMFR0, VMSA) >= 4; |
| 746 | } |
| 747 | |
| 748 | static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) |
| 749 | { |
| 750 | return FIELD_EX32_IDREG(id, ID_MMFR3, PAN) != 0; |
| 751 | } |
| 752 | |
| 753 | static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) |
| 754 | { |
| 755 | return FIELD_EX32_IDREG(id, ID_MMFR3, PAN) >= 2; |
| 756 | } |
| 757 | |
| 758 | static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) |
| 759 | { |
| 760 | /* 0xf means "non-standard IMPDEF PMU" */ |
| 761 | return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >= 4 && |
| 762 | FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) != 0xf; |
| 763 | } |
| 764 | |
| 765 | static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) |
| 766 | { |
| 767 | /* 0xf means "non-standard IMPDEF PMU" */ |
| 768 | return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >= 5 && |
| 769 | FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) != 0xf; |
| 770 | } |
| 771 | |
| 772 | static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) |
| 773 | { |
| 774 | /* 0xf means "non-standard IMPDEF PMU" */ |
| 775 | return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >= 6 && |
| 776 | FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) != 0xf; |
| 777 | } |
| 778 | |
| 779 | static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) |
| 780 | { |
| 781 | return FIELD_EX32_IDREG(id, ID_MMFR4, HPDS) != 0; |
| 782 | } |
| 783 | |
| 784 | static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) |
| 785 | { |
| 786 | return FIELD_EX32_IDREG(id, ID_MMFR4, AC2) != 0; |
| 787 | } |
| 788 | |
| 789 | static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) |
| 790 | { |
| 791 | return FIELD_EX32_IDREG(id, ID_MMFR4, CCIDX) != 0; |
| 792 | } |
| 793 | |
| 794 | static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) |
| 795 | { |
| 796 | return FIELD_EX32_IDREG(id, ID_MMFR4, XNX) != 0; |
| 797 | } |
| 798 | |
| 799 | static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) |
| 800 | { |
| 801 | return FIELD_EX32_IDREG(id, ID_MMFR4, EVT) >= 1; |
| 802 | } |
| 803 | |
| 804 | static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) |
| 805 | { |
| 806 | return FIELD_EX32_IDREG(id, ID_MMFR4, EVT) >= 2; |
| 807 | } |
| 808 | |
| 809 | static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) |
| 810 | { |
| 811 | return FIELD_EX32_IDREG(id, ID_PFR0, DIT) != 0; |
| 812 | } |
| 813 | |
| 814 | static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) |
| 815 | { |
| 816 | return FIELD_EX32_IDREG(id, ID_PFR2, SSBS) != 0; |
| 817 | } |
| 818 | |
| 819 | static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) |
| 820 | { |
| 821 | return FIELD_EX32_IDREG(id, ID_DFR0, COPDBG) >= 5; |
| 822 | } |
| 823 | |
| 824 | static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) |
| 825 | { |
| 826 | return FIELD_EX32_IDREG(id, ID_DFR0, COPDBG) >= 8; |
| 827 | } |
| 828 | |
| 829 | static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) |
| 830 | { |
| 831 | return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0; |
| 832 | } |
| 833 | |
| 834 | /* |
| 835 | * 64-bit feature tests via id registers. |
| 836 | */ |
| 837 | static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) |
| 838 | { |
| 839 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) != 0; |
| 840 | } |
| 841 | |
| 842 | static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) |
| 843 | { |
| 844 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) > 1; |
| 845 | } |
| 846 | |
| 847 | static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) |
| 848 | { |
| 849 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA1) != 0; |
| 850 | } |
| 851 | |
| 852 | static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) |
| 853 | { |
| 854 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) != 0; |
| 855 | } |
| 856 | |
| 857 | static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) |
| 858 | { |
| 859 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) > 1; |
| 860 | } |
| 861 | |
| 862 | static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) |
| 863 | { |
| 864 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, CRC32) != 0; |
| 865 | } |
| 866 | |
| 867 | static inline bool isar_feature_aa64_lse(const ARMISARegisters *id) |
| 868 | { |
| 869 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) >= 2; |
| 870 | } |
| 871 | |
| 872 | static inline bool isar_feature_aa64_lse128(const ARMISARegisters *id) |
| 873 | { |
| 874 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) >= 3; |
| 875 | } |
| 876 | |
| 877 | static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) |
| 878 | { |
| 879 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RDM) != 0; |
| 880 | } |
| 881 | |
| 882 | static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) |
| 883 | { |
| 884 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA3) != 0; |
| 885 | } |
| 886 | |
| 887 | static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) |
| 888 | { |
| 889 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM3) != 0; |
| 890 | } |
| 891 | |
| 892 | static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) |
| 893 | { |
| 894 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM4) != 0; |
| 895 | } |
| 896 | |
| 897 | static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) |
| 898 | { |
| 899 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, DP) != 0; |
| 900 | } |
| 901 | |
| 902 | static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) |
| 903 | { |
| 904 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, FHM) != 0; |
| 905 | } |
| 906 | |
| 907 | static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) |
| 908 | { |
| 909 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) != 0; |
| 910 | } |
| 911 | |
| 912 | static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) |
| 913 | { |
| 914 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) >= 2; |
| 915 | } |
| 916 | |
| 917 | static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) |
| 918 | { |
| 919 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RNDR) != 0; |
| 920 | } |
| 921 | |
| 922 | static inline bool isar_feature_aa64_rng_trap(const ARMISARegisters *id) |
| 923 | { |
| 924 | return FIELD_EX64_IDREG(id, ID_AA64PFR1, RNDR_TRAP) != 0; |
| 925 | } |
| 926 | |
| 927 | static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) |
| 928 | { |
| 929 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) == 2; |
| 930 | } |
| 931 | |
| 932 | static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) |
| 933 | { |
| 934 | return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) != 0; |
| 935 | } |
| 936 | |
| 937 | static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) |
| 938 | { |
| 939 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, JSCVT) != 0; |
| 940 | } |
| 941 | |
| 942 | static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) |
| 943 | { |
| 944 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, FCMA) != 0; |
| 945 | } |
| 946 | |
| 947 | static inline bool isar_feature_aa64_xs(const ARMISARegisters *id) |
| 948 | { |
| 949 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, XS) != 0; |
| 950 | } |
| 951 | |
| 952 | /* |
| 953 | * These are the values from APA/API/APA3. |
| 954 | * In general these must be compared '>=', per the normal Arm ARM |
| 955 | * treatment of fields in ID registers. |
| 956 | */ |
| 957 | typedef enum { |
| 958 | PauthFeat_None = 0, |
| 959 | PauthFeat_1 = 1, |
| 960 | PauthFeat_EPAC = 2, |
| 961 | PauthFeat_2 = 3, |
| 962 | PauthFeat_FPAC = 4, |
| 963 | PauthFeat_FPACCOMBINED = 5, |
| 964 | } ARMPauthFeature; |
| 965 | |
| 966 | static inline ARMPauthFeature |
| 967 | isar_feature_pauth_feature(const ARMISARegisters *id) |
| 968 | { |
| 969 | /* |
| 970 | * Architecturally, only one of {APA,API,APA3} may be active (non-zero) |
| 971 | * and the other two must be zero. Thus we may avoid conditionals. |
| 972 | */ |
| 973 | return (FIELD_EX64_IDREG(id, ID_AA64ISAR1, APA) | |
| 974 | FIELD_EX64_IDREG(id, ID_AA64ISAR1, API) | |
| 975 | FIELD_EX64_IDREG(id, ID_AA64ISAR2, APA3)); |
| 976 | } |
| 977 | |
| 978 | static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) |
| 979 | { |
| 980 | /* |
| 981 | * Return true if any form of pauth is enabled, as this |
| 982 | * predicate controls migration of the 128-bit keys. |
| 983 | */ |
| 984 | return isar_feature_pauth_feature(id) != PauthFeat_None; |
| 985 | } |
| 986 | |
| 987 | static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id) |
| 988 | { |
| 989 | /* |
| 990 | * Return true if pauth is enabled with the architected QARMA5 algorithm. |
| 991 | * QEMU will always enable or disable both APA and GPA. |
| 992 | */ |
| 993 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, APA) != 0; |
| 994 | } |
| 995 | |
| 996 | static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id) |
| 997 | { |
| 998 | /* |
| 999 | * Return true if pauth is enabled with the architected QARMA3 algorithm. |
| 1000 | * QEMU will always enable or disable both APA3 and GPA3. |
| 1001 | */ |
| 1002 | return FIELD_EX64_IDREG(id, ID_AA64ISAR2, APA3) != 0; |
| 1003 | } |
| 1004 | |
| 1005 | static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) |
| 1006 | { |
| 1007 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, SB) != 0; |
| 1008 | } |
| 1009 | |
| 1010 | static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) |
| 1011 | { |
| 1012 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, SPECRES) != 0; |
| 1013 | } |
| 1014 | |
| 1015 | static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) |
| 1016 | { |
| 1017 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, FRINTTS) != 0; |
| 1018 | } |
| 1019 | |
| 1020 | static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) |
| 1021 | { |
| 1022 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, DPB) != 0; |
| 1023 | } |
| 1024 | |
| 1025 | static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) |
| 1026 | { |
| 1027 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, DPB) >= 2; |
| 1028 | } |
| 1029 | |
| 1030 | static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) |
| 1031 | { |
| 1032 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, BF16) != 0; |
| 1033 | } |
| 1034 | |
| 1035 | static inline bool isar_feature_aa64_ebf16(const ARMISARegisters *id) |
| 1036 | { |
| 1037 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, BF16) > 1; |
| 1038 | } |
| 1039 | |
| 1040 | static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) |
| 1041 | { |
| 1042 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, LRCPC) != 0; |
| 1043 | } |
| 1044 | |
| 1045 | static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) |
| 1046 | { |
| 1047 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, LRCPC) >= 2; |
| 1048 | } |
| 1049 | |
| 1050 | static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) |
| 1051 | { |
| 1052 | return FIELD_EX64_IDREG(id, ID_AA64ISAR1, I8MM) != 0; |
| 1053 | } |
| 1054 | |
| 1055 | static inline bool isar_feature_aa64_wfxt(const ARMISARegisters *id) |
| 1056 | { |
| 1057 | return FIELD_EX64_IDREG(id, ID_AA64ISAR2, WFXT) >= 2; |
| 1058 | } |
| 1059 | |
| 1060 | static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id) |
| 1061 | { |
| 1062 | return FIELD_EX64_IDREG(id, ID_AA64ISAR2, BC) != 0; |
| 1063 | } |
| 1064 | |
| 1065 | static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) |
| 1066 | { |
| 1067 | return FIELD_EX64_IDREG(id, ID_AA64ISAR2, MOPS); |
| 1068 | } |
| 1069 | |
| 1070 | static inline bool isar_feature_aa64_rpres(const ARMISARegisters *id) |
| 1071 | { |
| 1072 | return FIELD_EX64_IDREG(id, ID_AA64ISAR2, RPRES); |
| 1073 | } |
| 1074 | |
| 1075 | static inline bool isar_feature_aa64_cssc(const ARMISARegisters *id) |
| 1076 | { |
| 1077 | return FIELD_EX64_IDREG(id, ID_AA64ISAR2, CSSC) != 0; |
| 1078 | } |
| 1079 | |
| 1080 | static inline bool isar_feature_aa64_cmpbr(const ARMISARegisters *id) |
| 1081 | { |
| 1082 | return FIELD_EX64_IDREG(id, ID_AA64ISAR2, CSSC) >= 2; |
| 1083 | } |
| 1084 | |
| 1085 | static inline bool isar_feature_aa64_lut(const ARMISARegisters *id) |
| 1086 | { |
| 1087 | return FIELD_EX64_IDREG(id, ID_AA64ISAR2, LUT); |
| 1088 | } |
| 1089 | |
| 1090 | static inline bool isar_feature_aa64_ats1a(const ARMISARegisters *id) |
| 1091 | { |
| 1092 | return FIELD_EX64_IDREG(id, ID_AA64ISAR2, ATS1A); |
| 1093 | } |
| 1094 | |
| 1095 | static inline bool isar_feature_aa64_faminmax(const ARMISARegisters *id) |
| 1096 | { |
| 1097 | return FIELD_EX64_IDREG(id, ID_AA64ISAR3, FAMINMAX) != 0; |
| 1098 | } |
| 1099 | |
| 1100 | static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) |
| 1101 | { |
| 1102 | /* We always set the AdvSIMD and FP fields identically. */ |
| 1103 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, FP) != 0xf; |
| 1104 | } |
| 1105 | |
| 1106 | static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) |
| 1107 | { |
| 1108 | /* We always set the AdvSIMD and FP fields identically wrt FP16. */ |
| 1109 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, FP) == 1; |
| 1110 | } |
| 1111 | |
| 1112 | static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) |
| 1113 | { |
| 1114 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL0) >= 2; |
| 1115 | } |
| 1116 | |
| 1117 | static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) |
| 1118 | { |
| 1119 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL1) >= 2; |
| 1120 | } |
| 1121 | |
| 1122 | static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) |
| 1123 | { |
| 1124 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL2) >= 2; |
| 1125 | } |
| 1126 | |
| 1127 | static inline bool isar_feature_aa64_aa32_el3(const ARMISARegisters *id) |
| 1128 | { |
| 1129 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL3) >= 2; |
| 1130 | } |
| 1131 | |
| 1132 | static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) |
| 1133 | { |
| 1134 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) != 0; |
| 1135 | } |
| 1136 | |
| 1137 | static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) |
| 1138 | { |
| 1139 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) >= 2; |
| 1140 | } |
| 1141 | |
| 1142 | static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) |
| 1143 | { |
| 1144 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, SVE) != 0; |
| 1145 | } |
| 1146 | |
| 1147 | static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) |
| 1148 | { |
| 1149 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, SEL2) != 0; |
| 1150 | } |
| 1151 | |
| 1152 | static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) |
| 1153 | { |
| 1154 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) != 0; |
| 1155 | } |
| 1156 | |
| 1157 | static inline bool isar_feature_aa64_rme_gpc2(const ARMISARegisters *id) |
| 1158 | { |
| 1159 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) >= 2; |
| 1160 | } |
| 1161 | |
| 1162 | static inline bool isar_feature_aa64_rme_gpc3(const ARMISARegisters *id) |
| 1163 | { |
| 1164 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) >= 3; |
| 1165 | } |
| 1166 | |
| 1167 | static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) |
| 1168 | { |
| 1169 | return FIELD_EX64_IDREG(id, ID_AA64PFR0, DIT) != 0; |
| 1170 | } |
| 1171 | |
| 1172 | static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) |
| 1173 | { |
| 1174 | int key = FIELD_EX64_IDREG(id, ID_AA64PFR0, CSV2); |
| 1175 | if (key >= 2) { |
| 1176 | return true; /* FEAT_CSV2_2 */ |
| 1177 | } |
| 1178 | if (key == 1) { |
| 1179 | key = FIELD_EX64_IDREG(id, ID_AA64PFR1, CSV2_FRAC); |
| 1180 | return key >= 2; /* FEAT_CSV2_1p2 */ |
| 1181 | } |
| 1182 | return false; |
| 1183 | } |
| 1184 | |
| 1185 | static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) |
| 1186 | { |
| 1187 | return FIELD_EX64_IDREG(id, ID_AA64PFR1, SSBS) != 0; |
| 1188 | } |
| 1189 | |
| 1190 | static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) |
| 1191 | { |
| 1192 | return FIELD_EX64_IDREG(id, ID_AA64PFR1, BT) != 0; |
| 1193 | } |
| 1194 | |
| 1195 | static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) |
| 1196 | { |
| 1197 | return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) != 0; |
| 1198 | } |
| 1199 | |
| 1200 | static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) |
| 1201 | { |
| 1202 | return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >= 2; |
| 1203 | } |
| 1204 | |
| 1205 | static inline bool isar_feature_aa64_mte3(const ARMISARegisters *id) |
| 1206 | { |
| 1207 | return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >= 3; |
| 1208 | } |
| 1209 | |
| 1210 | static inline bool isar_feature_aa64_mteperm(const ARMISARegisters *id) |
| 1211 | { |
| 1212 | return FIELD_EX64_IDREG(id, ID_AA64PFR2, MTEPERM) >= 1; |
| 1213 | } |
| 1214 | |
| 1215 | static inline bool isar_feature_aa64_mte_store_only(const ARMISARegisters *id) |
| 1216 | { |
| 1217 | return FIELD_EX64_IDREG(id, ID_AA64PFR2, MTESTOREONLY) == 1; |
| 1218 | } |
| 1219 | |
| 1220 | static inline bool isar_feature_aa64_mte_mtx(const ARMISARegisters *id) |
| 1221 | { |
| 1222 | return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTEX) != 0; |
| 1223 | } |
| 1224 | |
| 1225 | static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) |
| 1226 | { |
| 1227 | return FIELD_EX64_IDREG(id, ID_AA64PFR1, SME) != 0; |
| 1228 | } |
| 1229 | |
| 1230 | static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id) |
| 1231 | { |
| 1232 | return FIELD_EX64_IDREG(id, ID_AA64PFR1, NMI) != 0; |
| 1233 | } |
| 1234 | |
| 1235 | static inline bool isar_feature_aa64_gcs(const ARMISARegisters *id) |
| 1236 | { |
| 1237 | return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) != 0; |
| 1238 | } |
| 1239 | |
| 1240 | static inline bool isar_feature_aa64_gcie(const ARMISARegisters *id) |
| 1241 | { |
| 1242 | return FIELD_EX64_IDREG(id, ID_AA64PFR2, GCIE) != 0; |
| 1243 | } |
| 1244 | |
| 1245 | static inline bool isar_feature_aa64_fpmr(const ARMISARegisters *id) |
| 1246 | { |
| 1247 | return FIELD_EX64_IDREG(id, ID_AA64PFR2, FPMR) != 0; |
| 1248 | } |
| 1249 | |
| 1250 | static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) |
| 1251 | { |
| 1252 | return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >= 1; |
| 1253 | } |
| 1254 | |
| 1255 | static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) |
| 1256 | { |
| 1257 | unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN4_2); |
| 1258 | return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); |
| 1259 | } |
| 1260 | |
| 1261 | static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) |
| 1262 | { |
| 1263 | return FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16) >= 2; |
| 1264 | } |
| 1265 | |
| 1266 | static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) |
| 1267 | { |
| 1268 | unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16_2); |
| 1269 | return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); |
| 1270 | } |
| 1271 | |
| 1272 | static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) |
| 1273 | { |
| 1274 | return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >= 0; |
| 1275 | } |
| 1276 | |
| 1277 | static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) |
| 1278 | { |
| 1279 | return FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16) >= 1; |
| 1280 | } |
| 1281 | |
| 1282 | static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) |
| 1283 | { |
| 1284 | return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN64) >= 0; |
| 1285 | } |
| 1286 | |
| 1287 | static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) |
| 1288 | { |
| 1289 | unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN4_2); |
| 1290 | return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id)); |
| 1291 | } |
| 1292 | |
| 1293 | static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) |
| 1294 | { |
| 1295 | unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16_2); |
| 1296 | return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id)); |
| 1297 | } |
| 1298 | |
| 1299 | static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) |
| 1300 | { |
| 1301 | unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN64_2); |
| 1302 | return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); |
| 1303 | } |
| 1304 | |
| 1305 | static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) |
| 1306 | { |
| 1307 | return FIELD_EX64_IDREG(id, ID_AA64MMFR0, FGT) != 0; |
| 1308 | } |
| 1309 | |
| 1310 | static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id) |
| 1311 | { |
| 1312 | return FIELD_EX64_IDREG(id, ID_AA64MMFR0, ECV) > 0; |
| 1313 | } |
| 1314 | |
| 1315 | static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id) |
| 1316 | { |
| 1317 | return FIELD_EX64_IDREG(id, ID_AA64MMFR0, ECV) > 1; |
| 1318 | } |
| 1319 | |
| 1320 | static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) |
| 1321 | { |
| 1322 | return FIELD_EX64_IDREG(id, ID_AA64MMFR1, VH) != 0; |
| 1323 | } |
| 1324 | |
| 1325 | static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) |
| 1326 | { |
| 1327 | return FIELD_EX64_IDREG(id, ID_AA64MMFR1, LO) != 0; |
| 1328 | } |
| 1329 | |
| 1330 | static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) |
| 1331 | { |
| 1332 | return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) != 0; |
| 1333 | } |
| 1334 | |
| 1335 | static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) |
| 1336 | { |
| 1337 | return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) >= 2; |
| 1338 | } |
| 1339 | |
| 1340 | static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id) |
| 1341 | { |
| 1342 | return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) >= 3; |
| 1343 | } |
| 1344 | |
| 1345 | static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) |
| 1346 | { |
| 1347 | return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HCX) != 0; |
| 1348 | } |
| 1349 | |
| 1350 | static inline bool isar_feature_aa64_afp(const ARMISARegisters *id) |
| 1351 | { |
| 1352 | return FIELD_EX64_IDREG(id, ID_AA64MMFR1, AFP) != 0; |
| 1353 | } |
| 1354 | |
| 1355 | static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) |
| 1356 | { |
| 1357 | return FIELD_EX64_IDREG(id, ID_AA64MMFR1, TIDCP1) != 0; |
| 1358 | } |
| 1359 | |
| 1360 | static inline bool isar_feature_aa64_cmow(const ARMISARegisters *id) |
| 1361 | { |
| 1362 | return FIELD_EX64_IDREG(id, ID_AA64MMFR1, CMOW) != 0; |
| 1363 | } |
| 1364 | |
| 1365 | static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) |
| 1366 | { |
| 1367 | return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HAFDBS) != 0; |
| 1368 | } |
| 1369 | |
| 1370 | static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) |
| 1371 | { |
| 1372 | return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HAFDBS) >= 2; |
| 1373 | } |
| 1374 | |
| 1375 | static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) |
| 1376 | { |
| 1377 | return FIELD_EX64_IDREG(id, ID_AA64MMFR1, XNX) != 0; |
| 1378 | } |
| 1379 | |
| 1380 | static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) |
| 1381 | { |
| 1382 | return FIELD_EX64_IDREG(id, ID_AA64MMFR2, UAO) != 0; |
| 1383 | } |
| 1384 | |
| 1385 | static inline bool isar_feature_aa64_st(const ARMISARegisters *id) |
| 1386 | { |
| 1387 | return FIELD_EX64_IDREG(id, ID_AA64MMFR2, ST) != 0; |
| 1388 | } |
| 1389 | |
| 1390 | static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id) |
| 1391 | { |
| 1392 | return FIELD_EX64_IDREG(id, ID_AA64MMFR2, AT) != 0; |
| 1393 | } |
| 1394 | |
| 1395 | static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) |
| 1396 | { |
| 1397 | return FIELD_EX64_IDREG(id, ID_AA64MMFR2, FWB) != 0; |
| 1398 | } |
| 1399 | |
| 1400 | static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) |
| 1401 | { |
| 1402 | return FIELD_EX64_IDREG(id, ID_AA64MMFR2, IDS) != 0; |
| 1403 | } |
| 1404 | |
| 1405 | static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) |
| 1406 | { |
| 1407 | return FIELD_EX64_IDREG(id, ID_AA64MMFR2, EVT) >= 1; |
| 1408 | } |
| 1409 | |
| 1410 | static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) |
| 1411 | { |
| 1412 | return FIELD_EX64_IDREG(id, ID_AA64MMFR2, EVT) >= 2; |
| 1413 | } |
| 1414 | |
| 1415 | static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) |
| 1416 | { |
| 1417 | return FIELD_EX64_IDREG(id, ID_AA64MMFR2, CCIDX) != 0; |
| 1418 | } |
| 1419 | |
| 1420 | static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) |
| 1421 | { |
| 1422 | return FIELD_EX64_IDREG(id, ID_AA64MMFR2, VARANGE) != 0; |
| 1423 | } |
| 1424 | |
| 1425 | static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) |
| 1426 | { |
| 1427 | return FIELD_EX64_IDREG(id, ID_AA64MMFR2, E0PD) != 0; |
| 1428 | } |
| 1429 | |
| 1430 | static inline bool isar_feature_aa64_nv(const ARMISARegisters *id) |
| 1431 | { |
| 1432 | return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) != 0; |
| 1433 | } |
| 1434 | |
| 1435 | static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id) |
| 1436 | { |
| 1437 | return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >= 2; |
| 1438 | } |
| 1439 | |
| 1440 | static inline bool isar_feature_aa64_tcr2(const ARMISARegisters *id) |
| 1441 | { |
| 1442 | return FIELD_EX64_IDREG(id, ID_AA64MMFR3, TCRX) != 0; |
| 1443 | } |
| 1444 | |
| 1445 | static inline bool isar_feature_aa64_sctlr2(const ARMISARegisters *id) |
| 1446 | { |
| 1447 | return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) != 0; |
| 1448 | } |
| 1449 | |
| 1450 | static inline bool isar_feature_aa64_s1pie(const ARMISARegisters *id) |
| 1451 | { |
| 1452 | return FIELD_EX64_IDREG(id, ID_AA64MMFR3, S1PIE) != 0; |
| 1453 | } |
| 1454 | |
| 1455 | static inline bool isar_feature_aa64_s2pie(const ARMISARegisters *id) |
| 1456 | { |
| 1457 | return FIELD_EX64_IDREG(id, ID_AA64MMFR3, S2PIE) != 0; |
| 1458 | } |
| 1459 | |
| 1460 | static inline bool isar_feature_aa64_aie(const ARMISARegisters *id) |
| 1461 | { |
| 1462 | return FIELD_EX64_IDREG(id, ID_AA64MMFR3, AIE) != 0; |
| 1463 | } |
| 1464 | |
| 1465 | static inline bool isar_feature_aa64_asid2(const ARMISARegisters *id) |
| 1466 | { |
| 1467 | return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) != 0; |
| 1468 | } |
| 1469 | |
| 1470 | static inline bool isar_feature_aa64_fgwte3(const ARMISARegisters *id) |
| 1471 | { |
| 1472 | return FIELD_EX64_IDREG(id, ID_AA64MMFR4, FGWTE3) != 0; |
| 1473 | } |
| 1474 | |
| 1475 | /* |
| 1476 | * Note the E2H0 ID fields is signed, increasingly negative as more |
| 1477 | * isn't implemented. |
| 1478 | */ |
| 1479 | static inline bool isar_feature_aa64_e2h0(const ARMISARegisters *id) |
| 1480 | { |
| 1481 | return FIELD_SEX64_IDREG(id, ID_AA64MMFR4, E2H0) >= 0; |
| 1482 | } |
| 1483 | |
| 1484 | static inline bool isar_feature_aa64_nv1_res0(const ARMISARegisters *id) |
| 1485 | { |
| 1486 | return FIELD_SEX64_IDREG(id, ID_AA64MMFR4, E2H0) <= -2; |
| 1487 | } |
| 1488 | |
| 1489 | static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) |
| 1490 | { |
| 1491 | return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) != 0; |
| 1492 | } |
| 1493 | |
| 1494 | static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) |
| 1495 | { |
| 1496 | return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >= 4 && |
| 1497 | FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) != 0xf; |
| 1498 | } |
| 1499 | |
| 1500 | static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) |
| 1501 | { |
| 1502 | return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >= 5 && |
| 1503 | FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) != 0xf; |
| 1504 | } |
| 1505 | |
| 1506 | static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) |
| 1507 | { |
| 1508 | return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >= 6 && |
| 1509 | FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) != 0xf; |
| 1510 | } |
| 1511 | |
| 1512 | static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) |
| 1513 | { |
| 1514 | return FIELD_EX64_IDREG(id, ID_AA64DFR0, DEBUGVER) >= 8; |
| 1515 | } |
| 1516 | |
| 1517 | static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) |
| 1518 | { |
| 1519 | return FIELD_SEX64_IDREG(id, ID_AA64DFR0, DOUBLELOCK) >= 0; |
| 1520 | } |
| 1521 | |
| 1522 | static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) |
| 1523 | { |
| 1524 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) != 0; |
| 1525 | } |
| 1526 | |
| 1527 | static inline bool isar_feature_aa64_sve2p1(const ARMISARegisters *id) |
| 1528 | { |
| 1529 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) >= 2; |
| 1530 | } |
| 1531 | |
| 1532 | static inline bool isar_feature_aa64_sve2p2(const ARMISARegisters *id) |
| 1533 | { |
| 1534 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) >= 3; |
| 1535 | } |
| 1536 | |
| 1537 | static inline bool isar_feature_aa64_sve_aes(const ARMISARegisters *id) |
| 1538 | { |
| 1539 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) != 0; |
| 1540 | } |
| 1541 | |
| 1542 | static inline bool isar_feature_aa64_sve_pmull128(const ARMISARegisters *id) |
| 1543 | { |
| 1544 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) >= 2; |
| 1545 | } |
| 1546 | |
| 1547 | static inline bool isar_feature_aa64_sve_aes2(const ARMISARegisters *id) |
| 1548 | { |
| 1549 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) >= 3; |
| 1550 | } |
| 1551 | |
| 1552 | static inline bool isar_feature_aa64_sve_bitperm(const ARMISARegisters *id) |
| 1553 | { |
| 1554 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BITPERM) != 0; |
| 1555 | } |
| 1556 | |
| 1557 | static inline bool isar_feature_aa64_sme_sve_bf16(const ARMISARegisters *id) |
| 1558 | { |
| 1559 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BFLOAT16) != 0; |
| 1560 | } |
| 1561 | |
| 1562 | static inline bool isar_feature_aa64_sve_sha3(const ARMISARegisters *id) |
| 1563 | { |
| 1564 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SHA3) != 0; |
| 1565 | } |
| 1566 | |
| 1567 | static inline bool isar_feature_aa64_sve_sm4(const ARMISARegisters *id) |
| 1568 | { |
| 1569 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SM4) != 0; |
| 1570 | } |
| 1571 | |
| 1572 | /* Note that this is true if either SVE or SME are implemented with I8MM */ |
| 1573 | static inline bool isar_feature_aa64_sme_sve_i8mm(const ARMISARegisters *id) |
| 1574 | { |
| 1575 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, I8MM) != 0; |
| 1576 | } |
| 1577 | |
| 1578 | static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) |
| 1579 | { |
| 1580 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F32MM) != 0; |
| 1581 | } |
| 1582 | |
| 1583 | static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) |
| 1584 | { |
| 1585 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F64MM) != 0; |
| 1586 | } |
| 1587 | |
| 1588 | static inline bool isar_feature_aa64_sve_b16b16(const ARMISARegisters *id) |
| 1589 | { |
| 1590 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16); |
| 1591 | } |
| 1592 | |
| 1593 | static inline bool isar_feature_aa64_sve_bfscale(const ARMISARegisters *id) |
| 1594 | { |
| 1595 | return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16) >= 2; |
| 1596 | } |
| 1597 | |
| 1598 | static inline bool isar_feature_aa64_ssve_fexpa(const ARMISARegisters *id) |
| 1599 | { |
| 1600 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SFEXPA); |
| 1601 | } |
| 1602 | |
| 1603 | static inline bool isar_feature_aa64_sme_mop4(const ARMISARegisters *id) |
| 1604 | { |
| 1605 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMOP4); |
| 1606 | } |
| 1607 | |
| 1608 | static inline bool isar_feature_aa64_sme_tmop(const ARMISARegisters *id) |
| 1609 | { |
| 1610 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, STMOP); |
| 1611 | } |
| 1612 | |
| 1613 | static inline bool isar_feature_aa64_ssve_aes(const ARMISARegisters *id) |
| 1614 | { |
| 1615 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, AES); |
| 1616 | } |
| 1617 | |
| 1618 | static inline bool isar_feature_aa64_ssve_bitperm(const ARMISARegisters *id) |
| 1619 | { |
| 1620 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SBITPERM); |
| 1621 | } |
| 1622 | |
| 1623 | static inline bool isar_feature_aa64_ssve_f8fma(const ARMISARegisters *id) |
| 1624 | { |
| 1625 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8FMA); |
| 1626 | } |
| 1627 | |
| 1628 | static inline bool isar_feature_aa64_ssve_f8dp4(const ARMISARegisters *id) |
| 1629 | { |
| 1630 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8DP4); |
| 1631 | } |
| 1632 | |
| 1633 | static inline bool isar_feature_aa64_ssve_f8dp2(const ARMISARegisters *id) |
| 1634 | { |
| 1635 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8DP2); |
| 1636 | } |
| 1637 | |
| 1638 | static inline bool isar_feature_aa64_sme_b16b16(const ARMISARegisters *id) |
| 1639 | { |
| 1640 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, B16B16); |
| 1641 | } |
| 1642 | |
| 1643 | static inline bool isar_feature_aa64_sme_f8f32(const ARMISARegisters *id) |
| 1644 | { |
| 1645 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F8F32); |
| 1646 | } |
| 1647 | |
| 1648 | static inline bool isar_feature_aa64_sme_f8f16(const ARMISARegisters *id) |
| 1649 | { |
| 1650 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F8F16); |
| 1651 | } |
| 1652 | |
| 1653 | static inline bool isar_feature_aa64_sme_f16f16(const ARMISARegisters *id) |
| 1654 | { |
| 1655 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F16F16); |
| 1656 | } |
| 1657 | |
| 1658 | static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) |
| 1659 | { |
| 1660 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F64F64); |
| 1661 | } |
| 1662 | |
| 1663 | static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) |
| 1664 | { |
| 1665 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, I16I64) == 0xf; |
| 1666 | } |
| 1667 | |
| 1668 | static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) |
| 1669 | { |
| 1670 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, FA64); |
| 1671 | } |
| 1672 | |
| 1673 | static inline bool isar_feature_aa64_sme_lutv2(const ARMISARegisters *id) |
| 1674 | { |
| 1675 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, LUTv2); |
| 1676 | } |
| 1677 | |
| 1678 | static inline bool isar_feature_aa64_sme2(const ARMISARegisters *id) |
| 1679 | { |
| 1680 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMEVER) != 0; |
| 1681 | } |
| 1682 | |
| 1683 | static inline bool isar_feature_aa64_sme2p1(const ARMISARegisters *id) |
| 1684 | { |
| 1685 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMEVER) >= 2; |
| 1686 | } |
| 1687 | |
| 1688 | static inline bool isar_feature_aa64_sme2p2(const ARMISARegisters *id) |
| 1689 | { |
| 1690 | return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMEVER) >= 3; |
| 1691 | } |
| 1692 | |
| 1693 | static inline bool isar_feature_aa64_f8cvt(const ARMISARegisters *id) |
| 1694 | { |
| 1695 | return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8CVT); |
| 1696 | } |
| 1697 | |
| 1698 | static inline bool isar_feature_aa64_f8fma(const ARMISARegisters *id) |
| 1699 | { |
| 1700 | return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8FMA); |
| 1701 | } |
| 1702 | |
| 1703 | static inline bool isar_feature_aa64_f8dp4(const ARMISARegisters *id) |
| 1704 | { |
| 1705 | return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8DP4); |
| 1706 | } |
| 1707 | |
| 1708 | static inline bool isar_feature_aa64_f8dp2(const ARMISARegisters *id) |
| 1709 | { |
| 1710 | return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8DP2); |
| 1711 | } |
| 1712 | |
| 1713 | static inline bool isar_feature_aa64_f8mm8(const ARMISARegisters *id) |
| 1714 | { |
| 1715 | return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8MM8); |
| 1716 | } |
| 1717 | |
| 1718 | static inline bool isar_feature_aa64_f8mm4(const ARMISARegisters *id) |
| 1719 | { |
| 1720 | return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8MM4); |
| 1721 | } |
| 1722 | |
| 1723 | static inline bool isar_feature_aa64_fprcvt(const ARMISARegisters *id) |
| 1724 | { |
| 1725 | return FIELD_EX64_IDREG(id, ID_AA64ISAR3, FPRCVT); |
| 1726 | } |
| 1727 | |
| 1728 | /* |
| 1729 | * Combinations of feature tests, for ease of use with TRANS_FEAT. |
| 1730 | */ |
| 1731 | static inline bool isar_feature_aa64_sme_or_sve(const ARMISARegisters *id) |
| 1732 | { |
| 1733 | return isar_feature_aa64_sme(id) || isar_feature_aa64_sve(id); |
| 1734 | } |
| 1735 | |
| 1736 | static inline bool isar_feature_aa64_sme_or_sve2(const ARMISARegisters *id) |
| 1737 | { |
| 1738 | return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2(id); |
| 1739 | } |
| 1740 | |
| 1741 | static inline bool isar_feature_aa64_sme2_or_sve2(const ARMISARegisters *id) |
| 1742 | { |
| 1743 | return isar_feature_aa64_sme2(id) || isar_feature_aa64_sve2(id); |
| 1744 | } |
| 1745 | |
| 1746 | static inline bool isar_feature_aa64_sme_or_sve2p1(const ARMISARegisters *id) |
| 1747 | { |
| 1748 | return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2p1(id); |
| 1749 | } |
| 1750 | |
| 1751 | static inline bool isar_feature_aa64_sme2_or_sve2p1(const ARMISARegisters *id) |
| 1752 | { |
| 1753 | return isar_feature_aa64_sme2(id) || isar_feature_aa64_sve2p1(id); |
| 1754 | } |
| 1755 | |
| 1756 | static inline bool isar_feature_aa64_sme2p1_or_sve2p1(const ARMISARegisters *id) |
| 1757 | { |
| 1758 | return isar_feature_aa64_sme2p1(id) || isar_feature_aa64_sve2p1(id); |
| 1759 | } |
| 1760 | |
| 1761 | static inline bool isar_feature_aa64_sme2p2_or_sve2p2(const ARMISARegisters *id) |
| 1762 | { |
| 1763 | return isar_feature_aa64_sme2p2(id) || isar_feature_aa64_sve2p2(id); |
| 1764 | } |
| 1765 | |
| 1766 | static inline bool isar_feature_aa64_sme2_sve_b16b16(const ARMISARegisters *id) |
| 1767 | { |
| 1768 | return isar_feature_aa64_sme2(id) && isar_feature_aa64_sve_b16b16(id); |
| 1769 | } |
| 1770 | |
| 1771 | static inline bool isar_feature_aa64_sme2_i16i64(const ARMISARegisters *id) |
| 1772 | { |
| 1773 | return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_i16i64(id); |
| 1774 | } |
| 1775 | |
| 1776 | static inline bool isar_feature_aa64_sme2_f64f64(const ARMISARegisters *id) |
| 1777 | { |
| 1778 | return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_f64f64(id); |
| 1779 | } |
| 1780 | |
| 1781 | static inline bool isar_feature_aa64_sme2_faminmax(const ARMISARegisters *id) |
| 1782 | { |
| 1783 | return isar_feature_aa64_sme2(id) && isar_feature_aa64_faminmax(id); |
| 1784 | } |
| 1785 | |
| 1786 | static inline bool isar_feature_aa64_sme2_f8cvt(const ARMISARegisters *id) |
| 1787 | { |
| 1788 | return isar_feature_aa64_sme2(id) && isar_feature_aa64_f8cvt(id); |
| 1789 | } |
| 1790 | |
| 1791 | static inline bool isar_feature_aa64_sme2p1_lutv2(const ARMISARegisters *id) |
| 1792 | { |
| 1793 | return isar_feature_aa64_sme2p1(id) && isar_feature_aa64_sme_lutv2(id); |
| 1794 | } |
| 1795 | |
| 1796 | static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) |
| 1797 | { |
| 1798 | return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id); |
| 1799 | } |
| 1800 | |
| 1801 | static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) |
| 1802 | { |
| 1803 | return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_bf16(id); |
| 1804 | } |
| 1805 | |
| 1806 | static inline bool isar_feature_aa64_sve2_f8mm8(const ARMISARegisters *id) |
| 1807 | { |
| 1808 | return isar_feature_aa64_sve2(id) && isar_feature_aa64_f8mm8(id); |
| 1809 | } |
| 1810 | |
| 1811 | static inline bool isar_feature_aa64_sve2_f8mm4(const ARMISARegisters *id) |
| 1812 | { |
| 1813 | return isar_feature_aa64_sve2(id) && isar_feature_aa64_f8mm4(id); |
| 1814 | } |
| 1815 | |
| 1816 | static inline bool |
| 1817 | isar_feature_aa64_sme2_or_sve2_faminmax(const ARMISARegisters *id) |
| 1818 | { |
| 1819 | return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_faminmax(id); |
| 1820 | } |
| 1821 | |
| 1822 | static inline bool |
| 1823 | isar_feature_aa64_sme2_or_sve2_f8cvt(const ARMISARegisters *id) |
| 1824 | { |
| 1825 | return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_f8cvt(id); |
| 1826 | } |
| 1827 | |
| 1828 | static inline bool |
| 1829 | isar_feature_aa64_sme2_or_sve2_lut(const ARMISARegisters *id) |
| 1830 | { |
| 1831 | return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_lut(id); |
| 1832 | } |
| 1833 | |
| 1834 | static inline bool |
| 1835 | isar_feature_aa64_sme_f16f16_or_f8f16(const ARMISARegisters *id) |
| 1836 | { |
| 1837 | return isar_feature_aa64_sme_f16f16(id) || isar_feature_aa64_sme_f8f16(id); |
| 1838 | } |
| 1839 | |
| 1840 | static inline bool isar_feature_aa64_sme_mop4_b16b16(const ARMISARegisters *id) |
| 1841 | { |
| 1842 | return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_b16b16(id); |
| 1843 | } |
| 1844 | |
| 1845 | static inline bool isar_feature_aa64_sme_mop4_f16f16(const ARMISARegisters *id) |
| 1846 | { |
| 1847 | return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_f16f16(id); |
| 1848 | } |
| 1849 | |
| 1850 | static inline bool isar_feature_aa64_sme_mop4_f64f64(const ARMISARegisters *id) |
| 1851 | { |
| 1852 | return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_f64f64(id); |
| 1853 | } |
| 1854 | |
| 1855 | static inline bool isar_feature_aa64_sme_mop4_f8f32(const ARMISARegisters *id) |
| 1856 | { |
| 1857 | return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_f8f32(id); |
| 1858 | } |
| 1859 | |
| 1860 | static inline bool isar_feature_aa64_sme_mop4_f8f16(const ARMISARegisters *id) |
| 1861 | { |
| 1862 | return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_f8f16(id); |
| 1863 | } |
| 1864 | |
| 1865 | static inline bool isar_feature_aa64_sme_mop4_i16i64(const ARMISARegisters *id) |
| 1866 | { |
| 1867 | return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_i16i64(id); |
| 1868 | } |
| 1869 | |
| 1870 | static inline bool isar_feature_aa64_sme_tmop_b16b16(const ARMISARegisters *id) |
| 1871 | { |
| 1872 | return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_b16b16(id); |
| 1873 | } |
| 1874 | |
| 1875 | static inline bool isar_feature_aa64_sme_tmop_f16f16(const ARMISARegisters *id) |
| 1876 | { |
| 1877 | return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_f16f16(id); |
| 1878 | } |
| 1879 | |
| 1880 | static inline bool isar_feature_aa64_sme_tmop_f8f16(const ARMISARegisters *id) |
| 1881 | { |
| 1882 | return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_f8f16(id); |
| 1883 | } |
| 1884 | |
| 1885 | static inline bool isar_feature_aa64_sme_tmop_f8f32(const ARMISARegisters *id) |
| 1886 | { |
| 1887 | return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_f8f32(id); |
| 1888 | } |
| 1889 | |
| 1890 | static inline bool isar_feature_aa64_sme2_sve_bfscale(const ARMISARegisters *id) |
| 1891 | { |
| 1892 | return isar_feature_aa64_sme2(id) && isar_feature_aa64_sve_bfscale(id); |
| 1893 | } |
| 1894 | |
| 1895 | /* |
| 1896 | * Feature tests for "does this exist in either 32-bit or 64-bit?" |
| 1897 | */ |
| 1898 | static inline bool isar_feature_any_fp16(const ARMISARegisters *id) |
| 1899 | { |
| 1900 | return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); |
| 1901 | } |
| 1902 | |
| 1903 | static inline bool isar_feature_any_predinv(const ARMISARegisters *id) |
| 1904 | { |
| 1905 | return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); |
| 1906 | } |
| 1907 | |
| 1908 | static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id) |
| 1909 | { |
| 1910 | return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id); |
| 1911 | } |
| 1912 | |
| 1913 | static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) |
| 1914 | { |
| 1915 | return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); |
| 1916 | } |
| 1917 | |
| 1918 | static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) |
| 1919 | { |
| 1920 | return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); |
| 1921 | } |
| 1922 | |
| 1923 | static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) |
| 1924 | { |
| 1925 | return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); |
| 1926 | } |
| 1927 | |
| 1928 | static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) |
| 1929 | { |
| 1930 | return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); |
| 1931 | } |
| 1932 | |
| 1933 | static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) |
| 1934 | { |
| 1935 | return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); |
| 1936 | } |
| 1937 | |
| 1938 | static inline bool isar_feature_any_ras(const ARMISARegisters *id) |
| 1939 | { |
| 1940 | return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); |
| 1941 | } |
| 1942 | |
| 1943 | static inline bool isar_feature_any_half_evt(const ARMISARegisters *id) |
| 1944 | { |
| 1945 | return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id); |
| 1946 | } |
| 1947 | |
| 1948 | static inline bool isar_feature_any_evt(const ARMISARegisters *id) |
| 1949 | { |
| 1950 | return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); |
| 1951 | } |
| 1952 | |
| 1953 | typedef enum { |
| 1954 | CCSIDR_FORMAT_LEGACY, |
| 1955 | CCSIDR_FORMAT_CCIDX, |
| 1956 | } CCSIDRFormat; |
| 1957 | |
| 1958 | static inline uint64_t make_ccsidr(CCSIDRFormat format, unsigned assoc, |
| 1959 | unsigned linesize, unsigned cachesize, |
| 1960 | uint8_t flags) |
| 1961 | { |
| 1962 | unsigned lg_linesize = ctz32(linesize); |
| 1963 | unsigned sets; |
| 1964 | uint64_t ccsidr = 0; |
| 1965 | |
| 1966 | assert(assoc != 0); |
| 1967 | assert(is_power_of_2(linesize)); |
| 1968 | assert(lg_linesize >= 4 && lg_linesize <= 7 + 4); |
| 1969 | |
| 1970 | /* sets * associativity * linesize == cachesize. */ |
| 1971 | sets = cachesize / (assoc * linesize); |
| 1972 | assert(cachesize % (assoc * linesize) == 0); |
| 1973 | |
| 1974 | if (format == CCSIDR_FORMAT_LEGACY) { |
| 1975 | /* |
| 1976 | * The 32-bit CCSIDR format is: |
| 1977 | * [27:13] number of sets - 1 |
| 1978 | * [12:3] associativity - 1 |
| 1979 | * [2:0] log2(linesize) - 4 |
| 1980 | * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc |
| 1981 | */ |
| 1982 | ccsidr = deposit32(ccsidr, 28, 4, flags); |
| 1983 | ccsidr = deposit32(ccsidr, 13, 15, sets - 1); |
| 1984 | ccsidr = deposit32(ccsidr, 3, 10, assoc - 1); |
| 1985 | ccsidr = deposit32(ccsidr, 0, 3, lg_linesize - 4); |
| 1986 | } else { |
| 1987 | /* |
| 1988 | * The 64-bit CCSIDR_EL1 format is: |
| 1989 | * [55:32] number of sets - 1 |
| 1990 | * [23:3] associativity - 1 |
| 1991 | * [2:0] log2(linesize) - 4 |
| 1992 | * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc |
| 1993 | */ |
| 1994 | ccsidr = deposit64(ccsidr, 32, 24, sets - 1); |
| 1995 | ccsidr = deposit64(ccsidr, 3, 21, assoc - 1); |
| 1996 | ccsidr = deposit64(ccsidr, 0, 3, lg_linesize - 4); |
| 1997 | } |
| 1998 | |
| 1999 | return ccsidr; |
| 2000 | } |
| 2001 | |
| 2002 | /* |
| 2003 | * Forward to the above feature tests given an ARMCPU pointer. |
| 2004 | */ |
| 2005 | #define cpu_isar_feature(name, cpu) \ |
| 2006 | ({ const ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) |
| 2007 | |
| 2008 | #endif |