cpu.c · samitouri/QOSamiQemu · siGit Code & Deploy

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1	/*
2	* QEMU ARM CPU
3	*
4	* Copyright (c) 2012 SUSE LINUX Products GmbH
5	*
6	* This program is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU General Public License
8	* as published by the Free Software Foundation; either version 2
9	* of the License, or (at your option) any later version.
10	*
11	* This program is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14	* GNU General Public License for more details.
15	*
16	* You should have received a copy of the GNU General Public License
17	* along with this program; if not, see
18	* <http://www.gnu.org/licenses/gpl-2.0.html>
19	*/
20
21	#include "qemu/osdep.h"
22	#include "qemu/qemu-print.h"
23	#include "qemu/timer.h"
24	#include "qemu/log.h"
25	#include "exec/page-vary.h"
26	#include "system/whpx.h"
27	#include "target/arm/tcg/idau.h"
28	#include "qemu/module.h"
29	#include "qapi/error.h"
30	#include "cpu.h"
31	#ifdef CONFIG_TCG
32	#include "exec/translation-block.h"
33	#include "accel/tcg/cpu-ops.h"
34	#endif /* CONFIG_TCG */
35	#include "internals.h"
36	#include "cpu-features.h"
37	#include "exec/target_page.h"
38	#include "hw/core/qdev-properties.h"
39	#if !defined(CONFIG_USER_ONLY)
40	#include "hw/core/loader.h"
41	#include "hw/core/boards.h"
42	#include "hw/intc/arm_gicv5_stream.h"
43	#ifdef CONFIG_TCG
44	#include "hw/intc/armv7m_nvic.h"
45	#endif /* CONFIG_TCG */
46	#endif /* !CONFIG_USER_ONLY */
47	#include "system/tcg.h"
48	#include "system/qtest.h"
49	#include "system/hw_accel.h"
50	#include "kvm_arm.h"
51	#include "disas/capstone.h"
52	#include "fpu/softfloat.h"
53	#include "cpregs.h"
54	#include "target/arm/cpu-qom.h"
55	#include "target/arm/gtimer.h"
56
57	#include "trace.h"
58
59	static void arm_cpu_set_pc(CPUState *cs, vaddr value)
60	{
61	ARMCPU *cpu = ARM_CPU(cs);
62	CPUARMState *env = &cpu->env;
63
64	if (is_a64(env)) {
65	env->pc = value;
66	env->thumb = false;
67	} else {
68	env->regs[15] = value & ~1;
69	env->thumb = value & 1;
70	}
71	}
72
73	static vaddr arm_cpu_get_pc(CPUState *cs)
74	{
75	ARMCPU *cpu = ARM_CPU(cs);
76	CPUARMState *env = &cpu->env;
77
78	if (is_a64(env)) {
79	return env->pc;
80	} else {
81	return env->regs[15];
82	}
83	}
84
85	#ifdef CONFIG_TCG
86	void arm_cpu_synchronize_from_tb(CPUState *cs,
87	const TranslationBlock *tb)
88	{
89	/* The program counter is always up to date with CF_PCREL. */
90	if (!(tb_cflags(tb) & CF_PCREL)) {
91	CPUARMState *env = cpu_env(cs);
92	/*
93	* It's OK to look at env for the current mode here, because it's
94	* never possible for an AArch64 TB to chain to an AArch32 TB.
95	*/
96	if (is_a64(env)) {
97	env->pc = tb->pc;
98	} else {
99	env->regs[15] = tb->pc;
100	}
101	}
102	}
103
104	void arm_restore_state_to_opc(CPUState *cs,
105	const TranslationBlock *tb,
106	const uint64_t *data)
107	{
108	CPUARMState *env = cpu_env(cs);
109
110	if (is_a64(env)) {
111	if (tb_cflags(tb) & CF_PCREL) {
112	env->pc = (env->pc & TARGET_PAGE_MASK) \| data[0];
113	} else {
114	env->pc = data[0];
115	}
116	env->condexec_bits = 0;
117	env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
118	} else {
119	if (tb_cflags(tb) & CF_PCREL) {
120	env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) \| data[0];
121	} else {
122	env->regs[15] = data[0];
123	}
124	env->condexec_bits = data[1];
125	env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
126	}
127	}
128
129	int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
130	{
131	return arm_env_mmu_index(cpu_env(cs));
132	}
133
134	#endif /* CONFIG_TCG */
135
136	#ifndef CONFIG_USER_ONLY
137	/*
138	* With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with
139	* IRQ without Superpriority. Moreover, if the GIC is configured so that
140	* FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see
141	* CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here
142	* unconditionally.
143	*/
144	static bool arm_cpu_has_work(CPUState *cs)
145	{
146	ARMCPU *cpu = ARM_CPU(cs);
147
148	/*
149	* Only another PSCI call can wake the CPU up in which case the
150	* power_state would be set by arm_set_cpu_on_and_reset_async_work()
151	*/
152	if (cpu->power_state == PSCI_OFF) {
153	g_assert(cpu->env.halt_reason == HALT_PSCI);
154	return false;
155	}
156
157	/*
158	* A wake-up event should only wake us if we are halted on a WFE
159	*/
160	if (cpu->env.halt_reason == HALT_WFE && cpu->env.event_register) {
161	return true;
162	}
163
164	/*
165	* Otherwise pretty much any IRQ would wake us up
166	*/
167	if (cpu_test_interrupt(cs,
168	CPU_INTERRUPT_FIQ \| CPU_INTERRUPT_HARD
169	\| CPU_INTERRUPT_NMI \| CPU_INTERRUPT_VINMI \| CPU_INTERRUPT_VFNMI
170	\| CPU_INTERRUPT_VFIQ \| CPU_INTERRUPT_VIRQ \| CPU_INTERRUPT_VSERR
171	\| CPU_INTERRUPT_EXITTB)) {
172	return true;
173	}
174
175	return false;
176	}
177	#endif /* !CONFIG_USER_ONLY */
178
179	void arm_register_pre_el_change_hook(ARMCPU cpu, ARMELChangeHookFn hook,
180	void *opaque)
181	{
182	ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
183
184	entry->hook = hook;
185	entry->opaque = opaque;
186
187	QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
188	}
189
190	void arm_register_el_change_hook(ARMCPU cpu, ARMELChangeHookFn hook,
191	void *opaque)
192	{
193	ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
194
195	entry->hook = hook;
196	entry->opaque = opaque;
197
198	QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
199	}
200
201	static ARMCPRegMigTolerance find_mig_tolerance(ARMCPU cpu, uint64_t kvmidx)
202	{
203	ARMCPRegMigTolerance *t;
204	QLIST_FOREACH(t, &cpu->cpreg_mig_tolerances, node) {
205	if (t->kvmidx == kvmidx) {
206	return t;
207	}
208	}
209	return NULL;
210	}
211
212	void arm_register_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx,
213	uint64_t mask, uint64_t value,
214	ARMCPRegMigToleranceType type)
215	{
216	ARMCPRegMigTolerance *entry;
217
218	/* make sure the kvmidx has not tolerance already registered */
219	assert(!find_mig_tolerance(cpu, kvmidx));
220
221	assert(type == ToleranceNotOnBothEnds \|\|
222	type == ToleranceOnlySrcTestValue);
223
224	entry = g_new0(ARMCPRegMigTolerance, 1);
225
226	entry->kvmidx = kvmidx;
227	entry->mask = mask;
228	entry->value = value;
229	entry->type = type;
230
231	QLIST_INSERT_HEAD(&cpu->cpreg_mig_tolerances, entry, node);
232	}
233
234	bool arm_cpu_match_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx,
235	uint64_t vmstate_value, uint64_t local_value,
236	ARMCPRegMigToleranceType type)
237	{
238	ARMCPRegMigTolerance *t = find_mig_tolerance(cpu, kvmidx);
239	uint64_t diff, diff_outside_mask, field;
240
241	if (!t \|\| t->type != type) {
242	return false;
243	}
244
245	if (type == ToleranceNotOnBothEnds) {
246	return true;
247	}
248
249	if (type == ToleranceOnlySrcTestValue &&
250	((vmstate_value & t->mask) == t->value)) {
251	return true;
252	}
253
254	/* Need to check the mask */
255	diff = vmstate_value ^ local_value;
256	diff_outside_mask = diff & ~t->mask;
257
258	if (diff_outside_mask) {
259	/* there are differences outside of the mask */
260	return false;
261	}
262	if (type == ToleranceDiffInMask) {
263	/* differences only in the field, tolerance matched */
264	return true;
265	}
266	/* need to compare field value against authorized ones */
267	field = vmstate_value & t->mask;
268	if (type == ToleranceFieldLT && (field < t->value)) {
269	return true;
270	}
271	if (type == ToleranceFieldGT && (field > t->value)) {
272	return true;
273	}
274	return false;
275	}
276
277	static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
278	{
279	/* Reset a single ARMCPRegInfo register */
280	ARMCPRegInfo *ri = value;
281	ARMCPU *cpu = opaque;
282
283	if (ri->type & (ARM_CP_SPECIAL_MASK \| ARM_CP_ALIAS)) {
284	return;
285	}
286
287	if (ri->resetfn) {
288	ri->resetfn(&cpu->env, ri);
289	return;
290	}
291
292	/* A zero offset is never possible as it would be regs[0]
293	* so we use it to indicate that reset is being handled elsewhere.
294	* This is basically only used for fields in non-core coprocessors
295	* (like the pxa2xx ones).
296	*/
297	if (ri->fieldoffset) {
298	raw_write(&cpu->env, ri, ri->resetvalue);
299	}
300	}
301
302	static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
303	{
304	/* Purely an assertion check: we've already done reset once,
305	* so now check that running the reset for the cpreg doesn't
306	* change its value. This traps bugs where two different cpregs
307	* both try to reset the same state field but to different values.
308	*/
309	ARMCPRegInfo *ri = value;
310	ARMCPU *cpu = opaque;
311	uint64_t oldvalue, newvalue;
312
313	if (ri->type & (ARM_CP_SPECIAL_MASK \| ARM_CP_ALIAS \| ARM_CP_NO_RAW)) {
314	return;
315	}
316
317	oldvalue = read_raw_cp_reg(&cpu->env, ri);
318	cp_reg_reset(key, value, opaque);
319	newvalue = read_raw_cp_reg(&cpu->env, ri);
320	assert(oldvalue == newvalue);
321	}
322
323	static void arm_init_fp_status(float_status *s)
324	{
325	memset(s, 0, sizeof(*s));
326	arm_set_default_fp_behaviours(s);
327	set_float_e4m3_nan_is_snan(true, s);
328	/* We want 0 for all other settings. */
329	}
330
331	static void arm_cpu_reset_hold(Object *obj, ResetType type)
332	{
333	CPUState *cs = CPU(obj);
334	ARMCPU *cpu = ARM_CPU(cs);
335	ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
336	CPUARMState *env = &cpu->env;
337
338	trace_arm_cpu_reset(arm_cpu_mp_affinity(cpu));
339
340	if (acc->parent_phases.hold) {
341	acc->parent_phases.hold(obj, type);
342	}
343
344	memset(env, 0, offsetof(CPUARMState, end_reset_fields));
345
346	g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
347	g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
348
349	env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
350	env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
351	env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
352	env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
353
354	arm_set_cpu_power_state(cpu, cs->start_powered_off ? PSCI_OFF : PSCI_ON);
355
356	if (arm_feature(env, ARM_FEATURE_AARCH64)) {
357	/* 64 bit CPUs always start in 64 bit mode */
358	env->aarch64 = true;
359	#if defined(CONFIG_USER_ONLY)
360	env->pstate = PSTATE_MODE_EL0t;
361	/* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
362	env->cp15.sctlr_el[1] \|= SCTLR_UCT \| SCTLR_UCI \| SCTLR_DZE;
363	/* Enable all PAC keys. */
364	env->cp15.sctlr_el[1] \|= (SCTLR_EnIA \| SCTLR_EnIB \|
365	SCTLR_EnDA \| SCTLR_EnDB);
366	/* Trap on btype=3 for PACIxSP. */
367	env->cp15.sctlr_el[1] \|= SCTLR_BT0;
368	/* Trap on implementation defined registers. */
369	if (cpu_isar_feature(aa64_tidcp1, cpu)) {
370	env->cp15.sctlr_el[1] \|= SCTLR_TIDCP;
371	}
372	/* and to the FP/Neon instructions */
373	env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
374	CPACR_EL1, FPEN, 3);
375	/* and to the SVE instructions, with default vector length */
376	if (cpu_isar_feature(aa64_sve, cpu)) {
377	env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
378	CPACR_EL1, ZEN, 3);
379	env->vfp.zcr_el[1] = cpu->sve_default_vq - 1;
380	}
381	/* and for SME instructions, with default vector length, and TPIDR2 */
382	if (cpu_isar_feature(aa64_sme, cpu)) {
383	env->cp15.sctlr_el[1] \|= SCTLR_EnTP2;
384	env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
385	CPACR_EL1, SMEN, 3);
386	env->vfp.smcr_el[1] = cpu->sme_default_vq - 1;
387	if (cpu_isar_feature(aa64_sme_fa64, cpu)) {
388	env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1],
389	SMCR, FA64, 1);
390	}
391	}
392	/*
393	* Enable 48-bit address space (TODO: take reserved_va into account).
394	* Enable TBI0 but not TBI1.
395	* Note that this must match useronly_clean_ptr.
396	*/
397	env->cp15.tcr_el[1] = 5 \| (1ULL << 37);
398
399	/* Enable MTE */
400	if (cpu_isar_feature(aa64_mte, cpu)) {
401	/* Enable tag access, but leave TCF0 as No Effect (0). */
402	env->cp15.sctlr_el[1] \|= SCTLR_ATA0;
403	/*
404	* Exclude all tags, so that tag 0 is always used.
405	* This corresponds to Linux current->thread.gcr_incl = 0.
406	*
407	* Set RRND, so that helper_irg() will generate a seed later.
408	* Here in cpu_reset(), the crypto subsystem has not yet been
409	* initialized.
410	*/
411	env->cp15.gcr_el1 = 0x1ffff;
412	}
413	/*
414	* Disable access to SCXTNUM_EL0 from CSV2_1p2.
415	* This is not yet exposed from the Linux kernel in any way.
416	*/
417	env->cp15.sctlr_el[1] \|= SCTLR_TSCXT;
418	/* Disable access to Debug Communication Channel (DCC). */
419	env->cp15.mdscr_el1 \|= 1 << 12;
420	/* Enable FEAT_MOPS */
421	env->cp15.sctlr_el[1] \|= SCTLR_MSCEN;
422	/* Enable FEAT_FPMR */
423	if (cpu_isar_feature(aa64_fpmr, cpu)) {
424	env->cp15.sctlr_el[1] \|= SCTLR_EnFPM;
425	}
426	/* For Linux, GCSPR_EL0 is always readable. */
427	if (cpu_isar_feature(aa64_gcs, cpu)) {
428	env->cp15.gcscr_el[0] = GCSCRE0_NTR;
429	}
430	#else
431	/* Reset into the highest available EL */
432	if (arm_feature(env, ARM_FEATURE_EL3)) {
433	env->pstate = PSTATE_MODE_EL3h;
434	} else if (arm_feature(env, ARM_FEATURE_EL2)) {
435	env->pstate = PSTATE_MODE_EL2h;
436	} else {
437	env->pstate = PSTATE_MODE_EL1h;
438	}
439
440	/* Sample rvbar at reset. */
441	env->cp15.rvbar = cpu->rvbar_prop;
442	env->pc = env->cp15.rvbar;
443	#endif
444	} else {
445	#if defined(CONFIG_USER_ONLY)
446	/* Userspace expects access to cp10 and cp11 for FP/Neon */
447	env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
448	CPACR, CP10, 3);
449	env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
450	CPACR, CP11, 3);
451	#endif
452	if (arm_feature(env, ARM_FEATURE_V8)) {
453	env->cp15.rvbar = cpu->rvbar_prop;
454	env->regs[15] = cpu->rvbar_prop;
455	}
456	}
457
458	#if defined(CONFIG_USER_ONLY)
459	env->uncached_cpsr = ARM_CPU_MODE_USR;
460	/* For user mode we must enable access to coprocessors */
461	env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
462	#else
463
464	/*
465	* If the highest available EL is EL2, AArch32 will start in Hyp
466	* mode; otherwise it starts in SVC. Note that if we start in
467	* AArch64 then these values in the uncached_cpsr will be ignored.
468	*/
469	if (arm_feature(env, ARM_FEATURE_EL2) &&
470	!arm_feature(env, ARM_FEATURE_EL3)) {
471	env->uncached_cpsr = ARM_CPU_MODE_HYP;
472	} else {
473	env->uncached_cpsr = ARM_CPU_MODE_SVC;
474	}
475	env->daif = PSTATE_D \| PSTATE_A \| PSTATE_I \| PSTATE_F;
476
477	/* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
478	* executing as AArch32 then check if highvecs are enabled and
479	* adjust the PC accordingly.
480	*/
481	if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
482	env->regs[15] = 0xFFFF0000;
483	}
484
485	env->vfp.xregs[ARM_VFP_FPEXC] = 0;
486	#endif
487
488	if (arm_feature(env, ARM_FEATURE_M)) {
489	#ifndef CONFIG_USER_ONLY
490	uint32_t initial_msp; /* Loaded from 0x0 */
491	uint32_t initial_pc; /* Loaded from 0x4 */
492	uint8_t *rom;
493	uint32_t vecbase;
494	#endif
495
496	if (cpu_isar_feature(aa32_lob, cpu)) {
497	/*
498	* LTPSIZE is constant 4 if MVE not implemented, and resets
499	* to an UNKNOWN value if MVE is implemented. We choose to
500	* always reset to 4.
501	*/
502	env->v7m.ltpsize = 4;
503	/* The LTPSIZE field in FPDSCR is constant and reads as 4. */
504	env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
505	env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
506	}
507
508	if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
509	env->v7m.secure = true;
510	} else {
511	/* This bit resets to 0 if security is supported, but 1 if
512	* it is not. The bit is not present in v7M, but we set it
513	* here so we can avoid having to make checks on it conditional
514	* on ARM_FEATURE_V8 (we don't let the guest see the bit).
515	*/
516	env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
517	/*
518	* Set NSACR to indicate "NS access permitted to everything";
519	* this avoids having to have all the tests of it being
520	* conditional on ARM_FEATURE_M_SECURITY. Note also that from
521	* v8.1M the guest-visible value of NSACR in a CPU without the
522	* Security Extension is 0xcff.
523	*/
524	env->v7m.nsacr = 0xcff;
525	}
526
527	/* In v7M the reset value of this bit is IMPDEF, but ARM recommends
528	* that it resets to 1, so QEMU always does that rather than making
529	* it dependent on CPU model. In v8M it is RES1.
530	*/
531	env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
532	env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
533	if (arm_feature(env, ARM_FEATURE_V8)) {
534	/* in v8M the NONBASETHRDENA bit [0] is RES1 */
535	env->v7m.ccr[M_REG_NS] \|= R_V7M_CCR_NONBASETHRDENA_MASK;
536	env->v7m.ccr[M_REG_S] \|= R_V7M_CCR_NONBASETHRDENA_MASK;
537	}
538	if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
539	env->v7m.ccr[M_REG_NS] \|= R_V7M_CCR_UNALIGN_TRP_MASK;
540	env->v7m.ccr[M_REG_S] \|= R_V7M_CCR_UNALIGN_TRP_MASK;
541	}
542
543	if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
544	env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
545	env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK \|
546	R_V7M_FPCCR_LSPEN_MASK \| R_V7M_FPCCR_S_MASK;
547	}
548
549	#ifndef CONFIG_USER_ONLY
550	/* Unlike A/R profile, M profile defines the reset LR value */
551	env->regs[14] = 0xffffffff;
552
553	env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
554	env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80;
555
556	/* Load the initial SP and PC from offset 0 and 4 in the vector table */
557	vecbase = env->v7m.vecbase[env->v7m.secure];
558	rom = rom_ptr_for_as(cs->as, vecbase, 8);
559	if (rom) {
560	/* Address zero is covered by ROM which hasn't yet been
561	* copied into physical memory.
562	*/
563	initial_msp = ldl_p(rom);
564	initial_pc = ldl_p(rom + 4);
565	} else {
566	/* Address zero not covered by a ROM blob, or the ROM blob
567	* is in non-modifiable memory and this is a second reset after
568	* it got copied into memory. In the latter case, rom_ptr
569	* will return a NULL pointer and we should use ldl_phys instead.
570	*/
571	initial_msp = ldl_phys(cs->as, vecbase);
572	initial_pc = ldl_phys(cs->as, vecbase + 4);
573	}
574
575	qemu_log_mask(CPU_LOG_INT,
576	"Loaded reset SP 0x%x PC 0x%x from vector table\n",
577	initial_msp, initial_pc);
578
579	env->regs[13] = initial_msp & 0xFFFFFFFC;
580	env->regs[15] = initial_pc & ~1;
581	env->thumb = initial_pc & 1;
582	#else
583	/*
584	* For user mode we run non-secure and with access to the FPU.
585	* The FPU context is active (ie does not need further setup)
586	* and is owned by non-secure.
587	*/
588	env->v7m.secure = false;
589	env->v7m.nsacr = 0xcff;
590	env->v7m.cpacr[M_REG_NS] = 0xf0ffff;
591	env->v7m.fpccr[M_REG_S] &=
592	~(R_V7M_FPCCR_LSPEN_MASK \| R_V7M_FPCCR_S_MASK);
593	env->v7m.control[M_REG_S] \|= R_V7M_CONTROL_FPCA_MASK;
594	#endif
595	}
596
597	/* M profile requires that reset clears the exclusive monitor;
598	* A profile does not, but clearing it makes more sense than having it
599	* set with an exclusive access on address zero.
600	*/
601	arm_clear_exclusive(env);
602
603	if (arm_feature(env, ARM_FEATURE_PMSA)) {
604	if (cpu->pmsav7_dregion > 0) {
605	if (arm_feature(env, ARM_FEATURE_V8)) {
606	memset(env->pmsav8.rbar[M_REG_NS], 0,
607	sizeof(*env->pmsav8.rbar[M_REG_NS])
608	* cpu->pmsav7_dregion);
609	memset(env->pmsav8.rlar[M_REG_NS], 0,
610	sizeof(*env->pmsav8.rlar[M_REG_NS])
611	* cpu->pmsav7_dregion);
612	if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
613	memset(env->pmsav8.rbar[M_REG_S], 0,
614	sizeof(*env->pmsav8.rbar[M_REG_S])
615	* cpu->pmsav7_dregion);
616	memset(env->pmsav8.rlar[M_REG_S], 0,
617	sizeof(*env->pmsav8.rlar[M_REG_S])
618	* cpu->pmsav7_dregion);
619	}
620	} else if (arm_feature(env, ARM_FEATURE_V7)) {
621	memset(env->pmsav7.drbar, 0,
622	sizeof(env->pmsav7.drbar) cpu->pmsav7_dregion);
623	memset(env->pmsav7.drsr, 0,
624	sizeof(env->pmsav7.drsr) cpu->pmsav7_dregion);
625	memset(env->pmsav7.dracr, 0,
626	sizeof(env->pmsav7.dracr) cpu->pmsav7_dregion);
627	}
628	}
629
630	if (cpu->pmsav8r_hdregion > 0) {
631	memset(env->pmsav8.hprbar, 0,
632	sizeof(env->pmsav8.hprbar) cpu->pmsav8r_hdregion);
633	memset(env->pmsav8.hprlar, 0,
634	sizeof(env->pmsav8.hprlar) cpu->pmsav8r_hdregion);
635	}
636
637	env->pmsav7.rnr[M_REG_NS] = 0;
638	env->pmsav7.rnr[M_REG_S] = 0;
639	env->pmsav8.mair0[M_REG_NS] = 0;
640	env->pmsav8.mair0[M_REG_S] = 0;
641	env->pmsav8.mair1[M_REG_NS] = 0;
642	env->pmsav8.mair1[M_REG_S] = 0;
643	}
644
645	if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
646	if (cpu->sau_sregion > 0) {
647	memset(env->sau.rbar, 0, sizeof(env->sau.rbar) cpu->sau_sregion);
648	memset(env->sau.rlar, 0, sizeof(env->sau.rlar) cpu->sau_sregion);
649	}
650	env->sau.rnr = 0;
651	/* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
652	* the Cortex-M33 does.
653	*/
654	env->sau.ctrl = 0;
655	}
656
657	for (int i = 0; i < FPST_COUNT; i++) {
658	arm_init_fp_status(&env->vfp.fp_status[i]);
659	}
660
661	set_flush_to_zero(1, &env->vfp.fp_status[FPST_STD]);
662	set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]);
663	set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]);
664	set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]);
665	set_default_nan_mode(1, &env->vfp.fp_status[FPST_ZA]);
666	set_default_nan_mode(1, &env->vfp.fp_status[FPST_ZA_F16]);
667	arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]);
668	set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]);
669	set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_AH]);
670	arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]);
671
672	#ifndef CONFIG_USER_ONLY
673	if (kvm_enabled()) {
674	kvm_arm_reset_vcpu(cpu);
675	}
676	#endif
677
678	if (tcg_enabled()) {
679	hw_breakpoint_update_all(cpu);
680	hw_watchpoint_update_all(cpu);
681
682	arm_rebuild_hflags(env);
683	}
684	}
685
686	void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
687	{
688	ARMCPU *cpu = ARM_CPU(cpustate);
689	CPUARMState *env = &cpu->env;
690	bool have_el3 = arm_feature(env, ARM_FEATURE_EL3);
691	bool have_el2 = arm_feature(env, ARM_FEATURE_EL2);
692
693	trace_arm_emulate_firmware_reset(arm_cpu_mp_affinity(cpu), target_el);
694
695	/*
696	* Check we have the EL we're aiming for. If that is the
697	* highest implemented EL, then cpu_reset has already done
698	* all the work.
699	*/
700	switch (target_el) {
701	case 3:
702	assert(have_el3);
703	return;
704	case 2:
705	assert(have_el2);
706	if (!have_el3) {
707	return;
708	}
709	break;
710	case 1:
711	if (!have_el3 && !have_el2) {
712	return;
713	}
714	break;
715	default:
716	g_assert_not_reached();
717	}
718
719	if (have_el3) {
720	/*
721	* Set the EL3 state so code can run at EL2. This should match
722	* the requirements set by Linux in its booting spec.
723	*/
724	if (env->aarch64) {
725	env->cp15.scr_el3 \|= SCR_RW;
726	if (cpu_isar_feature(aa64_pauth, cpu)) {
727	env->cp15.scr_el3 \|= SCR_API \| SCR_APK;
728	}
729	if (cpu_isar_feature(aa64_mte, cpu)) {
730	env->cp15.scr_el3 \|= SCR_ATA;
731	}
732	if (cpu_isar_feature(aa64_sve, cpu)) {
733	env->cp15.cptr_el[3] \|= R_CPTR_EL3_EZ_MASK;
734	env->vfp.zcr_el[3] = 0xf;
735	}
736	if (cpu_isar_feature(aa64_sme, cpu)) {
737	env->cp15.cptr_el[3] \|= R_CPTR_EL3_ESM_MASK;
738	env->cp15.scr_el3 \|= SCR_ENTP2;
739	env->vfp.smcr_el[3] = 0xf;
740	if (cpu_isar_feature(aa64_sme2, cpu)) {
741	env->vfp.smcr_el[3] \|= R_SMCR_EZT0_MASK;
742	}
743	}
744	if (cpu_isar_feature(aa64_hcx, cpu)) {
745	env->cp15.scr_el3 \|= SCR_HXEN;
746	}
747	if (cpu_isar_feature(aa64_fgt, cpu)) {
748	env->cp15.scr_el3 \|= SCR_FGTEN;
749	}
750	if (cpu_isar_feature(aa64_gcs, cpu)) {
751	env->cp15.scr_el3 \|= SCR_GCSEN;
752	}
753	if (cpu_isar_feature(aa64_tcr2, cpu)) {
754	env->cp15.scr_el3 \|= SCR_TCR2EN;
755	}
756	if (cpu_isar_feature(aa64_sctlr2, cpu)) {
757	env->cp15.scr_el3 \|= SCR_SCTLR2EN;
758	}
759	if (cpu_isar_feature(aa64_s1pie, cpu) \|\|
760	cpu_isar_feature(aa64_s2pie, cpu)) {
761	env->cp15.scr_el3 \|= SCR_PIEN;
762	}
763	if (cpu_isar_feature(aa64_aie, cpu)) {
764	env->cp15.scr_el3 \|= SCR_AIEN;
765	}
766	if (cpu_isar_feature(aa64_mec, cpu)) {
767	env->cp15.scr_el3 \|= SCR_MECEN;
768	}
769	if (cpu_isar_feature(aa64_fpmr, cpu)) {
770	env->cp15.scr_el3 \|= SCR_ENFPM;
771	}
772	}
773
774	if (target_el == 2) {
775	/* If the guest is at EL2 then Linux expects the HVC insn to work */
776	env->cp15.scr_el3 \|= SCR_HCE;
777	}
778
779	/* Put CPU into non-secure state */
780	env->cp15.scr_el3 \|= SCR_NS;
781	/* Set NSACR.{CP11,CP10} so NS can access the FPU */
782	env->cp15.nsacr \|= R_NSACR_CP10_MASK \| R_NSACR_CP11_MASK;
783	}
784
785	if (have_el2 && target_el < 2) {
786	/* Set EL2 state so code can run at EL1. */
787	if (env->aarch64) {
788	env->cp15.hcr_el2 \|= HCR_RW;
789	}
790	}
791
792	/* Set the CPU to the desired state */
793	if (env->aarch64) {
794	env->pstate = aarch64_pstate_mode(target_el, true);
795	} else {
796	static const uint32_t mode_for_el[] = {
797	0,
798	ARM_CPU_MODE_SVC,
799	ARM_CPU_MODE_HYP,
800	ARM_CPU_MODE_SVC,
801	};
802
803	cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw);
804	}
805	}
806
807
808	#ifndef CONFIG_USER_ONLY
809	static void arm_cpu_set_irq(void *opaque, int irq, int level)
810	{
811	ARMCPU *cpu = opaque;
812	CPUARMState *env = &cpu->env;
813	CPUState *cs = CPU(cpu);
814	static const int mask[] = {
815	[ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
816	[ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
817	[ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
818	[ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ,
819	[ARM_CPU_NMI] = CPU_INTERRUPT_NMI,
820	[ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI,
821	};
822
823	if (!arm_feature(env, ARM_FEATURE_EL2) &&
824	(irq == ARM_CPU_VIRQ \|\| irq == ARM_CPU_VFIQ)) {
825	/*
826	* The GIC might tell us about VIRQ and VFIQ state, but if we don't
827	* have EL2 support we don't care. (Unless the guest is doing something
828	* silly this will only be calls saying "level is still 0".)
829	*/
830	return;
831	}
832
833	if (level) {
834	env->irq_line_state \|= mask[irq];
835	} else {
836	env->irq_line_state &= ~mask[irq];
837	}
838
839	switch (irq) {
840	case ARM_CPU_VIRQ:
841	arm_cpu_update_virq(cpu);
842	break;
843	case ARM_CPU_VFIQ:
844	arm_cpu_update_vfiq(cpu);
845	break;
846	case ARM_CPU_VINMI:
847	arm_cpu_update_vinmi(cpu);
848	break;
849	case ARM_CPU_IRQ:
850	case ARM_CPU_FIQ:
851	case ARM_CPU_NMI:
852	if (level) {
853	cpu_interrupt(cs, mask[irq]);
854	} else {
855	cpu_reset_interrupt(cs, mask[irq]);
856	}
857	break;
858	default:
859	g_assert_not_reached();
860	}
861	}
862
863	static bool arm_cpu_internal_is_big_endian(CPUState *cs)
864	{
865	ARMCPU *cpu = ARM_CPU(cs);
866	CPUARMState *env = &cpu->env;
867
868	cpu_synchronize_state(cs);
869	return arm_cpu_data_is_big_endian(env);
870	}
871
872	#ifdef CONFIG_TCG
873	bool arm_cpu_exec_halt(CPUState *cs)
874	{
875	bool leave_halt = cpu_has_work(cs);
876
877	if (leave_halt) {
878	/* We're about to come out of WFI/WFE: disable the WFxT timer */
879	ARMCPU *cpu = ARM_CPU(cs);
880	if (cpu->wfxt_timer) {
881	timer_del(cpu->wfxt_timer);
882	}
883	/* clear the halt reason */
884	cpu->env.halt_reason = NOT_HALTED;
885	}
886	return leave_halt;
887	}
888	#endif
889
890	/*
891	* Unlike almost everything else that messes with the halt_reason and
892	* event_register details the timer callbacks are not in the vCPU
893	* context.
894	*
895	* To prevent races we atomically consume a HALT_WFE and set the event
896	* register. Either way we trigger the an exit event.
897	*/
898	static void arm_wfxt_timer_cb(void *opaque)
899	{
900	ARMCPU *cpu = opaque;
901	CPUState *cs = CPU(cpu);
902	CPUARMState *env = &cpu->env;
903
904	if (qatomic_cmpxchg(&env->halt_reason, HALT_WFE, NOT_HALTED)) {
905	qatomic_set(&env->event_register, true);
906	}
907
908	/*
909	* We expect the CPU to be halted; this will cause arm_cpu_is_work()
910	* to return true (so we will come out of halt even with no other
911	* pending interrupt), and the TCG accelerator's cpu_exec_interrupt()
912	* function auto-clears the CPU_INTERRUPT_EXITTB flag for us.
913	*/
914	cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
915	}
916	#endif
917
918	static void arm_disas_set_info(const CPUState cpu, disassemble_info info)
919	{
920	const ARMCPU *ac = ARM_CPU(cpu);
921	const CPUARMState *env = &ac->env;
922	bool sctlr_b = arm_sctlr_b(env);
923
924	if (is_a64(env)) {
925	info->cap_arch = CS_ARCH_ARM64;
926	info->cap_insn_unit = 4;
927	info->cap_insn_split = 4;
928	} else {
929	int cap_mode;
930	if (env->thumb) {
931	info->cap_insn_unit = 2;
932	info->cap_insn_split = 4;
933	cap_mode = CS_MODE_THUMB;
934	} else {
935	info->cap_insn_unit = 4;
936	info->cap_insn_split = 4;
937	cap_mode = CS_MODE_ARM;
938	}
939	if (arm_feature(env, ARM_FEATURE_V8)) {
940	cap_mode \|= CS_MODE_V8;
941	}
942	if (arm_feature(env, ARM_FEATURE_M)) {
943	cap_mode \|= CS_MODE_MCLASS;
944	}
945	info->cap_arch = CS_ARCH_ARM;
946	info->cap_mode = cap_mode;
947	}
948
949	info->endian = BFD_ENDIAN_LITTLE;
950	info->flags &= ~INSN_ARM_BE32;
951	if (sctlr_b) {
952	info->endian \|= BFD_ENDIAN_BIG;
953	info->flags \|= INSN_ARM_BE32;
954	}
955	}
956
957	static void aarch64_cpu_dump_state(CPUState cs, FILE f, int flags)
958	{
959	ARMCPU *cpu = ARM_CPU(cs);
960	CPUARMState *env = &cpu->env;
961	uint64_t psr = pstate_read(env);
962	int i, j;
963	int el = arm_current_el(env);
964	uint64_t hcr = arm_hcr_el2_eff(env);
965	const char *ns_status;
966	bool sve;
967
968	qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
969	for (i = 0; i < 32; i++) {
970	if (i == 31) {
971	qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
972	} else {
973	qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
974	(i + 2) % 3 ? " " : "\n");
975	}
976	}
977
978	if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
979	ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
980	} else {
981	ns_status = "";
982	}
983	qemu_fprintf(f, "PSTATE=%016" PRIx64 " %c%c%c%c %sEL%d%c",
984	psr,
985	psr & PSTATE_N ? 'N' : '-',
986	psr & PSTATE_Z ? 'Z' : '-',
987	psr & PSTATE_C ? 'C' : '-',
988	psr & PSTATE_V ? 'V' : '-',
989	ns_status,
990	el,
991	psr & PSTATE_SP ? 'h' : 't');
992
993	if (cpu_isar_feature(aa64_sme, cpu)) {
994	qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c",
995	env->svcr,
996	(FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'),
997	(FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-'));
998	}
999	if (cpu_isar_feature(aa64_bti, cpu)) {
1000	qemu_fprintf(f, " BTYPE=%d", (int)(psr & PSTATE_BTYPE) >> 10);
1001	}
1002	qemu_fprintf(f, "%s%s%s",
1003	(hcr & HCR_NV) ? " NV" : "",
1004	(hcr & HCR_NV1) ? " NV1" : "",
1005	(hcr & HCR_NV2) ? " NV2" : "");
1006	if (!(flags & CPU_DUMP_FPU)) {
1007	qemu_fprintf(f, "\n");
1008	return;
1009	}
1010	if (fp_exception_el(env, el) != 0) {
1011	qemu_fprintf(f, " FPU disabled\n");
1012	return;
1013	}
1014	qemu_fprintf(f, " FPCR=%08x FPSR=%08x",
1015	vfp_get_fpcr(env), vfp_get_fpsr(env));
1016	if (cpu_isar_feature(aa64_fpmr, cpu)) {
1017	qemu_fprintf(f, " FPMR=0x%" PRIx64, env->vfp.fpmr);
1018	}
1019	qemu_fprintf(f, "\n");
1020
1021	if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) {
1022	sve = sme_exception_el(env, el) == 0;
1023	} else if (cpu_isar_feature(aa64_sve, cpu)) {
1024	sve = sve_exception_el(env, el) == 0;
1025	} else {
1026	sve = false;
1027	}
1028
1029	if (sve) {
1030	int zcr_len = sve_vqm1_for_el(env, el);
1031
1032	for (i = 0; i <= FFR_PRED_NUM; i++) {
1033	bool eol;
1034	if (i == FFR_PRED_NUM) {
1035	qemu_fprintf(f, "FFR=");
1036	/* It's last, so end the line. */
1037	eol = true;
1038	} else {
1039	qemu_fprintf(f, "P%02d=", i);
1040	switch (zcr_len) {
1041	case 0:
1042	eol = i % 8 == 7;
1043	break;
1044	case 1:
1045	eol = i % 6 == 5;
1046	break;
1047	case 2:
1048	case 3:
1049	eol = i % 3 == 2;
1050	break;
1051	default:
1052	/* More than one quadword per predicate. */
1053	eol = true;
1054	break;
1055	}
1056	}
1057	for (j = zcr_len / 4; j >= 0; j--) {
1058	int digits;
1059	if (j * 4 + 4 <= zcr_len + 1) {
1060	digits = 16;
1061	} else {
1062	digits = (zcr_len % 4 + 1) * 4;
1063	}
1064	qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
1065	env->vfp.pregs[i].p[j],
1066	j ? ":" : eol ? "\n" : " ");
1067	}
1068	}
1069
1070	if (zcr_len == 0) {
1071	/*
1072	* With vl=16, there are only 37 columns per register,
1073	* so output two registers per line.
1074	*/
1075	for (i = 0; i < 32; i++) {
1076	qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
1077	i, env->vfp.zregs[i].d[1],
1078	env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
1079	}
1080	} else {
1081	for (i = 0; i < 32; i++) {
1082	qemu_fprintf(f, "Z%02d=", i);
1083	for (j = zcr_len; j >= 0; j--) {
1084	qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
1085	env->vfp.zregs[i].d[j * 2 + 1],
1086	env->vfp.zregs[i].d[j * 2 + 0],
1087	j ? ":" : "\n");
1088	}
1089	}
1090	}
1091	} else {
1092	for (i = 0; i < 32; i++) {
1093	uint64_t *q = aa64_vfp_qreg(env, i);
1094	qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
1095	i, q[1], q[0], (i & 1 ? "\n" : " "));
1096	}
1097	}
1098
1099	if (cpu_isar_feature(aa64_sme, cpu) &&
1100	FIELD_EX64(env->svcr, SVCR, ZA) &&
1101	sme_exception_el(env, el) == 0) {
1102	int zcr_len = sve_vqm1_for_el_sm(env, el, true);
1103	int svl = (zcr_len + 1) * 16;
1104	int svl_lg10 = svl < 100 ? 2 : 3;
1105
1106	for (i = 0; i < svl; i++) {
1107	qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i);
1108	for (j = zcr_len; j >= 0; --j) {
1109	qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c",
1110	env->za_state.za[i].d[2 * j + 1],
1111	env->za_state.za[i].d[2 * j],
1112	j ? ':' : '\n');
1113	}
1114	}
1115	}
1116	}
1117
1118	static void arm_cpu_dump_state(CPUState cs, FILE f, int flags)
1119	{
1120	ARMCPU *cpu = ARM_CPU(cs);
1121	CPUARMState *env = &cpu->env;
1122	int i;
1123
1124	if (is_a64(env)) {
1125	aarch64_cpu_dump_state(cs, f, flags);
1126	return;
1127	}
1128
1129	for (i = 0; i < 16; i++) {
1130	qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
1131	if ((i % 4) == 3) {
1132	qemu_fprintf(f, "\n");
1133	} else {
1134	qemu_fprintf(f, " ");
1135	}
1136	}
1137
1138	if (arm_feature(env, ARM_FEATURE_M)) {
1139	uint32_t xpsr = xpsr_read(env);
1140	const char *mode;
1141	const char *ns_status = "";
1142
1143	if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1144	ns_status = env->v7m.secure ? "S " : "NS ";
1145	}
1146
1147	if (xpsr & XPSR_EXCP) {
1148	mode = "handler";
1149	} else {
1150	if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
1151	mode = "unpriv-thread";
1152	} else {
1153	mode = "priv-thread";
1154	}
1155	}
1156
1157	qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
1158	xpsr,
1159	xpsr & XPSR_N ? 'N' : '-',
1160	xpsr & XPSR_Z ? 'Z' : '-',
1161	xpsr & XPSR_C ? 'C' : '-',
1162	xpsr & XPSR_V ? 'V' : '-',
1163	xpsr & XPSR_T ? 'T' : 'A',
1164	ns_status,
1165	mode);
1166	} else {
1167	uint32_t psr = cpsr_read(env);
1168	const char *ns_status = "";
1169
1170	if (arm_feature(env, ARM_FEATURE_EL3) &&
1171	(psr & CPSR_M) != ARM_CPU_MODE_MON) {
1172	ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
1173	}
1174
1175	qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1176	psr,
1177	psr & CPSR_N ? 'N' : '-',
1178	psr & CPSR_Z ? 'Z' : '-',
1179	psr & CPSR_C ? 'C' : '-',
1180	psr & CPSR_V ? 'V' : '-',
1181	psr & CPSR_T ? 'T' : 'A',
1182	ns_status,
1183	aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
1184	}
1185
1186	if (flags & CPU_DUMP_FPU) {
1187	int numvfpregs = 0;
1188	if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1189	numvfpregs = 32;
1190	} else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
1191	numvfpregs = 16;
1192	}
1193	for (i = 0; i < numvfpregs; i++) {
1194	uint64_t v = *aa32_vfp_dreg(env, i);
1195	qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
1196	i * 2, (uint32_t)v,
1197	i * 2 + 1, (uint32_t)(v >> 32),
1198	i, v);
1199	}
1200	qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
1201	if (cpu_isar_feature(aa32_mve, cpu)) {
1202	qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr);
1203	}
1204	}
1205	}
1206
1207	#ifndef CONFIG_USER_ONLY
1208	bool gicv5_set_gicv5state(ARMCPU cpu, GICv5Common cs, uint32_t iaffid)
1209	{
1210	/*
1211	* Set this CPU's gicv5state pointer to point to the GIC that we are
1212	* connected to, and record our IAFFID.
1213	*/
1214	if (!cpu_isar_feature(aa64_gcie, cpu)) {
1215	return false;
1216	}
1217	cpu->env.gicv5state = cs;
1218	cpu->env.gicv5_iaffid = iaffid;
1219	return true;
1220	}
1221	#endif
1222
1223	uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)
1224	{
1225	uint32_t Aff1 = idx / clustersz;
1226	uint32_t Aff0 = idx % clustersz;
1227	return (Aff1 << ARM_AFF1_SHIFT) \| Aff0;
1228	}
1229
1230	uint64_t arm_cpu_mp_affinity(ARMCPU *cpu)
1231	{
1232	return cpu->mp_affinity;
1233	}
1234
1235	static void arm_cpu_initfn(Object *obj)
1236	{
1237	ARMCPU *cpu = ARM_CPU(obj);
1238
1239	cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
1240	NULL, g_free);
1241
1242	QLIST_INIT(&cpu->pre_el_change_hooks);
1243	QLIST_INIT(&cpu->el_change_hooks);
1244	QLIST_INIT(&cpu->cpreg_mig_tolerances);
1245
1246	#ifdef CONFIG_USER_ONLY
1247	# ifdef TARGET_AARCH64
1248	/*
1249	* The linux kernel defaults to 512-bit for SVE, and 256-bit for SME.
1250	* These values were chosen to fit within the default signal frame.
1251	* See documentation for /proc/sys/abi/{sve,sme}_default_vector_length,
1252	* and our corresponding cpu property.
1253	*/
1254	cpu->sve_default_vq = 4;
1255	cpu->sme_default_vq = 2;
1256	# endif
1257	#else
1258	/* Our inbound IRQ and FIQ lines */
1259	if (kvm_enabled()) {
1260	/*
1261	* VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add
1262	* them to maintain the same interface as non-KVM CPUs.
1263	*/
1264	qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6);
1265	} else {
1266	qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6);
1267	}
1268
1269	qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
1270	ARRAY_SIZE(cpu->gt_timer_outputs));
1271
1272	qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
1273	"gicv3-maintenance-interrupt", 1);
1274	qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
1275	"pmu-interrupt", 1);
1276	#endif
1277
1278	/* DTB consumers generally don't in fact care what the 'compatible'
1279	* string is, so always provide some string and trust that a hypothetical
1280	* picky DTB consumer will also provide a helpful error message.
1281	*/
1282	cpu->dtb_compatible = "qemu,unknown";
1283	if (!kvm_enabled()) {
1284	/* By default KVM will use the newest PSCI version that it knows about.
1285	* This can be changed using the kvm-psci-version property.
1286	* For others assume PSCI v0.1 by default.
1287	*/
1288	cpu->psci_version = QEMU_PSCI_VERSION_0_1;
1289	}
1290	cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
1291
1292	if (tcg_enabled() \|\| hvf_enabled()) {
1293	/* TCG and HVF implement PSCI 1.1 */
1294	cpu->psci_version = QEMU_PSCI_VERSION_1_1;
1295	} else if (whpx_enabled()) {
1296	cpu->psci_version = QEMU_PSCI_VERSION_1_3;
1297	}
1298	}
1299
1300	/*
1301	* 0 means "unset, use the default value". That default might vary depending
1302	* on the CPU type, and is set in the realize fn.
1303	*/
1304	#ifndef CONFIG_USER_ONLY
1305	static const Property arm_cpu_gt_cntfrq_property =
1306	DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0);
1307
1308	static const Property arm_cpu_reset_cbar_property =
1309	DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
1310
1311	static const Property arm_cpu_reset_hivecs_property =
1312	DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
1313
1314	static const Property arm_cpu_has_el2_property =
1315	DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
1316
1317	static const Property arm_cpu_has_el3_property =
1318	DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
1319
1320	static const Property arm_cpu_has_gcie_property =
1321	DEFINE_PROP_BOOL("has_gcie", ARMCPU, has_gcie, false);
1322	#endif
1323
1324	static const Property arm_cpu_cfgend_property =
1325	DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
1326
1327	static const Property arm_cpu_has_vfp_property =
1328	DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1329
1330	static const Property arm_cpu_has_vfp_d32_property =
1331	DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true);
1332
1333	static const Property arm_cpu_has_neon_property =
1334	DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1335
1336	static const Property arm_cpu_has_dsp_property =
1337	DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1338
1339	#ifndef CONFIG_USER_ONLY
1340	static const Property arm_cpu_has_mpu_property =
1341	DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1342
1343	/* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1344	* because the CPU initfn will have already set cpu->pmsav7_dregion to
1345	* the right value for that particular CPU type, and we don't want
1346	* to override that with an incorrect constant value.
1347	*/
1348	static const Property arm_cpu_pmsav7_dregion_property =
1349	DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1350	pmsav7_dregion,
1351	qdev_prop_uint32, uint32_t);
1352	#endif
1353
1354	static bool arm_get_pmu(Object obj, Error *errp)
1355	{
1356	ARMCPU *cpu = ARM_CPU(obj);
1357
1358	return cpu->has_pmu;
1359	}
1360
1361	static void arm_set_pmu(Object obj, bool value, Error *errp)
1362	{
1363	ARMCPU *cpu = ARM_CPU(obj);
1364
1365	if (value) {
1366	set_feature(&cpu->env, ARM_FEATURE_PMU);
1367	} else {
1368	unset_feature(&cpu->env, ARM_FEATURE_PMU);
1369	}
1370	cpu->has_pmu = value;
1371	}
1372
1373	static bool aarch64_cpu_get_aarch64(Object obj, Error *errp)
1374	{
1375	ARMCPU *cpu = ARM_CPU(obj);
1376
1377	return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
1378	}
1379
1380	static void aarch64_cpu_set_aarch64(Object obj, bool value, Error *errp)
1381	{
1382	ARMCPU *cpu = ARM_CPU(obj);
1383
1384	/*
1385	* At this time, this property is only allowed if KVM is enabled. This
1386	* restriction allows us to avoid fixing up functionality that assumes a
1387	* uniform execution state like do_interrupt.
1388	*/
1389	if (value == false) {
1390	if (kvm_enabled()) {
1391	if (!kvm_arm_aarch32_supported()) {
1392	error_setg(errp, "'aarch64' feature cannot be disabled for KVM "
1393	"because this host does not support 32-bit EL1");
1394	return;
1395	}
1396	} else if (tcg_enabled()) {
1397	#ifdef CONFIG_USER_ONLY
1398	error_setg(errp, "'aarch64' feature cannot be disabled for "
1399	"usermode emulator qemu-aarch64; use qemu-arm instead");
1400	return;
1401	#else
1402	bool aa32_at_highest_el;
1403	if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1404	aa32_at_highest_el = cpu_isar_feature(aa64_aa32_el3, cpu);
1405	} else if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1406	aa32_at_highest_el = cpu_isar_feature(aa64_aa32_el2, cpu);
1407	} else {
1408	aa32_at_highest_el = cpu_isar_feature(aa64_aa32_el1, cpu);
1409	}
1410
1411	if (!aa32_at_highest_el) {
1412	error_setg(errp, "'aarch64' feature cannot be disabled for "
1413	"this TCG CPU because it does not support 32-bit "
1414	"execution at its highest implemented exception "
1415	"level");
1416	return;
1417	}
1418	#endif
1419	} else {
1420	error_setg(errp, "'aarch64' feature cannot be disabled for "
1421	"this accelerator");
1422	return;
1423	}
1424	unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
1425	} else {
1426	set_feature(&cpu->env, ARM_FEATURE_AARCH64);
1427	}
1428	}
1429
1430	unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
1431	{
1432	/*
1433	* The exact approach to calculating guest ticks is:
1434	*
1435	* muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1436	* NANOSECONDS_PER_SECOND);
1437	*
1438	* We don't do that. Rather we intentionally use integer division
1439	* truncation below and in the caller for the conversion of host monotonic
1440	* time to guest ticks to provide the exact inverse for the semantics of
1441	* the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1442	* it loses precision when representing frequencies where
1443	* `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1444	* provide an exact inverse leads to scheduling timers with negative
1445	* periods, which in turn leads to sticky behaviour in the guest.
1446	*
1447	* Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1448	* cannot become zero.
1449	*/
1450	return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ?
1451	NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
1452	}
1453
1454	static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
1455	{
1456	CPUARMState *env = &cpu->env;
1457	bool no_aa32 = false;
1458
1459	/*
1460	* Some features automatically imply others: set the feature
1461	* bits explicitly for these cases.
1462	*/
1463
1464	if (arm_feature(env, ARM_FEATURE_M)) {
1465	set_feature(env, ARM_FEATURE_PMSA);
1466	}
1467
1468	if (arm_feature(env, ARM_FEATURE_V8)) {
1469	if (arm_feature(env, ARM_FEATURE_M)) {
1470	set_feature(env, ARM_FEATURE_V7);
1471	} else {
1472	set_feature(env, ARM_FEATURE_V7VE);
1473	}
1474	}
1475
1476	/*
1477	* There exist AArch64 cpus without AArch32 support. When KVM
1478	* queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1479	* Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1480	* As a general principle, we also do not make ID register
1481	* consistency checks anywhere unless using TCG, because only
1482	* for TCG would a consistency-check failure be a QEMU bug.
1483	*/
1484	if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1485	no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1486	}
1487
1488	if (arm_feature(env, ARM_FEATURE_V7VE)) {
1489	/*
1490	* v7 Virtualization Extensions. In real hardware this implies
1491	* EL2 and also the presence of the Security Extensions.
1492	* For QEMU, for backwards-compatibility we implement some
1493	* CPUs or CPU configs which have no actual EL2 or EL3 but do
1494	* include the various other features that V7VE implies.
1495	* Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1496	* Security Extensions is ARM_FEATURE_EL3.
1497	*/
1498	assert(!tcg_enabled() \|\| no_aa32 \|\|
1499	cpu_isar_feature(aa32_arm_div, cpu));
1500	set_feature(env, ARM_FEATURE_LPAE);
1501	set_feature(env, ARM_FEATURE_V7);
1502	}
1503	if (arm_feature(env, ARM_FEATURE_V7)) {
1504	set_feature(env, ARM_FEATURE_VAPA);
1505	set_feature(env, ARM_FEATURE_THUMB2);
1506	set_feature(env, ARM_FEATURE_MPIDR);
1507	if (!arm_feature(env, ARM_FEATURE_M)) {
1508	set_feature(env, ARM_FEATURE_V6K);
1509	} else {
1510	set_feature(env, ARM_FEATURE_V6);
1511	}
1512
1513	/*
1514	* Always define VBAR for V7 CPUs even if it doesn't exist in
1515	* non-EL3 configs. This is needed by some legacy boards.
1516	*/
1517	set_feature(env, ARM_FEATURE_VBAR);
1518	}
1519	if (arm_feature(env, ARM_FEATURE_V6K)) {
1520	set_feature(env, ARM_FEATURE_V6);
1521	set_feature(env, ARM_FEATURE_MVFR);
1522	}
1523	if (arm_feature(env, ARM_FEATURE_V6)) {
1524	set_feature(env, ARM_FEATURE_V5);
1525	if (!arm_feature(env, ARM_FEATURE_M)) {
1526	assert(!tcg_enabled() \|\| no_aa32 \|\|
1527	cpu_isar_feature(aa32_jazelle, cpu));
1528	set_feature(env, ARM_FEATURE_AUXCR);
1529	}
1530	}
1531	if (arm_feature(env, ARM_FEATURE_V5)) {
1532	set_feature(env, ARM_FEATURE_V4T);
1533	}
1534	if (arm_feature(env, ARM_FEATURE_LPAE)) {
1535	set_feature(env, ARM_FEATURE_V7MP);
1536	}
1537	if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1538	set_feature(env, ARM_FEATURE_CBAR);
1539	}
1540	if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1541	!arm_feature(env, ARM_FEATURE_M)) {
1542	set_feature(env, ARM_FEATURE_THUMB_DSP);
1543	}
1544	}
1545
1546	static void arm_cpu_post_init(Object *obj)
1547	{
1548	ARMCPU *cpu = ARM_CPU(obj);
1549
1550	/*
1551	* Some features imply others. Figure this out now, because we
1552	* are going to look at the feature bits in deciding which
1553	* properties to add.
1554	*/
1555	arm_cpu_propagate_feature_implications(cpu);
1556
1557	if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1558	object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
1559	aarch64_cpu_set_aarch64);
1560	object_property_set_description(obj, "aarch64",
1561	"Set on/off to enable/disable aarch64 "
1562	"execution state ");
1563	}
1564	#ifndef CONFIG_USER_ONLY
1565	if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) \|\|
1566	arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
1567	qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
1568	}
1569
1570	if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
1571	qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
1572	}
1573
1574	if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1575	object_property_add_uint64_ptr(obj, "rvbar",
1576	&cpu->rvbar_prop,
1577	OBJ_PROP_FLAG_READWRITE);
1578
1579	/* We only allow GICv5 on a 64-bit v8 CPU */
1580	if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1581	qdev_property_add_static(DEVICE(obj), &arm_cpu_has_gcie_property);
1582	}
1583	}
1584
1585	if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1586	/* Add the has_el3 state CPU property only if EL3 is allowed. This will
1587	* prevent "has_el3" from existing on CPUs which cannot support EL3.
1588	*/
1589	qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property);
1590
1591	object_property_add_link(obj, "secure-memory",
1592	TYPE_MEMORY_REGION,
1593	(Object **)&cpu->secure_memory,
1594	qdev_prop_allow_set_link_before_realize,
1595	OBJ_PROP_LINK_STRONG);
1596	}
1597
1598	if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1599	qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property);
1600	}
1601	#endif
1602
1603	if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
1604	cpu->has_pmu = true;
1605	object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu);
1606	}
1607
1608	/*
1609	* Allow user to turn off VFP and Neon support, but only for TCG --
1610	* KVM does not currently allow us to lie to the guest about its
1611	* ID/feature registers, so the guest always sees what the host has.
1612	*/
1613	if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1614	if (cpu_isar_feature(aa64_fp_simd, cpu)) {
1615	cpu->has_vfp = true;
1616	cpu->has_vfp_d32 = true;
1617	if (tcg_enabled() \|\| qtest_enabled()) {
1618	qdev_property_add_static(DEVICE(obj),
1619	&arm_cpu_has_vfp_property);
1620	}
1621	}
1622	} else if (cpu_isar_feature(aa32_vfp, cpu)) {
1623	cpu->has_vfp = true;
1624	if (tcg_enabled() \|\| qtest_enabled()) {
1625	qdev_property_add_static(DEVICE(obj),
1626	&arm_cpu_has_vfp_property);
1627	}
1628	if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1629	cpu->has_vfp_d32 = true;
1630	/*
1631	* The permitted values of the SIMDReg bits [3:0] on
1632	* Armv8-A are either 0b0000 and 0b0010. On such CPUs,
1633	* make sure that has_vfp_d32 can not be set to false.
1634	*/
1635	if ((tcg_enabled() \|\| qtest_enabled())
1636	&& !(arm_feature(&cpu->env, ARM_FEATURE_V8)
1637	&& !arm_feature(&cpu->env, ARM_FEATURE_M))) {
1638	qdev_property_add_static(DEVICE(obj),
1639	&arm_cpu_has_vfp_d32_property);
1640	}
1641	}
1642	}
1643
1644	if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1645	cpu->has_neon = true;
1646	if (tcg_enabled() \|\| qtest_enabled()) {
1647	qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
1648	}
1649	}
1650
1651	if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1652	arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
1653	qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property);
1654	}
1655
1656	#ifndef CONFIG_USER_ONLY
1657	if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
1658	qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property);
1659	if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1660	qdev_property_add_static(DEVICE(obj),
1661	&arm_cpu_pmsav7_dregion_property);
1662	}
1663	}
1664
1665	if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1666	object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1667	qdev_prop_allow_set_link_before_realize,
1668	OBJ_PROP_LINK_STRONG);
1669	/*
1670	* M profile: initial value of the Secure VTOR. We can't just use
1671	* a simple DEFINE_PROP_UINT32 for this because we want to permit
1672	* the property to be set after realize.
1673	*/
1674	object_property_add_uint32_ptr(obj, "init-svtor",
1675	&cpu->init_svtor,
1676	OBJ_PROP_FLAG_READWRITE);
1677	}
1678	if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1679	/*
1680	* Initial value of the NS VTOR (for cores without the Security
1681	* extension, this is the only VTOR)
1682	*/
1683	object_property_add_uint32_ptr(obj, "init-nsvtor",
1684	&cpu->init_nsvtor,
1685	OBJ_PROP_FLAG_READWRITE);
1686	}
1687
1688	/* Not DEFINE_PROP_UINT32: we want this to be settable after realize */
1689	object_property_add_uint32_ptr(obj, "psci-conduit",
1690	&cpu->psci_conduit,
1691	OBJ_PROP_FLAG_READWRITE);
1692
1693	if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
1694	qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
1695	}
1696
1697	if (kvm_enabled()) {
1698	kvm_arm_add_vcpu_properties(cpu);
1699	}
1700
1701	if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) &&
1702	cpu_isar_feature(aa64_mte, cpu)) {
1703	object_property_add_link(obj, "tag-memory",
1704	TYPE_MEMORY_REGION,
1705	(Object **)&cpu->tag_memory,
1706	qdev_prop_allow_set_link_before_realize,
1707	OBJ_PROP_LINK_STRONG);
1708
1709	if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1710	object_property_add_link(obj, "secure-tag-memory",
1711	TYPE_MEMORY_REGION,
1712	(Object **)&cpu->secure_tag_memory,
1713	qdev_prop_allow_set_link_before_realize,
1714	OBJ_PROP_LINK_STRONG);
1715	}
1716	}
1717	#endif
1718	qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
1719	}
1720
1721	static void arm_cpu_finalizefn(Object *obj)
1722	{
1723	ARMCPU *cpu = ARM_CPU(obj);
1724	ARMELChangeHook hook, next;
1725	ARMCPRegMigTolerance t, n;
1726
1727	g_hash_table_destroy(cpu->cp_regs);
1728
1729	QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1730	QLIST_REMOVE(hook, node);
1731	g_free(hook);
1732	}
1733	QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1734	QLIST_REMOVE(hook, node);
1735	g_free(hook);
1736	}
1737	QLIST_FOREACH_SAFE(t, &cpu->cpreg_mig_tolerances, node, n) {
1738	QLIST_REMOVE(t, node);
1739	g_free(t);
1740	}
1741	#ifndef CONFIG_USER_ONLY
1742	if (cpu->pmu_timer) {
1743	timer_free(cpu->pmu_timer);
1744	}
1745	if (cpu->wfxt_timer) {
1746	timer_free(cpu->wfxt_timer);
1747	}
1748	#endif
1749	}
1750
1751	void arm_cpu_finalize_features(ARMCPU cpu, Error *errp)
1752	{
1753	Error *local_err = NULL;
1754
1755	if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1756	aarch64_cpu_sve_finalize(cpu, &local_err);
1757	if (local_err != NULL) {
1758	error_propagate(errp, local_err);
1759	return;
1760	}
1761
1762	aarch64_cpu_sme_finalize(cpu, &local_err);
1763	if (local_err != NULL) {
1764	error_propagate(errp, local_err);
1765	return;
1766	}
1767
1768	aarch64_cpu_pauth_finalize(cpu, &local_err);
1769	if (local_err != NULL) {
1770	error_propagate(errp, local_err);
1771	return;
1772	}
1773
1774	aarch64_cpu_lpa2_finalize(cpu, &local_err);
1775	if (local_err != NULL) {
1776	error_propagate(errp, local_err);
1777	return;
1778	}
1779	}
1780
1781	if (kvm_enabled()) {
1782	kvm_arm_steal_time_finalize(cpu, &local_err);
1783	if (local_err != NULL) {
1784	error_propagate(errp, local_err);
1785	return;
1786	}
1787	}
1788	}
1789
1790	static void arm_clear_aarch64_idregs(ARMCPU *cpu)
1791	{
1792	/* Zero out all the AArch64 ID registers in ARMISARegisters */
1793	SET_IDREG(&cpu->isar, ID_AA64ISAR0, 0);
1794	SET_IDREG(&cpu->isar, ID_AA64ISAR1, 0);
1795	SET_IDREG(&cpu->isar, ID_AA64ISAR2, 0);
1796	SET_IDREG(&cpu->isar, ID_AA64ISAR3, 0);
1797	SET_IDREG(&cpu->isar, ID_AA64PFR0, 0);
1798	SET_IDREG(&cpu->isar, ID_AA64PFR1, 0);
1799	SET_IDREG(&cpu->isar, ID_AA64PFR2, 0);
1800	SET_IDREG(&cpu->isar, ID_AA64MMFR0, 0);
1801	SET_IDREG(&cpu->isar, ID_AA64MMFR1, 0);
1802	SET_IDREG(&cpu->isar, ID_AA64MMFR2, 0);
1803	SET_IDREG(&cpu->isar, ID_AA64MMFR3, 0);
1804	SET_IDREG(&cpu->isar, ID_AA64DFR0, 0);
1805	SET_IDREG(&cpu->isar, ID_AA64DFR1, 0);
1806	SET_IDREG(&cpu->isar, ID_AA64AFR0, 0);
1807	SET_IDREG(&cpu->isar, ID_AA64AFR1, 0);
1808	SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0);
1809	SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0);
1810	SET_IDREG(&cpu->isar, ID_AA64FPFR0, 0);
1811	}
1812
1813	static void arm_cpu_realizefn(DeviceState dev, Error *errp)
1814	{
1815	CPUState *cs = CPU(dev);
1816	ARMCPU *cpu = ARM_CPU(dev);
1817	ARMISARegisters *isar = &cpu->isar;
1818	ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
1819	CPUARMState *env = &cpu->env;
1820	Error *local_err = NULL;
1821
1822	#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
1823	/* Use pc-relative instructions in system-mode */
1824	tcg_cflags_set(cs, CF_PCREL);
1825	#endif
1826
1827	/* If we needed to query the host kernel for the CPU features
1828	* then it's possible that might have failed in the initfn, but
1829	* this is the first point where we can report it.
1830	*/
1831	if (cpu->host_cpu_probe_failed) {
1832	if (!kvm_enabled() && !hvf_enabled() && !whpx_enabled()) {
1833	error_setg(errp, "The 'host' CPU type can only be used with KVM, HVF or WHPX");
1834	} else {
1835	error_setg(errp, "Failed to retrieve host CPU features");
1836	}
1837	return;
1838	}
1839
1840	#ifndef CONFIG_USER_ONLY
1841	/* The NVIC and M-profile CPU are two halves of a single piece of
1842	* hardware; trying to use one without the other is a command line
1843	* error and will result in segfaults if not caught here.
1844	*/
1845	if (arm_feature(env, ARM_FEATURE_M)) {
1846	if (!env->nvic) {
1847	error_setg(errp, "This board cannot be used with Cortex-M CPUs");
1848	return;
1849	}
1850	} else {
1851	if (env->nvic) {
1852	error_setg(errp, "This board can only be used with Cortex-M CPUs");
1853	return;
1854	}
1855	}
1856
1857	if (!tcg_enabled() && !qtest_enabled()) {
1858	/*
1859	* We assume that no accelerator except TCG (and the "not really an
1860	* accelerator" qtest) can handle these features, because Arm hardware
1861	* virtualization can't virtualize them.
1862	*
1863	* Catch all the cases which might cause us to create more than one
1864	* address space for the CPU (otherwise we will assert() later in
1865	* cpu_address_space_init()).
1866	*/
1867	if (arm_feature(env, ARM_FEATURE_M)) {
1868	error_setg(errp,
1869	"Cannot enable %s when using an M-profile guest CPU",
1870	current_accel_name());
1871	return;
1872	}
1873	if (cpu->has_el3) {
1874	error_setg(errp,
1875	"Cannot enable %s when guest CPU has EL3 enabled",
1876	current_accel_name());
1877	return;
1878	}
1879	if (cpu->tag_memory) {
1880	error_setg(errp,
1881	"Cannot enable %s when guest CPUs has MTE enabled",
1882	current_accel_name());
1883	return;
1884	}
1885	if (cpu->has_gcie) {
1886	error_setg(errp,
1887	"Cannot enable %s when guest CPU has GICv5 enabled",
1888	current_accel_name());
1889	return;
1890	}
1891	}
1892	#endif
1893
1894	cpu_common_realize(cs, &local_err);
1895	if (local_err != NULL) {
1896	error_propagate(errp, local_err);
1897	return;
1898	}
1899
1900	arm_cpu_finalize_features(cpu, &local_err);
1901	if (local_err != NULL) {
1902	error_propagate(errp, local_err);
1903	return;
1904	}
1905
1906	if (!cpu->gt_cntfrq_hz) {
1907	/*
1908	* 0 means "the board didn't set a value, use the default". (We also
1909	* get here for the CONFIG_USER_ONLY case.)
1910	* ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
1911	* that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
1912	* which gives a 16ns tick period.
1913	*
1914	* We will use the back-compat value:
1915	* - for QEMU CPU types added before we standardized on 1GHz
1916	* - for versioned machine types with a version of 9.0 or earlier
1917	*/
1918	if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) \|\|
1919	cpu->backcompat_cntfrq) {
1920	cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
1921	} else {
1922	cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
1923	}
1924	}
1925	#ifndef CONFIG_USER_ONLY
1926	{
1927	uint64_t scale = gt_cntfrq_period_ns(cpu);
1928
1929	cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1930	arm_gt_ptimer_cb, cpu);
1931	cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1932	arm_gt_vtimer_cb, cpu);
1933	cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1934	arm_gt_htimer_cb, cpu);
1935	cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1936	arm_gt_stimer_cb, cpu);
1937	cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1938	arm_gt_hvtimer_cb, cpu);
1939	cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1940	arm_gt_sel2timer_cb, cpu);
1941	cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1942	arm_gt_sel2vtimer_cb, cpu);
1943	}
1944	#endif
1945
1946	/*
1947	* A TCG aarch64=off CPU has no AArch64 at all, so we clear out the
1948	* ID registers to avoid cpu_isar_feature(aa64_something, cpu) tests
1949	* incorrectly returning true. We don't do this for other accelerators
1950	* (which in practice means "for KVM", since no others have AArch32
1951	* guest support) because from KVM's point of view the AArch64 ID
1952	* registers still exist and must have their correct values. So we
1953	* avoid clearing them out so that we don't have QEMU and KVM with
1954	* different ideas of the ID registers.
1955	*/
1956	if (tcg_enabled() && !arm_feature(env, ARM_FEATURE_AARCH64)) {
1957	arm_clear_aarch64_idregs(cpu);
1958	}
1959
1960	#ifdef CONFIG_USER_ONLY
1961	/*
1962	* User mode relies on IC IVAU instructions to catch modification of
1963	* dual-mapped code.
1964	*
1965	* Clear CTR_EL0.DIC to ensure that software that honors these flags uses
1966	* IC IVAU even if the emulated processor does not normally require it.
1967	*/
1968	cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0);
1969	#endif
1970
1971	if (arm_feature(env, ARM_FEATURE_AARCH64) &&
1972	cpu->has_vfp != cpu->has_neon) {
1973	/*
1974	* This is an architectural requirement for AArch64; AArch32 is
1975	* more flexible and permits VFP-no-Neon and Neon-no-VFP.
1976	*/
1977	error_setg(errp,
1978	"AArch64 CPUs must have both VFP and Neon or neither");
1979	return;
1980	}
1981
1982	if (cpu->has_vfp_d32 != cpu->has_neon) {
1983	error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither");
1984	return;
1985	}
1986
1987	if (!cpu->has_vfp_d32) {
1988	uint32_t u;
1989
1990	u = cpu->isar.mvfr0;
1991	u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */
1992	cpu->isar.mvfr0 = u;
1993	}
1994
1995	if (!cpu->has_vfp) {
1996	uint32_t u;
1997
1998	FIELD_DP64_IDREG(isar, ID_AA64ISAR1, JSCVT, 0);
1999
2000	FIELD_DP64_IDREG(isar, ID_AA64PFR0, FP, 0xf);
2001
2002	u = GET_IDREG(isar, ID_ISAR6);
2003	u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
2004	u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
2005	SET_IDREG(isar, ID_ISAR6, u);
2006
2007	u = cpu->isar.mvfr0;
2008	u = FIELD_DP32(u, MVFR0, FPSP, 0);
2009	u = FIELD_DP32(u, MVFR0, FPDP, 0);
2010	u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
2011	u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
2012	u = FIELD_DP32(u, MVFR0, FPROUND, 0);
2013	if (!arm_feature(env, ARM_FEATURE_M)) {
2014	u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
2015	u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
2016	}
2017	cpu->isar.mvfr0 = u;
2018
2019	u = cpu->isar.mvfr1;
2020	u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
2021	u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
2022	u = FIELD_DP32(u, MVFR1, FPHP, 0);
2023	if (arm_feature(env, ARM_FEATURE_M)) {
2024	u = FIELD_DP32(u, MVFR1, FP16, 0);
2025	}
2026	cpu->isar.mvfr1 = u;
2027
2028	u = cpu->isar.mvfr2;
2029	u = FIELD_DP32(u, MVFR2, FPMISC, 0);
2030	cpu->isar.mvfr2 = u;
2031	}
2032
2033	if (!cpu->has_neon) {
2034	uint64_t t;
2035	uint32_t u;
2036
2037	unset_feature(env, ARM_FEATURE_NEON);
2038
2039	t = GET_IDREG(isar, ID_AA64ISAR0);
2040	t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
2041	t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
2042	t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
2043	t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0);
2044	t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
2045	t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
2046	t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
2047	SET_IDREG(isar, ID_AA64ISAR0, t);
2048
2049	t = GET_IDREG(isar, ID_AA64ISAR1);
2050	t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
2051	t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0);
2052	t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
2053	SET_IDREG(isar, ID_AA64ISAR1, t);
2054
2055	FIELD_DP64_IDREG(isar, ID_AA64PFR0, ADVSIMD, 0xf);
2056
2057	u = GET_IDREG(isar, ID_ISAR5);
2058	u = FIELD_DP32(u, ID_ISAR5, AES, 0);
2059	u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
2060	u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
2061	u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
2062	u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
2063	SET_IDREG(isar, ID_ISAR5, u);
2064
2065	u = GET_IDREG(isar, ID_ISAR6);
2066	u = FIELD_DP32(u, ID_ISAR6, DP, 0);
2067	u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
2068	u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
2069	u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);
2070	SET_IDREG(isar, ID_ISAR6, u);
2071
2072	if (!arm_feature(env, ARM_FEATURE_M)) {
2073	u = cpu->isar.mvfr1;
2074	u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
2075	u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
2076	u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
2077	u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
2078	cpu->isar.mvfr1 = u;
2079
2080	u = cpu->isar.mvfr2;
2081	u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
2082	cpu->isar.mvfr2 = u;
2083	}
2084	}
2085
2086	if (!cpu->has_neon && !cpu->has_vfp) {
2087	uint32_t u;
2088
2089	FIELD_DP64_IDREG(isar, ID_AA64ISAR0, FHM, 0);
2090
2091	FIELD_DP64_IDREG(isar, ID_AA64ISAR1, FRINTTS, 0);
2092
2093	u = cpu->isar.mvfr0;
2094	u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
2095	cpu->isar.mvfr0 = u;
2096
2097	/* Despite the name, this field covers both VFP and Neon */
2098	u = cpu->isar.mvfr1;
2099	u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
2100	cpu->isar.mvfr1 = u;
2101	}
2102
2103	if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
2104	uint32_t u;
2105
2106	unset_feature(env, ARM_FEATURE_THUMB_DSP);
2107
2108	FIELD_DP32_IDREG(isar, ID_ISAR1, EXTEND, 1);
2109
2110	u = GET_IDREG(isar, ID_ISAR2);
2111	u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
2112	u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
2113	SET_IDREG(isar, ID_ISAR2, u);
2114
2115	u = GET_IDREG(isar, ID_ISAR3);
2116	u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
2117	u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
2118	SET_IDREG(isar, ID_ISAR3, u);
2119	}
2120
2121
2122	#ifndef CONFIG_USER_ONLY
2123	{
2124	int pagebits;
2125	if (arm_feature(env, ARM_FEATURE_V7) &&
2126	!arm_feature(env, ARM_FEATURE_M) &&
2127	!arm_feature(env, ARM_FEATURE_PMSA)) {
2128	/*
2129	* v7VMSA drops support for the old ARMv5 tiny pages,
2130	* so we can use 4K pages.
2131	*/
2132	pagebits = 12;
2133	} else {
2134	/*
2135	* For CPUs which might have tiny 1K pages, or which have an
2136	* MPU and might have small region sizes, stick with 1K pages.
2137	*/
2138	pagebits = 10;
2139	}
2140	if (!set_preferred_target_page_bits(pagebits)) {
2141	/*
2142	* This can only ever happen for hotplugging a CPU, or if
2143	* the board code incorrectly creates a CPU which it has
2144	* promised via minimum_page_size that it will not.
2145	*/
2146	error_setg(errp, "This CPU requires a smaller page size "
2147	"than the system is using");
2148	return;
2149	}
2150	}
2151	#endif
2152
2153	/* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
2154	* We don't support setting cluster ID ([16..23]) (known as Aff2
2155	* in later ARM ARM versions), or any of the higher affinity level fields,
2156	* so these bits always RAZ.
2157	*/
2158	if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
2159	cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index,
2160	ARM_DEFAULT_CPUS_PER_CLUSTER);
2161	}
2162
2163	if (cpu->reset_hivecs) {
2164	cpu->reset_sctlr \|= (1 << 13);
2165	}
2166
2167	if (cpu->cfgend) {
2168	if (arm_feature(env, ARM_FEATURE_V7)) {
2169	cpu->reset_sctlr \|= SCTLR_EE;
2170	} else {
2171	cpu->reset_sctlr \|= SCTLR_B;
2172	}
2173	}
2174
2175	if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
2176	/* If the has_el3 CPU property is disabled then we need to disable the
2177	* feature.
2178	*/
2179	unset_feature(env, ARM_FEATURE_EL3);
2180
2181	/*
2182	* Disable the security extension feature bits in the processor
2183	* feature registers as well.
2184	*/
2185	FIELD_DP32_IDREG(isar, ID_PFR1, SECURITY, 0);
2186	FIELD_DP32_IDREG(isar, ID_DFR0, COPSDBG, 0);
2187	FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0);
2188
2189	/* Disable the realm management extension, which requires EL3. */
2190	FIELD_DP64_IDREG(isar, ID_AA64PFR0, RME, 0);
2191	}
2192
2193	if (!cpu->has_el2) {
2194	unset_feature(env, ARM_FEATURE_EL2);
2195	}
2196
2197	if (!cpu->has_pmu) {
2198	unset_feature(env, ARM_FEATURE_PMU);
2199	}
2200	if (arm_feature(env, ARM_FEATURE_PMU)) {
2201	pmu_init(cpu);
2202
2203	if (tcg_enabled() \|\| hvf_enabled()) {
2204	arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
2205	arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
2206	}
2207
2208	#ifndef CONFIG_USER_ONLY
2209	cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
2210	cpu);
2211	#endif
2212	} else {
2213	FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMUVER, 0);
2214	FIELD_DP32_IDREG(isar, ID_DFR0, PERFMON, 0);
2215	cpu->pmceid0 = 0;
2216	cpu->pmceid1 = 0;
2217	}
2218
2219	if (!arm_feature(env, ARM_FEATURE_EL2)) {
2220	/*
2221	* Disable the hypervisor feature bits in the processor feature
2222	* registers if we don't have EL2.
2223	*/
2224	FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0);
2225	FIELD_DP32_IDREG(isar, ID_PFR1, VIRTUALIZATION, 0);
2226	}
2227
2228	/* Report FEAT_GCIE in our ID registers if property was set */
2229	FIELD_DP64_IDREG(isar, ID_AA64PFR2, GCIE, cpu->has_gcie);
2230	if (cpu_isar_feature(aa64_gcie, cpu)) {
2231	if (!arm_feature(env, ARM_FEATURE_AARCH64)) {
2232	/*
2233	* We only create the have_gcie property for AArch64 CPUs,
2234	* but the user might have tried aarch64=off with has_gcie=on.
2235	*/
2236	error_setg(errp, "Cannot both enable has_gcie and disable aarch64");
2237	return;
2238	}
2239
2240	/*
2241	* FEAT_GCIE implies Armv9, which implies no AArch32 above EL0.
2242	* Usually we don't strictly insist on this kind of feature
2243	* dependency, but in this case we enforce it, because the
2244	* GICv5 CPU interface has no AArch32 versions of its system
2245	* registers, so interrupts wouldn't work if we allowed AArch32
2246	* in EL1 or above. Downgrade "AArch32 and AArch64" to "AArch64".
2247	*/
2248	if (cpu_isar_feature(aa64_aa32_el3, cpu)) {
2249	FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 1);
2250	}
2251	if (cpu_isar_feature(aa64_aa32_el2, cpu)) {
2252	FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 1);
2253	}
2254	if (cpu_isar_feature(aa64_aa32_el1, cpu)) {
2255	FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL1, 1);
2256	}
2257	}
2258
2259	if (cpu_isar_feature(aa64_mte, cpu)) {
2260	/*
2261	* The architectural range of GM blocksize is 2-6, however qemu
2262	* doesn't support blocksize of 2 (see HELPER(ldgm)).
2263	*/
2264	if (tcg_enabled()) {
2265	assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
2266	}
2267
2268	#ifndef CONFIG_USER_ONLY
2269	/*
2270	* If we run with TCG and do not have tag-memory provided by
2271	* the machine, then reduce MTE support to instructions enabled at EL0.
2272	* This matches Cortex-A710 BROADCASTMTE input being LOW.
2273	*/
2274	if (tcg_enabled() && cpu->tag_memory == NULL) {
2275	FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 1);
2276	}
2277
2278	/*
2279	* If MTE is supported by the host, however it should not be
2280	* enabled on the guest (i.e mte=off), clear guest's MTE bits."
2281	*/
2282	if (kvm_enabled() && !cpu->kvm_mte) {
2283	FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 0);
2284	}
2285	#endif
2286	}
2287
2288	#ifndef CONFIG_USER_ONLY
2289	/*
2290	* We use the wfxt_timer for timeouts and event stream so we
2291	* enable from V6K up. There is no event stream on M-profile.
2292	*/
2293	if (tcg_enabled() && arm_feature(env, ARM_FEATURE_V6K)) {
2294	cpu->wfxt_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2295	arm_wfxt_timer_cb, cpu);
2296	}
2297	#endif
2298
2299	if (tcg_enabled()) {
2300	/*
2301	* Don't report some architectural features in the ID registers
2302	* where TCG does not yet implement it (not even a minimal
2303	* stub version). This avoids guests falling over when they
2304	* try to access the non-existent system registers for them.
2305	*/
2306	/* FEAT_SPE (Statistical Profiling Extension) */
2307	FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMSVER, 0);
2308	/* FEAT_TRBE (Trace Buffer Extension) */
2309	FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEBUFFER, 0);
2310	/* FEAT_TRF (Self-hosted Trace Extension) */
2311	FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEFILT, 0);
2312	FIELD_DP32_IDREG(isar, ID_DFR0, TRACEFILT, 0);
2313	/* Trace Macrocell system register access */
2314	FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEVER, 0);
2315	FIELD_DP32_IDREG(isar, ID_DFR0, COPTRC, 0);
2316	/* Memory mapped trace */
2317	FIELD_DP32_IDREG(isar, ID_DFR0, MMAPTRC, 0);
2318	/* FEAT_AMU (Activity Monitors Extension) */
2319	FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0);
2320	FIELD_DP32_IDREG(isar, ID_PFR0, AMU, 0);
2321	/* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
2322	FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0);
2323	}
2324
2325	/* MPU can be configured out of a PMSA CPU either by setting has-mpu
2326	* to false or by setting pmsav7-dregion to 0.
2327	*/
2328	if (!cpu->has_mpu \|\| cpu->pmsav7_dregion == 0) {
2329	cpu->has_mpu = false;
2330	cpu->pmsav7_dregion = 0;
2331	cpu->pmsav8r_hdregion = 0;
2332	}
2333
2334	if (arm_feature(env, ARM_FEATURE_PMSA) &&
2335	arm_feature(env, ARM_FEATURE_V7)) {
2336	uint32_t nr = cpu->pmsav7_dregion;
2337
2338	if (nr > 0xff) {
2339	error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
2340	return;
2341	}
2342
2343	if (nr) {
2344	if (arm_feature(env, ARM_FEATURE_V8)) {
2345	/* PMSAv8 */
2346	env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
2347	env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
2348	if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
2349	env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
2350	env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
2351	}
2352	} else {
2353	env->pmsav7.drbar = g_new0(uint32_t, nr);
2354	env->pmsav7.drsr = g_new0(uint32_t, nr);
2355	env->pmsav7.dracr = g_new0(uint32_t, nr);
2356	}
2357	}
2358
2359	if (cpu->pmsav8r_hdregion > 0xff) {
2360	error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32,
2361	cpu->pmsav8r_hdregion);
2362	return;
2363	}
2364
2365	if (cpu->pmsav8r_hdregion) {
2366	env->pmsav8.hprbar = g_new0(uint32_t,
2367	cpu->pmsav8r_hdregion);
2368	env->pmsav8.hprlar = g_new0(uint32_t,
2369	cpu->pmsav8r_hdregion);
2370	}
2371	}
2372
2373	if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
2374	uint32_t nr = cpu->sau_sregion;
2375
2376	if (nr > 0xff) {
2377	error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
2378	return;
2379	}
2380
2381	if (nr) {
2382	env->sau.rbar = g_new0(uint32_t, nr);
2383	env->sau.rlar = g_new0(uint32_t, nr);
2384	}
2385	}
2386
2387	if (arm_feature(env, ARM_FEATURE_EL3)) {
2388	set_feature(env, ARM_FEATURE_VBAR);
2389	}
2390
2391	#ifndef CONFIG_USER_ONLY
2392	if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) {
2393	arm_register_el_change_hook(cpu, &gt_rme_post_el_change, 0);
2394	}
2395	#endif
2396
2397	register_cp_regs_for_features(cpu);
2398	arm_cpu_register_gdb_regs_for_features(cpu);
2399	arm_cpu_register_gdb_commands(cpu);
2400
2401	arm_init_cpreg_list(cpu);
2402
2403	#ifndef CONFIG_USER_ONLY
2404	MachineState *ms = MACHINE(qdev_get_machine());
2405	unsigned int smp_cpus = ms->smp.cpus;
2406	bool has_secure = cpu->has_el3 \|\| arm_feature(env, ARM_FEATURE_M_SECURITY);
2407
2408	cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
2409
2410	if (has_secure) {
2411	if (!cpu->secure_memory) {
2412	cpu->secure_memory = cs->memory;
2413	}
2414	cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
2415	cpu->secure_memory);
2416	}
2417
2418	if (cpu->tag_memory != NULL) {
2419	cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory",
2420	cpu->tag_memory);
2421	if (has_secure) {
2422	cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
2423	cpu->secure_tag_memory);
2424	}
2425	}
2426
2427	/* No core_count specified, default to smp_cpus. */
2428	if (cpu->core_count == -1) {
2429	cpu->core_count = smp_cpus;
2430	}
2431	#endif
2432
2433	if (tcg_enabled()) {
2434	int dcz_blocklen = 4 << get_dczid_bs(cpu);
2435
2436	/*
2437	* We only support DCZ blocklen that fits on one page.
2438	*
2439	* Architectually this is always true. However TARGET_PAGE_SIZE
2440	* is variable and, for compatibility with -machine virt-2.7,
2441	* is only 1KiB, as an artifact of legacy ARMv5 subpage support.
2442	* But even then, while the largest architectural DCZ blocklen
2443	* is 2KiB, no cpu actually uses such a large blocklen.
2444	*/
2445	assert(dcz_blocklen <= TARGET_PAGE_SIZE);
2446
2447	/*
2448	* We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
2449	* both nibbles of each byte storing tag data may be written at once.
2450	* Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
2451	*/
2452	if (cpu_isar_feature(aa64_mte, cpu)) {
2453	assert(dcz_blocklen >= 2 * TAG_GRANULE);
2454	}
2455	}
2456
2457	qemu_init_vcpu(cs);
2458	cpu_reset(cs);
2459
2460	acc->parent_realize(dev, errp);
2461	}
2462
2463	static ObjectClass arm_cpu_class_by_name(const char cpu_model)
2464	{
2465	ObjectClass *oc;
2466	char *typename;
2467	char **cpuname;
2468	const char *cpunamestr;
2469
2470	cpuname = g_strsplit(cpu_model, ",", 1);
2471	cpunamestr = cpuname[0];
2472	#ifdef CONFIG_USER_ONLY
2473	/* For backwards compatibility usermode emulation allows "-cpu any",
2474	* which has the same semantics as "-cpu max".
2475	*/
2476	if (!strcmp(cpunamestr, "any")) {
2477	cpunamestr = "max";
2478	}
2479	#endif
2480	typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
2481	oc = object_class_by_name(typename);
2482	g_strfreev(cpuname);
2483	g_free(typename);
2484
2485	return oc;
2486	}
2487
2488	static const Property arm_cpu_properties[] = {
2489	DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
2490	DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2491	mp_affinity, ARM64_AFFINITY_INVALID),
2492	DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2493	DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2494	/* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
2495	DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
2496	DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU,
2497	backcompat_pauth_default_use_qarma5, false),
2498	};
2499
2500	static const gchar arm_gdb_arch_name(CPUState cs)
2501	{
2502	ARMCPU *cpu = ARM_CPU(cs);
2503
2504	if (arm_gdbstub_is_aarch64(cpu)) {
2505	return "aarch64";
2506	}
2507	return "arm";
2508	}
2509
2510	static const char arm_gdb_get_core_xml_file(CPUState cs)
2511	{
2512	ARMCPU *cpu = ARM_CPU(cs);
2513	CPUARMState *env = &cpu->env;
2514
2515	if (arm_gdbstub_is_aarch64(cpu)) {
2516	return "aarch64-core.xml";
2517	}
2518	if (arm_feature(env, ARM_FEATURE_M)) {
2519	return "arm-m-profile.xml";
2520	}
2521	return "arm-core.xml";
2522	}
2523
2524	#ifdef CONFIG_USER_ONLY
2525	/**
2526	* aarch64_untagged_addr:
2527	*
2528	* Remove any address tag from @x. This is explicitly related to the
2529	* linux syscall TIF_TAGGED_ADDR setting, not TBI in general.
2530	*
2531	* There should be a better place to put this, but we need this in
2532	* include/accel/tcg/cpu-ldst.h, and not some place linux-user specific.
2533	*
2534	* Note that arm-*-user will never set tagged_addr_enable.
2535	*/
2536	static vaddr aarch64_untagged_addr(CPUState *cs, vaddr x)
2537	{
2538	CPUARMState *env = cpu_env(cs);
2539	if (env->tagged_addr_enable) {
2540	/*
2541	* TBI is enabled for userspace but not kernelspace addresses.
2542	* Only clear the tag if bit 55 is clear.
2543	*/
2544	x &= sextract64(x, 0, 56);
2545	}
2546	return x;
2547	}
2548	#else
2549	#include "hw/core/sysemu-cpu-ops.h"
2550
2551	static const struct SysemuCPUOps arm_sysemu_ops = {
2552	.has_work = arm_cpu_has_work,
2553	.translate_for_debug = arm_cpu_translate_for_debug,
2554	.asidx_from_attrs = arm_asidx_from_attrs,
2555	.write_elf32_note = arm_cpu_write_elf32_note,
2556	.write_elf64_note = arm_cpu_write_elf64_note,
2557	.internal_is_big_endian = arm_cpu_internal_is_big_endian,
2558	.legacy_vmsd = &vmstate_arm_cpu,
2559	};
2560	#endif
2561
2562	#ifdef CONFIG_TCG
2563	#ifndef CONFIG_USER_ONLY
2564	static vaddr aprofile_pointer_wrap(CPUState *cs, int mmu_idx,
2565	vaddr result, vaddr base)
2566	{
2567	/*
2568	* The Stage2 and Phys indexes are only used for ptw on arm32,
2569	* and all pte's are aligned, so we never produce a wrap for these.
2570	* Double check that we're not truncating a 40-bit physical address.
2571	*/
2572	assert((unsigned)mmu_idx < (ARMMMUIdx_Stage2_S & ARM_MMU_IDX_COREIDX_MASK));
2573
2574	if (!is_a64(cpu_env(cs))) {
2575	return (uint32_t)result;
2576	}
2577
2578	/*
2579	* TODO: For FEAT_CPA2, decide how to we want to resolve
2580	* Unpredictable_CPACHECK in AddressIncrement.
2581	*/
2582	return result;
2583	}
2584	#endif /* !CONFIG_USER_ONLY */
2585
2586	static const TCGCPUOps arm_tcg_ops = {
2587	.mttcg_supported = true,
2588	/* ARM processors have a weak memory model */
2589	.guest_default_memory_order = 0,
2590
2591	.initialize = arm_translate_init,
2592	.translate_code = arm_translate_code,
2593	.get_tb_cpu_state = arm_get_tb_cpu_state,
2594	.synchronize_from_tb = arm_cpu_synchronize_from_tb,
2595	.debug_excp_handler = arm_debug_excp_handler,
2596	.restore_state_to_opc = arm_restore_state_to_opc,
2597	.mmu_index = arm_cpu_mmu_index,
2598
2599	#ifdef CONFIG_USER_ONLY
2600	.record_sigsegv = arm_cpu_record_sigsegv,
2601	.record_sigbus = arm_cpu_record_sigbus,
2602	.untagged_addr = aarch64_untagged_addr,
2603	#else
2604	.tlb_fill_align = arm_cpu_tlb_fill_align,
2605	.pointer_wrap = aprofile_pointer_wrap,
2606	.cpu_exec_interrupt = arm_cpu_exec_interrupt,
2607	.cpu_exec_halt = arm_cpu_exec_halt,
2608	.cpu_exec_reset = cpu_reset,
2609	.do_interrupt = arm_cpu_do_interrupt,
2610	.do_transaction_failed = arm_cpu_do_transaction_failed,
2611	.do_unaligned_access = arm_cpu_do_unaligned_access,
2612	.adjust_watchpoint_address = arm_adjust_watchpoint_address,
2613	.debug_check_watchpoint = arm_debug_check_watchpoint,
2614	.debug_check_breakpoint = arm_debug_check_breakpoint,
2615	#endif /* !CONFIG_USER_ONLY */
2616	};
2617	#endif /* CONFIG_TCG */
2618
2619	static void arm_cpu_class_init(ObjectClass oc, const void data)
2620	{
2621	ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2622	CPUClass *cc = CPU_CLASS(acc);
2623	DeviceClass *dc = DEVICE_CLASS(oc);
2624	ResettableClass *rc = RESETTABLE_CLASS(oc);
2625
2626	device_class_set_parent_realize(dc, arm_cpu_realizefn,
2627	&acc->parent_realize);
2628
2629	device_class_set_props(dc, arm_cpu_properties);
2630
2631	resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL,
2632	&acc->parent_phases);
2633
2634	cc->class_by_name = arm_cpu_class_by_name;
2635	cc->dump_state = arm_cpu_dump_state;
2636	cc->set_pc = arm_cpu_set_pc;
2637	cc->get_pc = arm_cpu_get_pc;
2638	cc->gdb_read_register = arm_cpu_gdb_read_register;
2639	cc->gdb_write_register = arm_cpu_gdb_write_register;
2640	#ifndef CONFIG_USER_ONLY
2641	cc->max_as = ARMASIdx_MAX;
2642	cc->sysemu_ops = &arm_sysemu_ops;
2643	#endif
2644	cc->gdb_arch_name = arm_gdb_arch_name;
2645	cc->gdb_get_core_xml_file = arm_gdb_get_core_xml_file;
2646	cc->gdb_stop_before_watchpoint = true;
2647	cc->disas_set_info = arm_disas_set_info;
2648
2649	#ifdef CONFIG_TCG
2650	cc->tcg_ops = &arm_tcg_ops;
2651	#endif /* CONFIG_TCG */
2652	}
2653
2654	static void arm_cpu_instance_init(Object *obj)
2655	{
2656	ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2657
2658	acc->info->initfn(obj);
2659	arm_cpu_post_init(obj);
2660	}
2661
2662	static void cpu_register_class_init(ObjectClass oc, const void data)
2663	{
2664	ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2665	CPUClass *cc = CPU_CLASS(acc);
2666
2667	acc->info = data;
2668	if (acc->info->deprecation_note) {
2669	cc->deprecation_note = acc->info->deprecation_note;
2670	}
2671	}
2672
2673	void arm_cpu_register(const ARMCPUInfo *info)
2674	{
2675	TypeInfo type_info = {
2676	.parent = TYPE_ARM_CPU,
2677	.instance_init = arm_cpu_instance_init,
2678	.class_init = info->class_init ?: cpu_register_class_init,
2679	.class_data = info,
2680	};
2681
2682	type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2683	type_register_static(&type_info);
2684	g_free((void *)type_info.name);
2685	}
2686
2687	static const TypeInfo arm_cpu_type_info = {
2688	.name = TYPE_ARM_CPU,
2689	.parent = TYPE_CPU,
2690	.instance_size = sizeof(ARMCPU),
2691	.instance_align = __alignof__(ARMCPU),
2692	.instance_init = arm_cpu_initfn,
2693	.instance_finalize = arm_cpu_finalizefn,
2694	.abstract = true,
2695	.class_size = sizeof(ARMCPUClass),
2696	.class_init = arm_cpu_class_init,
2697	};
2698
2699	static void arm_cpu_register_types(void)
2700	{
2701	type_register_static(&arm_cpu_type_info);
2702	}
2703
2704	type_init(arm_cpu_register_types)