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1 /*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef ARM_CPU_H
21 #define ARM_CPU_H
22
23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
25 #include "hw/core/registerfields.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-common.h"
28 #include "exec/cpu-interrupt.h"
29 #include "exec/gdbstub.h"
30 #include "exec/page-protection.h"
31 #include "qapi/qapi-types-common.h"
32 #include "target/arm/multiprocessing.h"
33 #include "hw/arm/arm-security.h"
34 #include "target/arm/gtimer.h"
35 #include "target/arm/cpu-sysregs.h"
36 #include "target/arm/mmuidx.h"
37 #include "hw/intc/arm_gicv5_types.h"
38 #include "target/arm/vector-type.h"
39
40 #define EXCP_UDEF 1 /* undefined instruction */
41 #define EXCP_SWI 2 /* software interrupt */
42 #define EXCP_PREFETCH_ABORT 3
43 #define EXCP_DATA_ABORT 4
44 #define EXCP_IRQ 5
45 #define EXCP_FIQ 6
46 #define EXCP_BKPT 7
47 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
48 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
49 #define EXCP_HVC 11 /* HyperVisor Call */
50 #define EXCP_HYP_TRAP 12
51 #define EXCP_SMC 13 /* Secure Monitor Call */
52 #define EXCP_VIRQ 14
53 #define EXCP_VFIQ 15
54 #define EXCP_SEMIHOST 16 /* semihosting call */
55 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */
56 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
57 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */
58 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */
59 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */
60 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
61 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */
62 #define EXCP_VSERR 24
63 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */
64 #define EXCP_NMI 26
65 #define EXCP_VINMI 27
66 #define EXCP_VFNMI 28
67 #define EXCP_MON_TRAP 29 /* AArch32 trap to Monitor mode */
68 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
69
70 #define ARMV7M_EXCP_RESET 1
71 #define ARMV7M_EXCP_NMI 2
72 #define ARMV7M_EXCP_HARD 3
73 #define ARMV7M_EXCP_MEM 4
74 #define ARMV7M_EXCP_BUS 5
75 #define ARMV7M_EXCP_USAGE 6
76 #define ARMV7M_EXCP_SECURE 7
77 #define ARMV7M_EXCP_SVC 11
78 #define ARMV7M_EXCP_DEBUG 12
79 #define ARMV7M_EXCP_PENDSV 14
80 #define ARMV7M_EXCP_SYSTICK 15
81
82 /* ARM-specific interrupt pending bits. */
83 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
84 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
85 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
86 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
87 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4
88 #define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0
89 #define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1
90
91 /* The usual mapping for an AArch64 system register to its AArch32
92 * counterpart is for the 32 bit world to have access to the lower
93 * half only (with writes leaving the upper half untouched). It's
94 * therefore useful to be able to pass TCG the offset of the least
95 * significant half of a uint64_t struct member.
96 */
97 #if HOST_BIG_ENDIAN
98 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
99 #define offsetofhigh32(S, M) offsetof(S, M)
100 #else
101 #define offsetoflow32(S, M) offsetof(S, M)
102 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
103 #endif
104
105 /* The 2nd extra word holding syndrome info for data aborts does not use
106 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to
107 * help the sleb128 encoder do a better job.
108 * When restoring the CPU state, we shift it back up.
109 */
110 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
111 #define ARM_INSN_START_WORD2_SHIFT 13
112
113 /* We currently assume float and double are IEEE single and double
114 precision respectively.
115 Doing runtime conversions is tricky because VFP registers may contain
116 integer values (eg. as the result of a FTOSI instruction).
117 s<2n> maps to the least significant half of d<n>
118 s<2n+1> maps to the most significant half of d<n>
119 */
120
121 /**
122 * DynamicGDBFeatureInfo:
123 * @desc: Contains the feature descriptions.
124 * @data: A union with data specific to the set of registers
125 * @cpregs_keys: Array that contains the corresponding Key of
126 * a given cpreg with the same order of the cpreg
127 * in the XML description.
128 */
129 typedef struct DynamicGDBFeatureInfo {
130 GDBFeature desc;
131 union {
132 struct {
133 uint32_t *keys;
134 } cpregs;
135 } data;
136 } DynamicGDBFeatureInfo;
137
138 /* CPU state for each instance of a generic timer (in cp15 c14) */
139 typedef struct ARMGenericTimer {
140 uint64_t cval; /* Timer CompareValue register */
141 uint64_t ctl; /* Timer Control register */
142 } ARMGenericTimer;
143
144 /* In AArch32 mode, PAC keys do not exist at all. */
145 typedef struct ARMPACKey {
146 uint64_t lo, hi;
147 } ARMPACKey;
148
149 /* See the commentary above the TBFLAG field definitions. */
150 typedef struct CPUARMTBFlags {
151 uint32_t flags;
152 uint64_t flags2;
153 } CPUARMTBFlags;
154
155 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
156
157 typedef struct NVICState NVICState;
158
159 /*
160 * Enum for indexing vfp.fp_status[].
161 *
162 * FPST_A32: is the "normal" fp status for AArch32 insns
163 * FPST_A64: is the "normal" fp status for AArch64 insns
164 * FPST_A32_F16: used for AArch32 half-precision calculations
165 * FPST_A64_F16: used for AArch64 half-precision calculations
166 * FPST_STD: the ARM "Standard FPSCR Value"
167 * FPST_STD_F16: used for half-precision
168 * calculations with the ARM "Standard FPSCR Value"
169 * FPST_AH: used for the A64 insns which change behaviour
170 * when FPCR.AH == 1 (bfloat16 conversions and multiplies,
171 * and the reciprocal and square root estimate/step insns)
172 * FPST_AH_F16: used for the A64 insns which change behaviour
173 * when FPCR.AH == 1 (bfloat16 conversions and multiplies,
174 * and the reciprocal and square root estimate/step insns);
175 * for half-precision
176 * ZA: the "streaming sve" fp status.
177 * ZA_F16: likewise for half-precision.
178 *
179 * Half-precision operations are governed by a separate
180 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
181 * status structure to control this.
182 *
183 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
184 * round-to-nearest and is used by any operations (generally
185 * Neon) which the architecture defines as controlled by the
186 * standard FPSCR value rather than the FPSCR.
187 *
188 * The "standard FPSCR but for fp16 ops" is needed because
189 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than
190 * using a fixed value for it.
191 *
192 * FPST_AH is needed because some insns have different
193 * behaviour when FPCR.AH == 1: they don't update cumulative
194 * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and
195 * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16,
196 * which means we need an FPST_AH_F16 as well.
197 *
198 * The "ZA" float_status are for Streaming SVE operations which use
199 * default-NaN and do not generate fp exceptions, which means that they
200 * do not accumulate exception bits back into FPCR.
201 * See e.g. FPAdd vs FPAdd_ZA pseudocode functions, and the setting
202 * of fpcr.DN and fpexec parameters.
203 *
204 * To avoid having to transfer exception bits around, we simply
205 * say that the FPSCR cumulative exception flags are the logical
206 * OR of the flags in the four fp statuses. This relies on the
207 * only thing which needs to read the exception flags being
208 * an explicit FPSCR read.
209 */
210 typedef enum ARMFPStatusFlavour {
211 FPST_A32,
212 FPST_A64,
213 FPST_A32_F16,
214 FPST_A64_F16,
215 FPST_AH,
216 FPST_AH_F16,
217 FPST_ZA,
218 FPST_ZA_F16,
219 FPST_STD,
220 FPST_STD_F16,
221 } ARMFPStatusFlavour;
222 #define FPST_COUNT 10
223
224 /* Architecturally there are 128 PPIs in a GICv5 */
225 #define GICV5_NUM_PPIS 128
226
227 /**
228 * ARMHaltReason - the reason we have entered halt state
229 *
230 * To be able to correctly wake up via arm_cpu_has_work() we need to
231 * track the reason we went to sleep.
232 */
233 typedef enum {
234 NOT_HALTED = 0,
235 HALT_PSCI,
236 HALT_WFI,
237 HALT_WFE
238 } ARMHaltReason;
239
240 typedef struct CPUArchState {
241 /* Regs for current mode. */
242 uint32_t regs[16];
243
244 /* 32/64 switch only happens when taking and returning from
245 * exceptions so the overlap semantics are taken care of then
246 * instead of having a complicated union.
247 */
248 /* Regs for A64 mode. */
249 uint64_t xregs[32];
250 uint64_t pc;
251 /* PSTATE isn't an architectural register for ARMv8. However, it is
252 * convenient for us to assemble the underlying state into a 64 bit format
253 * identical to the architectural format used for the SPSR. (This is also
254 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
255 * 'pstate' register are.) Of the PSTATE bits:
256 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
257 * semantics as for AArch32, as described in the comments on each field)
258 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
259 * DAIF (exception masks) are kept in env->daif
260 * BTYPE is kept in env->btype
261 * SM and ZA are kept in env->svcr
262 * all other bits are stored in their correct places in env->pstate
263 */
264 uint64_t pstate;
265 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */
266 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */
267
268 /* Cached TBFLAGS state. See below for which bits are included. */
269 CPUARMTBFlags hflags;
270
271 /* Frequently accessed CPSR bits are stored separately for efficiency.
272 This contains all the other bits. Use cpsr_{read,write} to access
273 the whole CPSR. */
274 uint32_t uncached_cpsr;
275 uint32_t spsr;
276
277 /* Banked registers. */
278 uint64_t banked_spsr[8];
279 uint32_t banked_r13[8];
280 uint32_t banked_r14[8];
281
282 /* These hold r8-r12. */
283 uint32_t usr_regs[5];
284 uint32_t fiq_regs[5];
285
286 /* cpsr flag cache for faster execution */
287 uint32_t CF; /* 0 or 1 */
288 uint32_t VF; /* V is the bit 31. All other bits are undefined */
289 uint32_t NF; /* N is bit 31. All other bits are undefined. */
290 uint32_t ZF; /* Z set if zero. */
291 uint32_t QF; /* 0 or 1 */
292 uint32_t GE; /* cpsr[19:16] */
293 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
294 uint32_t btype; /* BTI branch type. spsr[11:10]. */
295 uint64_t daif; /* exception masks, in the bits they are in PSTATE */
296 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */
297
298 uint64_t elr_el[4]; /* AArch64 exception link regs */
299 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
300
301 /* System control coprocessor (cp15) */
302 struct {
303 uint32_t c0_cpuid;
304 union { /* Cache size selection */
305 struct {
306 uint64_t _unused_csselr0;
307 uint64_t csselr_ns;
308 uint64_t _unused_csselr1;
309 uint64_t csselr_s;
310 };
311 uint64_t csselr_el[4];
312 };
313 union { /* System control register. */
314 struct {
315 uint64_t _unused_sctlr;
316 uint64_t sctlr_ns;
317 uint64_t hsctlr;
318 uint64_t sctlr_s;
319 };
320 uint64_t sctlr_el[4];
321 };
322 uint64_t sctlr2_el[4]; /* Extension to System control register. */
323 uint64_t vsctlr; /* Virtualization System control register. */
324 uint64_t cpacr_el1; /* Architectural feature access control register */
325 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
326 uint64_t sder; /* Secure debug enable register. */
327 uint32_t nsacr; /* Non-secure access control register. */
328 union { /* MMU translation table base 0. */
329 struct {
330 uint64_t _unused_ttbr0_0;
331 uint64_t ttbr0_ns;
332 uint64_t _unused_ttbr0_1;
333 uint64_t ttbr0_s;
334 };
335 uint64_t ttbr0_el[4];
336 };
337 union { /* MMU translation table base 1. */
338 struct {
339 uint64_t _unused_ttbr1_0;
340 uint64_t ttbr1_ns;
341 uint64_t _unused_ttbr1_1;
342 uint64_t ttbr1_s;
343 };
344 uint64_t ttbr1_el[4];
345 };
346 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
347 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */
348 /* MMU translation table base control. */
349 uint64_t tcr_el[4];
350 uint64_t tcr2_el[3];
351 uint64_t vtcr_el2; /* Virtualization Translation Control. */
352 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */
353 uint64_t pir_el[4]; /* PIRE0_EL1, PIR_EL1, PIR_EL2, PIR_EL3 */
354 uint64_t pire0_el2;
355 uint64_t s2pir_el2;
356 uint32_t c2_data; /* MPU data cacheable bits. */
357 uint32_t c2_insn; /* MPU instruction cacheable bits. */
358 union { /* MMU domain access control register
359 * MPU write buffer control.
360 */
361 struct {
362 uint64_t dacr_ns;
363 uint64_t dacr_s;
364 };
365 struct {
366 uint64_t dacr32_el2;
367 };
368 };
369 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
370 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
371 uint64_t hcr_el2; /* Hypervisor configuration register */
372 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */
373 uint64_t scr_el3; /* Secure configuration register. */
374 union { /* Fault status registers. */
375 struct {
376 uint64_t ifsr_ns;
377 uint64_t ifsr_s;
378 };
379 struct {
380 uint64_t ifsr32_el2;
381 };
382 };
383 union {
384 struct {
385 uint64_t _unused_dfsr;
386 uint64_t dfsr_ns;
387 uint64_t hsr;
388 uint64_t dfsr_s;
389 };
390 uint64_t esr_el[4];
391 };
392 uint32_t c6_region[8]; /* MPU base/size registers. */
393 union { /* Fault address registers. */
394 struct {
395 uint64_t _unused_far0;
396 #if HOST_BIG_ENDIAN
397 uint32_t ifar_ns;
398 uint32_t dfar_ns;
399 uint32_t ifar_s;
400 uint32_t dfar_s;
401 #else
402 uint32_t dfar_ns;
403 uint32_t ifar_ns;
404 uint32_t dfar_s;
405 uint32_t ifar_s;
406 #endif
407 uint64_t _unused_far3;
408 };
409 uint64_t far_el[4];
410 };
411 uint64_t hpfar_el2;
412 uint64_t hstr_el2;
413 union { /* Translation result. */
414 struct {
415 uint64_t _unused_par_0;
416 uint64_t par_ns;
417 uint64_t _unused_par_1;
418 uint64_t par_s;
419 };
420 uint64_t par_el[4];
421 };
422
423 uint32_t c9_insn; /* Cache lockdown registers. */
424 uint32_t c9_data;
425 uint64_t c9_pmcr; /* performance monitor control register */
426 uint64_t c9_pmcnten; /* perf monitor counter enables */
427 uint64_t c9_pmovsr; /* perf monitor overflow status */
428 uint64_t c9_pmuserenr; /* perf monitor user enable */
429 uint64_t c9_pmselr; /* perf monitor counter selection register */
430 uint64_t c9_pminten; /* perf monitor interrupt enables */
431 /* Memory attribute redirection */
432 union {
433 struct {
434 #if HOST_BIG_ENDIAN
435 uint64_t _unused_mair_0;
436 uint32_t mair1_ns;
437 uint32_t mair0_ns;
438 uint64_t _unused_mair_1;
439 uint32_t mair1_s;
440 uint32_t mair0_s;
441 #else
442 uint64_t _unused_mair_0;
443 uint32_t mair0_ns;
444 uint32_t mair1_ns;
445 uint64_t _unused_mair_1;
446 uint32_t mair0_s;
447 uint32_t mair1_s;
448 #endif
449 };
450 uint64_t mair_el[4];
451 };
452 uint64_t mair2_el[4];
453 union { /* vector base address register */
454 struct {
455 uint64_t _unused_vbar;
456 uint64_t vbar_ns;
457 uint64_t hvbar;
458 uint64_t vbar_s;
459 };
460 uint64_t vbar_el[4];
461 };
462 uint32_t mvbar; /* (monitor) vector base address register */
463 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */
464 struct { /* FCSE PID. */
465 uint32_t fcseidr_ns;
466 uint32_t fcseidr_s;
467 };
468 union { /* Context ID. */
469 struct {
470 uint64_t _unused_contextidr_0;
471 uint64_t contextidr_ns;
472 uint64_t _unused_contextidr_1;
473 uint64_t contextidr_s;
474 };
475 uint64_t contextidr_el[4];
476 };
477 union { /* User RW Thread register. */
478 struct {
479 uint64_t tpidrurw_ns;
480 uint64_t tpidrprw_ns;
481 uint64_t htpidr;
482 uint64_t _tpidr_el3;
483 };
484 uint64_t tpidr_el[4];
485 };
486 uint64_t tpidr2_el0;
487 /* The secure banks of these registers don't map anywhere */
488 uint64_t tpidrurw_s;
489 uint64_t tpidrprw_s;
490 uint64_t tpidruro_s;
491
492 union { /* User RO Thread register. */
493 uint64_t tpidruro_ns;
494 uint64_t tpidrro_el[1];
495 };
496 uint64_t c14_cntfrq; /* Counter Frequency register */
497 uint64_t c14_cntkctl; /* Timer Control register */
498 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
499 uint64_t cntvoff_el2; /* Counter Virtual Offset register */
500 uint64_t cntpoff_el2; /* Counter Physical Offset register */
501 ARMGenericTimer c14_timer[NUM_GTIMERS];
502 uint32_t c15_ticonfig; /* TI925T configuration byte. */
503 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
504 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
505 uint32_t c15_threadid; /* TI debugger thread-ID. */
506 uint32_t c15_config_base_address; /* SCU base address. */
507 uint32_t c15_diagnostic; /* diagnostic register */
508 uint32_t c15_power_diagnostic;
509 uint32_t c15_power_control; /* power control */
510 uint64_t dbgbvr[16]; /* breakpoint value registers */
511 uint64_t dbgbcr[16]; /* breakpoint control registers */
512 uint64_t dbgwvr[16]; /* watchpoint value registers */
513 uint64_t dbgwcr[16]; /* watchpoint control registers */
514 uint64_t dbgclaim; /* DBGCLAIM bits */
515 uint64_t mdscr_el1;
516 uint64_t oslsr_el1; /* OS Lock Status */
517 uint64_t osdlr_el1; /* OS DoubleLock status */
518 uint64_t mdcr_el2;
519 uint64_t mdcr_el3;
520 /* Stores the architectural value of the counter *the last time it was
521 * updated* by pmccntr_op_start. Accesses should always be surrounded
522 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
523 * architecturally-correct value is being read/set.
524 */
525 uint64_t c15_ccnt;
526 /* Stores the delta between the architectural value and the underlying
527 * cycle count during normal operation. It is used to update c15_ccnt
528 * to be the correct architectural value before accesses. During
529 * accesses, c15_ccnt_delta contains the underlying count being used
530 * for the access, after which it reverts to the delta value in
531 * pmccntr_op_finish.
532 */
533 uint64_t c15_ccnt_delta;
534 uint64_t c14_pmevcntr[31];
535 uint64_t c14_pmevcntr_delta[31];
536 uint64_t c14_pmevtyper[31];
537 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
538 uint64_t vpidr_el2; /* Virtualization Processor ID Register */
539 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
540 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
541 uint64_t gcr_el1;
542 uint64_t rgsr_el1;
543
544 /* Minimal RAS registers */
545 uint64_t disr_el1;
546 uint64_t vdisr_el2;
547 uint64_t vsesr_el2;
548
549 /*
550 * Fine-Grained Trap registers. We store these as arrays so the
551 * access checking code doesn't have to manually select
552 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test.
553 * FEAT_FGT2 will add more elements to these arrays.
554 */
555 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
556 uint64_t fgt_write[3]; /* HFGWTR, HDFGWTR, FGWTE3 */
557 uint64_t fgt_exec[1]; /* HFGITR */
558
559 /* RME registers */
560 uint64_t gpccr_el3;
561 uint64_t gptbr_el3;
562 uint64_t gpcbw_el3;
563 uint64_t mfar_el3;
564
565 /* NV2 register */
566 uint64_t vncr_el2;
567
568 uint64_t gcscr_el[4]; /* GCSCRE0_EL1, GCSCR_EL[123] */
569 uint64_t gcspr_el[4]; /* GCSPR_EL[0123] */
570
571 /* MEC registers */
572 uint64_t mecid_p0_el2;
573 uint64_t mecid_a0_el2;
574 uint64_t mecid_p1_el2;
575 uint64_t mecid_a1_el2;
576 uint64_t mecid_rl_a_el3;
577 uint64_t vmecid_p_el2;
578 uint64_t vmecid_a_el2;
579 } cp15;
580
581 struct {
582 /* GICv5 CPU interface data */
583 uint64_t icc_icsr_el1;
584 uint64_t icc_apr[NUM_GICV5_DOMAINS];
585 uint64_t icc_cr0[NUM_GICV5_DOMAINS];
586 uint64_t icc_pcr[NUM_GICV5_DOMAINS];
587 /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register */
588 uint64_t ppi_active[GICV5_NUM_PPIS / 64];
589 uint64_t ppi_hm[GICV5_NUM_PPIS / 64];
590 uint64_t ppi_pend[GICV5_NUM_PPIS / 64];
591 uint64_t ppi_enable[GICV5_NUM_PPIS / 64];
592 /* The PRIO regs have 1 byte per PPI, so 8 PPIs to a register */
593 uint64_t ppi_priority[GICV5_NUM_PPIS / 8];
594
595 /* Cached highest-priority pending PPI for each domain */
596 GICv5PendingIrq ppi_hppi[NUM_GICV5_DOMAINS];
597 } gicv5_cpuif;
598
599 struct {
600 /* M profile has up to 4 stack pointers:
601 * a Main Stack Pointer and a Process Stack Pointer for each
602 * of the Secure and Non-Secure states. (If the CPU doesn't support
603 * the security extension then it has only two SPs.)
604 * In QEMU we always store the currently active SP in regs[13],
605 * and the non-active SP for the current security state in
606 * v7m.other_sp. The stack pointers for the inactive security state
607 * are stored in other_ss_msp and other_ss_psp.
608 * switch_v7m_security_state() is responsible for rearranging them
609 * when we change security state.
610 */
611 uint32_t other_sp;
612 uint32_t other_ss_msp;
613 uint32_t other_ss_psp;
614 uint32_t vecbase[M_REG_NUM_BANKS];
615 uint32_t basepri[M_REG_NUM_BANKS];
616 uint32_t control[M_REG_NUM_BANKS];
617 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
618 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
619 uint32_t hfsr; /* HardFault Status */
620 uint32_t dfsr; /* Debug Fault Status Register */
621 uint32_t sfsr; /* Secure Fault Status Register */
622 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
623 uint32_t bfar; /* BusFault Address */
624 uint32_t sfar; /* Secure Fault Address Register */
625 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
626 int exception;
627 uint32_t primask[M_REG_NUM_BANKS];
628 uint32_t faultmask[M_REG_NUM_BANKS];
629 uint32_t aircr; /* only holds r/w state if security extn implemented */
630 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
631 uint32_t csselr[M_REG_NUM_BANKS];
632 uint32_t scr[M_REG_NUM_BANKS];
633 uint32_t msplim[M_REG_NUM_BANKS];
634 uint32_t psplim[M_REG_NUM_BANKS];
635 uint32_t fpcar[M_REG_NUM_BANKS];
636 uint32_t fpccr[M_REG_NUM_BANKS];
637 uint32_t fpdscr[M_REG_NUM_BANKS];
638 uint32_t cpacr[M_REG_NUM_BANKS];
639 uint32_t nsacr;
640 uint32_t ltpsize;
641 uint32_t vpr;
642 } v7m;
643
644 /* Information associated with an exception about to be taken:
645 * code which raises an exception must set cs->exception_index and
646 * the relevant parts of this structure; the cpu_do_interrupt function
647 * will then set the guest-visible registers as part of the exception
648 * entry process.
649 */
650 struct {
651 uint64_t syndrome; /* AArch64 format syndrome register */
652 uint64_t vaddress; /* virtual addr associated with exception, if any */
653 uint32_t fsr; /* AArch32 format fault status register info */
654 uint32_t target_el; /* EL the exception should be targeted for */
655 } exception;
656
657 /* Information associated with an SError */
658 struct {
659 uint8_t pending;
660 uint8_t has_esr;
661 uint64_t esr;
662 } serror;
663
664 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
665
666 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
667 uint32_t irq_line_state;
668
669 /* Thumb-2 EE state. */
670 uint32_t teecr;
671 uint32_t teehbr;
672
673 /* VFP coprocessor state. */
674 struct {
675 ARMVectorReg zregs[32];
676
677 /* Store FFR as pregs[16] to make it easier to treat as any other. */
678 #define FFR_PRED_NUM 16
679 ARMPredicateReg pregs[17];
680 /* Scratch space for aa64 sve predicate temporary. */
681 ARMPredicateReg preg_tmp;
682
683 /* We store these fpcsr fields separately for convenience. */
684 uint32_t qc[4] QEMU_ALIGNED(16);
685 int vec_len;
686 int vec_stride;
687
688 /*
689 * Floating point status and control registers. Some bits are
690 * stored separately in other fields or in the float_status below.
691 */
692 uint64_t fpsr;
693 uint64_t fpcr;
694 uint64_t fpmr;
695
696 uint32_t xregs[16];
697
698 /* There are a number of distinct float control structures. */
699 float_status fp_status[FPST_COUNT];
700
701 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */
702 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */
703 } vfp;
704
705 uint64_t exclusive_addr;
706 uint64_t exclusive_val;
707 /*
708 * Contains the 'val' for the second 64-bit register of LDXP, which comes
709 * from the higher address, not the high part of a complete 128-bit value.
710 * In some ways it might be more convenient to record the exclusive value
711 * as the low and high halves of a 128 bit data value, but the current
712 * semantics of these fields are baked into the migration format.
713 */
714 uint64_t exclusive_high;
715
716 struct {
717 ARMPACKey apia;
718 ARMPACKey apib;
719 ARMPACKey apda;
720 ARMPACKey apdb;
721 ARMPACKey apga;
722 } keys;
723
724 uint64_t scxtnum_el[4];
725
726 struct {
727 /* SME2 ZT0 -- 512 bit array, with data ordered like ARMVectorReg. */
728 uint64_t zt0[512 / 64] QEMU_ALIGNED(16);
729
730 /*
731 * SME ZA storage -- 256 x 256 byte array, with bytes in host
732 * word order, as we do with vfp.zregs[]. This corresponds to
733 * the architectural ZA array, where ZA[N] is in the least
734 * significant bytes of env->za_state.za[N].
735 *
736 * When SVL is less than the architectural maximum, the accessible
737 * storage is restricted, such that if the SVL is X bytes the guest
738 * can see only the bottom X elements of zarray[], and only the least
739 * significant X bytes of each element of the array. (In other words,
740 * the observable part is always square.)
741 *
742 * The ZA storage can also be considered as a set of square tiles of
743 * elements of different sizes. The mapping from tiles to the ZA array
744 * is architecturally defined, such that for tiles of elements of esz
745 * bytes, the Nth row (or "horizontal slice") of tile T is in
746 * ZA[T + N * esz]. Note that this means that each tile is not
747 * contiguous in the ZA storage, because its rows are striped through
748 * the ZA array.
749 *
750 * Because this is so large, keep this toward the end of the
751 * reset area, to keep the offsets into the rest of the structure
752 * smaller.
753 */
754 ARMVectorReg za[ARM_MAX_VQ * 16];
755 } za_state;
756
757 struct CPUBreakpoint *cpu_breakpoint[16];
758 struct CPUWatchpoint *cpu_watchpoint[16];
759
760 /* Optional fault info across tlb lookup. */
761 ARMMMUFaultInfo *tlb_fi;
762
763 /* Reason the CPU is halted */
764 ARMHaltReason halt_reason;
765
766 /*
767 * The event register is shared by all ARM profiles (A/R/M),
768 * so it is stored in the top-level CPU state.
769 */
770 bool event_register;
771
772 /* Fields up to this point are cleared by a CPU reset */
773 struct {} end_reset_fields;
774
775 /* Fields after this point are preserved across CPU reset. */
776
777 /* Internal CPU feature flags. */
778 uint64_t features;
779
780 /* PMSAv7 MPU */
781 struct {
782 uint32_t *drbar;
783 uint32_t *drsr;
784 uint32_t *dracr;
785 uint32_t rnr[M_REG_NUM_BANKS];
786 } pmsav7;
787
788 /* PMSAv8 MPU */
789 struct {
790 /* The PMSAv8 implementation also shares some PMSAv7 config
791 * and state:
792 * pmsav7.rnr (region number register)
793 * pmsav7_dregion (number of configured regions)
794 */
795 uint32_t *rbar[M_REG_NUM_BANKS];
796 uint32_t *rlar[M_REG_NUM_BANKS];
797 uint32_t *hprbar;
798 uint32_t *hprlar;
799 uint32_t mair0[M_REG_NUM_BANKS];
800 uint32_t mair1[M_REG_NUM_BANKS];
801 uint32_t hprselr;
802 } pmsav8;
803
804 /* v8M SAU */
805 struct {
806 uint32_t *rbar;
807 uint32_t *rlar;
808 uint32_t rnr;
809 uint32_t ctrl;
810 } sau;
811
812 #if !defined(CONFIG_USER_ONLY)
813 NVICState *nvic;
814 const struct arm_boot_info *boot_info;
815 /* Store GICv3CPUState to access from this struct */
816 void *gicv3state;
817 /* Similarly, for a GICv5Common */
818 void *gicv5state;
819 /* For GICv5, this CPU's IAFFID */
820 uint64_t gicv5_iaffid;
821 #else /* CONFIG_USER_ONLY */
822 /* For usermode syscall translation. */
823 bool eabi;
824 /* Linux syscall tagged address support */
825 bool tagged_addr_enable;
826 #endif /* CONFIG_USER_ONLY */
827 } CPUARMState;
828
829 static inline void set_feature(CPUARMState *env, int feature)
830 {
831 env->features |= 1ULL << feature;
832 }
833
834 static inline void unset_feature(CPUARMState *env, int feature)
835 {
836 env->features &= ~(1ULL << feature);
837 }
838
839 /**
840 * ARMELChangeHookFn:
841 * type of a function which can be registered via arm_register_el_change_hook()
842 * to get callbacks when the CPU changes its exception level or mode.
843 */
844 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
845 typedef struct ARMELChangeHook ARMELChangeHook;
846 struct ARMELChangeHook {
847 ARMELChangeHookFn *hook;
848 void *opaque;
849 QLIST_ENTRY(ARMELChangeHook) node;
850 };
851
852 /* These values map onto the return values for
853 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
854 typedef enum ARMPSCIState {
855 PSCI_ON = 0,
856 PSCI_OFF = 1,
857 PSCI_ON_PENDING = 2
858 } ARMPSCIState;
859
860 typedef struct ARMISARegisters ARMISARegisters;
861
862 /*
863 * In map, each set bit is a supported vector length of (bit-number + 1) * 16
864 * bytes, i.e. each bit number + 1 is the vector length in quadwords.
865 *
866 * While processing properties during initialization, corresponding init bits
867 * are set for bits in sve_vq_map that have been set by properties.
868 *
869 * Bits set in supported represent valid vector lengths for the CPU type.
870 */
871 typedef struct {
872 uint32_t map, init, supported;
873 } ARMVQMap;
874
875 /* REG is ID_XXX */
876 #define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \
877 ({ \
878 ARMISARegisters *i_ = (ISAR); \
879 uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \
880 regval = FIELD_DP64(regval, REG, FIELD, VALUE); \
881 i_->idregs[REG ## _EL1_IDX] = regval; \
882 })
883
884 #define FIELD_DP32_IDREG(ISAR, REG, FIELD, VALUE) \
885 ({ \
886 ARMISARegisters *i_ = (ISAR); \
887 uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \
888 regval = FIELD_DP32(regval, REG, FIELD, VALUE); \
889 i_->idregs[REG ## _EL1_IDX] = regval; \
890 })
891
892 #define FIELD_EX64_IDREG(ISAR, REG, FIELD) \
893 ({ \
894 const ARMISARegisters *i_ = (ISAR); \
895 FIELD_EX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
896 })
897
898 #define FIELD_EX32_IDREG(ISAR, REG, FIELD) \
899 ({ \
900 const ARMISARegisters *i_ = (ISAR); \
901 FIELD_EX32(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
902 })
903
904 #define FIELD_SEX64_IDREG(ISAR, REG, FIELD) \
905 ({ \
906 const ARMISARegisters *i_ = (ISAR); \
907 FIELD_SEX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
908 })
909
910 #define SET_IDREG(ISAR, REG, VALUE) \
911 ({ \
912 ARMISARegisters *i_ = (ISAR); \
913 i_->idregs[REG ## _EL1_IDX] = VALUE; \
914 })
915
916 #define GET_IDREG(ISAR, REG) \
917 ({ \
918 const ARMISARegisters *i_ = (ISAR); \
919 i_->idregs[REG ## _EL1_IDX]; \
920 })
921
922 /**
923 * ARMCPU:
924 * @env: #CPUARMState
925 *
926 * An ARM CPU core.
927 */
928 struct ArchCPU {
929 CPUState parent_obj;
930
931 CPUARMState env;
932
933 /* Coprocessor information */
934 GHashTable *cp_regs;
935 /* For marshalling (mostly coprocessor) register state between the
936 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
937 * we use these arrays.
938 */
939 /* List of register indexes managed via these arrays; (full KVM style
940 * 64 bit indexes, not CPRegInfo 32 bit indexes)
941 */
942 uint64_t *cpreg_indexes;
943 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
944 uint64_t *cpreg_values;
945 /* Length of the indexes, values, reset_values arrays */
946 int32_t cpreg_array_len;
947 /* These are used only for migration: incoming data arrives in
948 * these fields and is sanity checked in post_load before copying
949 * to the working data structures above.
950 */
951 uint64_t *cpreg_vmstate_indexes;
952 uint64_t *cpreg_vmstate_values;
953 int32_t cpreg_vmstate_array_len;
954
955 DynamicGDBFeatureInfo dyn_sysreg_feature;
956 DynamicGDBFeatureInfo dyn_svereg_feature;
957 DynamicGDBFeatureInfo dyn_smereg_feature;
958 DynamicGDBFeatureInfo dyn_m_systemreg_feature;
959 DynamicGDBFeatureInfo dyn_m_secextreg_feature;
960 DynamicGDBFeatureInfo dyn_tls_feature;
961
962 /* Timers used by the generic (architected) timer */
963 QEMUTimer *gt_timer[NUM_GTIMERS];
964 /*
965 * Timer used by the PMU. Its state is restored after migration by
966 * pmu_op_finish() - it does not need other handling during migration
967 */
968 QEMUTimer *pmu_timer;
969 /* Timer used for WFxT timeouts OR event stream events */
970 QEMUTimer *wfxt_timer;
971
972 /* GPIO outputs for generic timer */
973 qemu_irq gt_timer_outputs[NUM_GTIMERS];
974 /* GPIO output for GICv3 maintenance interrupt signal */
975 qemu_irq gicv3_maintenance_interrupt;
976 /* GPIO output for the PMU interrupt */
977 qemu_irq pmu_interrupt;
978
979 /* MemoryRegion to use for secure physical accesses */
980 MemoryRegion *secure_memory;
981
982 /* MemoryRegion to use for allocation tag accesses */
983 MemoryRegion *tag_memory;
984 MemoryRegion *secure_tag_memory;
985
986 /* For v8M, pointer to the IDAU interface provided by board/SoC */
987 Object *idau;
988
989 /* 'compatible' string for this CPU for Linux device trees */
990 const char *dtb_compatible;
991
992 /* PSCI version for this CPU
993 * Bits[31:16] = Major Version
994 * Bits[15:0] = Minor Version
995 */
996 uint32_t psci_version;
997
998 /* Current power state, access guarded by BQL */
999 ARMPSCIState power_state;
1000
1001 /* CPU has virtualization extension */
1002 bool has_el2;
1003 /* CPU has security extension */
1004 bool has_el3;
1005 /* CPU has PMU (Performance Monitor Unit) */
1006 bool has_pmu;
1007 /* CPU has VFP */
1008 bool has_vfp;
1009 /* CPU has 32 VFP registers */
1010 bool has_vfp_d32;
1011 /* CPU has Neon */
1012 bool has_neon;
1013 /* CPU has M-profile DSP extension */
1014 bool has_dsp;
1015 /* CPU has FEAT_GCIE GICv5 CPU interface */
1016 bool has_gcie;
1017
1018 /* CPU has memory protection unit */
1019 bool has_mpu;
1020 /* CPU has MTE enabled in KVM mode */
1021 bool kvm_mte;
1022 /* PMSAv7 MPU number of supported regions */
1023 uint32_t pmsav7_dregion;
1024 /* PMSAv8 MPU number of supported hyp regions */
1025 uint32_t pmsav8r_hdregion;
1026 /* v8M SAU number of supported regions */
1027 uint32_t sau_sregion;
1028
1029 /* PSCI conduit used to invoke PSCI methods
1030 * 0 - disabled, 1 - smc, 2 - hvc
1031 */
1032 uint32_t psci_conduit;
1033
1034 /* For v8M, initial value of the Secure VTOR */
1035 uint32_t init_svtor;
1036 /* For v8M, initial value of the Non-secure VTOR */
1037 uint32_t init_nsvtor;
1038
1039 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
1040 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
1041 */
1042 uint32_t kvm_target;
1043
1044 /* KVM init features for this CPU */
1045 uint32_t kvm_init_features[7];
1046
1047 /* KVM CPU state */
1048
1049 /* KVM virtual time adjustment */
1050 bool kvm_adjvtime;
1051 bool kvm_vtime_dirty;
1052 uint64_t kvm_vtime;
1053
1054 /* KVM steal time */
1055 OnOffAuto kvm_steal_time;
1056
1057 /* Uniprocessor system with MP extensions */
1058 bool mp_is_up;
1059
1060 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init
1061 * and the probe failed (so we need to report the error in realize)
1062 */
1063 bool host_cpu_probe_failed;
1064
1065 /* QOM property to indicate we should use the back-compat CNTFRQ default */
1066 bool backcompat_cntfrq;
1067
1068 /* QOM property to indicate we should use the back-compat QARMA5 default */
1069 bool backcompat_pauth_default_use_qarma5;
1070
1071 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
1072 * register.
1073 */
1074 int32_t core_count;
1075
1076 /* The instance init functions for implementation-specific subclasses
1077 * set these fields to specify the implementation-dependent values of
1078 * various constant registers and reset values of non-constant
1079 * registers.
1080 * Some of these might become QOM properties eventually.
1081 * Field names match the official register names as defined in the
1082 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
1083 * is used for reset values of non-constant registers; no reset_
1084 * prefix means a constant register.
1085 * Some of these registers are split out into a substructure that
1086 * is shared with the translators to control the ISA.
1087 *
1088 * Note that if you add an ID register to the ARMISARegisters struct
1089 * you need to also update the 32-bit and 64-bit versions of the
1090 * kvm_arm_get_host_cpu_features() function to correctly populate the
1091 * field by reading the value from the KVM vCPU. If it is an AArch64
1092 * ID register then you also must update arm_clear_aarch64_idregs().
1093 */
1094 struct ARMISARegisters {
1095 uint32_t mvfr0;
1096 uint32_t mvfr1;
1097 uint32_t mvfr2;
1098 uint32_t dbgdidr;
1099 uint32_t dbgdevid;
1100 uint32_t dbgdevid1;
1101 uint64_t reset_pmcr_el0;
1102 uint64_t idregs[NUM_ID_IDX];
1103 } isar;
1104 uint64_t midr;
1105 uint32_t revidr;
1106 uint32_t reset_fpsid;
1107 uint64_t ctr;
1108 uint32_t reset_sctlr;
1109 uint64_t pmceid0;
1110 uint64_t pmceid1;
1111 uint64_t mp_affinity; /* MP ID without feature bits */
1112 /* The elements of this array are the CCSIDR values for each cache,
1113 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
1114 */
1115 uint64_t ccsidr[16];
1116 uint64_t reset_cbar;
1117 uint32_t reset_auxcr;
1118 bool reset_hivecs;
1119 uint8_t reset_l0gptsz;
1120
1121 /*
1122 * Intermediate values used during property parsing.
1123 * Once finalized, the values should be read from ID_AA64*.
1124 */
1125 bool prop_pauth;
1126 bool prop_pauth_impdef;
1127 bool prop_pauth_qarma3;
1128 bool prop_pauth_qarma5;
1129 bool prop_lpa2;
1130
1131 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
1132 uint8_t gm_blocksize;
1133
1134 uint64_t rvbar_prop; /* Property/input signals. */
1135
1136 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
1137 int gic_num_lrs; /* number of list registers */
1138 int gic_vpribits; /* number of virtual priority bits */
1139 int gic_vprebits; /* number of virtual preemption bits */
1140 int gic_pribits; /* number of physical priority bits */
1141
1142 /* Whether the cfgend input is high (i.e. this CPU should reset into
1143 * big-endian mode). This setting isn't used directly: instead it modifies
1144 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
1145 * architecture version.
1146 */
1147 bool cfgend;
1148
1149 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
1150 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
1151 QLIST_HEAD(, ARMCPRegMigTolerance) cpreg_mig_tolerances;
1152
1153 int32_t node_id; /* NUMA node this CPU belongs to */
1154
1155 /* Used to synchronize KVM and QEMU in-kernel device levels */
1156 uint8_t device_irq_level;
1157
1158 /* Used to set the maximum vector length the cpu will support. */
1159 uint32_t sve_max_vq;
1160 uint32_t sme_max_vq;
1161
1162 #ifdef CONFIG_USER_ONLY
1163 /* Used to set the default vector length at process start. */
1164 uint32_t sve_default_vq;
1165 uint32_t sme_default_vq;
1166 #endif
1167
1168 ARMVQMap sve_vq;
1169 ARMVQMap sme_vq;
1170
1171 /* Generic timer counter frequency, in Hz */
1172 uint64_t gt_cntfrq_hz;
1173 };
1174
1175 typedef struct ARMCPUInfo {
1176 const char *name;
1177 const char *deprecation_note;
1178 void (*initfn)(Object *obj);
1179 void (*class_init)(ObjectClass *oc, const void *data);
1180 } ARMCPUInfo;
1181
1182 /**
1183 * ARMCPUClass:
1184 * @parent_realize: The parent class' realize handler.
1185 * @parent_phases: The parent class' reset phase handlers.
1186 *
1187 * An ARM CPU model.
1188 */
1189 struct ARMCPUClass {
1190 CPUClass parent_class;
1191
1192 const ARMCPUInfo *info;
1193 DeviceRealize parent_realize;
1194 ResettablePhases parent_phases;
1195 };
1196
1197 static inline uint8_t get_dczid_bs(ARMCPU *cpu)
1198 {
1199 return extract64(cpu->isar.idregs[DCZID_EL0_IDX], 0, 4);
1200 }
1201
1202 static inline void set_dczid_bs(ARMCPU *cpu, uint8_t bs)
1203 {
1204 /* keep dzp unchanged */
1205 cpu->isar.idregs[DCZID_EL0_IDX] =
1206 deposit64(cpu->isar.idregs[DCZID_EL0_IDX], 0, 4, bs);
1207 }
1208
1209 /* Callback functions for the generic timer's timers. */
1210 void arm_gt_ptimer_cb(void *opaque);
1211 void arm_gt_vtimer_cb(void *opaque);
1212 void arm_gt_htimer_cb(void *opaque);
1213 void arm_gt_stimer_cb(void *opaque);
1214 void arm_gt_hvtimer_cb(void *opaque);
1215 void arm_gt_sel2timer_cb(void *opaque);
1216 void arm_gt_sel2vtimer_cb(void *opaque);
1217
1218 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
1219 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
1220
1221 #define ARM_AFF0_SHIFT 0
1222 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
1223 #define ARM_AFF1_SHIFT 8
1224 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
1225 #define ARM_AFF2_SHIFT 16
1226 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
1227 #define ARM_AFF3_SHIFT 32
1228 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
1229 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8
1230
1231 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK)
1232 #define ARM64_AFFINITY_MASK \
1233 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK)
1234 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
1235
1236 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz);
1237
1238 #ifndef CONFIG_USER_ONLY
1239 extern const VMStateDescription vmstate_arm_cpu;
1240
1241 void arm_cpu_do_interrupt(CPUState *cpu);
1242 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1243
1244 typedef struct ARMGranuleProtectionConfig {
1245 /* GPCCR_EL3 */
1246 uint64_t gpccr;
1247 /* GPCBW_EL3 */
1248 uint64_t gpcbw;
1249 /* GPTBR_EL3 */
1250 uint64_t gptbr;
1251 /* ID_AA64MMFR0_EL1.PARange */
1252 uint8_t parange;
1253 /* FEAT_SEL2 */
1254 bool support_sel2;
1255 /* Address space to access Granule Protection Table */
1256 AddressSpace *gpt_as;
1257 } ARMGranuleProtectionConfig;
1258
1259 /**
1260 * arm_granule_protection_check
1261 * @config: granule protection configuration
1262 * @paddress: address accessed
1263 * @pspace: physical address space accessed
1264 * @ss: security state for access
1265 * @fi: fault information in case a fault is detected
1266 *
1267 * Checks if @paddress can be accessed in physical adress space @pspace
1268 * for @ss secure state, following granule protection setup with @config.
1269 * If a fault is detected, @fi is set accordingly.
1270 * See GranuleProtectionCheck() in A-profile manual.
1271 *
1272 * Returns: true if access is authorized, else false.
1273 */
1274 bool arm_granule_protection_check(ARMGranuleProtectionConfig config,
1275 uint64_t paddress,
1276 ARMSecuritySpace pspace,
1277 ARMSecuritySpace ss,
1278 ARMMMUFaultInfo *fi);
1279 #endif /* !CONFIG_USER_ONLY */
1280
1281 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1282 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1283
1284 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1285 int cpuid, DumpState *s);
1286 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1287 int cpuid, DumpState *s);
1288
1289 /**
1290 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling
1291 * @cpu: CPU (which must have been freshly reset)
1292 * @target_el: exception level to put the CPU into
1293 * @secure: whether to put the CPU in secure state
1294 *
1295 * When QEMU is directly running a guest kernel at a lower level than
1296 * EL3 it implicitly emulates some aspects of the guest firmware.
1297 * This includes that on reset we need to configure the parts of the
1298 * CPU corresponding to EL3 so that the real guest code can run at its
1299 * lower exception level. This function does that post-reset CPU setup,
1300 * for when we do direct boot of a guest kernel, and for when we
1301 * emulate PSCI and similar firmware interfaces starting a CPU at a
1302 * lower exception level.
1303 *
1304 * @target_el must be an EL implemented by the CPU between 1 and 3.
1305 * We do not support dropping into a Secure EL other than 3.
1306 *
1307 * It is the responsibility of the caller to call arm_rebuild_hflags().
1308 */
1309 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el);
1310
1311 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1312 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1313 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1314 void aarch64_sve_change_el(CPUARMState *env, int old_el,
1315 int new_el, bool el0_a64);
1316 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask);
1317
1318 /*
1319 * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1320 * The byte at offset i from the start of the in-memory representation contains
1321 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
1322 * lowest offsets are stored in the lowest memory addresses, then that nearly
1323 * matches QEMU's representation, which is to use an array of host-endian
1324 * uint64_t's, where the lower offsets are at the lower indices. To complete
1325 * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1326 */
1327 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1328 {
1329 #if HOST_BIG_ENDIAN
1330 int i;
1331
1332 for (i = 0; i < nr; ++i) {
1333 dst[i] = bswap64(src[i]);
1334 }
1335
1336 return dst;
1337 #else
1338 return src;
1339 #endif
1340 }
1341
1342 void aarch64_sync_32_to_64(CPUARMState *env);
1343 void aarch64_sync_64_to_32(CPUARMState *env);
1344
1345 int fp_exception_el(CPUARMState *env, int cur_el);
1346 int sve_exception_el(CPUARMState *env, int cur_el);
1347 int sme_exception_el(CPUARMState *env, int cur_el);
1348
1349 /**
1350 * sve_vqm1_for_el_sm:
1351 * @env: CPUARMState
1352 * @el: exception level
1353 * @sm: streaming mode
1354 *
1355 * Compute the current vector length for @el & @sm, in units of
1356 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
1357 * If @sm, compute for SVL, otherwise NVL.
1358 */
1359 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm);
1360
1361 /* Likewise, but using @sm = PSTATE.SM. */
1362 uint32_t sve_vqm1_for_el(CPUARMState *env, int el);
1363
1364 static inline bool is_a64(const CPUARMState *env)
1365 {
1366 return env->aarch64;
1367 }
1368
1369 /**
1370 * pmu_op_start/finish
1371 * @env: CPUARMState
1372 *
1373 * Convert all PMU counters between their delta form (the typical mode when
1374 * they are enabled) and the guest-visible values. These two calls must
1375 * surround any action which might affect the counters.
1376 */
1377 void pmu_op_start(CPUARMState *env);
1378 void pmu_op_finish(CPUARMState *env);
1379
1380 /*
1381 * Called when a PMU counter is due to overflow
1382 */
1383 void arm_pmu_timer_cb(void *opaque);
1384
1385 /**
1386 * Functions to register as EL change hooks for PMU mode filtering
1387 */
1388 void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1389 void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1390
1391 /*
1392 * pmu_init
1393 * @cpu: ARMCPU
1394 *
1395 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state
1396 * for the current configuration
1397 */
1398 void pmu_init(ARMCPU *cpu);
1399
1400 /* SCTLR bit meanings. Several bits have been reused in newer
1401 * versions of the architecture; in that case we define constants
1402 * for both old and new bit meanings. Code which tests against those
1403 * bits should probably check or otherwise arrange that the CPU
1404 * is the architectural version it expects.
1405 */
1406 #define SCTLR_M (1U << 0)
1407 #define SCTLR_A (1U << 1)
1408 #define SCTLR_C (1U << 2)
1409 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
1410 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1411 #define SCTLR_SA (1U << 3) /* AArch64 only */
1412 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
1413 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1414 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
1415 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
1416 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1417 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1418 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */
1419 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
1420 #define SCTLR_ITD (1U << 7) /* v8 onward */
1421 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
1422 #define SCTLR_SED (1U << 8) /* v8 onward */
1423 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
1424 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
1425 #define SCTLR_F (1U << 10) /* up to v6 */
1426 #define SCTLR_SW (1U << 10) /* v7 */
1427 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
1428 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */
1429 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
1430 #define SCTLR_I (1U << 12)
1431 #define SCTLR_V (1U << 13) /* AArch32 only */
1432 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */
1433 #define SCTLR_RR (1U << 14) /* up to v7 */
1434 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
1435 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
1436 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
1437 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
1438 #define SCTLR_nTWI (1U << 16) /* v8 onward */
1439 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */
1440 #define SCTLR_BR (1U << 17) /* PMSA only */
1441 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
1442 #define SCTLR_nTWE (1U << 18) /* v8 onward */
1443 #define SCTLR_WXN (1U << 19)
1444 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
1445 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
1446 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
1447 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
1448 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1449 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
1450 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */
1451 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
1452 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
1453 #define SCTLR_VE (1U << 24) /* up to v7 */
1454 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
1455 #define SCTLR_EE (1U << 25)
1456 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
1457 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
1458 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1459 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */
1460 #define SCTLR_TRE (1U << 28) /* AArch32 only */
1461 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1462 #define SCTLR_AFE (1U << 29) /* AArch32 only */
1463 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1464 #define SCTLR_TE (1U << 30) /* AArch32 only */
1465 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
1466 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
1467 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
1468 #define SCTLR_CMOW (1ULL << 32) /* FEAT_CMOW */
1469 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */
1470 #define SCTLR_EnFPM (1ULL << 34) /* FEAT_FPMR */
1471 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1472 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1473 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1474 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
1475 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
1476 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1477 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
1478 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
1479 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */
1480 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */
1481 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */
1482 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */
1483 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */
1484 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */
1485 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */
1486 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */
1487 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */
1488 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */
1489 #define SCTLR_TCSO0 (1ULL << 58) /* FEAT_MTE_STORE_ONLY */
1490 #define SCTLR_TCSO (1ULL << 59) /* FEAT_MTE_STORE_ONLY */
1491 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */
1492 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */
1493 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
1494 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
1495
1496 #define SCTLR2_EMEC (1ULL << 1) /* FEAT_MEC */
1497 #define SCTLR2_NMEA (1ULL << 2) /* FEAT_DoubleFault2 */
1498 #define SCTLR2_ENADERR (1ULL << 3) /* FEAT_ADERR */
1499 #define SCTLR2_ENANERR (1ULL << 4) /* FEAT_ANERR */
1500 #define SCTLR2_EASE (1ULL << 5) /* FEAT_DoubleFault2 */
1501 #define SCTLR2_ENIDCP128 (1ULL << 6) /* FEAT_SYSREG128 */
1502 #define SCTLR2_ENPACM (1ULL << 7) /* FEAT_PAuth_LR */
1503 #define SCTLR2_ENPACM0 (1ULL << 8) /* FEAT_PAuth_LR */
1504 #define SCTLR2_CPTA (1ULL << 9) /* FEAT_CPA2 */
1505 #define SCTLR2_CPTA0 (1ULL << 10) /* FEAT_CPA2 */
1506 #define SCTLR2_CPTM (1ULL << 11) /* FEAT_CPA2 */
1507 #define SCTLR2_CPTM0 (1ULL << 12) /* FEAT_CAP2 */
1508
1509 #define CPSR_M (0x1fU)
1510 #define CPSR_T (1U << 5)
1511 #define CPSR_F (1U << 6)
1512 #define CPSR_I (1U << 7)
1513 #define CPSR_A (1U << 8)
1514 #define CPSR_E (1U << 9)
1515 #define CPSR_IT_2_7 (0xfc00U)
1516 #define CPSR_GE (0xfU << 16)
1517 #define CPSR_IL (1U << 20)
1518 #define CPSR_DIT (1U << 21)
1519 #define CPSR_PAN (1U << 22)
1520 #define CPSR_SSBS (1U << 23)
1521 #define CPSR_J (1U << 24)
1522 #define CPSR_IT_0_1 (3U << 25)
1523 #define CPSR_Q (1U << 27)
1524 #define CPSR_V (1U << 28)
1525 #define CPSR_C (1U << 29)
1526 #define CPSR_Z (1U << 30)
1527 #define CPSR_N (1U << 31)
1528 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1529 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1530 #define ISR_FS (1U << 9)
1531 #define ISR_IS (1U << 10)
1532
1533 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1534 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1535 | CPSR_NZCV)
1536 /* Bits writable in user mode. */
1537 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1538 /* Execution state bits. MRS read as zero, MSR writes ignored. */
1539 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1540
1541 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1542 #define XPSR_EXCP 0x1ffU
1543 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1544 #define XPSR_IT_2_7 CPSR_IT_2_7
1545 #define XPSR_GE CPSR_GE
1546 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1547 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1548 #define XPSR_IT_0_1 CPSR_IT_0_1
1549 #define XPSR_Q CPSR_Q
1550 #define XPSR_V CPSR_V
1551 #define XPSR_C CPSR_C
1552 #define XPSR_Z CPSR_Z
1553 #define XPSR_N CPSR_N
1554 #define XPSR_NZCV CPSR_NZCV
1555 #define XPSR_IT CPSR_IT
1556
1557 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1558 * Only these are valid when in AArch64 mode; in
1559 * AArch32 mode SPSRs are basically CPSR-format.
1560 */
1561 #define PSTATE_SP (1U)
1562 #define PSTATE_M (0xFU)
1563 #define PSTATE_nRW (1U << 4)
1564 #define PSTATE_F (1U << 6)
1565 #define PSTATE_I (1U << 7)
1566 #define PSTATE_A (1U << 8)
1567 #define PSTATE_D (1U << 9)
1568 #define PSTATE_BTYPE (3U << 10)
1569 #define PSTATE_SSBS (1U << 12)
1570 #define PSTATE_ALLINT (1U << 13)
1571 #define PSTATE_IL (1U << 20)
1572 #define PSTATE_SS (1U << 21)
1573 #define PSTATE_PAN (1U << 22)
1574 #define PSTATE_UAO (1U << 23)
1575 #define PSTATE_DIT (1U << 24)
1576 #define PSTATE_TCO (1U << 25)
1577 #define PSTATE_V (1U << 28)
1578 #define PSTATE_C (1U << 29)
1579 #define PSTATE_Z (1U << 30)
1580 #define PSTATE_N (1U << 31)
1581 #define PSTATE_EXLOCK (1ULL << 34)
1582 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1583 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1584 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1585 /* Mode values for AArch64 */
1586 #define PSTATE_MODE_EL3h 13
1587 #define PSTATE_MODE_EL3t 12
1588 #define PSTATE_MODE_EL2h 9
1589 #define PSTATE_MODE_EL2t 8
1590 #define PSTATE_MODE_EL1h 5
1591 #define PSTATE_MODE_EL1t 4
1592 #define PSTATE_MODE_EL0t 0
1593
1594 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */
1595 FIELD(SVCR, SM, 0, 1)
1596 FIELD(SVCR, ZA, 1, 1)
1597
1598 /* Fields for SMCR_ELx. */
1599 FIELD(SMCR, LEN, 0, 4)
1600 FIELD(SMCR, EZT0, 30, 1)
1601 FIELD(SMCR, FA64, 31, 1)
1602
1603 /* Write a new value to v7m.exception, thus transitioning into or out
1604 * of Handler mode; this may result in a change of active stack pointer.
1605 */
1606 void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1607
1608 /* Map EL and handler into a PSTATE_MODE. */
1609 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1610 {
1611 return (el << 2) | handler;
1612 }
1613
1614 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1615 * interprocessing, so we don't attempt to sync with the cpsr state used by
1616 * the 32 bit decoder.
1617 */
1618 static inline uint64_t pstate_read(CPUARMState *env)
1619 {
1620 int ZF;
1621
1622 ZF = (env->ZF == 0);
1623 return (env->NF & 0x80000000) | (ZF << 30)
1624 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1625 | env->pstate | env->daif | (env->btype << 10);
1626 }
1627
1628 static inline void pstate_write(CPUARMState *env, uint64_t val)
1629 {
1630 env->ZF = (~val) & PSTATE_Z;
1631 env->NF = val;
1632 env->CF = (val >> 29) & 1;
1633 env->VF = (val << 3) & 0x80000000;
1634 env->daif = val & PSTATE_DAIF;
1635 env->btype = (val >> 10) & 3;
1636 env->pstate = val & ~CACHED_PSTATE_BITS;
1637 }
1638
1639 /* Return the current CPSR value. */
1640 uint32_t cpsr_read(CPUARMState *env);
1641
1642 typedef enum CPSRWriteType {
1643 CPSRWriteByInstr = 0, /* from guest MSR or CPS */
1644 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1645 CPSRWriteRaw = 2,
1646 /* trust values, no reg bank switch, no hflags rebuild */
1647 CPSRWriteByGDBStub = 3, /* from the GDB stub */
1648 } CPSRWriteType;
1649
1650 /*
1651 * Set the CPSR. Note that some bits of mask must be all-set or all-clear.
1652 * This will do an arm_rebuild_hflags() if any of the bits in @mask
1653 * correspond to TB flags bits cached in the hflags, unless @write_type
1654 * is CPSRWriteRaw.
1655 */
1656 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1657 CPSRWriteType write_type);
1658
1659 /* Return the current xPSR value. */
1660 static inline uint32_t xpsr_read(CPUARMState *env)
1661 {
1662 int ZF;
1663 ZF = (env->ZF == 0);
1664 return (env->NF & 0x80000000) | (ZF << 30)
1665 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1666 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1667 | ((env->condexec_bits & 0xfc) << 8)
1668 | (env->GE << 16)
1669 | env->v7m.exception;
1670 }
1671
1672 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
1673 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1674 {
1675 if (mask & XPSR_NZCV) {
1676 env->ZF = (~val) & XPSR_Z;
1677 env->NF = val;
1678 env->CF = (val >> 29) & 1;
1679 env->VF = (val << 3) & 0x80000000;
1680 }
1681 if (mask & XPSR_Q) {
1682 env->QF = ((val & XPSR_Q) != 0);
1683 }
1684 if (mask & XPSR_GE) {
1685 env->GE = (val & XPSR_GE) >> 16;
1686 }
1687 #ifndef CONFIG_USER_ONLY
1688 if (mask & XPSR_T) {
1689 env->thumb = ((val & XPSR_T) != 0);
1690 }
1691 if (mask & XPSR_IT_0_1) {
1692 env->condexec_bits &= ~3;
1693 env->condexec_bits |= (val >> 25) & 3;
1694 }
1695 if (mask & XPSR_IT_2_7) {
1696 env->condexec_bits &= 3;
1697 env->condexec_bits |= (val >> 8) & 0xfc;
1698 }
1699 if (mask & XPSR_EXCP) {
1700 /* Note that this only happens on exception exit */
1701 write_v7m_exception(env, val & XPSR_EXCP);
1702 }
1703 #endif
1704 }
1705
1706 #define HCR_VM (1ULL << 0)
1707 #define HCR_SWIO (1ULL << 1)
1708 #define HCR_PTW (1ULL << 2)
1709 #define HCR_FMO (1ULL << 3)
1710 #define HCR_IMO (1ULL << 4)
1711 #define HCR_AMO (1ULL << 5)
1712 #define HCR_VF (1ULL << 6)
1713 #define HCR_VI (1ULL << 7)
1714 #define HCR_VSE (1ULL << 8)
1715 #define HCR_FB (1ULL << 9)
1716 #define HCR_BSU_MASK (3ULL << 10)
1717 #define HCR_DC (1ULL << 12)
1718 #define HCR_TWI (1ULL << 13)
1719 #define HCR_TWE (1ULL << 14)
1720 #define HCR_TID0 (1ULL << 15)
1721 #define HCR_TID1 (1ULL << 16)
1722 #define HCR_TID2 (1ULL << 17)
1723 #define HCR_TID3 (1ULL << 18)
1724 #define HCR_TSC (1ULL << 19)
1725 #define HCR_TIDCP (1ULL << 20)
1726 #define HCR_TACR (1ULL << 21)
1727 #define HCR_TSW (1ULL << 22)
1728 #define HCR_TPCP (1ULL << 23)
1729 #define HCR_TPU (1ULL << 24)
1730 #define HCR_TTLB (1ULL << 25)
1731 #define HCR_TVM (1ULL << 26)
1732 #define HCR_TGE (1ULL << 27)
1733 #define HCR_TDZ (1ULL << 28)
1734 #define HCR_HCD (1ULL << 29)
1735 #define HCR_TRVM (1ULL << 30)
1736 #define HCR_RW (1ULL << 31)
1737 #define HCR_CD (1ULL << 32)
1738 #define HCR_ID (1ULL << 33)
1739 #define HCR_E2H (1ULL << 34)
1740 #define HCR_TLOR (1ULL << 35)
1741 #define HCR_TERR (1ULL << 36)
1742 #define HCR_TEA (1ULL << 37)
1743 #define HCR_MIOCNCE (1ULL << 38)
1744 #define HCR_TME (1ULL << 39)
1745 #define HCR_APK (1ULL << 40)
1746 #define HCR_API (1ULL << 41)
1747 #define HCR_NV (1ULL << 42)
1748 #define HCR_NV1 (1ULL << 43)
1749 #define HCR_AT (1ULL << 44)
1750 #define HCR_NV2 (1ULL << 45)
1751 #define HCR_FWB (1ULL << 46)
1752 #define HCR_FIEN (1ULL << 47)
1753 #define HCR_GPF (1ULL << 48)
1754 #define HCR_TID4 (1ULL << 49)
1755 #define HCR_TICAB (1ULL << 50)
1756 #define HCR_AMVOFFEN (1ULL << 51)
1757 #define HCR_TOCU (1ULL << 52)
1758 #define HCR_ENSCXT (1ULL << 53)
1759 #define HCR_TTLBIS (1ULL << 54)
1760 #define HCR_TTLBOS (1ULL << 55)
1761 #define HCR_ATA (1ULL << 56)
1762 #define HCR_DCT (1ULL << 57)
1763 #define HCR_TID5 (1ULL << 58)
1764 #define HCR_TWEDEN (1ULL << 59)
1765 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1766
1767 #define SCR_NS (1ULL << 0)
1768 #define SCR_IRQ (1ULL << 1)
1769 #define SCR_FIQ (1ULL << 2)
1770 #define SCR_EA (1ULL << 3)
1771 #define SCR_FW (1ULL << 4)
1772 #define SCR_AW (1ULL << 5)
1773 #define SCR_NET (1ULL << 6)
1774 #define SCR_SMD (1ULL << 7)
1775 #define SCR_HCE (1ULL << 8)
1776 #define SCR_SIF (1ULL << 9)
1777 #define SCR_RW (1ULL << 10)
1778 #define SCR_ST (1ULL << 11)
1779 #define SCR_TWI (1ULL << 12)
1780 #define SCR_TWE (1ULL << 13)
1781 #define SCR_TLOR (1ULL << 14)
1782 #define SCR_TERR (1ULL << 15)
1783 #define SCR_APK (1ULL << 16)
1784 #define SCR_API (1ULL << 17)
1785 #define SCR_EEL2 (1ULL << 18)
1786 #define SCR_EASE (1ULL << 19)
1787 #define SCR_NMEA (1ULL << 20)
1788 #define SCR_FIEN (1ULL << 21)
1789 #define SCR_ENSCXT (1ULL << 25)
1790 #define SCR_ATA (1ULL << 26)
1791 #define SCR_FGTEN (1ULL << 27)
1792 #define SCR_ECVEN (1ULL << 28)
1793 #define SCR_TWEDEN (1ULL << 29)
1794 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4)
1795 #define SCR_TME (1ULL << 34)
1796 #define SCR_AMVOFFEN (1ULL << 35)
1797 #define SCR_ENAS0 (1ULL << 36)
1798 #define SCR_ADEN (1ULL << 37)
1799 #define SCR_HXEN (1ULL << 38)
1800 #define SCR_GCSEN (1ULL << 39)
1801 #define SCR_TRNDR (1ULL << 40)
1802 #define SCR_ENTP2 (1ULL << 41)
1803 #define SCR_TCR2EN (1ULL << 43)
1804 #define SCR_SCTLR2EN (1ULL << 44)
1805 #define SCR_PIEN (1ULL << 45)
1806 #define SCR_AIEN (1ULL << 46)
1807 #define SCR_GPF (1ULL << 48)
1808 #define SCR_MECEN (1ULL << 49)
1809 #define SCR_ENFPM (1ULL << 50)
1810 #define SCR_TMEA (1ULL << 51)
1811 #define SCR_TWERR (1ULL << 52)
1812 #define SCR_PFAREN (1ULL << 53)
1813 #define SCR_SRMASKEN (1ULL << 54)
1814 #define SCR_ENIDCP128 (1ULL << 55)
1815 #define SCR_DSE (1ULL << 57)
1816 #define SCR_ENDSE (1ULL << 58)
1817 #define SCR_FGTEN2 (1ULL << 59)
1818 #define SCR_HDBSSEN (1ULL << 60)
1819 #define SCR_HACDBSEN (1ULL << 61)
1820 #define SCR_NSE (1ULL << 62)
1821
1822 /* GCSCR_ELx fields */
1823 #define GCSCR_PCRSEL (1ULL << 0)
1824 #define GCSCR_RVCHKEN (1ULL << 5)
1825 #define GCSCR_EXLOCKEN (1ULL << 6)
1826 #define GCSCR_PUSHMEN (1ULL << 8)
1827 #define GCSCR_STREN (1ULL << 9)
1828 #define GCSCRE0_NTR (1ULL << 10)
1829
1830 /* Return the current FPSCR value. */
1831 uint32_t vfp_get_fpscr(CPUARMState *env);
1832 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1833
1834 /*
1835 * FPCR, Floating Point Control Register
1836 * FPSR, Floating Point Status Register
1837 *
1838 * For A64 floating point control and status bits are stored in
1839 * two logically distinct registers, FPCR and FPSR. We store these
1840 * in QEMU in vfp.fpcr and vfp.fpsr.
1841 * For A32 there was only one register, FPSCR. The bits are arranged
1842 * such that FPSCR bits map to FPCR or FPSR bits in the same bit positions,
1843 * so we can use appropriate masking to handle FPSCR reads and writes.
1844 * Note that the FPCR has some bits which are not visible in the
1845 * AArch32 view (for FEAT_AFP). Writing the FPSCR leaves these unchanged.
1846 */
1847
1848 /* FPCR bits */
1849 #define FPCR_FIZ (1 << 0) /* Flush Inputs to Zero (FEAT_AFP) */
1850 #define FPCR_AH (1 << 1) /* Alternate Handling (FEAT_AFP) */
1851 #define FPCR_NEP (1 << 2) /* SIMD scalar ops preserve elts (FEAT_AFP) */
1852 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
1853 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */
1854 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */
1855 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */
1856 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
1857 #define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */
1858 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
1859 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */
1860 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1861 #define FPCR_STRIDE_MASK (3 << 20) /* Stride */
1862 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
1863 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1864 #define FPCR_DN (1 << 25) /* Default NaN enable bit */
1865 #define FPCR_AHP (1 << 26) /* Alternative half-precision */
1866
1867 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
1868 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
1869 #define FPCR_LTPSIZE_LENGTH 3
1870
1871 /* Cumulative exception trap enable bits */
1872 #define FPCR_EEXC_MASK (FPCR_IOE | FPCR_DZE | FPCR_OFE | FPCR_UFE | FPCR_IXE | FPCR_IDE)
1873
1874 /* FPSR bits */
1875 #define FPSR_IOC (1 << 0) /* Invalid Operation cumulative exception */
1876 #define FPSR_DZC (1 << 1) /* Divide by Zero cumulative exception */
1877 #define FPSR_OFC (1 << 2) /* Overflow cumulative exception */
1878 #define FPSR_UFC (1 << 3) /* Underflow cumulative exception */
1879 #define FPSR_IXC (1 << 4) /* Inexact cumulative exception */
1880 #define FPSR_IDC (1 << 7) /* Input Denormal cumulative exception */
1881 #define FPSR_QC (1 << 27) /* Cumulative saturation bit */
1882 #define FPSR_V (1 << 28) /* FP overflow flag */
1883 #define FPSR_C (1 << 29) /* FP carry flag */
1884 #define FPSR_Z (1 << 30) /* FP zero flag */
1885 #define FPSR_N (1 << 31) /* FP negative flag */
1886
1887 /* Cumulative exception status bits */
1888 #define FPSR_CEXC_MASK (FPSR_IOC | FPSR_DZC | FPSR_OFC | FPSR_UFC | FPSR_IXC | FPSR_IDC)
1889
1890 #define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V)
1891 #define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC)
1892
1893 /* A32 FPSCR bits which architecturally map to FPSR bits */
1894 #define FPSCR_FPSR_MASK (FPSR_NZCVQC_MASK | FPSR_CEXC_MASK)
1895 /* A32 FPSCR bits which architecturally map to FPCR bits */
1896 #define FPSCR_FPCR_MASK (FPCR_EEXC_MASK | FPCR_LEN_MASK | FPCR_FZ16 | \
1897 FPCR_STRIDE_MASK | FPCR_RMODE_MASK | \
1898 FPCR_FZ | FPCR_DN | FPCR_AHP)
1899 /* These masks don't overlap: each bit lives in only one place */
1900 QEMU_BUILD_BUG_ON(FPSCR_FPSR_MASK & FPSCR_FPCR_MASK);
1901
1902 /**
1903 * vfp_get_fpsr: read the AArch64 FPSR
1904 * @env: CPU context
1905 *
1906 * Return the current AArch64 FPSR value
1907 */
1908 uint32_t vfp_get_fpsr(CPUARMState *env);
1909
1910 /**
1911 * vfp_get_fpcr: read the AArch64 FPCR
1912 * @env: CPU context
1913 *
1914 * Return the current AArch64 FPCR value
1915 */
1916 uint32_t vfp_get_fpcr(CPUARMState *env);
1917
1918 /**
1919 * vfp_set_fpsr: write the AArch64 FPSR
1920 * @env: CPU context
1921 * @value: new value
1922 */
1923 void vfp_set_fpsr(CPUARMState *env, uint32_t value);
1924
1925 /**
1926 * vfp_set_fpcr: write the AArch64 FPCR
1927 * @env: CPU context
1928 * @value: new value
1929 */
1930 void vfp_set_fpcr(CPUARMState *env, uint32_t value);
1931
1932 enum arm_cpu_mode {
1933 ARM_CPU_MODE_USR = 0x10,
1934 ARM_CPU_MODE_FIQ = 0x11,
1935 ARM_CPU_MODE_IRQ = 0x12,
1936 ARM_CPU_MODE_SVC = 0x13,
1937 ARM_CPU_MODE_MON = 0x16,
1938 ARM_CPU_MODE_ABT = 0x17,
1939 ARM_CPU_MODE_HYP = 0x1a,
1940 ARM_CPU_MODE_UND = 0x1b,
1941 ARM_CPU_MODE_SYS = 0x1f
1942 };
1943
1944 /* VFP system registers. */
1945 #define ARM_VFP_FPSID 0
1946 #define ARM_VFP_FPSCR 1
1947 #define ARM_VFP_MVFR2 5
1948 #define ARM_VFP_MVFR1 6
1949 #define ARM_VFP_MVFR0 7
1950 #define ARM_VFP_FPEXC 8
1951 #define ARM_VFP_FPINST 9
1952 #define ARM_VFP_FPINST2 10
1953 /* These ones are M-profile only */
1954 #define ARM_VFP_FPSCR_NZCVQC 2
1955 #define ARM_VFP_VPR 12
1956 #define ARM_VFP_P0 13
1957 #define ARM_VFP_FPCXT_NS 14
1958 #define ARM_VFP_FPCXT_S 15
1959
1960 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
1961 #define QEMU_VFP_FPSCR_NZCV 0xffff
1962
1963 /* V7M CCR bits */
1964 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1965 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1966 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1967 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1968 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1969 FIELD(V7M_CCR, STKALIGN, 9, 1)
1970 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1971 FIELD(V7M_CCR, DC, 16, 1)
1972 FIELD(V7M_CCR, IC, 17, 1)
1973 FIELD(V7M_CCR, BP, 18, 1)
1974 FIELD(V7M_CCR, LOB, 19, 1)
1975 FIELD(V7M_CCR, TRD, 20, 1)
1976
1977 /* V7M SCR bits */
1978 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1979 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1980 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1981 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1982
1983 /* V7M AIRCR bits */
1984 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1985 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1986 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1987 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1988 FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1989 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1990 FIELD(V7M_AIRCR, PRIS, 14, 1)
1991 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1992 FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1993
1994 /* V7M CFSR bits for MMFSR */
1995 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1996 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1997 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1998 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1999 FIELD(V7M_CFSR, MLSPERR, 5, 1)
2000 FIELD(V7M_CFSR, MMARVALID, 7, 1)
2001
2002 /* V7M CFSR bits for BFSR */
2003 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
2004 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
2005 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
2006 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
2007 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
2008 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
2009 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
2010
2011 /* V7M CFSR bits for UFSR */
2012 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
2013 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
2014 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
2015 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
2016 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
2017 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
2018 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
2019
2020 /* V7M CFSR bit masks covering all of the subregister bits */
2021 FIELD(V7M_CFSR, MMFSR, 0, 8)
2022 FIELD(V7M_CFSR, BFSR, 8, 8)
2023 FIELD(V7M_CFSR, UFSR, 16, 16)
2024
2025 /* V7M HFSR bits */
2026 FIELD(V7M_HFSR, VECTTBL, 1, 1)
2027 FIELD(V7M_HFSR, FORCED, 30, 1)
2028 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
2029
2030 /* V7M DFSR bits */
2031 FIELD(V7M_DFSR, HALTED, 0, 1)
2032 FIELD(V7M_DFSR, BKPT, 1, 1)
2033 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
2034 FIELD(V7M_DFSR, VCATCH, 3, 1)
2035 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
2036
2037 /* V7M SFSR bits */
2038 FIELD(V7M_SFSR, INVEP, 0, 1)
2039 FIELD(V7M_SFSR, INVIS, 1, 1)
2040 FIELD(V7M_SFSR, INVER, 2, 1)
2041 FIELD(V7M_SFSR, AUVIOL, 3, 1)
2042 FIELD(V7M_SFSR, INVTRAN, 4, 1)
2043 FIELD(V7M_SFSR, LSPERR, 5, 1)
2044 FIELD(V7M_SFSR, SFARVALID, 6, 1)
2045 FIELD(V7M_SFSR, LSERR, 7, 1)
2046
2047 /* v7M MPU_CTRL bits */
2048 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
2049 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
2050 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
2051
2052 /* v7M CLIDR bits */
2053 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
2054 FIELD(V7M_CLIDR, LOUIS, 21, 3)
2055 FIELD(V7M_CLIDR, LOC, 24, 3)
2056 FIELD(V7M_CLIDR, LOUU, 27, 3)
2057 FIELD(V7M_CLIDR, ICB, 30, 2)
2058
2059 FIELD(V7M_CSSELR, IND, 0, 1)
2060 FIELD(V7M_CSSELR, LEVEL, 1, 3)
2061 /* We use the combination of InD and Level to index into cpu->ccsidr[];
2062 * define a mask for this and check that it doesn't permit running off
2063 * the end of the array.
2064 */
2065 FIELD(V7M_CSSELR, INDEX, 0, 4)
2066
2067 /* v7M FPCCR bits */
2068 FIELD(V7M_FPCCR, LSPACT, 0, 1)
2069 FIELD(V7M_FPCCR, USER, 1, 1)
2070 FIELD(V7M_FPCCR, S, 2, 1)
2071 FIELD(V7M_FPCCR, THREAD, 3, 1)
2072 FIELD(V7M_FPCCR, HFRDY, 4, 1)
2073 FIELD(V7M_FPCCR, MMRDY, 5, 1)
2074 FIELD(V7M_FPCCR, BFRDY, 6, 1)
2075 FIELD(V7M_FPCCR, SFRDY, 7, 1)
2076 FIELD(V7M_FPCCR, MONRDY, 8, 1)
2077 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
2078 FIELD(V7M_FPCCR, UFRDY, 10, 1)
2079 FIELD(V7M_FPCCR, RES0, 11, 15)
2080 FIELD(V7M_FPCCR, TS, 26, 1)
2081 FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
2082 FIELD(V7M_FPCCR, CLRONRET, 28, 1)
2083 FIELD(V7M_FPCCR, LSPENS, 29, 1)
2084 FIELD(V7M_FPCCR, LSPEN, 30, 1)
2085 FIELD(V7M_FPCCR, ASPEN, 31, 1)
2086 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
2087 #define R_V7M_FPCCR_BANKED_MASK \
2088 (R_V7M_FPCCR_LSPACT_MASK | \
2089 R_V7M_FPCCR_USER_MASK | \
2090 R_V7M_FPCCR_THREAD_MASK | \
2091 R_V7M_FPCCR_MMRDY_MASK | \
2092 R_V7M_FPCCR_SPLIMVIOL_MASK | \
2093 R_V7M_FPCCR_UFRDY_MASK | \
2094 R_V7M_FPCCR_ASPEN_MASK)
2095
2096 /* v7M VPR bits */
2097 FIELD(V7M_VPR, P0, 0, 16)
2098 FIELD(V7M_VPR, MASK01, 16, 4)
2099 FIELD(V7M_VPR, MASK23, 20, 4)
2100
2101 FIELD(GPCCR, PPS, 0, 3)
2102 FIELD(GPCCR, RLPAD, 5, 1)
2103 FIELD(GPCCR, NSPAD, 6, 1)
2104 FIELD(GPCCR, SPAD, 7, 1)
2105 FIELD(GPCCR, IRGN, 8, 2)
2106 FIELD(GPCCR, ORGN, 10, 2)
2107 FIELD(GPCCR, SH, 12, 2)
2108 FIELD(GPCCR, PGS, 14, 2)
2109 FIELD(GPCCR, GPC, 16, 1)
2110 FIELD(GPCCR, GPCP, 17, 1)
2111 FIELD(GPCCR, TBGPCD, 18, 1)
2112 FIELD(GPCCR, NSO, 19, 1)
2113 FIELD(GPCCR, L0GPTSZ, 20, 4)
2114 FIELD(GPCCR, APPSAA, 24, 1)
2115 FIELD(GPCCR, SA, 25, 1)
2116 FIELD(GPCCR, NSP, 26, 1)
2117 FIELD(GPCCR, NA6, 27, 1)
2118 FIELD(GPCCR, NA7, 28, 1)
2119 FIELD(GPCCR, GPCBW, 29, 1)
2120
2121 FIELD(GPCBW, BWSIZE, 37, 2)
2122 FIELD(GPCBW, BWSTRIDE, 32, 5)
2123 FIELD(GPCBW, BWADDR, 0, 25)
2124
2125 FIELD(MFAR, FPA, 12, 40)
2126 FIELD(MFAR, NSE, 62, 1)
2127 FIELD(MFAR, NS, 63, 1)
2128
2129 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2130
2131 /* If adding a feature bit which corresponds to a Linux ELF
2132 * HWCAP bit, remember to update the feature-bit-to-hwcap
2133 * mapping in linux-user/elfload.c:get_elf_hwcap().
2134 */
2135 enum arm_features {
2136 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
2137 ARM_FEATURE_V6,
2138 ARM_FEATURE_V6K,
2139 ARM_FEATURE_V7,
2140 ARM_FEATURE_THUMB2,
2141 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
2142 ARM_FEATURE_NEON,
2143 ARM_FEATURE_M, /* Microcontroller profile. */
2144 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
2145 ARM_FEATURE_THUMB2EE,
2146 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
2147 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
2148 ARM_FEATURE_V4T,
2149 ARM_FEATURE_V5,
2150 ARM_FEATURE_STRONGARM,
2151 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
2152 ARM_FEATURE_GENERIC_TIMER,
2153 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
2154 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
2155 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
2156 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
2157 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
2158 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
2159 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
2160 ARM_FEATURE_V8,
2161 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
2162 ARM_FEATURE_CBAR, /* has cp15 CBAR */
2163 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
2164 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
2165 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
2166 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
2167 ARM_FEATURE_PMU, /* has PMU support */
2168 ARM_FEATURE_VBAR, /* has cp15 VBAR */
2169 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
2170 ARM_FEATURE_M_MAIN, /* M profile Main Extension */
2171 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
2172 /*
2173 * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
2174 * if the board doesn't set a value, instead of 1GHz. It is for backwards
2175 * compatibility and used only with CPU definitions that were already
2176 * in QEMU before we changed the default. It should not be set on any
2177 * CPU types added in future.
2178 */
2179 ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
2180 /*
2181 * ARM_FEATURE_NEON_TRAPS should be set if the CPU implements the
2182 * CPACR.ASEDIS and HCPTR.TASE bits for trapping A32 Neon. This
2183 * is architecturally IMPDEF, but seems to be implemented by all
2184 * ARM_FEATURE_NEON CPUs except the Cortex-A8.
2185 */
2186 ARM_FEATURE_NEON_TRAPS,
2187 /* Does the CPU implement CPACR.D32DIS ? */
2188 ARM_FEATURE_D32DIS,
2189 };
2190
2191 static inline int arm_feature(const CPUARMState *env, int feature)
2192 {
2193 return (env->features & (1ULL << feature)) != 0;
2194 }
2195
2196 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
2197
2198
2199 #if !defined(CONFIG_USER_ONLY)
2200 /**
2201 * arm_security_space_below_el3:
2202 * @env: cpu context
2203 *
2204 * Return the security space of exception levels below EL3, following
2205 * an exception return to those levels. Unlike arm_security_space,
2206 * this doesn't care about the current EL.
2207 */
2208 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env);
2209
2210 /**
2211 * arm_is_secure_below_el3:
2212 * @env: cpu context
2213 *
2214 * Return true if exception levels below EL3 are in secure state,
2215 * or would be following an exception return to those levels.
2216 */
2217 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2218 {
2219 ARMSecuritySpace ss = arm_security_space_below_el3(env);
2220 return ss == ARMSS_Secure;
2221 }
2222
2223 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
2224 static inline bool arm_is_el3_or_mon(CPUARMState *env)
2225 {
2226 assert(!arm_feature(env, ARM_FEATURE_M));
2227 if (arm_feature(env, ARM_FEATURE_EL3)) {
2228 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2229 /* CPU currently in AArch64 state and EL3 */
2230 return true;
2231 } else if (!is_a64(env) &&
2232 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2233 /* CPU currently in AArch32 state and monitor mode */
2234 return true;
2235 }
2236 }
2237 return false;
2238 }
2239
2240 /**
2241 * arm_security_space:
2242 * @env: cpu context
2243 *
2244 * Return the current security space of the cpu.
2245 */
2246 ARMSecuritySpace arm_security_space(CPUARMState *env);
2247
2248 /**
2249 * arm_is_secure:
2250 * @env: cpu context
2251 *
2252 * Return true if the processor is in secure state.
2253 */
2254 static inline bool arm_is_secure(CPUARMState *env)
2255 {
2256 return arm_space_is_secure(arm_security_space(env));
2257 }
2258
2259 /*
2260 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
2261 * This corresponds to the pseudocode EL2Enabled().
2262 */
2263 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
2264 ARMSecuritySpace space)
2265 {
2266 assert(space != ARMSS_Root);
2267 return arm_feature(env, ARM_FEATURE_EL2)
2268 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2));
2269 }
2270
2271 static inline bool arm_is_el2_enabled(CPUARMState *env)
2272 {
2273 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env));
2274 }
2275
2276 #else
2277 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env)
2278 {
2279 return ARMSS_NonSecure;
2280 }
2281
2282 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2283 {
2284 return false;
2285 }
2286
2287 static inline bool arm_is_el3_or_mon(CPUARMState *env)
2288 {
2289 return false;
2290 }
2291
2292 static inline ARMSecuritySpace arm_security_space(CPUARMState *env)
2293 {
2294 return ARMSS_NonSecure;
2295 }
2296
2297 static inline bool arm_is_secure(CPUARMState *env)
2298 {
2299 return false;
2300 }
2301
2302 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
2303 ARMSecuritySpace space)
2304 {
2305 return false;
2306 }
2307
2308 static inline bool arm_is_el2_enabled(CPUARMState *env)
2309 {
2310 return false;
2311 }
2312 #endif
2313
2314 /**
2315 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
2316 * E.g. when in secure state, fields in HCR_EL2 are suppressed,
2317 * "for all purposes other than a direct read or write access of HCR_EL2."
2318 * Not included here is HCR_RW.
2319 */
2320 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space);
2321 uint64_t arm_hcr_el2_eff(CPUARMState *env);
2322 uint64_t arm_hcr_el2_nvx_eff(CPUARMState *env);
2323 uint64_t arm_hcrx_el2_eff(CPUARMState *env);
2324
2325 /*
2326 * Function for determining whether guest cp register reads and writes should
2327 * access the secure or non-secure bank of a cp register. When EL3 is
2328 * operating in AArch32 state, the NS-bit determines whether the secure
2329 * instance of a cp register should be used. When EL3 is AArch64 (or if
2330 * it doesn't exist at all) then there is no register banking, and all
2331 * accesses are to the non-secure version.
2332 */
2333 bool access_secure_reg(CPUARMState *env);
2334
2335 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2336 uint32_t cur_el, bool secure);
2337
2338 /* Return the highest implemented Exception Level */
2339 static inline int arm_highest_el(CPUARMState *env)
2340 {
2341 if (arm_feature(env, ARM_FEATURE_EL3)) {
2342 return 3;
2343 }
2344 if (arm_feature(env, ARM_FEATURE_EL2)) {
2345 return 2;
2346 }
2347 return 1;
2348 }
2349
2350 /* Return true if a v7M CPU is in Handler mode */
2351 static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2352 {
2353 return env->v7m.exception != 0;
2354 }
2355
2356 /**
2357 * write_list_to_cpustate
2358 * @cpu: ARMCPU
2359 *
2360 * For each register listed in the ARMCPU cpreg_indexes list, write
2361 * its value from the cpreg_values list into the ARMCPUState structure.
2362 * This updates TCG's working data structures from KVM data or
2363 * from incoming migration state.
2364 *
2365 * Returns: true if all register values were updated correctly,
2366 * false if some register was unknown or could not be written.
2367 * Note that we do not stop early on failure -- we will attempt
2368 * writing all registers in the list.
2369 */
2370 bool write_list_to_cpustate(ARMCPU *cpu);
2371
2372 /**
2373 * write_cpustate_to_list:
2374 * @cpu: ARMCPU
2375 * @kvm_sync: true if this is for syncing back to KVM
2376 *
2377 * For each register listed in the ARMCPU cpreg_indexes list, write
2378 * its value from the ARMCPUState structure into the cpreg_values list.
2379 * This is used to copy info from TCG's working data structures into
2380 * KVM or for outbound migration.
2381 *
2382 * @kvm_sync is true if we are doing this in order to sync the
2383 * register state back to KVM. In this case we will only update
2384 * values in the list if the previous list->cpustate sync actually
2385 * successfully wrote the CPU state. Otherwise we will keep the value
2386 * that is in the list.
2387 *
2388 * Returns: true if all register values were read correctly,
2389 * false if some register was unknown or could not be read.
2390 * Note that we do not stop early on failure -- we will attempt
2391 * reading all registers in the list.
2392 */
2393 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2394
2395 #define ARM_CPUID_TI915T 0x54029152
2396 #define ARM_CPUID_TI925T 0x54029252
2397
2398 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2399
2400 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
2401
2402 /* Indexes used when registering address spaces with cpu_address_space_init */
2403 typedef enum ARMASIdx {
2404 ARMASIdx_NS = 0,
2405 ARMASIdx_S = 1,
2406 ARMASIdx_TagNS = 2,
2407 ARMASIdx_TagS = 3,
2408 ARMASIdx_MAX = ARMASIdx_TagS
2409 } ARMASIdx;
2410
2411 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space)
2412 {
2413 /* Assert the relative order of the physical mmu indexes. */
2414 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0);
2415 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure);
2416 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root);
2417 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm);
2418
2419 return ARMMMUIdx_Phys_S + space;
2420 }
2421
2422 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx)
2423 {
2424 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm);
2425 return idx - ARMMMUIdx_Phys_S;
2426 }
2427
2428 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
2429 {
2430 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
2431 * CSSELR is RAZ/WI.
2432 */
2433 return (GET_IDREG(&cpu->isar, CLIDR) & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
2434 }
2435
2436 static inline bool arm_sctlr_b(const CPUARMState *env)
2437 {
2438 return
2439 /* We need not implement SCTLR.ITD in user-mode emulation, so
2440 * let linux-user ignore the fact that it conflicts with SCTLR_B.
2441 * This lets people run BE32 binaries with "-cpu any".
2442 */
2443 #ifndef CONFIG_USER_ONLY
2444 !arm_feature(env, ARM_FEATURE_V7) &&
2445 #endif
2446 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
2447 }
2448
2449 uint64_t arm_sctlr(CPUARMState *env, int el);
2450
2451 /*
2452 * We have more than 32-bits worth of state per TB, so we split the data
2453 * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
2454 * We collect these two parts in CPUARMTBFlags where they are named
2455 * flags and flags2 respectively.
2456 *
2457 * The flags that are shared between all execution modes, TBFLAG_ANY, are stored
2458 * in flags. The flags that are specific to a given mode are stored in flags2.
2459 * flags2 always has 64-bits, even though only 32-bits are used for A32 and M32.
2460 *
2461 * The bits for 32-bit A-profile and M-profile partially overlap:
2462 *
2463 * 31 23 11 10 0
2464 * +-------------+----------+----------------+
2465 * | | | TBFLAG_A32 |
2466 * | TBFLAG_AM32 | +-----+----------+
2467 * | | |TBFLAG_M32|
2468 * +-------------+----------------+----------+
2469 * 31 23 6 5 0
2470 *
2471 * Unless otherwise noted, these bits are cached in env->hflags.
2472 */
2473 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
2474 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
2475 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */
2476 FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
2477 FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
2478 /* Target EL if we take a floating-point-disabled exception */
2479 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
2480 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
2481 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
2482 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
2483 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
2484 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
2485
2486 /*
2487 * Bit usage when in AArch32 state, both A- and M-profile.
2488 */
2489 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */
2490 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */
2491
2492 /*
2493 * Bit usage when in AArch32 state, for A-profile only.
2494 */
2495 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */
2496 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */
2497 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */
2498 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */
2499 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
2500 /*
2501 * Indicates whether cp register reads and writes by guest code should access
2502 * the secure or nonsecure bank of banked registers; note that this is not
2503 * the same thing as the current security state of the processor!
2504 */
2505 FIELD(TBFLAG_A32, NS, 10, 1)
2506 /*
2507 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not.
2508 * This requires an SME trap from AArch32 mode when using NEON.
2509 */
2510 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
2511 /*
2512 * Target EL for a Neon-disabled exception via CPACR.ASEDIS, HCPTR.TASE.
2513 * If FPEXC_EL indicates a trap to a lower EL than this, that will
2514 * take precedence.
2515 */
2516 FIELD(TBFLAG_A32, NEONEXC_EL, 12, 2)
2517 /* Should VFP insns touching D16..D31 UNDEF? (CPACR.D32DIS) */
2518 FIELD(TBFLAG_A32, D32DIS, 14, 1)
2519
2520 /*
2521 * Bit usage when in AArch32 state, for M-profile only.
2522 */
2523 /* Handler (ie not Thread) mode */
2524 FIELD(TBFLAG_M32, HANDLER, 0, 1)
2525 /* Whether we should generate stack-limit checks */
2526 FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
2527 /* Set if FPCCR.LSPACT is set */
2528 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */
2529 /* Set if we must create a new FP context */
2530 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */
2531 /* Set if FPCCR.S does not match current security state */
2532 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */
2533 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */
2534 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */
2535 /* Set if in secure mode */
2536 FIELD(TBFLAG_M32, SECURE, 6, 1)
2537
2538 /*
2539 * Bit usage when in AArch64 state
2540 */
2541 FIELD(TBFLAG_A64, TBII, 0, 2)
2542 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
2543 /* The current vector length, either NVL or SVL. */
2544 FIELD(TBFLAG_A64, VL, 4, 4)
2545 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
2546 FIELD(TBFLAG_A64, BT, 9, 1)
2547 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */
2548 FIELD(TBFLAG_A64, TBID, 12, 2)
2549 FIELD(TBFLAG_A64, UNPRIV, 14, 1)
2550 FIELD(TBFLAG_A64, ATA, 15, 1)
2551 FIELD(TBFLAG_A64, TCMA, 16, 2)
2552 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
2553 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
2554 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
2555 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
2556 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
2557 FIELD(TBFLAG_A64, SVL, 24, 4)
2558 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
2559 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
2560 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1)
2561 FIELD(TBFLAG_A64, NAA, 30, 1)
2562 FIELD(TBFLAG_A64, ATA0, 31, 1)
2563 FIELD(TBFLAG_A64, NV, 32, 1)
2564 FIELD(TBFLAG_A64, NV1, 33, 1)
2565 FIELD(TBFLAG_A64, NV2, 34, 1)
2566 FIELD(TBFLAG_A64, E2H, 35, 1)
2567 /* Set if FEAT_NV2 RAM accesses are big-endian */
2568 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1)
2569 FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */
2570 FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */
2571 FIELD(TBFLAG_A64, ZT0EXC_EL, 39, 2)
2572 FIELD(TBFLAG_A64, GCS_EN, 41, 1)
2573 FIELD(TBFLAG_A64, GCS_RVCEN, 42, 1)
2574 FIELD(TBFLAG_A64, GCSSTR_EL, 43, 2)
2575 FIELD(TBFLAG_A64, FPMR_EL, 45, 2)
2576 FIELD(TBFLAG_A64, MTE_STORE_ONLY, 47, 1)
2577 FIELD(TBFLAG_A64, MTE0_STORE_ONLY, 48, 1)
2578 FIELD(TBFLAG_A64, MTX, 49, 2)
2579
2580 /*
2581 * Helpers for using the above. Note that only the A64 accessors use
2582 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags
2583 * word either is or might be 32 bits only.
2584 */
2585 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \
2586 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
2587 #define DP_TBFLAG_A64(DST, WHICH, VAL) \
2588 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL))
2589 #define DP_TBFLAG_A32(DST, WHICH, VAL) \
2590 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
2591 #define DP_TBFLAG_M32(DST, WHICH, VAL) \
2592 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
2593 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \
2594 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
2595
2596 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
2597 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH)
2598 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
2599 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
2600 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
2601
2602 /**
2603 * sve_vq
2604 * @env: the cpu context
2605 *
2606 * Return the VL cached within env->hflags, in units of quadwords.
2607 */
2608 static inline int sve_vq(CPUARMState *env)
2609 {
2610 return EX_TBFLAG_A64(env->hflags, VL) + 1;
2611 }
2612
2613 /**
2614 * sme_vq
2615 * @env: the cpu context
2616 *
2617 * Return the SVL cached within env->hflags, in units of quadwords.
2618 */
2619 static inline int sme_vq(CPUARMState *env)
2620 {
2621 return EX_TBFLAG_A64(env->hflags, SVL) + 1;
2622 }
2623
2624 static inline bool bswap_code(bool sctlr_b)
2625 {
2626 #ifdef CONFIG_USER_ONLY
2627 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian.
2628 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0
2629 * would also end up as a mixed-endian mode with BE code, LE data.
2630 */
2631 return TARGET_BIG_ENDIAN ^ sctlr_b;
2632 #else
2633 /* All code access in ARM is little endian, and there are no loaders
2634 * doing swaps that need to be reversed
2635 */
2636 return 0;
2637 #endif
2638 }
2639
2640 enum {
2641 QEMU_PSCI_CONDUIT_DISABLED = 0,
2642 QEMU_PSCI_CONDUIT_SMC = 1,
2643 QEMU_PSCI_CONDUIT_HVC = 2,
2644 };
2645
2646 #ifndef CONFIG_USER_ONLY
2647 /* Return the address space index to use for a memory access */
2648 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2649 {
2650 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
2651 }
2652
2653 /* Return the AddressSpace to use for a memory access
2654 * (which depends on whether the access is S or NS, and whether
2655 * the board gave us a separate AddressSpace for S accesses).
2656 */
2657 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
2658 {
2659 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
2660 }
2661 #endif
2662
2663 /**
2664 * arm_register_pre_el_change_hook:
2665 * Register a hook function which will be called immediately before this
2666 * CPU changes exception level or mode. The hook function will be
2667 * passed a pointer to the ARMCPU and the opaque data pointer passed
2668 * to this function when the hook was registered.
2669 *
2670 * Note that if a pre-change hook is called, any registered post-change hooks
2671 * are guaranteed to subsequently be called.
2672 */
2673 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
2674 void *opaque);
2675 /**
2676 * arm_register_el_change_hook:
2677 * Register a hook function which will be called immediately after this
2678 * CPU changes exception level or mode. The hook function will be
2679 * passed a pointer to the ARMCPU and the opaque data pointer passed
2680 * to this function when the hook was registered.
2681 *
2682 * Note that any registered hooks registered here are guaranteed to be called
2683 * if pre-change hooks have been.
2684 */
2685 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
2686 *opaque);
2687
2688 /**
2689 * arm_rebuild_hflags:
2690 * Rebuild the cached TBFLAGS for arbitrary changed processor state.
2691 */
2692 void arm_rebuild_hflags(CPUARMState *env);
2693
2694 /**
2695 * aa32_vfp_dreg:
2696 * Return a pointer to the Dn register within env in 32-bit mode.
2697 */
2698 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
2699 {
2700 return &env->vfp.zregs[regno >> 1].d[regno & 1];
2701 }
2702
2703 /**
2704 * aa32_vfp_qreg:
2705 * Return a pointer to the Qn register within env in 32-bit mode.
2706 */
2707 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
2708 {
2709 return &env->vfp.zregs[regno].d[0];
2710 }
2711
2712 /**
2713 * aa64_vfp_qreg:
2714 * Return a pointer to the Qn register within env in 64-bit mode.
2715 */
2716 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
2717 {
2718 return &env->vfp.zregs[regno].d[0];
2719 }
2720
2721 /* Shared between translate-sve.c and sve_helper.c. */
2722 extern const uint64_t pred_esz_masks[5];
2723
2724 /*
2725 * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
2726 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect
2727 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR.
2728 */
2729 #define PAGE_BTI PAGE_TARGET_1
2730 #define PAGE_MTE PAGE_TARGET_2
2731
2732 /* We associate one allocation tag per 16 bytes, the minimum. */
2733 #define LOG2_TAG_GRANULE 4
2734 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
2735
2736 #endif