| 1 | /* |
| 2 | * QEMU AArch64 CPU |
| 3 | * |
| 4 | * Copyright (c) 2013 Linaro Ltd |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, see |
| 18 | * <http://www.gnu.org/licenses/gpl-2.0.html> |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qapi/error.h" |
| 23 | #include "cpu.h" |
| 24 | #include "cpregs.h" |
| 25 | #include "qemu/module.h" |
| 26 | #include "qemu/units.h" |
| 27 | #include "system/kvm.h" |
| 28 | #include "system/hvf.h" |
| 29 | #include "system/whpx.h" |
| 30 | #include "system/hw_accel.h" |
| 31 | #include "system/qtest.h" |
| 32 | #include "system/tcg.h" |
| 33 | #include "kvm_arm.h" |
| 34 | #include "hvf_arm.h" |
| 35 | #include "whpx_arm.h" |
| 36 | #include "qapi/visitor.h" |
| 37 | #include "hw/core/qdev-properties.h" |
| 38 | #include "internals.h" |
| 39 | #include "cpu-features.h" |
| 40 | |
| 41 | /* convert between <register>_IDX and SYS_<register> */ |
| 42 | #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ |
| 43 | [NAME##_IDX] = SYS_##NAME, |
| 44 | |
| 45 | const uint32_t id_register_sysreg[NUM_ID_IDX] = { |
| 46 | #include "cpu-sysregs.h.inc" |
| 47 | }; |
| 48 | |
| 49 | #undef DEF |
| 50 | #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ |
| 51 | case SYS_##NAME: return NAME##_IDX; |
| 52 | |
| 53 | int get_sysreg_idx(ARMSysRegs sysreg) |
| 54 | { |
| 55 | switch (sysreg) { |
| 56 | #include "cpu-sysregs.h.inc" |
| 57 | } |
| 58 | g_assert_not_reached(); |
| 59 | } |
| 60 | |
| 61 | #undef DEF |
| 62 | |
| 63 | void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp) |
| 64 | { |
| 65 | /* |
| 66 | * If any vector lengths are explicitly enabled with sve<N> properties, |
| 67 | * then all other lengths are implicitly disabled. If sve-max-vq is |
| 68 | * specified then it is the same as explicitly enabling all lengths |
| 69 | * up to and including the specified maximum, which means all larger |
| 70 | * lengths will be implicitly disabled. If no sve<N> properties |
| 71 | * are enabled and sve-max-vq is not specified, then all lengths not |
| 72 | * explicitly disabled will be enabled. Additionally, all power-of-two |
| 73 | * vector lengths less than the maximum enabled length will be |
| 74 | * automatically enabled and all vector lengths larger than the largest |
| 75 | * disabled power-of-two vector length will be automatically disabled. |
| 76 | * Errors are generated if the user provided input that interferes with |
| 77 | * any of the above. Finally, if SVE is not disabled, then at least one |
| 78 | * vector length must be enabled. |
| 79 | */ |
| 80 | uint32_t vq_map = cpu->sve_vq.map; |
| 81 | uint32_t vq_init = cpu->sve_vq.init; |
| 82 | uint32_t vq_supported = cpu->sve_vq.supported; |
| 83 | uint32_t vq_mask = 0; |
| 84 | uint32_t tmp, vq, max_vq = 0; |
| 85 | |
| 86 | /* |
| 87 | * Process explicit sve<N> properties. |
| 88 | * From the properties, sve_vq_map<N> implies sve_vq_init<N>. |
| 89 | * Check first for any sve<N> enabled. |
| 90 | */ |
| 91 | if (vq_map != 0) { |
| 92 | max_vq = 32 - clz32(vq_map); |
| 93 | vq_mask = MAKE_64BIT_MASK(0, max_vq); |
| 94 | |
| 95 | if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { |
| 96 | error_setg(errp, "cannot enable sve%d", max_vq * 128); |
| 97 | error_append_hint(errp, "sve%d is larger than the maximum vector " |
| 98 | "length, sve-max-vq=%d (%d bits)\n", |
| 99 | max_vq * 128, cpu->sve_max_vq, |
| 100 | cpu->sve_max_vq * 128); |
| 101 | return; |
| 102 | } |
| 103 | |
| 104 | if (kvm_enabled()) { |
| 105 | /* |
| 106 | * For KVM we have to automatically enable all supported uninitialized |
| 107 | * lengths, even when the smaller lengths are not all powers-of-two. |
| 108 | */ |
| 109 | vq_map |= vq_supported & ~vq_init & vq_mask; |
| 110 | } else { |
| 111 | /* Propagate enabled bits down through required powers-of-two. */ |
| 112 | vq_map |= SVE_VQ_POW2_MAP & ~vq_init & vq_mask; |
| 113 | } |
| 114 | } else if (cpu->sve_max_vq == 0) { |
| 115 | /* |
| 116 | * No explicit bits enabled, and no implicit bits from sve-max-vq. |
| 117 | */ |
| 118 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
| 119 | /* |
| 120 | * SVE is disabled and so are all vector lengths. Good. |
| 121 | * Disable all SVE extensions as well. Note that some ZFR0 |
| 122 | * fields are used also by SME so must not be wiped in |
| 123 | * an SME-no-SVE config. We will clear the rest in |
| 124 | * aarch_cpu_sme_finalize() if necessary. |
| 125 | */ |
| 126 | FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F64MM, 0); |
| 127 | FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F32MM, 0); |
| 128 | FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F16MM, 0); |
| 129 | FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, SM4, 0); |
| 130 | FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, B16B16, 0); |
| 131 | FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, SVEVER, 0); |
| 132 | return; |
| 133 | } |
| 134 | |
| 135 | if (kvm_enabled()) { |
| 136 | /* Disabling a supported length disables all larger lengths. */ |
| 137 | tmp = vq_init & vq_supported; |
| 138 | } else { |
| 139 | /* Disabling a power-of-two disables all larger lengths. */ |
| 140 | tmp = vq_init & SVE_VQ_POW2_MAP; |
| 141 | } |
| 142 | vq = ctz32(tmp) + 1; |
| 143 | |
| 144 | max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; |
| 145 | vq_mask = max_vq > 0 ? MAKE_64BIT_MASK(0, max_vq) : 0; |
| 146 | vq_map = vq_supported & ~vq_init & vq_mask; |
| 147 | |
| 148 | if (vq_map == 0) { |
| 149 | error_setg(errp, "cannot disable sve%d", vq * 128); |
| 150 | error_append_hint(errp, "Disabling sve%d results in all " |
| 151 | "vector lengths being disabled.\n", |
| 152 | vq * 128); |
| 153 | error_append_hint(errp, "With SVE enabled, at least one " |
| 154 | "vector length must be enabled.\n"); |
| 155 | return; |
| 156 | } |
| 157 | |
| 158 | max_vq = 32 - clz32(vq_map); |
| 159 | vq_mask = MAKE_64BIT_MASK(0, max_vq); |
| 160 | } |
| 161 | |
| 162 | /* |
| 163 | * Process the sve-max-vq property. |
| 164 | * Note that we know from the above that no bit above |
| 165 | * sve-max-vq is currently set. |
| 166 | */ |
| 167 | if (cpu->sve_max_vq != 0) { |
| 168 | max_vq = cpu->sve_max_vq; |
| 169 | vq_mask = MAKE_64BIT_MASK(0, max_vq); |
| 170 | |
| 171 | if (vq_init & ~vq_map & (1 << (max_vq - 1))) { |
| 172 | error_setg(errp, "cannot disable sve%d", max_vq * 128); |
| 173 | error_append_hint(errp, "The maximum vector length must be " |
| 174 | "enabled, sve-max-vq=%d (%d bits)\n", |
| 175 | max_vq, max_vq * 128); |
| 176 | return; |
| 177 | } |
| 178 | |
| 179 | /* Set all bits not explicitly set within sve-max-vq. */ |
| 180 | vq_map |= ~vq_init & vq_mask; |
| 181 | } |
| 182 | |
| 183 | /* |
| 184 | * We should know what max-vq is now. Also, as we're done |
| 185 | * manipulating sve-vq-map, we ensure any bits above max-vq |
| 186 | * are clear, just in case anybody looks. |
| 187 | */ |
| 188 | assert(max_vq != 0); |
| 189 | assert(vq_mask != 0); |
| 190 | vq_map &= vq_mask; |
| 191 | |
| 192 | /* Ensure the set of lengths matches what is supported. */ |
| 193 | tmp = vq_map ^ (vq_supported & vq_mask); |
| 194 | if (tmp) { |
| 195 | vq = 32 - clz32(tmp); |
| 196 | if (vq_map & (1 << (vq - 1))) { |
| 197 | if (cpu->sve_max_vq) { |
| 198 | error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq); |
| 199 | error_append_hint(errp, "This CPU does not support " |
| 200 | "the vector length %d-bits.\n", vq * 128); |
| 201 | error_append_hint(errp, "It may not be possible to use " |
| 202 | "sve-max-vq with this CPU. Try " |
| 203 | "using only sve<N> properties.\n"); |
| 204 | } else { |
| 205 | error_setg(errp, "cannot enable sve%d", vq * 128); |
| 206 | if (vq_supported) { |
| 207 | error_append_hint(errp, "This CPU does not support " |
| 208 | "the vector length %d-bits.\n", vq * 128); |
| 209 | } else { |
| 210 | error_append_hint(errp, "SVE not supported by KVM " |
| 211 | "on this host\n"); |
| 212 | } |
| 213 | } |
| 214 | return; |
| 215 | } else { |
| 216 | if (kvm_enabled()) { |
| 217 | error_setg(errp, "cannot disable sve%d", vq * 128); |
| 218 | error_append_hint(errp, "The KVM host requires all " |
| 219 | "supported vector lengths smaller " |
| 220 | "than %d bits to also be enabled.\n", |
| 221 | max_vq * 128); |
| 222 | return; |
| 223 | } else { |
| 224 | /* Ensure all required powers-of-two are enabled. */ |
| 225 | tmp = SVE_VQ_POW2_MAP & vq_mask & ~vq_map; |
| 226 | if (tmp) { |
| 227 | vq = 32 - clz32(tmp); |
| 228 | error_setg(errp, "cannot disable sve%d", vq * 128); |
| 229 | error_append_hint(errp, "sve%d is required as it " |
| 230 | "is a power-of-two length smaller " |
| 231 | "than the maximum, sve%d\n", |
| 232 | vq * 128, max_vq * 128); |
| 233 | return; |
| 234 | } |
| 235 | } |
| 236 | } |
| 237 | } |
| 238 | |
| 239 | /* |
| 240 | * Now that we validated all our vector lengths, the only question |
| 241 | * left to answer is if we even want SVE at all. |
| 242 | */ |
| 243 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
| 244 | error_setg(errp, "cannot enable sve%d", max_vq * 128); |
| 245 | error_append_hint(errp, "SVE must be enabled to enable vector " |
| 246 | "lengths.\n"); |
| 247 | error_append_hint(errp, "Add sve=on to the CPU property list.\n"); |
| 248 | return; |
| 249 | } |
| 250 | |
| 251 | /* From now on sve_max_vq is the actual maximum supported length. */ |
| 252 | cpu->sve_max_vq = max_vq; |
| 253 | cpu->sve_vq.map = vq_map; |
| 254 | |
| 255 | /* FEAT_F64MM requires the existence of a 256-bit vector size. */ |
| 256 | if (max_vq < 2) { |
| 257 | uint64_t t = GET_IDREG(&cpu->isar, ID_AA64ZFR0); |
| 258 | t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 0); |
| 259 | SET_IDREG(&cpu->isar, ID_AA64ZFR0, t); |
| 260 | } |
| 261 | } |
| 262 | |
| 263 | /* |
| 264 | * Note that cpu_arm_{get,set}_vq cannot use the simpler |
| 265 | * object_property_add_bool interface because they make use of the |
| 266 | * contents of "name" to determine which bit on which to operate. |
| 267 | */ |
| 268 | static void cpu_arm_get_vq(Object *obj, Visitor *v, const char *name, |
| 269 | void *opaque, Error **errp) |
| 270 | { |
| 271 | ARMCPU *cpu = ARM_CPU(obj); |
| 272 | ARMVQMap *vq_map = opaque; |
| 273 | uint32_t vq = atoi(&name[3]) / 128; |
| 274 | bool sve = vq_map == &cpu->sve_vq; |
| 275 | bool value; |
| 276 | |
| 277 | /* All vector lengths are disabled when feature is off. */ |
| 278 | if (sve |
| 279 | ? !cpu_isar_feature(aa64_sve, cpu) |
| 280 | : !cpu_isar_feature(aa64_sme, cpu)) { |
| 281 | value = false; |
| 282 | } else { |
| 283 | value = extract32(vq_map->map, vq - 1, 1); |
| 284 | } |
| 285 | visit_type_bool(v, name, &value, errp); |
| 286 | } |
| 287 | |
| 288 | static void cpu_arm_set_vq(Object *obj, Visitor *v, const char *name, |
| 289 | void *opaque, Error **errp) |
| 290 | { |
| 291 | ARMVQMap *vq_map = opaque; |
| 292 | uint32_t vq = atoi(&name[3]) / 128; |
| 293 | bool value; |
| 294 | |
| 295 | if (!visit_type_bool(v, name, &value, errp)) { |
| 296 | return; |
| 297 | } |
| 298 | |
| 299 | vq_map->map = deposit32(vq_map->map, vq - 1, 1, value); |
| 300 | vq_map->init |= 1 << (vq - 1); |
| 301 | } |
| 302 | |
| 303 | static void prop_bool_get_false(Object *obj, Visitor *v, const char *name, |
| 304 | void *opaque, Error **errp) |
| 305 | { |
| 306 | bool value = false; |
| 307 | visit_type_bool(v, name, &value, errp); |
| 308 | } |
| 309 | |
| 310 | static void prop_bool_set_false(Object *obj, Visitor *v, const char *name, |
| 311 | void *opaque, Error **errp) |
| 312 | { |
| 313 | bool value; |
| 314 | |
| 315 | if (visit_type_bool(v, name, &value, errp) && value) { |
| 316 | error_setg(errp, "'%s' feature not supported by %s on this host", |
| 317 | name, current_accel_name()); |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | static void prop_add_stub_bool(Object *obj, const char *name) |
| 322 | { |
| 323 | object_property_add(obj, name, "bool", prop_bool_get_false, |
| 324 | prop_bool_set_false, NULL, NULL); |
| 325 | } |
| 326 | |
| 327 | static bool cpu_arm_get_sve(Object *obj, Error **errp) |
| 328 | { |
| 329 | ARMCPU *cpu = ARM_CPU(obj); |
| 330 | return cpu_isar_feature(aa64_sve, cpu); |
| 331 | } |
| 332 | |
| 333 | static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) |
| 334 | { |
| 335 | ARMCPU *cpu = ARM_CPU(obj); |
| 336 | FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value); |
| 337 | } |
| 338 | |
| 339 | void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp) |
| 340 | { |
| 341 | uint32_t vq_map = cpu->sme_vq.map; |
| 342 | uint32_t vq_init = cpu->sme_vq.init; |
| 343 | uint32_t vq_supported = cpu->sme_vq.supported; |
| 344 | uint32_t vq; |
| 345 | |
| 346 | if (vq_map == 0) { |
| 347 | if (!cpu_isar_feature(aa64_sme, cpu)) { |
| 348 | SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0); |
| 349 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
| 350 | /* This clears the "SVE or SME" fields in ZFR0 */ |
| 351 | SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0); |
| 352 | } |
| 353 | return; |
| 354 | } |
| 355 | |
| 356 | /* TODO: KVM will require limitations via SMCR_EL2. */ |
| 357 | vq_map = vq_supported & ~vq_init; |
| 358 | |
| 359 | if (vq_map == 0) { |
| 360 | vq = ctz32(vq_supported) + 1; |
| 361 | error_setg(errp, "cannot disable sme%d", vq * 128); |
| 362 | error_append_hint(errp, "All SME vector lengths are disabled.\n"); |
| 363 | error_append_hint(errp, "With SME enabled, at least one " |
| 364 | "vector length must be enabled.\n"); |
| 365 | return; |
| 366 | } |
| 367 | } else { |
| 368 | if (!cpu_isar_feature(aa64_sme, cpu)) { |
| 369 | vq = 32 - clz32(vq_map); |
| 370 | error_setg(errp, "cannot enable sme%d", vq * 128); |
| 371 | error_append_hint(errp, "SME must be enabled to enable " |
| 372 | "vector lengths.\n"); |
| 373 | error_append_hint(errp, "Add sme=on to the CPU property list.\n"); |
| 374 | return; |
| 375 | } |
| 376 | /* TODO: KVM will require limitations via SMCR_EL2. */ |
| 377 | } |
| 378 | |
| 379 | cpu->sme_vq.map = vq_map; |
| 380 | cpu->sme_max_vq = 32 - clz32(vq_map); |
| 381 | |
| 382 | /* |
| 383 | * The "sme" property setter writes a bool value into ID_AA64PFR1_EL1.SME |
| 384 | * (and at this point we know it's not 0). Correct that value to report |
| 385 | * the same SME version as ID_AA64SMFR0_EL1.SMEver. |
| 386 | */ |
| 387 | if (FIELD_EX64_IDREG(&cpu->isar, ID_AA64SMFR0, SMEVER) != 0) { |
| 388 | /* SME2 or better */ |
| 389 | FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, 2); |
| 390 | } |
| 391 | |
| 392 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
| 393 | /* FEAT_SME_FA64 requires SVE, not just SME */ |
| 394 | FIELD_DP64_IDREG(&cpu->isar, ID_AA64SMFR0, FA64, 0); |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | static bool cpu_arm_get_sme(Object *obj, Error **errp) |
| 399 | { |
| 400 | ARMCPU *cpu = ARM_CPU(obj); |
| 401 | return cpu_isar_feature(aa64_sme, cpu); |
| 402 | } |
| 403 | |
| 404 | static void cpu_arm_set_sme(Object *obj, bool value, Error **errp) |
| 405 | { |
| 406 | ARMCPU *cpu = ARM_CPU(obj); |
| 407 | |
| 408 | /* |
| 409 | * For now, write 0 for "off" and 1 for "on" into the PFR1 field. |
| 410 | * We will correct this value to report the right SME |
| 411 | * level (SME vs SME2) in aarch_cpu_sme_finalize() later. |
| 412 | */ |
| 413 | FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value); |
| 414 | } |
| 415 | |
| 416 | static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp) |
| 417 | { |
| 418 | ARMCPU *cpu = ARM_CPU(obj); |
| 419 | return cpu_isar_feature(aa64_sme, cpu) && |
| 420 | cpu_isar_feature(aa64_sme_fa64, cpu); |
| 421 | } |
| 422 | |
| 423 | static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp) |
| 424 | { |
| 425 | ARMCPU *cpu = ARM_CPU(obj); |
| 426 | |
| 427 | FIELD_DP64_IDREG(&cpu->isar, ID_AA64SMFR0, FA64, value); |
| 428 | } |
| 429 | |
| 430 | #ifdef CONFIG_USER_ONLY |
| 431 | /* Mirror linux /proc/sys/abi/{sve,sme}_default_vector_length. */ |
| 432 | static void cpu_arm_set_default_vec_len(Object *obj, Visitor *v, |
| 433 | const char *name, void *opaque, |
| 434 | Error **errp) |
| 435 | { |
| 436 | uint32_t *ptr_default_vq = opaque; |
| 437 | int32_t default_len, default_vq, remainder; |
| 438 | |
| 439 | if (!visit_type_int32(v, name, &default_len, errp)) { |
| 440 | return; |
| 441 | } |
| 442 | |
| 443 | /* Undocumented, but the kernel allows -1 to indicate "maximum". */ |
| 444 | if (default_len == -1) { |
| 445 | *ptr_default_vq = ARM_MAX_VQ; |
| 446 | return; |
| 447 | } |
| 448 | |
| 449 | default_vq = default_len / 16; |
| 450 | remainder = default_len % 16; |
| 451 | |
| 452 | /* |
| 453 | * Note that the 512 max comes from include/uapi/asm/sve_context.h |
| 454 | * and is the maximum architectural width of ZCR_ELx.LEN. |
| 455 | */ |
| 456 | if (remainder || default_vq < 1 || default_vq > 512) { |
| 457 | ARMCPU *cpu = ARM_CPU(obj); |
| 458 | const char *which = |
| 459 | (ptr_default_vq == &cpu->sve_default_vq ? "sve" : "sme"); |
| 460 | |
| 461 | error_setg(errp, "cannot set %s-default-vector-length", which); |
| 462 | if (remainder) { |
| 463 | error_append_hint(errp, "Vector length not a multiple of 16\n"); |
| 464 | } else if (default_vq < 1) { |
| 465 | error_append_hint(errp, "Vector length smaller than 16\n"); |
| 466 | } else { |
| 467 | error_append_hint(errp, "Vector length larger than %d\n", |
| 468 | 512 * 16); |
| 469 | } |
| 470 | return; |
| 471 | } |
| 472 | |
| 473 | *ptr_default_vq = default_vq; |
| 474 | } |
| 475 | |
| 476 | static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v, |
| 477 | const char *name, void *opaque, |
| 478 | Error **errp) |
| 479 | { |
| 480 | uint32_t *ptr_default_vq = opaque; |
| 481 | int32_t value = *ptr_default_vq * 16; |
| 482 | |
| 483 | visit_type_int32(v, name, &value, errp); |
| 484 | } |
| 485 | #endif |
| 486 | |
| 487 | void aarch64_add_sve_properties(Object *obj) |
| 488 | { |
| 489 | ARMCPU *cpu = ARM_CPU(obj); |
| 490 | uint32_t vq; |
| 491 | |
| 492 | /* |
| 493 | * For hw virtualization, we have already probed the set of vector |
| 494 | * lengths supported. If there are none, the host doesn't support |
| 495 | * SVE at all. In which case we register a stub property, to allow |
| 496 | * -cpu max,sve=off |
| 497 | * to always be valid. |
| 498 | * |
| 499 | * For TCG, this function is only called for cpu models which |
| 500 | * support SVE. The error message in the stub is written |
| 501 | * assuming host virtualiation is being used. |
| 502 | */ |
| 503 | if (cpu->sve_vq.supported) { |
| 504 | object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); |
| 505 | } else { |
| 506 | assert(!tcg_enabled()); |
| 507 | prop_add_stub_bool(obj, "sve"); |
| 508 | } |
| 509 | |
| 510 | for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { |
| 511 | char name[8]; |
| 512 | snprintf(name, sizeof(name), "sve%d", vq * 128); |
| 513 | object_property_add(obj, name, "bool", cpu_arm_get_vq, |
| 514 | cpu_arm_set_vq, NULL, &cpu->sve_vq); |
| 515 | } |
| 516 | |
| 517 | #ifdef CONFIG_USER_ONLY |
| 518 | /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ |
| 519 | object_property_add(obj, "sve-default-vector-length", "int32", |
| 520 | cpu_arm_get_default_vec_len, |
| 521 | cpu_arm_set_default_vec_len, NULL, |
| 522 | &cpu->sve_default_vq); |
| 523 | #endif |
| 524 | } |
| 525 | |
| 526 | void aarch64_add_sme_properties(Object *obj) |
| 527 | { |
| 528 | ARMCPU *cpu = ARM_CPU(obj); |
| 529 | uint32_t vq; |
| 530 | |
| 531 | object_property_add_bool(obj, "sme", cpu_arm_get_sme, cpu_arm_set_sme); |
| 532 | object_property_add_bool(obj, "sme_fa64", cpu_arm_get_sme_fa64, |
| 533 | cpu_arm_set_sme_fa64); |
| 534 | |
| 535 | for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) { |
| 536 | char name[8]; |
| 537 | snprintf(name, sizeof(name), "sme%d", vq * 128); |
| 538 | object_property_add(obj, name, "bool", cpu_arm_get_vq, |
| 539 | cpu_arm_set_vq, NULL, &cpu->sme_vq); |
| 540 | } |
| 541 | |
| 542 | #ifdef CONFIG_USER_ONLY |
| 543 | /* Mirror linux /proc/sys/abi/sme_default_vector_length. */ |
| 544 | object_property_add(obj, "sme-default-vector-length", "int32", |
| 545 | cpu_arm_get_default_vec_len, |
| 546 | cpu_arm_set_default_vec_len, NULL, |
| 547 | &cpu->sme_default_vq); |
| 548 | #endif |
| 549 | } |
| 550 | |
| 551 | void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) |
| 552 | { |
| 553 | ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu); |
| 554 | ARMISARegisters *isar = &cpu->isar; |
| 555 | uint64_t isar1, isar2; |
| 556 | |
| 557 | /* |
| 558 | * These properties enable or disable Pauth as a whole, or change |
| 559 | * the pauth algorithm, but do not change the set of features that |
| 560 | * are present. We have saved a copy of those features above and |
| 561 | * will now place it into the field that chooses the algorithm. |
| 562 | * |
| 563 | * Begin by disabling all fields. |
| 564 | */ |
| 565 | isar1 = GET_IDREG(isar, ID_AA64ISAR1); |
| 566 | isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, 0); |
| 567 | isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 0); |
| 568 | isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, 0); |
| 569 | isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0); |
| 570 | |
| 571 | isar2 = GET_IDREG(isar, ID_AA64ISAR2); |
| 572 | isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0); |
| 573 | isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0); |
| 574 | |
| 575 | if (hwaccel_enabled()) { |
| 576 | /* |
| 577 | * Exit early if PAuth is enabled and fall through to disable it. |
| 578 | * The algorithm selection properties are not present. |
| 579 | */ |
| 580 | if (cpu->prop_pauth) { |
| 581 | if (features == 0) { |
| 582 | error_setg(errp, "'pauth' feature not supported by " |
| 583 | "%s on this host", current_accel_name()); |
| 584 | } |
| 585 | return; |
| 586 | } |
| 587 | } else { |
| 588 | /* Pauth properties are only present when the model supports it. */ |
| 589 | if (features == 0) { |
| 590 | assert(!cpu->prop_pauth); |
| 591 | return; |
| 592 | } |
| 593 | |
| 594 | if (cpu->prop_pauth) { |
| 595 | if ((cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) || |
| 596 | (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma5) || |
| 597 | (cpu->prop_pauth_qarma3 && cpu->prop_pauth_qarma5)) { |
| 598 | error_setg(errp, |
| 599 | "cannot enable pauth-impdef, pauth-qarma3 and " |
| 600 | "pauth-qarma5 at the same time"); |
| 601 | return; |
| 602 | } |
| 603 | |
| 604 | bool use_default = !cpu->prop_pauth_qarma5 && |
| 605 | !cpu->prop_pauth_qarma3 && |
| 606 | !cpu->prop_pauth_impdef; |
| 607 | |
| 608 | if (cpu->prop_pauth_qarma5 || |
| 609 | (use_default && |
| 610 | cpu->backcompat_pauth_default_use_qarma5)) { |
| 611 | isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); |
| 612 | isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); |
| 613 | } else if (cpu->prop_pauth_qarma3) { |
| 614 | isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features); |
| 615 | isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1); |
| 616 | } else if (cpu->prop_pauth_impdef || |
| 617 | (use_default && |
| 618 | !cpu->backcompat_pauth_default_use_qarma5)) { |
| 619 | isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features); |
| 620 | isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1); |
| 621 | } else { |
| 622 | g_assert_not_reached(); |
| 623 | } |
| 624 | } else if (cpu->prop_pauth_impdef || |
| 625 | cpu->prop_pauth_qarma3 || |
| 626 | cpu->prop_pauth_qarma5) { |
| 627 | error_setg(errp, "cannot enable pauth-impdef, pauth-qarma3 or " |
| 628 | "pauth-qarma5 without pauth"); |
| 629 | error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); |
| 630 | } |
| 631 | } |
| 632 | |
| 633 | SET_IDREG(isar, ID_AA64ISAR1, isar1); |
| 634 | SET_IDREG(isar, ID_AA64ISAR2, isar2); |
| 635 | } |
| 636 | |
| 637 | static const Property arm_cpu_pauth_property = |
| 638 | DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); |
| 639 | static const Property arm_cpu_pauth_impdef_property = |
| 640 | DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); |
| 641 | static const Property arm_cpu_pauth_qarma3_property = |
| 642 | DEFINE_PROP_BOOL("pauth-qarma3", ARMCPU, prop_pauth_qarma3, false); |
| 643 | static Property arm_cpu_pauth_qarma5_property = |
| 644 | DEFINE_PROP_BOOL("pauth-qarma5", ARMCPU, prop_pauth_qarma5, false); |
| 645 | |
| 646 | void aarch64_add_pauth_properties(Object *obj) |
| 647 | { |
| 648 | ARMCPU *cpu = ARM_CPU(obj); |
| 649 | |
| 650 | /* Default to PAUTH on, with the architected algorithm on TCG. */ |
| 651 | qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); |
| 652 | if (hwaccel_enabled()) { |
| 653 | /* |
| 654 | * Mirror PAuth support from the probed sysregs back into the |
| 655 | * property for HW accel. Is it just a bit backward? Yes it is! |
| 656 | * Note that prop_pauth is true whether the host CPU supports the |
| 657 | * architected QARMA5 algorithm or the IMPDEF one. We don't |
| 658 | * provide the separate pauth-impdef property for KVM or hvf, |
| 659 | * only for TCG. |
| 660 | */ |
| 661 | cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); |
| 662 | } else { |
| 663 | qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); |
| 664 | qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma3_property); |
| 665 | qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma5_property); |
| 666 | } |
| 667 | } |
| 668 | |
| 669 | void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) |
| 670 | { |
| 671 | uint64_t t; |
| 672 | |
| 673 | /* |
| 674 | * We only install the property for tcg -cpu max; this is the |
| 675 | * only situation in which the cpu field can be true. |
| 676 | */ |
| 677 | if (!cpu->prop_lpa2) { |
| 678 | return; |
| 679 | } |
| 680 | |
| 681 | t = GET_IDREG(&cpu->isar, ID_AA64MMFR0); |
| 682 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */ |
| 683 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */ |
| 684 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */ |
| 685 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */ |
| 686 | SET_IDREG(&cpu->isar, ID_AA64MMFR0, t); |
| 687 | } |
| 688 | |
| 689 | static void aarch64_a57_initfn(Object *obj) |
| 690 | { |
| 691 | aarch64_aa32_a57_init(ARM_CPU(obj), true); |
| 692 | } |
| 693 | |
| 694 | static void aarch64_a53_initfn(Object *obj) |
| 695 | { |
| 696 | ARMCPU *cpu = ARM_CPU(obj); |
| 697 | ARMISARegisters *isar = &cpu->isar; |
| 698 | |
| 699 | cpu->dtb_compatible = "arm,cortex-a53"; |
| 700 | set_feature(&cpu->env, ARM_FEATURE_V8); |
| 701 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 702 | set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); |
| 703 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
| 704 | set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); |
| 705 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
| 706 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
| 707 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
| 708 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
| 709 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
| 710 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; |
| 711 | cpu->midr = 0x410fd034; |
| 712 | cpu->revidr = 0x00000100; |
| 713 | cpu->reset_fpsid = 0x41034070; |
| 714 | cpu->isar.mvfr0 = 0x10110222; |
| 715 | cpu->isar.mvfr1 = 0x12111111; |
| 716 | cpu->isar.mvfr2 = 0x00000043; |
| 717 | cpu->ctr = 0x84448004; /* L1Ip = VIPT */ |
| 718 | cpu->reset_sctlr = 0x00c50838; |
| 719 | SET_IDREG(isar, ID_PFR0, 0x00000131); |
| 720 | SET_IDREG(isar, ID_PFR1, 0x00011011); |
| 721 | SET_IDREG(isar, ID_DFR0, 0x03010066); |
| 722 | SET_IDREG(isar, ID_AFR0, 0x00000000); |
| 723 | SET_IDREG(isar, ID_MMFR0, 0x10101105); |
| 724 | SET_IDREG(isar, ID_MMFR1, 0x40000000); |
| 725 | SET_IDREG(isar, ID_MMFR2, 0x01260000); |
| 726 | SET_IDREG(isar, ID_MMFR3, 0x02102211); |
| 727 | SET_IDREG(isar, ID_ISAR0, 0x02101110); |
| 728 | SET_IDREG(isar, ID_ISAR1, 0x13112111); |
| 729 | SET_IDREG(isar, ID_ISAR2, 0x21232042); |
| 730 | SET_IDREG(isar, ID_ISAR3, 0x01112131); |
| 731 | SET_IDREG(isar, ID_ISAR4, 0x00011142); |
| 732 | SET_IDREG(isar, ID_ISAR5, 0x00011121); |
| 733 | SET_IDREG(isar, ID_ISAR6, 0); |
| 734 | SET_IDREG(isar, ID_AA64PFR0, 0x00002222); |
| 735 | SET_IDREG(isar, ID_AA64DFR0, 0x10305106); |
| 736 | SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); |
| 737 | SET_IDREG(isar, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */ |
| 738 | cpu->isar.dbgdidr = 0x3516d000; |
| 739 | cpu->isar.dbgdevid = 0x00110f13; |
| 740 | cpu->isar.dbgdevid1 = 0x1; |
| 741 | cpu->isar.reset_pmcr_el0 = 0x41033000; |
| 742 | SET_IDREG(isar, CLIDR, 0x0a200023); |
| 743 | /* 32KB L1 dcache */ |
| 744 | cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); |
| 745 | /* 32KB L1 icache */ |
| 746 | cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, 2); |
| 747 | /* 1024KB L2 cache */ |
| 748 | cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7); |
| 749 | set_dczid_bs(cpu, 4); /* 64 bytes */ |
| 750 | cpu->gic_num_lrs = 4; |
| 751 | cpu->gic_vpribits = 5; |
| 752 | cpu->gic_vprebits = 5; |
| 753 | cpu->gic_pribits = 5; |
| 754 | define_cortex_a72_a57_a53_cp_reginfo(cpu); |
| 755 | } |
| 756 | |
| 757 | #if defined(CONFIG_KVM) |
| 758 | static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *cpu) |
| 759 | { |
| 760 | /* |
| 761 | * Registers that may be in the incoming stream and not exposed |
| 762 | * on the destination |
| 763 | */ |
| 764 | |
| 765 | /* |
| 766 | * TCR_EL1 was erroneously unconditionnally exposed before linux v6.13. |
| 767 | * See commit 0fcb4eea5345 ("KVM: arm64: Hide TCR2_EL1 from userspace |
| 768 | * when disabled for guests") |
| 769 | */ |
| 770 | arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 2, 0, 3), |
| 771 | 0, 0, ToleranceNotOnBothEnds); |
| 772 | /* |
| 773 | * PIRE0_EL1 and PIR_EL1 were erroneously unconditionnally exposed |
| 774 | * before linux v6.13. See commit a68cddbe47ef ("KVM: arm64: Hide |
| 775 | * S1PIE registers from userspace when disabled for guests") |
| 776 | */ |
| 777 | arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 10, 2, 2), |
| 778 | 0, 0, ToleranceNotOnBothEnds); |
| 779 | arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 10, 2, 3), |
| 780 | 0, 0, ToleranceNotOnBothEnds); |
| 781 | |
| 782 | /* |
| 783 | * KVM_REG_ARM_VENDOR_HYP_BMAP_2 pseudo FW register is exposed |
| 784 | * from v6.15 onwards. Backward migration from a >= v6.15 to an older |
| 785 | * kernel would fail without cpreg migration tolerance definition. |
| 786 | * If the register is present on source but not on destination, make |
| 787 | * sure it has its reset value, ie. 0, meaning no service is exposed |
| 788 | * to the guest. |
| 789 | */ |
| 790 | arm_register_cpreg_mig_tolerance(cpu, KVM_REG_ARM_FW_FEAT_BMAP_REG(3), |
| 791 | UINT64_MAX, 0, ToleranceOnlySrcTestValue); |
| 792 | } |
| 793 | #endif |
| 794 | |
| 795 | void aarch64_host_initfn(Object *obj) |
| 796 | { |
| 797 | ARMCPU *cpu = ARM_CPU(obj); |
| 798 | |
| 799 | #if defined(CONFIG_NITRO) |
| 800 | if (nitro_enabled()) { |
| 801 | /* The nitro accel uses -cpu host, but does not actually consume it */ |
| 802 | return; |
| 803 | } |
| 804 | #endif |
| 805 | |
| 806 | #if defined(CONFIG_KVM) |
| 807 | kvm_arm_set_cpreg_mig_tolerances(cpu); |
| 808 | kvm_arm_set_cpu_features_from_host(cpu); |
| 809 | aarch64_add_sve_properties(obj); |
| 810 | #elif defined(CONFIG_HVF) |
| 811 | hvf_arm_set_cpu_features_from_host(cpu); |
| 812 | #elif defined(CONFIG_WHPX) |
| 813 | whpx_arm_set_cpu_features_from_host(cpu); |
| 814 | #else |
| 815 | g_assert_not_reached(); |
| 816 | #endif |
| 817 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
| 818 | aarch64_add_pauth_properties(obj); |
| 819 | } |
| 820 | } |
| 821 | |
| 822 | static const ARMCPUInfo aarch64_cpus[] = { |
| 823 | { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, |
| 824 | { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, |
| 825 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX) |
| 826 | { .name = "host", .initfn = aarch64_host_initfn }, |
| 827 | #endif |
| 828 | }; |
| 829 | |
| 830 | static void aarch64_cpu_register_types(void) |
| 831 | { |
| 832 | size_t i; |
| 833 | |
| 834 | for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { |
| 835 | arm_cpu_register(&aarch64_cpus[i]); |
| 836 | } |
| 837 | } |
| 838 | |
| 839 | type_init(aarch64_cpu_register_types) |