@samitouri / QOSamiQemu
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1 /*
2 * ARM gdb server stub: AArch64 specific functions.
3 *
4 * Copyright (c) 2013 SUSE LINUX Products GmbH
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu/log.h"
21 #include "cpu.h"
22 #include "internals.h"
23 #include "gdbstub/helpers.h"
24 #include "gdbstub/commands.h"
25 #include "tcg/mte_helper.h"
26 #if defined(CONFIG_USER_ONLY) && defined(CONFIG_LINUX)
27 #include <sys/prctl.h>
28 #include "mte_user_helper.h"
29 #endif
30 #ifdef CONFIG_TCG
31 #include "accel/tcg/cpu-mmu-index.h"
32 #include "exec/target_page.h"
33 #endif
34
35 int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
36 {
37 ARMCPU *cpu = ARM_CPU(cs);
38 CPUARMState *env = &cpu->env;
39
40 if (n < 31) {
41 /* Core integer register. */
42 return gdb_get_reg64(mem_buf, env->xregs[n]);
43 }
44 switch (n) {
45 case 31:
46 return gdb_get_reg64(mem_buf, env->xregs[31]);
47 case 32:
48 return gdb_get_reg64(mem_buf, env->pc);
49 case 33:
50 /* pstate is now a 64-bit value; can we simply adjust the xml? */
51 return gdb_get_reg32(mem_buf, pstate_read(env));
52 }
53 /* Unknown register. */
54 return 0;
55 }
56
57 int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
58 {
59 ARMCPU *cpu = ARM_CPU(cs);
60 CPUARMState *env = &cpu->env;
61 uint64_t tmp;
62
63 tmp = ldq_p(mem_buf);
64
65 if (n < 31) {
66 /* Core integer register. */
67 env->xregs[n] = tmp;
68 return 8;
69 }
70 switch (n) {
71 case 31:
72 env->xregs[31] = tmp;
73 return 8;
74 case 32:
75 env->pc = tmp;
76 return 8;
77 case 33:
78 /* CPSR */
79 /* pstate is now a 64-bit value; can we simply adjust the xml? */
80 pstate_write(env, tmp);
81 return 4;
82 }
83 /* Unknown register. */
84 return 0;
85 }
86
87 int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg)
88 {
89 ARMCPU *cpu = ARM_CPU(cs);
90 CPUARMState *env = &cpu->env;
91
92 switch (reg) {
93 case 0 ... 31:
94 {
95 /* 128 bit FP register - quads are in LE order */
96 uint64_t *q = aa64_vfp_qreg(env, reg);
97 return gdb_get_reg128(buf, q[1], q[0]);
98 }
99 case 32:
100 /* FPSR */
101 return gdb_get_reg32(buf, vfp_get_fpsr(env));
102 case 33:
103 /* FPCR */
104 return gdb_get_reg32(buf, vfp_get_fpcr(env));
105 default:
106 return 0;
107 }
108 }
109
110 int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg)
111 {
112 ARMCPU *cpu = ARM_CPU(cs);
113 CPUARMState *env = &cpu->env;
114
115 switch (reg) {
116 case 0 ... 31:
117 /* 128 bit FP register */
118 {
119 uint64_t *q = aa64_vfp_qreg(env, reg);
120
121 /*
122 * On the wire these are target-endian 128 bit values.
123 * In the CPU state these are host-order uint64_t values
124 * with the least-significant one first. This means they're
125 * the other way around for target_big_endian() (which is
126 * only true for us for aarch64_be-linux-user).
127 */
128 if (target_big_endian()) {
129 q[1] = ldq_p(buf);
130 q[0] = ldq_p(buf + 8);
131 } else{
132 q[0] = ldq_p(buf);
133 q[1] = ldq_p(buf + 8);
134 }
135
136 return 16;
137 }
138 case 32:
139 /* FPSR */
140 vfp_set_fpsr(env, ldl_p(buf));
141 return 4;
142 case 33:
143 /* FPCR */
144 vfp_set_fpcr(env, ldl_p(buf));
145 return 4;
146 default:
147 return 0;
148 }
149 }
150
151 int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg)
152 {
153 ARMCPU *cpu = ARM_CPU(cs);
154 CPUARMState *env = &cpu->env;
155
156 switch (reg) {
157 /* The first 32 registers are the zregs */
158 case 0 ... 31:
159 {
160 int vq, len = 0;
161 for (vq = 0; vq < arm_max_vq(cpu); vq++) {
162 len += gdb_get_reg128(buf,
163 env->vfp.zregs[reg].d[vq * 2 + 1],
164 env->vfp.zregs[reg].d[vq * 2]);
165 }
166 return len;
167 }
168 case 32:
169 return gdb_get_reg32(buf, vfp_get_fpsr(env));
170 case 33:
171 return gdb_get_reg32(buf, vfp_get_fpcr(env));
172 /* then 16 predicates and the ffr */
173 case 34 ... 50:
174 {
175 int preg = reg - 34;
176 int vq, len = 0;
177 for (vq = 0; vq < arm_max_vq(cpu); vq = vq + 4) {
178 len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
179 }
180 return len;
181 }
182 case 51:
183 {
184 /*
185 * We report in Vector Granules (VG) which is 64bit in a Z reg
186 * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
187 */
188 int vq = sve_vqm1_for_el(env, arm_current_el(env)) + 1;
189 return gdb_get_reg64(buf, vq * 2);
190 }
191 default:
192 /* gdbstub asked for something out our range */
193 qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
194 break;
195 }
196
197 return 0;
198 }
199
200 int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg)
201 {
202 ARMCPU *cpu = ARM_CPU(cs);
203 CPUARMState *env = &cpu->env;
204
205 /* The first 32 registers are the zregs */
206 switch (reg) {
207 /* The first 32 registers are the zregs */
208 case 0 ... 31:
209 {
210 int vq, len = 0;
211 for (vq = 0; vq < arm_max_vq(cpu); vq++) {
212 if (target_big_endian()) {
213 env->vfp.zregs[reg].d[vq * 2 + 1] = ldq_p(buf);
214 buf += 8;
215 env->vfp.zregs[reg].d[vq * 2] = ldq_p(buf);
216 } else{
217 env->vfp.zregs[reg].d[vq * 2] = ldq_p(buf);
218 buf += 8;
219 env->vfp.zregs[reg].d[vq * 2 + 1] = ldq_p(buf);
220 }
221 buf += 8;
222 len += 16;
223 }
224 return len;
225 }
226 case 32:
227 vfp_set_fpsr(env, *(uint32_t *)buf);
228 return 4;
229 case 33:
230 vfp_set_fpcr(env, *(uint32_t *)buf);
231 return 4;
232 case 34 ... 50:
233 {
234 int preg = reg - 34;
235 int vq, len = 0;
236 for (vq = 0; vq < arm_max_vq(cpu); vq = vq + 4) {
237 env->vfp.pregs[preg].p[vq / 4] = ldq_p(buf);
238 buf += 8;
239 len += 8;
240 }
241 return len;
242 }
243 case 51:
244 /* cannot set vg via gdbstub */
245 return 0;
246 default:
247 /* gdbstub asked for something out our range */
248 break;
249 }
250
251 return 0;
252 }
253
254 int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg)
255 {
256 ARMCPU *cpu = ARM_CPU(cs);
257 CPUARMState *env = &cpu->env;
258
259 switch (reg) {
260 case 0: /* svg register */
261 {
262 int vq = 0;
263 if (FIELD_EX64(env->svcr, SVCR, SM)) {
264 vq = sve_vqm1_for_el_sm(env, arm_current_el(env),
265 FIELD_EX64(env->svcr, SVCR, SM)) + 1;
266 }
267 /* svg = vector granules (2 * vector quardwords) in streaming mode */
268 return gdb_get_reg64(buf, vq * 2);
269 }
270 case 1: /* svcr register */
271 return gdb_get_reg64(buf, env->svcr);
272 case 2: /* za register */
273 {
274 int len = 0;
275 int vq = cpu->sme_max_vq;
276 int svl = vq * 16;
277 for (int i = 0; i < svl; i++) {
278 for (int q = 0; q < vq; q++) {
279 len += gdb_get_reg128(buf,
280 env->za_state.za[i].d[q * 2 + 1],
281 env->za_state.za[i].d[q * 2]);
282 }
283 }
284 return len;
285 }
286 default:
287 /* gdbstub asked for something out of range */
288 qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
289 break;
290 }
291
292 return 0;
293 }
294
295 int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg)
296 {
297 ARMCPU *cpu = ARM_CPU(cs);
298 CPUARMState *env = &cpu->env;
299
300 switch (reg) {
301 case 0: /* svg register */
302 /* cannot set svg via gdbstub */
303 return 8;
304 case 1: /* svcr register */
305 aarch64_set_svcr(env, ldq_le_p(buf),
306 R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
307 return 8;
308 case 2: /* za register */
309 {
310 int len = 0;
311 int vq = cpu->sme_max_vq;
312 int svl = vq * 16;
313 for (int i = 0; i < svl; i++) {
314 for (int q = 0; q < vq; q++) {
315 if (target_big_endian()) {
316 env->za_state.za[i].d[q * 2 + 1] = ldq_p(buf);
317 buf += 8;
318 env->za_state.za[i].d[q * 2] = ldq_p(buf);
319 } else{
320 env->za_state.za[i].d[q * 2] = ldq_p(buf);
321 buf += 8;
322 env->za_state.za[i].d[q * 2 + 1] = ldq_p(buf);
323 }
324 buf += 8;
325 len += 16;
326 }
327 }
328 return len;
329 }
330 default:
331 /* gdbstub asked for something out of range */
332 break;
333 }
334
335 return 0;
336 }
337
338 int aarch64_gdb_get_sme2_reg(CPUState *cs, GByteArray *buf, int reg)
339 {
340 ARMCPU *cpu = ARM_CPU(cs);
341 CPUARMState *env = &cpu->env;
342 int len = 0;
343
344 switch (reg) {
345 case 0: /* ZT0 */
346 for (int i = 0; i < ARRAY_SIZE(env->za_state.zt0); i += 2) {
347 len += gdb_get_reg128(buf, env->za_state.zt0[i + 1],
348 env->za_state.zt0[i]);
349 }
350 return len;
351 default:
352 /* gdbstub asked for something out of range */
353 qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
354 break;
355 }
356
357 return 0;
358 }
359
360 int aarch64_gdb_set_sme2_reg(CPUState *cs, uint8_t *buf, int reg)
361 {
362 ARMCPU *cpu = ARM_CPU(cs);
363 CPUARMState *env = &cpu->env;
364 int len = 0;
365
366 switch (reg) {
367 case 0: /* ZT0 */
368 for (int i = 0; i < ARRAY_SIZE(env->za_state.zt0); i += 2) {
369 if (target_big_endian()) {
370 env->za_state.zt0[i + 1] = ldq_p(buf);
371 buf += 8;
372 env->za_state.zt0[i] = ldq_p(buf);
373 } else {
374 env->za_state.zt0[i] = ldq_p(buf);
375 buf += 8;
376 env->za_state.zt0[i + 1] = ldq_p(buf);
377 }
378 buf += 8;
379 len += 16;
380 }
381 return len;
382 default:
383 /* gdbstub asked for something out of range */
384 break;
385 }
386
387 return 0;
388 }
389
390 int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg)
391 {
392 ARMCPU *cpu = ARM_CPU(cs);
393 CPUARMState *env = &cpu->env;
394
395 switch (reg) {
396 case 0: /* TPIDR_EL0 */
397 return gdb_get_reg64(buf, env->cp15.tpidr_el[0]);
398 case 1: /* TPIDR2_EL0 */
399 return gdb_get_reg64(buf, env->cp15.tpidr2_el0);
400 default:
401 /* gdbstub asked for something out of range */
402 break;
403 }
404
405 return 0;
406 }
407
408 int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg)
409 {
410 ARMCPU *cpu = ARM_CPU(cs);
411 CPUARMState *env = &cpu->env;
412
413 switch (reg) {
414 case 0: /* TPIDR_EL0 */
415 env->cp15.tpidr_el[0] = ldq_p(buf);
416 return 8;
417 case 1: /* TPIDR2_EL0 */
418 env->cp15.tpidr2_el0 = ldq_p(buf);
419 return 8;
420 default:
421 /* gdbstub asked for something out of range */
422 break;
423 }
424
425 return 0;
426 }
427
428 int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg)
429 {
430 ARMCPU *cpu = ARM_CPU(cs);
431 CPUARMState *env = &cpu->env;
432
433 switch (reg) {
434 case 0: /* pauth_dmask */
435 case 1: /* pauth_cmask */
436 case 2: /* pauth_dmask_high */
437 case 3: /* pauth_cmask_high */
438 /*
439 * Note that older versions of this feature only contained
440 * pauth_{d,c}mask, for use with Linux user processes, and
441 * thus exclusively in the low half of the address space.
442 *
443 * To support system mode, and to debug kernels, two new regs
444 * were added to cover the high half of the address space.
445 * For the purpose of pauth_ptr_mask, we can use any well-formed
446 * address within the address space half -- here, 0 and -1.
447 */
448 {
449 bool is_data = !(reg & 1);
450 bool is_high = reg & 2;
451 ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
452 ARMVAParameters param;
453
454 param = aa64_va_parameters(env, -is_high, mmu_idx, is_data, false);
455 return gdb_get_reg64(buf, pauth_ptr_mask(param));
456 }
457 default:
458 return 0;
459 }
460 }
461
462 int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg)
463 {
464 /* All pseudo registers are read-only. */
465 return 0;
466 }
467
468 static void output_vector_union_type(GDBFeatureBuilder *builder, int reg_width,
469 const char *name)
470 {
471 struct TypeSize {
472 const char *gdb_type;
473 short size;
474 char sz, suffix;
475 };
476
477 static const struct TypeSize vec_lanes[] = {
478 /* quads */
479 { "uint128", 128, 'q', 'u' },
480 { "int128", 128, 'q', 's' },
481 /* 64 bit */
482 { "ieee_double", 64, 'd', 'f' },
483 { "uint64", 64, 'd', 'u' },
484 { "int64", 64, 'd', 's' },
485 /* 32 bit */
486 { "ieee_single", 32, 's', 'f' },
487 { "uint32", 32, 's', 'u' },
488 { "int32", 32, 's', 's' },
489 /* 16 bit */
490 { "ieee_half", 16, 'h', 'f' },
491 { "uint16", 16, 'h', 'u' },
492 { "int16", 16, 'h', 's' },
493 /* bytes */
494 { "uint8", 8, 'b', 'u' },
495 { "int8", 8, 'b', 's' },
496 };
497
498 static const char suf[] = { 'b', 'h', 's', 'd', 'q' };
499 int i, j;
500
501 /* First define types and totals in a whole VL */
502 for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
503 gdb_feature_builder_append_tag(
504 builder, "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
505 name, vec_lanes[i].sz, vec_lanes[i].suffix,
506 vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
507 }
508
509 /*
510 * Now define a union for each size group containing unsigned and
511 * signed and potentially float versions of each size from 128 to
512 * 8 bits.
513 */
514 for (i = 0; i < ARRAY_SIZE(suf); i++) {
515 int bits = 8 << i;
516
517 gdb_feature_builder_append_tag(builder, "<union id=\"%sn%c\">",
518 name, suf[i]);
519 for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
520 if (vec_lanes[j].size == bits) {
521 gdb_feature_builder_append_tag(
522 builder, "<field name=\"%c\" type=\"%s%c%c\"/>",
523 vec_lanes[j].suffix, name,
524 vec_lanes[j].sz, vec_lanes[j].suffix);
525 }
526 }
527 gdb_feature_builder_append_tag(builder, "</union>");
528 }
529
530 /* And now the final union of unions */
531 gdb_feature_builder_append_tag(builder, "<union id=\"%s\">", name);
532 for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {
533 gdb_feature_builder_append_tag(builder,
534 "<field name=\"%c\" type=\"%sn%c\"/>",
535 suf[i], name, suf[i]);
536 }
537 gdb_feature_builder_append_tag(builder, "</union>");
538 }
539
540 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cs, int base_reg)
541 {
542 ARMCPU *cpu = ARM_CPU(cs);
543 int reg_width = arm_max_vq(cpu) * 128;
544 int pred_width = arm_max_vq(cpu) * 16;
545 GDBFeatureBuilder builder;
546 char *name;
547 int reg = 0;
548 int i;
549
550 gdb_feature_builder_init(&builder, &cpu->dyn_svereg_feature.desc,
551 "org.gnu.gdb.aarch64.sve", "sve-registers.xml",
552 base_reg);
553
554 /* Create the vector union type. */
555 output_vector_union_type(&builder, reg_width, "svev");
556
557 /* Create the predicate vector type. */
558 gdb_feature_builder_append_tag(
559 &builder, "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
560 pred_width / 8);
561
562 /* Define the vector registers. */
563 for (i = 0; i < 32; i++) {
564 name = g_strdup_printf("z%d", i);
565 gdb_feature_builder_append_reg(&builder, name, reg_width, reg++,
566 "svev", NULL);
567 }
568
569 /* fpscr & status registers */
570 gdb_feature_builder_append_reg(&builder, "fpsr", 32, reg++,
571 "int", "float");
572 gdb_feature_builder_append_reg(&builder, "fpcr", 32, reg++,
573 "int", "float");
574
575 /* Define the predicate registers. */
576 for (i = 0; i < 16; i++) {
577 name = g_strdup_printf("p%d", i);
578 gdb_feature_builder_append_reg(&builder, name, pred_width, reg++,
579 "svep", NULL);
580 }
581 gdb_feature_builder_append_reg(&builder, "ffr", pred_width, reg++,
582 "svep", "vector");
583
584 /* Define the vector length pseudo-register. */
585 gdb_feature_builder_append_reg(&builder, "vg", 64, reg++, "int", NULL);
586
587 gdb_feature_builder_end(&builder);
588
589 return &cpu->dyn_svereg_feature.desc;
590 }
591
592 GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cs, int base_reg)
593 {
594 ARMCPU *cpu = ARM_CPU(cs);
595 int vq = cpu->sme_max_vq;
596 int svl = vq * 16;
597 GDBFeatureBuilder builder;
598 int reg = 0;
599
600 gdb_feature_builder_init(&builder, &cpu->dyn_smereg_feature.desc,
601 "org.gnu.gdb.aarch64.sme", "sme-registers.xml",
602 base_reg);
603
604
605 /* Create the sme_bv vector type. */
606 gdb_feature_builder_append_tag(
607 &builder, "<vector id=\"sme_bv\" type=\"uint8\" count=\"%d\"/>",
608 svl);
609
610 /* Create the sme_bvv vector type. */
611 gdb_feature_builder_append_tag(
612 &builder, "<vector id=\"sme_bvv\" type=\"sme_bv\" count=\"%d\"/>",
613 svl);
614
615 /* Define the svg, svcr, and za registers. */
616
617 gdb_feature_builder_append_reg(&builder, "svg", 64, reg++, "int", NULL);
618 gdb_feature_builder_append_reg(&builder, "svcr", 64, reg++, "int", NULL);
619 gdb_feature_builder_append_reg(&builder, "za", svl * svl * 8, reg++,
620 "sme_bvv", NULL);
621
622 gdb_feature_builder_end(&builder);
623
624 return &cpu->dyn_smereg_feature.desc;
625 }
626
627 GDBFeature *arm_gen_dynamic_tls_feature(CPUState *cs, int base_reg)
628 {
629 ARMCPU *cpu = ARM_CPU(cs);
630 GDBFeatureBuilder builder;
631 int reg = 0;
632
633 gdb_feature_builder_init(&builder, &cpu->dyn_tls_feature.desc,
634 "org.gnu.gdb.aarch64.tls", "tls-registers.xml",
635 base_reg);
636
637 /*
638 * This feature must always have "tpidr", and may also have "tpidr2"
639 * if the CPU has that register.
640 */
641 gdb_feature_builder_append_reg(&builder, "tpidr", 64,
642 reg++, "data_ptr", NULL);
643 if (cpu_isar_feature(aa64_sme, cpu)) {
644 gdb_feature_builder_append_reg(&builder, "tpidr2", 64,
645 reg++, "data_ptr", NULL);
646 }
647 gdb_feature_builder_end(&builder);
648
649 return &cpu->dyn_tls_feature.desc;
650 }
651
652 #ifdef CONFIG_USER_ONLY
653 int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg)
654 {
655 ARMCPU *cpu = ARM_CPU(cs);
656 CPUARMState *env = &cpu->env;
657 uint64_t tcf0;
658
659 assert(reg == 0);
660
661 tcf0 = extract64(env->cp15.sctlr_el[1], 38, 2);
662
663 return gdb_get_reg64(buf, tcf0);
664 }
665
666 int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg)
667 {
668 #if defined(CONFIG_LINUX)
669 ARMCPU *cpu = ARM_CPU(cs);
670 CPUARMState *env = &cpu->env;
671
672 uint8_t tcf;
673
674 assert(reg == 0);
675
676 tcf = *buf << PR_MTE_TCF_SHIFT;
677
678 if (!tcf) {
679 return 0;
680 }
681
682 /*
683 * 'tag_ctl' register is actually a "pseudo-register" provided by GDB to
684 * expose options regarding the type of MTE fault that can be controlled at
685 * runtime.
686 */
687 arm_set_tagged_addr_ctrl(env, tcf);
688
689 return 1;
690 #else
691 return 0;
692 #endif
693 }
694 #endif /* CONFIG_USER_ONLY */
695
696 #ifdef CONFIG_TCG
697 static void handle_q_memtag(GArray *params, void *user_ctx)
698 {
699 ARMCPU *cpu = ARM_CPU(user_ctx);
700 CPUARMState *env = &cpu->env;
701 uint32_t mmu_index;
702
703 uint64_t addr = gdb_get_cmd_param(params, 0)->val_ull;
704 uint64_t len = gdb_get_cmd_param(params, 1)->val_ul;
705 int type = gdb_get_cmd_param(params, 2)->val_ul;
706
707 uint8_t *tags;
708 uint8_t addr_tag;
709
710 g_autoptr(GString) str_buf = g_string_new(NULL);
711
712 /*
713 * GDB does not query multiple tags for a memory range on remote targets, so
714 * that's not supported either by gdbstub.
715 */
716 if (len != 1) {
717 gdb_put_packet("E02");
718 }
719
720 /* GDB never queries a tag different from an allocation tag (type 1). */
721 if (type != 1) {
722 gdb_put_packet("E03");
723 }
724
725 /* Find out the current translation regime for probe. */
726 mmu_index = cpu_mmu_index(env_cpu(env), false);
727 /* Note that tags are packed here (2 tags packed in one byte). */
728 tags = allocation_tag_mem_probe(env, mmu_index, addr, MMU_DATA_LOAD, 1,
729 MMU_DATA_LOAD, true, 0);
730 if (!tags) {
731 /* Address is not in a tagged region. */
732 gdb_put_packet("E04");
733 return;
734 }
735
736 /* Unpack tag from byte. */
737 addr_tag = load_tag1(addr, tags);
738 g_string_printf(str_buf, "m%.2x", addr_tag);
739
740 gdb_put_packet(str_buf->str);
741 }
742
743 static void handle_q_isaddresstagged(GArray *params, void *user_ctx)
744 {
745 ARMCPU *cpu = ARM_CPU(user_ctx);
746 CPUARMState *env = &cpu->env;
747 uint32_t mmu_index;
748
749 uint64_t addr = gdb_get_cmd_param(params, 0)->val_ull;
750
751 uint8_t *tags;
752 const char *reply;
753
754 /* Find out the current translation regime for probe. */
755 mmu_index = cpu_mmu_index(env_cpu(env), false);
756 tags = allocation_tag_mem_probe(env, mmu_index, addr, MMU_DATA_LOAD, 1,
757 MMU_DATA_LOAD, true, 0);
758 reply = tags ? "01" : "00";
759
760 gdb_put_packet(reply);
761 }
762
763 static void handle_Q_memtag(GArray *params, void *user_ctx)
764 {
765 ARMCPU *cpu = ARM_CPU(user_ctx);
766 CPUARMState *env = &cpu->env;
767 uint32_t mmu_index;
768
769 uint64_t start_addr = gdb_get_cmd_param(params, 0)->val_ull;
770 uint64_t len = gdb_get_cmd_param(params, 1)->val_ul;
771 int type = gdb_get_cmd_param(params, 2)->val_ul;
772 char const *new_tags_str = gdb_get_cmd_param(params, 3)->data;
773
774 uint64_t end_addr;
775
776 int num_new_tags;
777 uint8_t *tags;
778
779 g_autoptr(GByteArray) new_tags = g_byte_array_new();
780
781 /*
782 * Only the allocation tag (i.e. type 1) can be set at the stub side.
783 */
784 if (type != 1) {
785 gdb_put_packet("E02");
786 return;
787 }
788
789 end_addr = start_addr + (len - 1); /* 'len' is always >= 1 */
790 /* Check if request's memory range does not cross page boundaries. */
791 if ((start_addr ^ end_addr) & TARGET_PAGE_MASK) {
792 gdb_put_packet("E03");
793 return;
794 }
795
796 /*
797 * Get all tags in the page starting from the tag of the start address.
798 * Note that there are two tags packed into a single byte here.
799 */
800 /* Find out the current translation regime for probe. */
801 mmu_index = cpu_mmu_index(env_cpu(env), false);
802 tags = allocation_tag_mem_probe(env, mmu_index, start_addr, MMU_DATA_STORE,
803 1, MMU_DATA_STORE, true, 0);
804 if (!tags) {
805 /* Address is not in a tagged region. */
806 gdb_put_packet("E04");
807 return;
808 }
809
810 /* Convert tags provided by GDB, 2 hex digits per tag. */
811 num_new_tags = strlen(new_tags_str) / 2;
812 gdb_hextomem(new_tags, new_tags_str, num_new_tags);
813
814 uint64_t address = start_addr;
815 int new_tag_index = 0;
816 while (address <= end_addr) {
817 uint8_t new_tag;
818 int packed_index;
819
820 /*
821 * Find packed tag index from unpacked tag index. There are two tags
822 * in one packed index (one tag per nibble).
823 */
824 packed_index = new_tag_index / 2;
825
826 new_tag = new_tags->data[new_tag_index % num_new_tags];
827 store_tag1(address, tags + packed_index, new_tag);
828
829 address += TAG_GRANULE;
830 new_tag_index++;
831 }
832
833 gdb_put_packet("OK");
834 }
835
836 enum Command {
837 qMemTags,
838 qIsAddressTagged,
839 QMemTags,
840 NUM_CMDS
841 };
842
843 static const GdbCmdParseEntry cmd_handler_table[NUM_CMDS] = {
844 [qMemTags] = {
845 .handler = handle_q_memtag,
846 .cmd_startswith = true,
847 .cmd = "MemTags:",
848 .schema = "L,l:l0",
849 .need_cpu_context = true
850 },
851 [qIsAddressTagged] = {
852 .handler = handle_q_isaddresstagged,
853 .cmd_startswith = true,
854 .cmd = "IsAddressTagged:",
855 .schema = "L0",
856 .need_cpu_context = true
857 },
858 [QMemTags] = {
859 .handler = handle_Q_memtag,
860 .cmd_startswith = true,
861 .cmd = "MemTags:",
862 .schema = "L,l:l:s0",
863 .need_cpu_context = true
864 },
865 };
866 #endif /* CONFIG_TCG */
867
868 void aarch64_cpu_register_gdb_commands(ARMCPU *cpu, GString *qsupported,
869 GPtrArray *qtable, GPtrArray *stable)
870 {
871 /* MTE */
872 #ifdef CONFIG_TCG
873 if (cpu_isar_feature(aa64_mte, cpu)) {
874 g_string_append(qsupported, ";memory-tagging+");
875
876 g_ptr_array_add(qtable, (gpointer) &cmd_handler_table[qMemTags]);
877 g_ptr_array_add(qtable, (gpointer) &cmd_handler_table[qIsAddressTagged]);
878 g_ptr_array_add(stable, (gpointer) &cmd_handler_table[QMemTags]);
879 }
880 #endif
881 }
882
883 void aarch64_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
884 {
885 CPUState *cs = CPU(cpu);
886 if (isar_feature_aa64_sve(&cpu->isar) ||
887 isar_feature_aa64_sme(&cpu->isar)) {
888 GDBFeature *feature = arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs);
889 gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
890 aarch64_gdb_set_sve_reg, feature);
891 } else {
892 gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,
893 aarch64_gdb_set_fpu_reg,
894 gdb_find_static_feature("aarch64-fpu.xml"));
895 }
896
897 if (isar_feature_aa64_sme(&cpu->isar)) {
898 GDBFeature *sme_feature =
899 arm_gen_dynamic_smereg_feature(cs, cs->gdb_num_regs);
900 gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg,
901 aarch64_gdb_set_sme_reg, sme_feature);
902 if (isar_feature_aa64_sme2(&cpu->isar)) {
903 gdb_register_coprocessor(cs, aarch64_gdb_get_sme2_reg,
904 aarch64_gdb_set_sme2_reg,
905 gdb_find_static_feature("aarch64-sme2.xml"));
906 }
907 }
908 /*
909 * Note that we report pauth information via the feature name
910 * org.gnu.gdb.aarch64.pauth_v2, not org.gnu.gdb.aarch64.pauth.
911 * GDB versions 9 through 12 have a bug where they will crash
912 * if they see the latter XML from QEMU.
913 */
914 if (isar_feature_aa64_pauth(&cpu->isar)) {
915 gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
916 aarch64_gdb_set_pauth_reg,
917 gdb_find_static_feature("aarch64-pauth.xml"));
918 }
919
920 #ifdef CONFIG_USER_ONLY
921 /* Memory Tagging Extension (MTE) 'tag_ctl' pseudo-register. */
922 if (cpu_isar_feature(aa64_mte, cpu)) {
923 gdb_register_coprocessor(cs, aarch64_gdb_get_tag_ctl_reg,
924 aarch64_gdb_set_tag_ctl_reg,
925 gdb_find_static_feature("aarch64-mte.xml"));
926 }
927 #endif
928
929 /* All AArch64 CPUs have at least TPIDR */
930 gdb_register_coprocessor(cs, aarch64_gdb_get_tls_reg,
931 aarch64_gdb_set_tls_reg,
932 arm_gen_dynamic_tls_feature(cs, cs->gdb_num_regs));
933 }