@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
h 172 lines 4.49 KB
Raw
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 typedef int32_t hv_return_t;
4 typedef uint64_t hv_vcpu_t;
5
6 static inline bool hvf_arm_sme2_supported(void)
7 {
8 return false;
9 }
10
11 static inline uint32_t hvf_arm_sme2_get_svl(void)
12 {
13 g_assert_not_reached();
14 }
15
16 typedef enum hv_sme_p_reg_t {
17 HV_SME_P_REG_0,
18 HV_SME_P_REG_1,
19 HV_SME_P_REG_2,
20 HV_SME_P_REG_3,
21 HV_SME_P_REG_4,
22 HV_SME_P_REG_5,
23 HV_SME_P_REG_6,
24 HV_SME_P_REG_7,
25 HV_SME_P_REG_8,
26 HV_SME_P_REG_9,
27 HV_SME_P_REG_10,
28 HV_SME_P_REG_11,
29 HV_SME_P_REG_12,
30 HV_SME_P_REG_13,
31 HV_SME_P_REG_14,
32 HV_SME_P_REG_15,
33 } hv_sme_p_reg_t;
34
35 /*
36 * The system version of this type declares it with
37 * __attribute__((ext_vector_type(64)))
38 * However, that is clang specific and not supported by GCC.
39 * Since these headers are only here for the case where the system
40 * headers do not provide these types (including both older macos
41 * and non-macos hosts), we don't need to make the type match
42 * exactly, so we declare it as a uint8_t array.
43 */
44 typedef uint8_t hv_sme_zt0_uchar64_t[64];
45
46 typedef enum hv_sme_z_reg_t {
47 HV_SME_Z_REG_0,
48 HV_SME_Z_REG_1,
49 HV_SME_Z_REG_2,
50 HV_SME_Z_REG_3,
51 HV_SME_Z_REG_4,
52 HV_SME_Z_REG_5,
53 HV_SME_Z_REG_6,
54 HV_SME_Z_REG_7,
55 HV_SME_Z_REG_8,
56 HV_SME_Z_REG_9,
57 HV_SME_Z_REG_10,
58 HV_SME_Z_REG_11,
59 HV_SME_Z_REG_12,
60 HV_SME_Z_REG_13,
61 HV_SME_Z_REG_14,
62 HV_SME_Z_REG_15,
63 HV_SME_Z_REG_16,
64 HV_SME_Z_REG_17,
65 HV_SME_Z_REG_18,
66 HV_SME_Z_REG_19,
67 HV_SME_Z_REG_20,
68 HV_SME_Z_REG_21,
69 HV_SME_Z_REG_22,
70 HV_SME_Z_REG_23,
71 HV_SME_Z_REG_24,
72 HV_SME_Z_REG_25,
73 HV_SME_Z_REG_26,
74 HV_SME_Z_REG_27,
75 HV_SME_Z_REG_28,
76 HV_SME_Z_REG_29,
77 HV_SME_Z_REG_30,
78 HV_SME_Z_REG_31,
79 } hv_sme_z_reg_t;
80
81 enum {
82 HV_SYS_REG_SMCR_EL1,
83 HV_SYS_REG_SMPRI_EL1,
84 HV_SYS_REG_TPIDR2_EL0,
85 HV_SYS_REG_ID_AA64ZFR0_EL1,
86 HV_SYS_REG_ID_AA64SMFR0_EL1,
87 };
88
89 enum {
90 HV_FEATURE_REG_ID_AA64SMFR0_EL1,
91 HV_FEATURE_REG_ID_AA64ZFR0_EL1,
92 };
93
94 typedef struct {
95 bool streaming_sve_mode_enabled;
96 bool za_storage_enabled;
97 } hv_vcpu_sme_state_t;
98
99 static inline hv_return_t hv_sme_config_get_max_svl_bytes(size_t *value)
100 {
101 g_assert_not_reached();
102 }
103
104 static inline hv_return_t hv_vcpu_get_sme_state(hv_vcpu_t vcpu,
105 hv_vcpu_sme_state_t *sme_state)
106 {
107 g_assert_not_reached();
108 }
109
110 static inline hv_return_t hv_vcpu_set_sme_state(hv_vcpu_t vcpu,
111 const hv_vcpu_sme_state_t *sme_state)
112 {
113 g_assert_not_reached();
114 }
115
116 static inline hv_return_t hv_vcpu_get_sme_z_reg(hv_vcpu_t vcpu,
117 hv_sme_z_reg_t reg,
118 uint8_t *value,
119 size_t length)
120 {
121 g_assert_not_reached();
122 }
123
124 static inline hv_return_t hv_vcpu_set_sme_z_reg(hv_vcpu_t vcpu,
125 hv_sme_z_reg_t reg,
126 const uint8_t *value,
127 size_t length)
128 {
129 g_assert_not_reached();
130 }
131
132 static inline hv_return_t hv_vcpu_get_sme_p_reg(hv_vcpu_t vcpu,
133 hv_sme_p_reg_t reg,
134 uint8_t *value,
135 size_t length)
136 {
137 g_assert_not_reached();
138 }
139
140 static inline hv_return_t hv_vcpu_set_sme_p_reg(hv_vcpu_t vcpu,
141 hv_sme_p_reg_t reg,
142 const uint8_t *value,
143 size_t length)
144 {
145 g_assert_not_reached();
146 }
147
148 static inline hv_return_t hv_vcpu_get_sme_za_reg(hv_vcpu_t vcpu,
149 uint8_t *value,
150 size_t length)
151 {
152 g_assert_not_reached();
153 }
154
155 static inline hv_return_t hv_vcpu_set_sme_za_reg(hv_vcpu_t vcpu,
156 const uint8_t *value,
157 size_t length)
158 {
159 g_assert_not_reached();
160 }
161
162 static inline hv_return_t hv_vcpu_get_sme_zt0_reg(hv_vcpu_t vcpu,
163 hv_sme_zt0_uchar64_t *value)
164 {
165 g_assert_not_reached();
166 }
167
168 static inline hv_return_t hv_vcpu_set_sme_zt0_reg(hv_vcpu_t vcpu,
169 const hv_sme_zt0_uchar64_t *value)
170 {
171 g_assert_not_reached();
172 }