| 1 | /* |
| 2 | * QEMU ARM CPU -- internal functions and types |
| 3 | * |
| 4 | * Copyright (c) 2014 Linaro Ltd |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, see |
| 18 | * <http://www.gnu.org/licenses/gpl-2.0.html> |
| 19 | * |
| 20 | * This header defines functions, types, etc which need to be shared |
| 21 | * between different source files within target/arm/ but which are |
| 22 | * private to it and not required by the rest of QEMU. |
| 23 | */ |
| 24 | |
| 25 | #ifndef TARGET_ARM_INTERNALS_H |
| 26 | #define TARGET_ARM_INTERNALS_H |
| 27 | |
| 28 | #include "exec/hwaddr.h" |
| 29 | #include "exec/vaddr.h" |
| 30 | #include "exec/breakpoint.h" |
| 31 | #include "exec/memop.h" |
| 32 | #include "gdbstub/enums.h" |
| 33 | #ifdef CONFIG_TCG |
| 34 | #include "accel/tcg/tb-cpu-state.h" |
| 35 | #include "tcg/tcg-gvec-desc.h" |
| 36 | #endif |
| 37 | #include "hw/core/registerfields.h" |
| 38 | #include "system/memory.h" |
| 39 | #include "syndrome.h" |
| 40 | #include "cpu-features.h" |
| 41 | #include "mmuidx-internal.h" |
| 42 | |
| 43 | /* register banks for CPU modes */ |
| 44 | #define BANK_USRSYS 0 |
| 45 | #define BANK_SVC 1 |
| 46 | #define BANK_ABT 2 |
| 47 | #define BANK_UND 3 |
| 48 | #define BANK_IRQ 4 |
| 49 | #define BANK_FIQ 5 |
| 50 | #define BANK_HYP 6 |
| 51 | #define BANK_MON 7 |
| 52 | |
| 53 | static inline MemOp mo_endian(CPUARMState *env) |
| 54 | { |
| 55 | return EX_TBFLAG_ANY(env->hflags, BE_DATA) ? MO_BE : MO_LE; |
| 56 | } |
| 57 | |
| 58 | static inline int arm_env_mmu_index(CPUARMState *env) |
| 59 | { |
| 60 | return EX_TBFLAG_ANY(env->hflags, MMUIDX); |
| 61 | } |
| 62 | |
| 63 | static inline bool excp_is_internal(int excp) |
| 64 | { |
| 65 | /* Return true if this exception number represents a QEMU-internal |
| 66 | * exception that will not be passed to the guest. |
| 67 | */ |
| 68 | return excp == EXCP_INTERRUPT |
| 69 | || excp == EXCP_HLT |
| 70 | || excp == EXCP_DEBUG |
| 71 | || excp == EXCP_HALTED |
| 72 | || excp == EXCP_EXCEPTION_EXIT |
| 73 | || excp == EXCP_KERNEL_TRAP |
| 74 | || excp == EXCP_SEMIHOST; |
| 75 | } |
| 76 | |
| 77 | /* |
| 78 | * Default frequency for the generic timer, in Hz. |
| 79 | * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before |
| 80 | * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, |
| 81 | * which gives a 16ns tick period. |
| 82 | * |
| 83 | * We will use the back-compat value: |
| 84 | * - for QEMU CPU types added before we standardized on 1GHz |
| 85 | * - for versioned machine types with a version of 9.0 or earlier |
| 86 | * In any case, the machine model may override via the cntfrq property. |
| 87 | */ |
| 88 | #define GTIMER_DEFAULT_HZ 1000000000 |
| 89 | #define GTIMER_BACKCOMPAT_HZ 62500000 |
| 90 | |
| 91 | /* Bit definitions for the v7M CONTROL register */ |
| 92 | FIELD(V7M_CONTROL, NPRIV, 0, 1) |
| 93 | FIELD(V7M_CONTROL, SPSEL, 1, 1) |
| 94 | FIELD(V7M_CONTROL, FPCA, 2, 1) |
| 95 | FIELD(V7M_CONTROL, SFPA, 3, 1) |
| 96 | |
| 97 | /* Bit definitions for v7M exception return payload */ |
| 98 | FIELD(V7M_EXCRET, ES, 0, 1) |
| 99 | FIELD(V7M_EXCRET, RES0, 1, 1) |
| 100 | FIELD(V7M_EXCRET, SPSEL, 2, 1) |
| 101 | FIELD(V7M_EXCRET, MODE, 3, 1) |
| 102 | FIELD(V7M_EXCRET, FTYPE, 4, 1) |
| 103 | FIELD(V7M_EXCRET, DCRS, 5, 1) |
| 104 | FIELD(V7M_EXCRET, S, 6, 1) |
| 105 | FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ |
| 106 | |
| 107 | /* Minimum value which is a magic number for exception return */ |
| 108 | #define EXC_RETURN_MIN_MAGIC 0xff000000 |
| 109 | /* Minimum number which is a magic number for function or exception return |
| 110 | * when using v8M security extension |
| 111 | */ |
| 112 | #define FNC_RETURN_MIN_MAGIC 0xfefffffe |
| 113 | |
| 114 | /* Bit definitions for DBGWCRn and DBGWCRn_EL1 */ |
| 115 | FIELD(DBGWCR, E, 0, 1) |
| 116 | FIELD(DBGWCR, PAC, 1, 2) |
| 117 | FIELD(DBGWCR, LSC, 3, 2) |
| 118 | FIELD(DBGWCR, BAS, 5, 8) |
| 119 | FIELD(DBGWCR, HMC, 13, 1) |
| 120 | FIELD(DBGWCR, SSC, 14, 2) |
| 121 | FIELD(DBGWCR, LBN, 16, 4) |
| 122 | FIELD(DBGWCR, WT, 20, 1) |
| 123 | FIELD(DBGWCR, MASK, 24, 5) |
| 124 | FIELD(DBGWCR, SSCE, 29, 1) |
| 125 | |
| 126 | /* Bit definitions for CPACR (AArch32 only) */ |
| 127 | FIELD(CPACR, CP10, 20, 2) |
| 128 | FIELD(CPACR, CP11, 22, 2) |
| 129 | FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ |
| 130 | FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ |
| 131 | FIELD(CPACR, ASEDIS, 31, 1) |
| 132 | |
| 133 | /* Bit definitions for CPACR_EL1 (AArch64 only) */ |
| 134 | FIELD(CPACR_EL1, ZEN, 16, 2) |
| 135 | FIELD(CPACR_EL1, FPEN, 20, 2) |
| 136 | FIELD(CPACR_EL1, SMEN, 24, 2) |
| 137 | FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ |
| 138 | |
| 139 | /* Bit definitions for NSACR (AArch32 only) */ |
| 140 | FIELD(NSACR, CP10, 10, 1) |
| 141 | FIELD(NSACR, CP11, 11, 1) |
| 142 | FIELD(NSACR, NSD32DIS, 14, 1) /* v7; RES0 in v8 */ |
| 143 | FIELD(NSACR, NSASEDIS, 15, 1) |
| 144 | FIELD(NSACR, RFR, 19, 1) /* v7; RES0 in v8 */ |
| 145 | FIELD(NSACR, NSTRCDIS, 20, 1) |
| 146 | |
| 147 | /* Bit definitions for HCPTR (AArch32 only) */ |
| 148 | FIELD(HCPTR, TCP10, 10, 1) |
| 149 | FIELD(HCPTR, TCP11, 11, 1) |
| 150 | FIELD(HCPTR, TASE, 15, 1) |
| 151 | FIELD(HCPTR, TTA, 20, 1) |
| 152 | FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ |
| 153 | FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ |
| 154 | |
| 155 | /* Bit definitions for CPTR_EL2 (AArch64 only) */ |
| 156 | FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ |
| 157 | FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ |
| 158 | FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ |
| 159 | FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ |
| 160 | FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ |
| 161 | FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ |
| 162 | FIELD(CPTR_EL2, TTA, 28, 1) |
| 163 | FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ |
| 164 | FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ |
| 165 | |
| 166 | /* Bit definitions for CPTR_EL3 (AArch64 only) */ |
| 167 | FIELD(CPTR_EL3, EZ, 8, 1) |
| 168 | FIELD(CPTR_EL3, TFP, 10, 1) |
| 169 | FIELD(CPTR_EL3, ESM, 12, 1) |
| 170 | FIELD(CPTR_EL3, TTA, 20, 1) |
| 171 | FIELD(CPTR_EL3, TAM, 30, 1) |
| 172 | FIELD(CPTR_EL3, TCPAC, 31, 1) |
| 173 | |
| 174 | #define MDCR_MTPME (1U << 28) |
| 175 | #define MDCR_TDCC (1U << 27) |
| 176 | #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ |
| 177 | #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ |
| 178 | #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ |
| 179 | #define MDCR_EPMAD (1U << 21) |
| 180 | #define MDCR_EDAD (1U << 20) |
| 181 | #define MDCR_TTRF (1U << 19) |
| 182 | #define MDCR_STE (1U << 18) /* MDCR_EL3 */ |
| 183 | #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ |
| 184 | #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ |
| 185 | #define MDCR_SDD (1U << 16) |
| 186 | #define MDCR_SPD (3U << 14) |
| 187 | #define MDCR_TDRA (1U << 11) |
| 188 | #define MDCR_TDOSA (1U << 10) |
| 189 | #define MDCR_TDA (1U << 9) |
| 190 | #define MDCR_TDE (1U << 8) |
| 191 | #define MDCR_HPME (1U << 7) |
| 192 | #define MDCR_TPM (1U << 6) |
| 193 | #define MDCR_TPMCR (1U << 5) |
| 194 | #define MDCR_HPMN (0x1fU) |
| 195 | |
| 196 | /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ |
| 197 | #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ |
| 198 | MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ |
| 199 | MDCR_STE | MDCR_SPME | MDCR_SPD) |
| 200 | |
| 201 | #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ |
| 202 | #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ |
| 203 | #define TTBCR_PD0 (1U << 4) |
| 204 | #define TTBCR_PD1 (1U << 5) |
| 205 | #define TTBCR_EPD0 (1U << 7) |
| 206 | #define TTBCR_IRGN0 (3U << 8) |
| 207 | #define TTBCR_ORGN0 (3U << 10) |
| 208 | #define TTBCR_SH0 (3U << 12) |
| 209 | #define TTBCR_T1SZ (3U << 16) |
| 210 | #define TTBCR_A1 (1U << 22) |
| 211 | #define TTBCR_EPD1 (1U << 23) |
| 212 | #define TTBCR_IRGN1 (3U << 24) |
| 213 | #define TTBCR_ORGN1 (3U << 26) |
| 214 | #define TTBCR_SH1 (1U << 28) |
| 215 | #define TTBCR_EAE (1U << 31) |
| 216 | |
| 217 | #define TCR2_PNCH (1ULL << 0) |
| 218 | #define TCR2_PIE (1ULL << 1) |
| 219 | #define TCR2_E0POE (1ULL << 2) |
| 220 | #define TCR2_POE (1ULL << 3) |
| 221 | #define TCR2_AIE (1ULL << 4) |
| 222 | #define TCR2_D128 (1ULL << 5) |
| 223 | #define TCR2_PTTWI (1ULL << 10) |
| 224 | #define TCR2_HAFT (1ULL << 11) |
| 225 | #define TCR2_AMEC0 (1ULL << 12) |
| 226 | #define TCR2_AMEC1 (1ULL << 13) |
| 227 | #define TCR2_DISCH0 (1ULL << 14) |
| 228 | #define TCR2_DISCH1 (1ULL << 15) |
| 229 | #define TCR2_A2 (1ULL << 16) |
| 230 | #define TCR2_FNG0 (1ULL << 17) |
| 231 | #define TCR2_FNG1 (1ULL << 18) |
| 232 | #define TCR2_FNGNA0 (1ULL << 20) |
| 233 | #define TCR2_FNGNA1 (1ULL << 21) |
| 234 | |
| 235 | FIELD(VTCR, T0SZ, 0, 6) |
| 236 | FIELD(VTCR, SL0, 6, 2) |
| 237 | FIELD(VTCR, IRGN0, 8, 2) |
| 238 | FIELD(VTCR, ORGN0, 10, 2) |
| 239 | FIELD(VTCR, SH0, 12, 2) |
| 240 | FIELD(VTCR, TG0, 14, 2) |
| 241 | FIELD(VTCR, PS, 16, 3) |
| 242 | FIELD(VTCR, VS, 19, 1) |
| 243 | FIELD(VTCR, HA, 21, 1) |
| 244 | FIELD(VTCR, HD, 22, 1) |
| 245 | FIELD(VTCR, HWU59, 25, 1) |
| 246 | FIELD(VTCR, HWU60, 26, 1) |
| 247 | FIELD(VTCR, HWU61, 27, 1) |
| 248 | FIELD(VTCR, HWU62, 28, 1) |
| 249 | FIELD(VTCR, NSW, 29, 1) |
| 250 | FIELD(VTCR, NSA, 30, 1) |
| 251 | FIELD(VTCR, DS, 32, 1) |
| 252 | FIELD(VTCR, SL2, 33, 1) |
| 253 | |
| 254 | FIELD(VSTCR, SW, 29, 1) |
| 255 | FIELD(VSTCR, SA, 30, 1) |
| 256 | |
| 257 | #define HCRX_ENAS0 (1ULL << 0) |
| 258 | #define HCRX_ENALS (1ULL << 1) |
| 259 | #define HCRX_ENASR (1ULL << 2) |
| 260 | #define HCRX_FNXS (1ULL << 3) |
| 261 | #define HCRX_FGTNXS (1ULL << 4) |
| 262 | #define HCRX_SMPME (1ULL << 5) |
| 263 | #define HCRX_TALLINT (1ULL << 6) |
| 264 | #define HCRX_VINMI (1ULL << 7) |
| 265 | #define HCRX_VFNMI (1ULL << 8) |
| 266 | #define HCRX_CMOW (1ULL << 9) |
| 267 | #define HCRX_MCE2 (1ULL << 10) |
| 268 | #define HCRX_MSCEN (1ULL << 11) |
| 269 | #define HCRX_TCR2EN (1ULL << 14) |
| 270 | #define HCRX_SCTLR2EN (1ULL << 15) |
| 271 | #define HCRX_GCSEN (1ULL << 22) |
| 272 | #define HCRX_ENFPM (1ULL << 23) |
| 273 | #define HCRX_PACMEN (1ULL << 24) |
| 274 | #define HCRX_SRMASKEN (1ULL << 26) |
| 275 | |
| 276 | #define HPFAR_NS (1ULL << 63) |
| 277 | |
| 278 | #define HSTR_TTEE (1 << 16) |
| 279 | #define HSTR_TJDBX (1 << 17) |
| 280 | |
| 281 | /* |
| 282 | * Depending on the value of HCR_EL2.E2H, bits 0 and 1 |
| 283 | * have different bit definitions, and EL1PCTEN might be |
| 284 | * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to |
| 285 | * disambiguate if necessary. |
| 286 | * |
| 287 | * The event stream bits (EVN*) are in the same position for |
| 288 | * CNTKCTL_EL1/CTNKCTL. |
| 289 | */ |
| 290 | FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1) |
| 291 | FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1) |
| 292 | FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1) |
| 293 | FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1) |
| 294 | FIELD(CNTxCTL, EVNTEN, 2, 1) |
| 295 | FIELD(CNTxCTL, EVNTDIR, 3, 1) |
| 296 | FIELD(CNTxCTL, EVNTI, 4, 4) |
| 297 | FIELD(CNTHCTL, EL0VTEN, 8, 1) |
| 298 | FIELD(CNTHCTL, EL0PTEN, 9, 1) |
| 299 | FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1) |
| 300 | FIELD(CNTHCTL, EL1PTEN, 11, 1) |
| 301 | FIELD(CNTHCTL, ECV, 12, 1) |
| 302 | FIELD(CNTHCTL, EL1TVT, 13, 1) |
| 303 | FIELD(CNTHCTL, EL1TVCT, 14, 1) |
| 304 | FIELD(CNTHCTL, EL1NVPCT, 15, 1) |
| 305 | FIELD(CNTHCTL, EL1NVVCT, 16, 1) |
| 306 | FIELD(CNTxCTL, EVNTIS, 17, 1) |
| 307 | FIELD(CNTHCTL, CNTVMASK, 18, 1) |
| 308 | FIELD(CNTHCTL, CNTPMASK, 19, 1) |
| 309 | |
| 310 | FIELD(FPMR, F8S1, 0, 3) |
| 311 | FIELD(FPMR, F8S2, 3, 3) |
| 312 | FIELD(FPMR, F8D, 6, 3) |
| 313 | FIELD(FPMR, OSM, 14, 1) |
| 314 | FIELD(FPMR, OSC, 15, 1) |
| 315 | FIELD(FPMR, LSCALE, 16, 7) |
| 316 | FIELD(FPMR, NSCALE, 24, 8) |
| 317 | FIELD(FPMR, NSCALE_F16, 24, 5) |
| 318 | FIELD(FPMR, LSCALE2, 32, 6) |
| 319 | |
| 320 | /* We use a few fake FSR values for internal purposes in M profile. |
| 321 | * M profile cores don't have A/R format FSRs, but currently our |
| 322 | * get_phys_addr() code assumes A/R profile and reports failures via |
| 323 | * an A/R format FSR value. We then translate that into the proper |
| 324 | * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt(). |
| 325 | * Mostly the FSR values we use for this are those defined for v7PMSA, |
| 326 | * since we share some of that codepath. A few kinds of fault are |
| 327 | * only for M profile and have no A/R equivalent, though, so we have |
| 328 | * to pick a value from the reserved range (which we never otherwise |
| 329 | * generate) to use for these. |
| 330 | * These values will never be visible to the guest. |
| 331 | */ |
| 332 | #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ |
| 333 | #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ |
| 334 | |
| 335 | /** |
| 336 | * raise_exception: Raise the specified exception. |
| 337 | * Raise a guest exception with the specified value, syndrome register |
| 338 | * and target exception level. This should be called from helper functions, |
| 339 | * and never returns because we will longjump back up to the CPU main loop. |
| 340 | */ |
| 341 | G_NORETURN void raise_exception(CPUARMState *env, uint32_t excp, |
| 342 | uint64_t syndrome, uint32_t target_el); |
| 343 | |
| 344 | /* |
| 345 | * Similarly, but also use unwinding to restore cpu state. |
| 346 | */ |
| 347 | G_NORETURN void raise_exception_ra(CPUARMState *env, uint32_t excp, |
| 348 | uint64_t syndrome, uint32_t target_el, |
| 349 | uintptr_t ra); |
| 350 | |
| 351 | /* |
| 352 | * For AArch64, map a given EL to an index in the banked_spsr array. |
| 353 | * Note that this mapping and the AArch32 mapping defined in bank_number() |
| 354 | * must agree such that the AArch64<->AArch32 SPSRs have the architecturally |
| 355 | * mandated mapping between each other. |
| 356 | */ |
| 357 | static inline unsigned int aarch64_banked_spsr_index(unsigned int el) |
| 358 | { |
| 359 | static const unsigned int map[4] = { |
| 360 | [1] = BANK_SVC, /* EL1. */ |
| 361 | [2] = BANK_HYP, /* EL2. */ |
| 362 | [3] = BANK_MON, /* EL3. */ |
| 363 | }; |
| 364 | assert(el >= 1 && el <= 3); |
| 365 | return map[el]; |
| 366 | } |
| 367 | |
| 368 | /* Map CPU modes onto saved register banks. */ |
| 369 | static inline int bank_number(int mode) |
| 370 | { |
| 371 | switch (mode) { |
| 372 | case ARM_CPU_MODE_USR: |
| 373 | case ARM_CPU_MODE_SYS: |
| 374 | return BANK_USRSYS; |
| 375 | case ARM_CPU_MODE_SVC: |
| 376 | return BANK_SVC; |
| 377 | case ARM_CPU_MODE_ABT: |
| 378 | return BANK_ABT; |
| 379 | case ARM_CPU_MODE_UND: |
| 380 | return BANK_UND; |
| 381 | case ARM_CPU_MODE_IRQ: |
| 382 | return BANK_IRQ; |
| 383 | case ARM_CPU_MODE_FIQ: |
| 384 | return BANK_FIQ; |
| 385 | case ARM_CPU_MODE_HYP: |
| 386 | return BANK_HYP; |
| 387 | case ARM_CPU_MODE_MON: |
| 388 | return BANK_MON; |
| 389 | } |
| 390 | g_assert_not_reached(); |
| 391 | } |
| 392 | |
| 393 | /** |
| 394 | * r14_bank_number: Map CPU mode onto register bank for r14 |
| 395 | * |
| 396 | * Given an AArch32 CPU mode, return the index into the saved register |
| 397 | * banks to use for the R14 (LR) in that mode. This is the same as |
| 398 | * bank_number(), except for the special case of Hyp mode, where |
| 399 | * R14 is shared with USR and SYS, unlike its R13 and SPSR. |
| 400 | * This should be used as the index into env->banked_r14[], and |
| 401 | * bank_number() used for the index into env->banked_r13[] and |
| 402 | * env->banked_spsr[]. |
| 403 | */ |
| 404 | static inline int r14_bank_number(int mode) |
| 405 | { |
| 406 | return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); |
| 407 | } |
| 408 | |
| 409 | void arm_cpu_register(const ARMCPUInfo *info); |
| 410 | |
| 411 | void arm_do_plugin_vcpu_discon_cb(CPUState *cs, uint64_t from); |
| 412 | void register_cp_regs_for_features(ARMCPU *cpu); |
| 413 | void arm_init_cpreg_list(ARMCPU *cpu); |
| 414 | |
| 415 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); |
| 416 | void arm_translate_init(void); |
| 417 | void aarch64_translate_code(CPUState *cs, TranslationBlock *tb, |
| 418 | int *max_insns, vaddr pc, void *host_pc); |
| 419 | void arm_translate_code(CPUState *cs, TranslationBlock *tb, |
| 420 | int *max_insns, vaddr pc, void *host_pc); |
| 421 | |
| 422 | void arm_cpu_register_gdb_commands(ARMCPU *cpu); |
| 423 | void aarch64_cpu_register_gdb_commands(ARMCPU *cpu, GString *, |
| 424 | GPtrArray *, GPtrArray *); |
| 425 | void aarch64_cpu_register_gdb_regs_for_features(ARMCPU *cpu); |
| 426 | |
| 427 | void arm_restore_state_to_opc(CPUState *cs, |
| 428 | const TranslationBlock *tb, |
| 429 | const uint64_t *data); |
| 430 | |
| 431 | #ifdef CONFIG_TCG |
| 432 | TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs); |
| 433 | void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); |
| 434 | |
| 435 | /* Our implementation of TCGCPUOps::cpu_exec_halt */ |
| 436 | bool arm_cpu_exec_halt(CPUState *cs); |
| 437 | int arm_cpu_mmu_index(CPUState *cs, bool ifetch); |
| 438 | #endif /* CONFIG_TCG */ |
| 439 | |
| 440 | typedef enum ARMFPRounding { |
| 441 | FPROUNDING_TIEEVEN, |
| 442 | FPROUNDING_POSINF, |
| 443 | FPROUNDING_NEGINF, |
| 444 | FPROUNDING_ZERO, |
| 445 | FPROUNDING_TIEAWAY, |
| 446 | FPROUNDING_ODD |
| 447 | } ARMFPRounding; |
| 448 | |
| 449 | extern const FloatRoundMode arm_rmode_to_sf_map[6]; |
| 450 | |
| 451 | static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode) |
| 452 | { |
| 453 | assert((unsigned)rmode < ARRAY_SIZE(arm_rmode_to_sf_map)); |
| 454 | return arm_rmode_to_sf_map[rmode]; |
| 455 | } |
| 456 | |
| 457 | /* Return the effective value of SCR_EL3.RW */ |
| 458 | static inline bool arm_scr_rw_eff(CPUARMState *env) |
| 459 | { |
| 460 | /* |
| 461 | * SCR_EL3.RW has an effective value of 1 if: |
| 462 | * - we are NS and EL2 is implemented but doesn't support AArch32 |
| 463 | * - we are S and EL2 is enabled (in which case it must be AArch64) |
| 464 | */ |
| 465 | ARMCPU *cpu = env_archcpu(env); |
| 466 | |
| 467 | if (env->cp15.scr_el3 & SCR_RW) { |
| 468 | return true; |
| 469 | } |
| 470 | if (env->cp15.scr_el3 & SCR_NS) { |
| 471 | return arm_feature(env, ARM_FEATURE_EL2) && |
| 472 | !cpu_isar_feature(aa64_aa32_el2, cpu); |
| 473 | } else { |
| 474 | return env->cp15.scr_el3 & SCR_EEL2; |
| 475 | } |
| 476 | } |
| 477 | |
| 478 | /* Return true if the specified exception level is running in AArch64 state. */ |
| 479 | static inline bool arm_el_is_aa64(CPUARMState *env, int el) |
| 480 | { |
| 481 | /* |
| 482 | * This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, |
| 483 | * and if we're not in EL0 then the state of EL0 isn't well defined.) |
| 484 | */ |
| 485 | assert(el >= 1 && el <= 3); |
| 486 | bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); |
| 487 | |
| 488 | /* |
| 489 | * The highest exception level is always at the maximum supported |
| 490 | * register width, and then lower levels have a register width controlled |
| 491 | * by bits in the SCR or HCR registers. |
| 492 | */ |
| 493 | if (el == 3) { |
| 494 | return aa64; |
| 495 | } |
| 496 | |
| 497 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
| 498 | aa64 = aa64 && arm_scr_rw_eff(env); |
| 499 | } |
| 500 | |
| 501 | if (el == 2) { |
| 502 | return aa64; |
| 503 | } |
| 504 | |
| 505 | if (arm_is_el2_enabled(env)) { |
| 506 | aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); |
| 507 | } |
| 508 | |
| 509 | return aa64; |
| 510 | } |
| 511 | |
| 512 | /* |
| 513 | * Return the current Exception Level (as per ARMv8; note that this differs |
| 514 | * from the ARMv7 Privilege Level). |
| 515 | */ |
| 516 | static inline int arm_current_el(CPUARMState *env) |
| 517 | { |
| 518 | if (arm_feature(env, ARM_FEATURE_M)) { |
| 519 | return arm_v7m_is_handler_mode(env) || |
| 520 | !(env->v7m.control[env->v7m.secure] & 1); |
| 521 | } |
| 522 | |
| 523 | if (is_a64(env)) { |
| 524 | return extract32(env->pstate, 2, 2); |
| 525 | } |
| 526 | |
| 527 | switch (env->uncached_cpsr & 0x1f) { |
| 528 | case ARM_CPU_MODE_USR: |
| 529 | return 0; |
| 530 | case ARM_CPU_MODE_HYP: |
| 531 | return 2; |
| 532 | case ARM_CPU_MODE_MON: |
| 533 | return 3; |
| 534 | default: |
| 535 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { |
| 536 | /* If EL3 is 32-bit then all secure privileged modes run in EL3 */ |
| 537 | return 3; |
| 538 | } |
| 539 | |
| 540 | return 1; |
| 541 | } |
| 542 | } |
| 543 | |
| 544 | static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, |
| 545 | bool sctlr_b) |
| 546 | { |
| 547 | #ifdef CONFIG_USER_ONLY |
| 548 | /* |
| 549 | * In system mode, BE32 is modelled in line with the |
| 550 | * architecture (as word-invariant big-endianness), where loads |
| 551 | * and stores are done little endian but from addresses which |
| 552 | * are adjusted by XORing with the appropriate constant. So the |
| 553 | * endianness to use for the raw data access is not affected by |
| 554 | * SCTLR.B. |
| 555 | * In user mode, however, we model BE32 as byte-invariant |
| 556 | * big-endianness (because user-only code cannot tell the |
| 557 | * difference), and so we need to use a data access endianness |
| 558 | * that depends on SCTLR.B. |
| 559 | */ |
| 560 | if (sctlr_b) { |
| 561 | return true; |
| 562 | } |
| 563 | #endif |
| 564 | /* In 32bit endianness is determined by looking at CPSR's E bit */ |
| 565 | return env->uncached_cpsr & CPSR_E; |
| 566 | } |
| 567 | |
| 568 | static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) |
| 569 | { |
| 570 | return sctlr & (el ? SCTLR_EE : SCTLR_E0E); |
| 571 | } |
| 572 | |
| 573 | /* Return true if the processor is in big-endian mode. */ |
| 574 | static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) |
| 575 | { |
| 576 | if (!is_a64(env)) { |
| 577 | return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); |
| 578 | } else { |
| 579 | int cur_el = arm_current_el(env); |
| 580 | uint64_t sctlr = arm_sctlr(env, cur_el); |
| 581 | return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); |
| 582 | } |
| 583 | } |
| 584 | |
| 585 | #ifdef CONFIG_USER_ONLY |
| 586 | static inline bool arm_cpu_bswap_data(CPUARMState *env) |
| 587 | { |
| 588 | return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); |
| 589 | } |
| 590 | #endif |
| 591 | |
| 592 | static inline void aarch64_save_sp(CPUARMState *env, int el) |
| 593 | { |
| 594 | if (env->pstate & PSTATE_SP) { |
| 595 | env->sp_el[el] = env->xregs[31]; |
| 596 | } else { |
| 597 | env->sp_el[0] = env->xregs[31]; |
| 598 | } |
| 599 | } |
| 600 | |
| 601 | static inline void aarch64_restore_sp(CPUARMState *env, int el) |
| 602 | { |
| 603 | if (env->pstate & PSTATE_SP) { |
| 604 | env->xregs[31] = env->sp_el[el]; |
| 605 | } else { |
| 606 | env->xregs[31] = env->sp_el[0]; |
| 607 | } |
| 608 | } |
| 609 | |
| 610 | static inline void update_spsel(CPUARMState *env, uint32_t imm) |
| 611 | { |
| 612 | unsigned int cur_el = arm_current_el(env); |
| 613 | /* Update PSTATE SPSel bit; this requires us to update the |
| 614 | * working stack pointer in xregs[31]. |
| 615 | */ |
| 616 | if (!((imm ^ env->pstate) & PSTATE_SP)) { |
| 617 | return; |
| 618 | } |
| 619 | aarch64_save_sp(env, cur_el); |
| 620 | env->pstate = deposit32(env->pstate, 0, 1, imm); |
| 621 | |
| 622 | /* We rely on illegal updates to SPsel from EL0 to get trapped |
| 623 | * at translation time. |
| 624 | */ |
| 625 | assert(cur_el >= 1 && cur_el <= 3); |
| 626 | aarch64_restore_sp(env, cur_el); |
| 627 | } |
| 628 | |
| 629 | /* |
| 630 | * arm_pamax |
| 631 | * @cpu: ARMCPU |
| 632 | * |
| 633 | * Returns the implementation defined bit-width of physical addresses. |
| 634 | * The ARMv8 reference manuals refer to this as PAMax(). |
| 635 | */ |
| 636 | unsigned int arm_pamax(ARMCPU *cpu); |
| 637 | |
| 638 | /* |
| 639 | * round_down_to_parange_index |
| 640 | * @bit_size: uint8_t |
| 641 | * |
| 642 | * Rounds down the bit_size supplied to the first supported ARM physical |
| 643 | * address range and returns the index for this. The index is intended to |
| 644 | * be used to set ID_AA64MMFR0_EL1's PARANGE bits. |
| 645 | */ |
| 646 | uint8_t round_down_to_parange_index(uint8_t bit_size); |
| 647 | |
| 648 | /* |
| 649 | * round_down_to_parange_bit_size |
| 650 | * @bit_size: uint8_t |
| 651 | * |
| 652 | * Rounds down the bit_size supplied to the first supported ARM physical |
| 653 | * address range bit size and returns this. |
| 654 | */ |
| 655 | uint8_t round_down_to_parange_bit_size(uint8_t bit_size); |
| 656 | |
| 657 | /* Return true if extended addresses are enabled. |
| 658 | * This is always the case if our translation regime is 64 bit, |
| 659 | * but depends on TTBCR.EAE for 32 bit. |
| 660 | */ |
| 661 | static inline bool extended_addresses_enabled(CPUARMState *env) |
| 662 | { |
| 663 | uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; |
| 664 | if (arm_feature(env, ARM_FEATURE_PMSA) && |
| 665 | arm_feature(env, ARM_FEATURE_V8)) { |
| 666 | return true; |
| 667 | } |
| 668 | return arm_el_is_aa64(env, 1) || |
| 669 | (arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE)); |
| 670 | } |
| 671 | |
| 672 | /* Update a QEMU watchpoint based on the information the guest has set in the |
| 673 | * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. |
| 674 | */ |
| 675 | void hw_watchpoint_update(ARMCPU *cpu, int n); |
| 676 | /* Update the QEMU watchpoints for every guest watchpoint. This does a |
| 677 | * complete delete-and-reinstate of the QEMU watchpoint list and so is |
| 678 | * suitable for use after migration or on reset. |
| 679 | */ |
| 680 | void hw_watchpoint_update_all(ARMCPU *cpu); |
| 681 | /* Update a QEMU breakpoint based on the information the guest has set in the |
| 682 | * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. |
| 683 | */ |
| 684 | void hw_breakpoint_update(ARMCPU *cpu, int n); |
| 685 | /* Update the QEMU breakpoints for every guest breakpoint. This does a |
| 686 | * complete delete-and-reinstate of the QEMU breakpoint list and so is |
| 687 | * suitable for use after migration or on reset. |
| 688 | */ |
| 689 | void hw_breakpoint_update_all(ARMCPU *cpu); |
| 690 | |
| 691 | /* Callback function for checking if a breakpoint should trigger. */ |
| 692 | bool arm_debug_check_breakpoint(CPUState *cs); |
| 693 | |
| 694 | /* Callback function for checking if a watchpoint should trigger. */ |
| 695 | bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); |
| 696 | |
| 697 | /* Adjust addresses (in BE32 mode) before testing against watchpoint |
| 698 | * addresses. |
| 699 | */ |
| 700 | vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); |
| 701 | |
| 702 | /* Callback function for when a watchpoint or breakpoint triggers. */ |
| 703 | void arm_debug_excp_handler(CPUState *cs); |
| 704 | |
| 705 | #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG) |
| 706 | static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) |
| 707 | { |
| 708 | return false; |
| 709 | } |
| 710 | #else |
| 711 | /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ |
| 712 | bool arm_is_psci_call(ARMCPU *cpu, int excp_type); |
| 713 | #endif |
| 714 | /* Actually handle a PSCI call */ |
| 715 | void arm_handle_psci_call(ARMCPU *cpu); |
| 716 | |
| 717 | /** |
| 718 | * arm_clear_exclusive: clear the exclusive monitor |
| 719 | * @env: CPU env |
| 720 | * Clear the CPU's exclusive monitor, like the guest CLREX instruction. |
| 721 | */ |
| 722 | static inline void arm_clear_exclusive(CPUARMState *env) |
| 723 | { |
| 724 | env->exclusive_addr = -1; |
| 725 | } |
| 726 | |
| 727 | /** |
| 728 | * ARMFaultType: type of an ARM MMU fault |
| 729 | * This corresponds to the v8A pseudocode's Fault enumeration, |
| 730 | * with extensions for QEMU internal conditions. |
| 731 | */ |
| 732 | typedef enum ARMFaultType { |
| 733 | ARMFault_None, |
| 734 | ARMFault_AccessFlag, |
| 735 | ARMFault_Alignment, |
| 736 | ARMFault_Background, |
| 737 | ARMFault_Domain, |
| 738 | ARMFault_Permission, |
| 739 | ARMFault_Translation, |
| 740 | ARMFault_AddressSize, |
| 741 | ARMFault_SyncExternal, |
| 742 | ARMFault_SyncExternalOnWalk, |
| 743 | ARMFault_SyncParity, |
| 744 | ARMFault_SyncParityOnWalk, |
| 745 | ARMFault_AsyncParity, |
| 746 | ARMFault_AsyncExternal, |
| 747 | ARMFault_Debug, |
| 748 | ARMFault_TLBConflict, |
| 749 | ARMFault_UnsuppAtomicUpdate, |
| 750 | ARMFault_Lockdown, |
| 751 | ARMFault_Exclusive, |
| 752 | ARMFault_ICacheMaint, |
| 753 | ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ |
| 754 | ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ |
| 755 | ARMFault_GPCFOnWalk, |
| 756 | ARMFault_GPCFOnOutput, |
| 757 | } ARMFaultType; |
| 758 | |
| 759 | typedef enum ARMGPCF { |
| 760 | GPCF_None, |
| 761 | GPCF_AddressSize, |
| 762 | GPCF_Walk, |
| 763 | GPCF_EABT, |
| 764 | GPCF_Fail, |
| 765 | } ARMGPCF; |
| 766 | |
| 767 | /** |
| 768 | * ARMMMUFaultInfo: Information describing an ARM MMU Fault |
| 769 | * @type: Type of fault |
| 770 | * @gpcf: Subtype of ARMFault_GPCFOn{Walk,Output}. |
| 771 | * @level: Table walk level (for translation, access flag and permission faults) |
| 772 | * @domain: Domain of the fault address (for non-LPAE CPUs only) |
| 773 | * @s2addr: Address that caused a fault at stage 2 |
| 774 | * @paddr: physical address that caused a fault for gpc |
| 775 | * @paddr_space: physical address space that caused a fault for gpc |
| 776 | * @stage2: True if we faulted at stage 2 |
| 777 | * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk |
| 778 | * @s1ns: True if we faulted on a non-secure IPA. Note that (unlike the |
| 779 | * HPFAR_EL2.NS bit) this is set for any stage 2 fault for an NS IPA, so |
| 780 | * code must check that this is for a fault taken to Secure EL2 before |
| 781 | * propagating s1ns to HPFAR_EL2.NS. |
| 782 | * @ea: True if we should set the EA (external abort type) bit in syndrome |
| 783 | */ |
| 784 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; |
| 785 | struct ARMMMUFaultInfo { |
| 786 | ARMFaultType type; |
| 787 | ARMGPCF gpcf; |
| 788 | hwaddr s2addr; |
| 789 | hwaddr paddr; |
| 790 | ARMSecuritySpace paddr_space; |
| 791 | int level; |
| 792 | int domain; |
| 793 | bool stage2; |
| 794 | bool s1ptw; |
| 795 | bool s1ns; |
| 796 | bool ea; |
| 797 | bool dirtybit; /* FEAT_S1PIE, FEAT_S2PIE */ |
| 798 | }; |
| 799 | |
| 800 | /** |
| 801 | * arm_fi_to_sfsc: Convert fault info struct to short-format FSC |
| 802 | * Compare pseudocode EncodeSDFSC(), though unlike that function |
| 803 | * we set up a whole FSR-format code including domain field and |
| 804 | * putting the high bit of the FSC into bit 10. |
| 805 | */ |
| 806 | static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi) |
| 807 | { |
| 808 | uint32_t fsc; |
| 809 | |
| 810 | switch (fi->type) { |
| 811 | case ARMFault_None: |
| 812 | return 0; |
| 813 | case ARMFault_AccessFlag: |
| 814 | fsc = fi->level == 1 ? 0x3 : 0x6; |
| 815 | break; |
| 816 | case ARMFault_Alignment: |
| 817 | fsc = 0x1; |
| 818 | break; |
| 819 | case ARMFault_Permission: |
| 820 | fsc = fi->level == 1 ? 0xd : 0xf; |
| 821 | break; |
| 822 | case ARMFault_Domain: |
| 823 | fsc = fi->level == 1 ? 0x9 : 0xb; |
| 824 | break; |
| 825 | case ARMFault_Translation: |
| 826 | fsc = fi->level == 1 ? 0x5 : 0x7; |
| 827 | break; |
| 828 | case ARMFault_SyncExternal: |
| 829 | fsc = 0x8 | (fi->ea << 12); |
| 830 | break; |
| 831 | case ARMFault_SyncExternalOnWalk: |
| 832 | fsc = fi->level == 1 ? 0xc : 0xe; |
| 833 | fsc |= (fi->ea << 12); |
| 834 | break; |
| 835 | case ARMFault_SyncParity: |
| 836 | fsc = 0x409; |
| 837 | break; |
| 838 | case ARMFault_SyncParityOnWalk: |
| 839 | fsc = fi->level == 1 ? 0x40c : 0x40e; |
| 840 | break; |
| 841 | case ARMFault_AsyncParity: |
| 842 | fsc = 0x408; |
| 843 | break; |
| 844 | case ARMFault_AsyncExternal: |
| 845 | fsc = 0x406 | (fi->ea << 12); |
| 846 | break; |
| 847 | case ARMFault_Debug: |
| 848 | fsc = 0x2; |
| 849 | break; |
| 850 | case ARMFault_TLBConflict: |
| 851 | fsc = 0x400; |
| 852 | break; |
| 853 | case ARMFault_Lockdown: |
| 854 | fsc = 0x404; |
| 855 | break; |
| 856 | case ARMFault_Exclusive: |
| 857 | fsc = 0x405; |
| 858 | break; |
| 859 | case ARMFault_ICacheMaint: |
| 860 | fsc = 0x4; |
| 861 | break; |
| 862 | case ARMFault_Background: |
| 863 | fsc = 0x0; |
| 864 | break; |
| 865 | case ARMFault_QEMU_NSCExec: |
| 866 | fsc = M_FAKE_FSR_NSC_EXEC; |
| 867 | break; |
| 868 | case ARMFault_QEMU_SFault: |
| 869 | fsc = M_FAKE_FSR_SFAULT; |
| 870 | break; |
| 871 | default: |
| 872 | /* Other faults can't occur in a context that requires a |
| 873 | * short-format status code. |
| 874 | */ |
| 875 | g_assert_not_reached(); |
| 876 | } |
| 877 | |
| 878 | fsc |= (fi->domain << 4); |
| 879 | return fsc; |
| 880 | } |
| 881 | |
| 882 | /** |
| 883 | * arm_fi_to_lfsc: Convert fault info struct to long-format FSC |
| 884 | * Compare pseudocode EncodeLDFSC(), though unlike that function |
| 885 | * we fill in also the LPAE bit 9 of a DFSR format. |
| 886 | */ |
| 887 | static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) |
| 888 | { |
| 889 | uint32_t fsc; |
| 890 | |
| 891 | switch (fi->type) { |
| 892 | case ARMFault_None: |
| 893 | return 0; |
| 894 | case ARMFault_AddressSize: |
| 895 | assert(fi->level >= -1 && fi->level <= 3); |
| 896 | if (fi->level < 0) { |
| 897 | fsc = 0b101001; |
| 898 | } else { |
| 899 | fsc = fi->level; |
| 900 | } |
| 901 | break; |
| 902 | case ARMFault_AccessFlag: |
| 903 | assert(fi->level >= 0 && fi->level <= 3); |
| 904 | fsc = 0b001000 | fi->level; |
| 905 | break; |
| 906 | case ARMFault_Permission: |
| 907 | assert(fi->level >= 0 && fi->level <= 3); |
| 908 | fsc = 0b001100 | fi->level; |
| 909 | break; |
| 910 | case ARMFault_Domain: |
| 911 | /* |
| 912 | * This can only happen when doing an AT insn at EL2 for an AArch32 |
| 913 | * stage 1 EL1&0 translation regime using short-descriptors, and |
| 914 | * the translation hits a Domain fault. This needs to be reported in |
| 915 | * the long-format PAR. Compare pseudocode AArch64_PARFaultStatus(). |
| 916 | */ |
| 917 | assert(fi->level == 1 || fi->level == 2); |
| 918 | fsc = 0b111100 | fi->level; |
| 919 | break; |
| 920 | case ARMFault_Translation: |
| 921 | assert(fi->level >= -1 && fi->level <= 3); |
| 922 | if (fi->level < 0) { |
| 923 | fsc = 0b101011; |
| 924 | } else { |
| 925 | fsc = 0b000100 | fi->level; |
| 926 | } |
| 927 | break; |
| 928 | case ARMFault_SyncExternal: |
| 929 | fsc = 0x10 | (fi->ea << 12); |
| 930 | break; |
| 931 | case ARMFault_SyncExternalOnWalk: |
| 932 | assert(fi->level >= -1 && fi->level <= 3); |
| 933 | if (fi->level < 0) { |
| 934 | fsc = 0b010011; |
| 935 | } else { |
| 936 | fsc = 0b010100 | fi->level; |
| 937 | } |
| 938 | fsc |= fi->ea << 12; |
| 939 | break; |
| 940 | case ARMFault_SyncParity: |
| 941 | fsc = 0x18; |
| 942 | break; |
| 943 | case ARMFault_SyncParityOnWalk: |
| 944 | assert(fi->level >= -1 && fi->level <= 3); |
| 945 | if (fi->level < 0) { |
| 946 | fsc = 0b011011; |
| 947 | } else { |
| 948 | fsc = 0b011100 | fi->level; |
| 949 | } |
| 950 | break; |
| 951 | case ARMFault_AsyncParity: |
| 952 | fsc = 0x19; |
| 953 | break; |
| 954 | case ARMFault_AsyncExternal: |
| 955 | fsc = 0x11 | (fi->ea << 12); |
| 956 | break; |
| 957 | case ARMFault_Alignment: |
| 958 | fsc = 0x21; |
| 959 | break; |
| 960 | case ARMFault_Debug: |
| 961 | fsc = 0x22; |
| 962 | break; |
| 963 | case ARMFault_TLBConflict: |
| 964 | fsc = 0x30; |
| 965 | break; |
| 966 | case ARMFault_UnsuppAtomicUpdate: |
| 967 | fsc = 0x31; |
| 968 | break; |
| 969 | case ARMFault_Lockdown: |
| 970 | fsc = 0x34; |
| 971 | break; |
| 972 | case ARMFault_Exclusive: |
| 973 | fsc = 0x35; |
| 974 | break; |
| 975 | case ARMFault_GPCFOnWalk: |
| 976 | assert(fi->level >= -1 && fi->level <= 3); |
| 977 | if (fi->level < 0) { |
| 978 | fsc = 0b100011; |
| 979 | } else { |
| 980 | fsc = 0b100100 | fi->level; |
| 981 | } |
| 982 | break; |
| 983 | case ARMFault_GPCFOnOutput: |
| 984 | fsc = 0b101000; |
| 985 | break; |
| 986 | default: |
| 987 | /* Other faults can't occur in a context that requires a |
| 988 | * long-format status code. |
| 989 | */ |
| 990 | g_assert_not_reached(); |
| 991 | } |
| 992 | |
| 993 | fsc |= 1 << 9; |
| 994 | return fsc; |
| 995 | } |
| 996 | |
| 997 | static inline bool arm_extabort_type(MemTxResult result) |
| 998 | { |
| 999 | /* The EA bit in syndromes and fault status registers is an |
| 1000 | * IMPDEF classification of external aborts. ARM implementations |
| 1001 | * usually use this to indicate AXI bus Decode error (0) or |
| 1002 | * Slave error (1); in QEMU we follow that. |
| 1003 | */ |
| 1004 | return result != MEMTX_DECODE_ERROR; |
| 1005 | } |
| 1006 | |
| 1007 | #ifdef CONFIG_USER_ONLY |
| 1008 | void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, |
| 1009 | MMUAccessType access_type, |
| 1010 | bool maperr, uintptr_t ra); |
| 1011 | void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, |
| 1012 | MMUAccessType access_type, uintptr_t ra); |
| 1013 | #else |
| 1014 | bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, |
| 1015 | MMUAccessType access_type, int mmu_idx, |
| 1016 | MemOp memop, int size, bool probe, uintptr_t ra); |
| 1017 | #endif |
| 1018 | |
| 1019 | static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) |
| 1020 | { |
| 1021 | int coreidx = mmu_idx & ARM_MMU_IDX_COREIDX_MASK; |
| 1022 | assert(coreidx < NB_MMU_MODES); |
| 1023 | return coreidx; |
| 1024 | } |
| 1025 | |
| 1026 | static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) |
| 1027 | { |
| 1028 | if (arm_feature(env, ARM_FEATURE_M)) { |
| 1029 | return mmu_idx | ARM_MMU_IDX_M; |
| 1030 | } else { |
| 1031 | return mmu_idx | ARM_MMU_IDX_A; |
| 1032 | } |
| 1033 | } |
| 1034 | |
| 1035 | static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) |
| 1036 | { |
| 1037 | /* AArch64 is always a-profile. */ |
| 1038 | return mmu_idx | ARM_MMU_IDX_A; |
| 1039 | } |
| 1040 | |
| 1041 | /* Return the MMU index for a v7M CPU in the specified security state */ |
| 1042 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); |
| 1043 | |
| 1044 | /* |
| 1045 | * Return true if the stage 1 translation regime is using LPAE |
| 1046 | * format page tables |
| 1047 | */ |
| 1048 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); |
| 1049 | |
| 1050 | /* Raise a data fault alignment exception for the specified virtual address */ |
| 1051 | G_NORETURN void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, |
| 1052 | MMUAccessType access_type, |
| 1053 | int mmu_idx, uintptr_t retaddr); |
| 1054 | |
| 1055 | #ifndef CONFIG_USER_ONLY |
| 1056 | /* arm_cpu_do_transaction_failed: handle a memory system error response |
| 1057 | * (eg "no device/memory present at address") by raising an external abort |
| 1058 | * exception |
| 1059 | */ |
| 1060 | void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
| 1061 | vaddr addr, unsigned size, |
| 1062 | MMUAccessType access_type, |
| 1063 | int mmu_idx, MemTxAttrs attrs, |
| 1064 | MemTxResult response, uintptr_t retaddr); |
| 1065 | #endif |
| 1066 | |
| 1067 | /* Call any registered EL change hooks */ |
| 1068 | static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) |
| 1069 | { |
| 1070 | ARMELChangeHook *hook, *next; |
| 1071 | QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { |
| 1072 | hook->hook(cpu, hook->opaque); |
| 1073 | } |
| 1074 | } |
| 1075 | static inline void arm_call_el_change_hook(ARMCPU *cpu) |
| 1076 | { |
| 1077 | ARMELChangeHook *hook, *next; |
| 1078 | QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { |
| 1079 | hook->hook(cpu, hook->opaque); |
| 1080 | } |
| 1081 | } |
| 1082 | |
| 1083 | /* Return the SCTLR value which controls this address translation regime */ |
| 1084 | static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) |
| 1085 | { |
| 1086 | return env->cp15.sctlr_el[regime_el(mmu_idx)]; |
| 1087 | } |
| 1088 | |
| 1089 | /* |
| 1090 | * These are the fields in VTCR_EL2 which affect both the Secure stage 2 |
| 1091 | * and the Non-Secure stage 2 translation regimes (and hence which are |
| 1092 | * not present in VSTCR_EL2). |
| 1093 | */ |
| 1094 | #define VTCR_SHARED_FIELD_MASK \ |
| 1095 | (R_VTCR_IRGN0_MASK | R_VTCR_ORGN0_MASK | R_VTCR_SH0_MASK | \ |
| 1096 | R_VTCR_PS_MASK | R_VTCR_VS_MASK | R_VTCR_HA_MASK | R_VTCR_HD_MASK | \ |
| 1097 | R_VTCR_DS_MASK) |
| 1098 | |
| 1099 | /* Return the value of the TCR controlling this translation regime */ |
| 1100 | static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) |
| 1101 | { |
| 1102 | if (mmu_idx == ARMMMUIdx_Stage2) { |
| 1103 | return env->cp15.vtcr_el2; |
| 1104 | } |
| 1105 | if (mmu_idx == ARMMMUIdx_Stage2_S) { |
| 1106 | /* |
| 1107 | * Secure stage 2 shares fields from VTCR_EL2. We merge those |
| 1108 | * in with the VSTCR_EL2 value to synthesize a single VTCR_EL2 format |
| 1109 | * value so the callers don't need to special case this. |
| 1110 | * |
| 1111 | * If a future architecture change defines bits in VSTCR_EL2 that |
| 1112 | * overlap with these VTCR_EL2 fields we may need to revisit this. |
| 1113 | */ |
| 1114 | uint64_t v = env->cp15.vstcr_el2 & ~VTCR_SHARED_FIELD_MASK; |
| 1115 | v |= env->cp15.vtcr_el2 & VTCR_SHARED_FIELD_MASK; |
| 1116 | return v; |
| 1117 | } |
| 1118 | return env->cp15.tcr_el[regime_el(mmu_idx)]; |
| 1119 | } |
| 1120 | |
| 1121 | /* Return true if the translation regime is using LPAE format page tables */ |
| 1122 | static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) |
| 1123 | { |
| 1124 | int el = regime_el(mmu_idx); |
| 1125 | if (el == 2 || arm_el_is_aa64(env, el)) { |
| 1126 | return true; |
| 1127 | } |
| 1128 | if (arm_feature(env, ARM_FEATURE_PMSA) && |
| 1129 | arm_feature(env, ARM_FEATURE_V8)) { |
| 1130 | return true; |
| 1131 | } |
| 1132 | if (arm_feature(env, ARM_FEATURE_LPAE) |
| 1133 | && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { |
| 1134 | return true; |
| 1135 | } |
| 1136 | return false; |
| 1137 | } |
| 1138 | |
| 1139 | /** |
| 1140 | * arm_num_brps: Return number of implemented breakpoints. |
| 1141 | * Note that the ID register BRPS field is "number of bps - 1", |
| 1142 | * and we return the actual number of breakpoints. |
| 1143 | */ |
| 1144 | static inline int arm_num_brps(ARMCPU *cpu) |
| 1145 | { |
| 1146 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
| 1147 | return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, BRPS) + 1; |
| 1148 | } else { |
| 1149 | return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; |
| 1150 | } |
| 1151 | } |
| 1152 | |
| 1153 | /** |
| 1154 | * arm_num_wrps: Return number of implemented watchpoints. |
| 1155 | * Note that the ID register WRPS field is "number of wps - 1", |
| 1156 | * and we return the actual number of watchpoints. |
| 1157 | */ |
| 1158 | static inline int arm_num_wrps(ARMCPU *cpu) |
| 1159 | { |
| 1160 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
| 1161 | return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, WRPS) + 1; |
| 1162 | } else { |
| 1163 | return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; |
| 1164 | } |
| 1165 | } |
| 1166 | |
| 1167 | /** |
| 1168 | * arm_num_ctx_cmps: Return number of implemented context comparators. |
| 1169 | * Note that the ID register CTX_CMPS field is "number of cmps - 1", |
| 1170 | * and we return the actual number of comparators. |
| 1171 | */ |
| 1172 | static inline int arm_num_ctx_cmps(ARMCPU *cpu) |
| 1173 | { |
| 1174 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
| 1175 | return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, CTX_CMPS) + 1; |
| 1176 | } else { |
| 1177 | return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; |
| 1178 | } |
| 1179 | } |
| 1180 | |
| 1181 | /** |
| 1182 | * v7m_using_psp: Return true if using process stack pointer |
| 1183 | * Return true if the CPU is currently using the process stack |
| 1184 | * pointer, or false if it is using the main stack pointer. |
| 1185 | */ |
| 1186 | static inline bool v7m_using_psp(CPUARMState *env) |
| 1187 | { |
| 1188 | /* Handler mode always uses the main stack; for thread mode |
| 1189 | * the CONTROL.SPSEL bit determines the answer. |
| 1190 | * Note that in v7M it is not possible to be in Handler mode with |
| 1191 | * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. |
| 1192 | */ |
| 1193 | return !arm_v7m_is_handler_mode(env) && |
| 1194 | env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; |
| 1195 | } |
| 1196 | |
| 1197 | /** |
| 1198 | * v7m_sp_limit: Return SP limit for current CPU state |
| 1199 | * Return the SP limit value for the current CPU security state |
| 1200 | * and stack pointer. |
| 1201 | */ |
| 1202 | static inline uint32_t v7m_sp_limit(CPUARMState *env) |
| 1203 | { |
| 1204 | if (v7m_using_psp(env)) { |
| 1205 | return env->v7m.psplim[env->v7m.secure]; |
| 1206 | } else { |
| 1207 | return env->v7m.msplim[env->v7m.secure]; |
| 1208 | } |
| 1209 | } |
| 1210 | |
| 1211 | /** |
| 1212 | * v7m_cpacr_pass: |
| 1213 | * Return true if the v7M CPACR permits access to the FPU for the specified |
| 1214 | * security state and privilege level. |
| 1215 | */ |
| 1216 | static inline bool v7m_cpacr_pass(CPUARMState *env, |
| 1217 | bool is_secure, bool is_priv) |
| 1218 | { |
| 1219 | switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { |
| 1220 | case 0: |
| 1221 | case 2: /* UNPREDICTABLE: we treat like 0 */ |
| 1222 | return false; |
| 1223 | case 1: |
| 1224 | return is_priv; |
| 1225 | case 3: |
| 1226 | return true; |
| 1227 | default: |
| 1228 | g_assert_not_reached(); |
| 1229 | } |
| 1230 | } |
| 1231 | |
| 1232 | /** |
| 1233 | * aarch32_mode_name(): Return name of the AArch32 CPU mode |
| 1234 | * @psr: Program Status Register indicating CPU mode |
| 1235 | * |
| 1236 | * Returns, for debug logging purposes, a printable representation |
| 1237 | * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by |
| 1238 | * the low bits of the specified PSR. |
| 1239 | */ |
| 1240 | static inline const char *aarch32_mode_name(uint32_t psr) |
| 1241 | { |
| 1242 | static const char cpu_mode_names[16][4] = { |
| 1243 | "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", |
| 1244 | "???", "???", "hyp", "und", "???", "???", "???", "sys" |
| 1245 | }; |
| 1246 | |
| 1247 | return cpu_mode_names[psr & 0xf]; |
| 1248 | } |
| 1249 | |
| 1250 | /** |
| 1251 | * arm_cpu_exec_interrupt(): Implementation of the cpu_exec_inrerrupt hook. |
| 1252 | */ |
| 1253 | bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request); |
| 1254 | |
| 1255 | /** |
| 1256 | * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request |
| 1257 | * |
| 1258 | * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following |
| 1259 | * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit. |
| 1260 | * Must be called with the BQL held. |
| 1261 | */ |
| 1262 | void arm_cpu_update_virq(ARMCPU *cpu); |
| 1263 | |
| 1264 | /** |
| 1265 | * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request |
| 1266 | * |
| 1267 | * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following |
| 1268 | * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit. |
| 1269 | * Must be called with the BQL held. |
| 1270 | */ |
| 1271 | void arm_cpu_update_vfiq(ARMCPU *cpu); |
| 1272 | |
| 1273 | /** |
| 1274 | * arm_cpu_update_vinmi: Update CPU_INTERRUPT_VINMI bit in cs->interrupt_request |
| 1275 | * |
| 1276 | * Update the CPU_INTERRUPT_VINMI bit in cs->interrupt_request, following |
| 1277 | * a change to either the input VNMI line from the GIC or the HCRX_EL2.VINMI. |
| 1278 | * Must be called with the BQL held. |
| 1279 | */ |
| 1280 | void arm_cpu_update_vinmi(ARMCPU *cpu); |
| 1281 | |
| 1282 | /** |
| 1283 | * arm_cpu_update_vfnmi: Update CPU_INTERRUPT_VFNMI bit in cs->interrupt_request |
| 1284 | * |
| 1285 | * Update the CPU_INTERRUPT_VFNMI bit in cs->interrupt_request, following |
| 1286 | * a change to the HCRX_EL2.VFNMI. |
| 1287 | * Must be called with the BQL held. |
| 1288 | */ |
| 1289 | void arm_cpu_update_vfnmi(ARMCPU *cpu); |
| 1290 | |
| 1291 | /** |
| 1292 | * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit |
| 1293 | * |
| 1294 | * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, |
| 1295 | * following a change to the HCR_EL2.VSE bit. |
| 1296 | */ |
| 1297 | void arm_cpu_update_vserr(ARMCPU *cpu); |
| 1298 | |
| 1299 | /** |
| 1300 | * arm_mmu_idx_el: |
| 1301 | * @env: The cpu environment |
| 1302 | * @el: The EL to use. |
| 1303 | * |
| 1304 | * Return the full ARMMMUIdx for the translation regime for EL. |
| 1305 | */ |
| 1306 | ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); |
| 1307 | |
| 1308 | /** |
| 1309 | * arm_mmu_idx: |
| 1310 | * @env: The cpu environment |
| 1311 | * |
| 1312 | * Return the full ARMMMUIdx for the current translation regime. |
| 1313 | */ |
| 1314 | ARMMMUIdx arm_mmu_idx(CPUARMState *env); |
| 1315 | |
| 1316 | /** |
| 1317 | * arm_stage1_mmu_idx: |
| 1318 | * @env: The cpu environment |
| 1319 | * |
| 1320 | * Return the ARMMMUIdx for the stage1 traversal for the current regime. |
| 1321 | */ |
| 1322 | #ifdef CONFIG_USER_ONLY |
| 1323 | static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) |
| 1324 | { |
| 1325 | return ARMMMUIdx_Stage1_E0; |
| 1326 | } |
| 1327 | static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) |
| 1328 | { |
| 1329 | return ARMMMUIdx_Stage1_E0; |
| 1330 | } |
| 1331 | #else |
| 1332 | ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx); |
| 1333 | ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); |
| 1334 | #endif |
| 1335 | |
| 1336 | static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, |
| 1337 | const ARMISARegisters *id) |
| 1338 | { |
| 1339 | uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; |
| 1340 | |
| 1341 | if ((features >> ARM_FEATURE_V4T) & 1) { |
| 1342 | valid |= CPSR_T; |
| 1343 | } |
| 1344 | if ((features >> ARM_FEATURE_V5) & 1) { |
| 1345 | valid |= CPSR_Q; /* V5TE in reality*/ |
| 1346 | } |
| 1347 | if ((features >> ARM_FEATURE_V6) & 1) { |
| 1348 | valid |= CPSR_E | CPSR_GE; |
| 1349 | } |
| 1350 | if ((features >> ARM_FEATURE_THUMB2) & 1) { |
| 1351 | valid |= CPSR_IT; |
| 1352 | } |
| 1353 | if (isar_feature_aa32_jazelle(id)) { |
| 1354 | valid |= CPSR_J; |
| 1355 | } |
| 1356 | if (isar_feature_aa32_pan(id)) { |
| 1357 | valid |= CPSR_PAN; |
| 1358 | } |
| 1359 | if (isar_feature_aa32_dit(id)) { |
| 1360 | valid |= CPSR_DIT; |
| 1361 | } |
| 1362 | if (isar_feature_aa32_ssbs(id)) { |
| 1363 | valid |= CPSR_SSBS; |
| 1364 | } |
| 1365 | |
| 1366 | return valid; |
| 1367 | } |
| 1368 | |
| 1369 | static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) |
| 1370 | { |
| 1371 | uint32_t valid; |
| 1372 | |
| 1373 | valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV; |
| 1374 | if (isar_feature_aa64_bti(id)) { |
| 1375 | valid |= PSTATE_BTYPE; |
| 1376 | } |
| 1377 | if (isar_feature_aa64_pan(id)) { |
| 1378 | valid |= PSTATE_PAN; |
| 1379 | } |
| 1380 | if (isar_feature_aa64_uao(id)) { |
| 1381 | valid |= PSTATE_UAO; |
| 1382 | } |
| 1383 | if (isar_feature_aa64_dit(id)) { |
| 1384 | valid |= PSTATE_DIT; |
| 1385 | } |
| 1386 | if (isar_feature_aa64_ssbs(id)) { |
| 1387 | valid |= PSTATE_SSBS; |
| 1388 | } |
| 1389 | if (isar_feature_aa64_mte(id)) { |
| 1390 | valid |= PSTATE_TCO; |
| 1391 | } |
| 1392 | if (isar_feature_aa64_nmi(id)) { |
| 1393 | valid |= PSTATE_ALLINT; |
| 1394 | } |
| 1395 | |
| 1396 | return valid; |
| 1397 | } |
| 1398 | |
| 1399 | /* Granule size (i.e. page size) */ |
| 1400 | typedef enum ARMGranuleSize { |
| 1401 | /* Same order as TG0 encoding */ |
| 1402 | Gran4K, |
| 1403 | Gran64K, |
| 1404 | Gran16K, |
| 1405 | GranInvalid, |
| 1406 | } ARMGranuleSize; |
| 1407 | |
| 1408 | /** |
| 1409 | * arm_granule_bits: Return address size of the granule in bits |
| 1410 | * |
| 1411 | * Return the address size of the granule in bits. This corresponds |
| 1412 | * to the pseudocode TGxGranuleBits(). |
| 1413 | */ |
| 1414 | static inline int arm_granule_bits(ARMGranuleSize gran) |
| 1415 | { |
| 1416 | switch (gran) { |
| 1417 | case Gran64K: |
| 1418 | return 16; |
| 1419 | case Gran16K: |
| 1420 | return 14; |
| 1421 | case Gran4K: |
| 1422 | return 12; |
| 1423 | default: |
| 1424 | g_assert_not_reached(); |
| 1425 | } |
| 1426 | } |
| 1427 | |
| 1428 | /* |
| 1429 | * Parameters of a given virtual address, as extracted from the |
| 1430 | * translation controls for a given regime. |
| 1431 | */ |
| 1432 | typedef struct ARMVAParameters { |
| 1433 | unsigned tsz : 8; |
| 1434 | unsigned ps : 3; |
| 1435 | unsigned sh : 2; |
| 1436 | unsigned select : 1; |
| 1437 | bool tbi : 1; |
| 1438 | bool epd : 1; |
| 1439 | bool hpd : 1; |
| 1440 | bool tsz_oob : 1; /* tsz has been clamped to legal range */ |
| 1441 | bool ds : 1; |
| 1442 | bool ha : 1; |
| 1443 | bool hd : 1; |
| 1444 | ARMGranuleSize gran : 2; |
| 1445 | bool pie : 1; |
| 1446 | bool aie : 1; |
| 1447 | bool mtx : 1; |
| 1448 | } ARMVAParameters; |
| 1449 | |
| 1450 | /** |
| 1451 | * aa64_va_parameters: Return parameters for an AArch64 virtual address |
| 1452 | * @env: CPU |
| 1453 | * @va: virtual address to look up |
| 1454 | * @mmu_idx: determines translation regime to use |
| 1455 | * @data: true if this is a data access |
| 1456 | * @el1_is_aa32: true if we are asking about stage 2 when EL1 is AArch32 |
| 1457 | * (ignored if @mmu_idx is for a stage 1 regime; only affects tsz/tsz_oob) |
| 1458 | */ |
| 1459 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
| 1460 | ARMMMUIdx mmu_idx, bool data, |
| 1461 | bool el1_is_aa32); |
| 1462 | |
| 1463 | int aa64_va_parameter_mtx(uint64_t tcr, ARMMMUIdx mmu_idx); |
| 1464 | int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); |
| 1465 | int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); |
| 1466 | int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx); |
| 1467 | |
| 1468 | /* Determine if allocation tags are available. */ |
| 1469 | static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, |
| 1470 | uint64_t sctlr) |
| 1471 | { |
| 1472 | if (el < 3 |
| 1473 | && arm_feature(env, ARM_FEATURE_EL3) |
| 1474 | && !(env->cp15.scr_el3 & SCR_ATA)) { |
| 1475 | return false; |
| 1476 | } |
| 1477 | if (el < 2 && arm_is_el2_enabled(env)) { |
| 1478 | uint64_t hcr = arm_hcr_el2_eff(env); |
| 1479 | if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { |
| 1480 | return false; |
| 1481 | } |
| 1482 | } |
| 1483 | sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA); |
| 1484 | return sctlr != 0; |
| 1485 | } |
| 1486 | |
| 1487 | #ifndef CONFIG_USER_ONLY |
| 1488 | |
| 1489 | /* Security attributes for an address, as returned by v8m_security_lookup. */ |
| 1490 | typedef struct V8M_SAttributes { |
| 1491 | bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */ |
| 1492 | bool ns; |
| 1493 | bool nsc; |
| 1494 | uint8_t sregion; |
| 1495 | bool srvalid; |
| 1496 | uint8_t iregion; |
| 1497 | bool irvalid; |
| 1498 | } V8M_SAttributes; |
| 1499 | |
| 1500 | void v8m_security_lookup(CPUARMState *env, uint32_t address, |
| 1501 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
| 1502 | bool secure, V8M_SAttributes *sattrs); |
| 1503 | |
| 1504 | /* Cacheability and shareability attributes for a memory access */ |
| 1505 | typedef struct ARMCacheAttrs { |
| 1506 | /* |
| 1507 | * If is_s2_format is true, attrs is the S2 descriptor bits [5:2] |
| 1508 | * Otherwise, attrs is the same as the MAIR_EL1 8-bit format |
| 1509 | */ |
| 1510 | unsigned int attrs:8; |
| 1511 | unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ |
| 1512 | bool is_s2_format:1; |
| 1513 | } ARMCacheAttrs; |
| 1514 | |
| 1515 | /* Fields that are valid upon success. */ |
| 1516 | typedef struct GetPhysAddrResult { |
| 1517 | CPUTLBEntryFull f; |
| 1518 | ARMCacheAttrs cacheattrs; |
| 1519 | /* |
| 1520 | * For ARMMMUIdx_Stage2*, the protection installed into f.prot |
| 1521 | * is the result for AccessType_TTW, i.e. the page table walk itself. |
| 1522 | * The protection installed info s2prot is the one to be merged |
| 1523 | * with the stage1 protection. |
| 1524 | */ |
| 1525 | int s2prot; |
| 1526 | } GetPhysAddrResult; |
| 1527 | |
| 1528 | /** |
| 1529 | * get_phys_addr: get the physical address for a virtual address |
| 1530 | * @env: CPUARMState |
| 1531 | * @address: virtual address to get physical address for |
| 1532 | * @access_type: 0 for read, 1 for write, 2 for execute |
| 1533 | * @memop: memory operation feeding this access, or 0 for none |
| 1534 | * @mmu_idx: MMU index indicating required translation regime |
| 1535 | * @result: set on translation success. |
| 1536 | * @fi: set to fault info if the translation fails |
| 1537 | * |
| 1538 | * Find the physical address corresponding to the given virtual address, |
| 1539 | * by doing a translation table walk on MMU based systems or using the |
| 1540 | * MPU state on MPU based systems. |
| 1541 | * |
| 1542 | * Returns true if the translation was successful. Otherwise, phys_ptr, attrs, |
| 1543 | * prot and page_size may not be filled in, and the populated fsr value provides |
| 1544 | * information on why the translation aborted, in the format of a |
| 1545 | * DFSR/IFSR fault register, with the following caveats: |
| 1546 | * * we honour the short vs long DFSR format differences. |
| 1547 | * * the WnR bit is never set (the caller must do this). |
| 1548 | * * for PSMAv5 based systems we don't bother to return a full FSR format |
| 1549 | * value. |
| 1550 | */ |
| 1551 | bool get_phys_addr(CPUARMState *env, vaddr address, |
| 1552 | MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, |
| 1553 | GetPhysAddrResult *result, ARMMMUFaultInfo *fi) |
| 1554 | __attribute__((nonnull)); |
| 1555 | |
| 1556 | /** |
| 1557 | * get_phys_addr_for_at: |
| 1558 | * @env: CPUARMState |
| 1559 | * @address: virtual address to get physical address for |
| 1560 | * @prot_check: PAGE_{READ,WRITE,EXEC}, or 0 |
| 1561 | * @mmu_idx: MMU index indicating required translation regime |
| 1562 | * @space: security space for the access |
| 1563 | * @result: set on translation success. |
| 1564 | * @fi: set to fault info if the translation fails |
| 1565 | * |
| 1566 | * Similar to get_phys_addr, but for use by AccessType_AT, i.e. |
| 1567 | * system instructions for address translation. |
| 1568 | * |
| 1569 | * Returns: false on translation failure, true on success. |
| 1570 | */ |
| 1571 | bool get_phys_addr_for_at(CPUARMState *env, vaddr address, unsigned prot_check, |
| 1572 | ARMMMUIdx mmu_idx, ARMSecuritySpace space, |
| 1573 | GetPhysAddrResult *result, ARMMMUFaultInfo *fi) |
| 1574 | __attribute__((nonnull)); |
| 1575 | |
| 1576 | bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, |
| 1577 | MMUAccessType access_type, unsigned prot_check, |
| 1578 | ARMMMUIdx mmu_idx, bool is_secure, |
| 1579 | GetPhysAddrResult *result, |
| 1580 | ARMMMUFaultInfo *fi, uint32_t *mregion); |
| 1581 | |
| 1582 | void arm_log_exception(CPUState *cs); |
| 1583 | |
| 1584 | /* Implementation of SysemuCPUOps::translate_for_debug */ |
| 1585 | bool arm_cpu_translate_for_debug(CPUState *cs, vaddr addr, |
| 1586 | TranslateForDebugResult *result); |
| 1587 | |
| 1588 | #endif /* !CONFIG_USER_ONLY */ |
| 1589 | |
| 1590 | /* |
| 1591 | * SVE predicates are 1/8 the size of SVE vectors, and cannot use |
| 1592 | * the same simd_desc() encoding due to restrictions on size. |
| 1593 | * Use these instead. |
| 1594 | */ |
| 1595 | FIELD(PREDDESC, OPRSZ, 0, 6) |
| 1596 | FIELD(PREDDESC, ESZ, 6, 2) |
| 1597 | FIELD(PREDDESC, DATA, 8, 24) |
| 1598 | |
| 1599 | /* Bits within a descriptor passed to the helper_mte_check* functions. */ |
| 1600 | FIELD(MTEDESC, MIDX, 0, 4) |
| 1601 | FIELD(MTEDESC, TBI, 4, 2) |
| 1602 | FIELD(MTEDESC, TCMA, 6, 2) |
| 1603 | FIELD(MTEDESC, WRITE, 8, 1) |
| 1604 | FIELD(MTEDESC, ALIGN, 9, 3) |
| 1605 | FIELD(MTEDESC, MTX, 12, 2) |
| 1606 | FIELD(MTEDESC, SIZEM1, 14, 32 - 14) /* size - 1 */ |
| 1607 | |
| 1608 | bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); |
| 1609 | uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra); |
| 1610 | |
| 1611 | /** |
| 1612 | * mte_mops_probe: Check where the next MTE failure is for a FEAT_MOPS operation |
| 1613 | * @env: CPU env |
| 1614 | * @ptr: start address of memory region (dirty pointer) |
| 1615 | * @size: length of region (guaranteed not to cross a page boundary) |
| 1616 | * @desc: MTEDESC descriptor word (0 means no MTE checks) |
| 1617 | * Returns: the size of the region that can be copied without hitting |
| 1618 | * an MTE tag failure |
| 1619 | * |
| 1620 | * Note that we assume that the caller has already checked the TBI |
| 1621 | * and TCMA bits with mte_checks_needed() and an MTE check is definitely |
| 1622 | * required. |
| 1623 | */ |
| 1624 | uint64_t mte_mops_probe(CPUARMState *env, uint64_t ptr, uint64_t size, |
| 1625 | uint32_t desc); |
| 1626 | |
| 1627 | /** |
| 1628 | * mte_mops_probe_rev: Check where the next MTE failure is for a FEAT_MOPS |
| 1629 | * operation going in the reverse direction |
| 1630 | * @env: CPU env |
| 1631 | * @ptr: *end* address of memory region (dirty pointer) |
| 1632 | * @size: length of region (guaranteed not to cross a page boundary) |
| 1633 | * @desc: MTEDESC descriptor word (0 means no MTE checks) |
| 1634 | * Returns: the size of the region that can be copied without hitting |
| 1635 | * an MTE tag failure |
| 1636 | * |
| 1637 | * Note that we assume that the caller has already checked the TBI |
| 1638 | * and TCMA bits with mte_checks_needed() and an MTE check is definitely |
| 1639 | * required. |
| 1640 | */ |
| 1641 | uint64_t mte_mops_probe_rev(CPUARMState *env, uint64_t ptr, uint64_t size, |
| 1642 | uint32_t desc); |
| 1643 | |
| 1644 | /** |
| 1645 | * mte_check_fail: Record an MTE tag check failure |
| 1646 | * @env: CPU env |
| 1647 | * @desc: MTEDESC descriptor word |
| 1648 | * @dirty_ptr: Failing dirty address |
| 1649 | * @ra: TCG retaddr |
| 1650 | * |
| 1651 | * This may never return (if the MTE tag checks are configured to fault). |
| 1652 | */ |
| 1653 | void mte_check_fail(CPUARMState *env, uint32_t desc, |
| 1654 | uint64_t dirty_ptr, uintptr_t ra); |
| 1655 | |
| 1656 | /** |
| 1657 | * mte_mops_set_tags: Set MTE tags for a portion of a FEAT_MOPS operation |
| 1658 | * @env: CPU env |
| 1659 | * @dirty_ptr: Start address of memory region (dirty pointer) |
| 1660 | * @size: length of region (guaranteed not to cross page boundary) |
| 1661 | * @desc: MTEDESC descriptor word |
| 1662 | */ |
| 1663 | void mte_mops_set_tags(CPUARMState *env, uint64_t dirty_ptr, uint64_t size, |
| 1664 | uint32_t desc); |
| 1665 | |
| 1666 | static inline int allocation_tag_from_addr(uint64_t ptr) |
| 1667 | { |
| 1668 | return extract64(ptr, 56, 4); |
| 1669 | } |
| 1670 | |
| 1671 | static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) |
| 1672 | { |
| 1673 | return deposit64(ptr, 56, 4, rtag); |
| 1674 | } |
| 1675 | |
| 1676 | /* Return true if mtx bits mean that the access is canonically checked. */ |
| 1677 | static inline bool mtx_check(uint32_t desc, int bit55) |
| 1678 | { |
| 1679 | return (desc >> (R_MTEDESC_MTX_SHIFT + bit55)) & 1; |
| 1680 | } |
| 1681 | |
| 1682 | /* Return true if tbi or mtx bits mean that the access is tag checked. */ |
| 1683 | static inline bool tbi_or_mtx_check(uint32_t desc, int bit55) |
| 1684 | { |
| 1685 | uint32_t mask = (1u << R_MTEDESC_TBI_SHIFT) | (1u << R_MTEDESC_MTX_SHIFT); |
| 1686 | return desc & (mask << bit55); |
| 1687 | } |
| 1688 | |
| 1689 | /* Return whether or not the second nibble of a VA matches bit 55. */ |
| 1690 | static inline bool tag_is_canonical(int ptr_tag, int bit55) |
| 1691 | { |
| 1692 | return ((ptr_tag + bit55) & 0xf) == 0; |
| 1693 | } |
| 1694 | |
| 1695 | /* Return true if tcma bits mean that the access is unchecked. */ |
| 1696 | static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag) |
| 1697 | { |
| 1698 | /* |
| 1699 | * We had extracted bit55 and ptr_tag for other reasons, so fold |
| 1700 | * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test. |
| 1701 | */ |
| 1702 | bool match = tag_is_canonical(ptr_tag, bit55); |
| 1703 | bool tcma = (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1; |
| 1704 | return tcma && match; |
| 1705 | } |
| 1706 | |
| 1707 | /* |
| 1708 | * For TBI, ideally, we would do nothing. Proper behaviour on fault is |
| 1709 | * for the tag to be present in the FAR_ELx register. But for user-only |
| 1710 | * mode, we do not have a TLB with which to implement this, so we must |
| 1711 | * remove the top byte. |
| 1712 | */ |
| 1713 | static inline uint64_t useronly_clean_ptr(uint64_t ptr) |
| 1714 | { |
| 1715 | #ifdef CONFIG_USER_ONLY |
| 1716 | /* TBI0 is known to be enabled, while TBI1 is disabled. */ |
| 1717 | ptr &= sextract64(ptr, 0, 56); |
| 1718 | #endif |
| 1719 | return ptr; |
| 1720 | } |
| 1721 | |
| 1722 | static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr) |
| 1723 | { |
| 1724 | #ifdef CONFIG_USER_ONLY |
| 1725 | int64_t clean_ptr = sextract64(ptr, 0, 56); |
| 1726 | if (tbi_or_mtx_check(desc, clean_ptr < 0)) { |
| 1727 | ptr = clean_ptr; |
| 1728 | } |
| 1729 | #endif |
| 1730 | return ptr; |
| 1731 | } |
| 1732 | |
| 1733 | /* Values for M-profile PSR.ECI for MVE insns */ |
| 1734 | enum MVEECIState { |
| 1735 | ECI_NONE = 0, /* No completed beats */ |
| 1736 | ECI_A0 = 1, /* Completed: A0 */ |
| 1737 | ECI_A0A1 = 2, /* Completed: A0, A1 */ |
| 1738 | /* 3 is reserved */ |
| 1739 | ECI_A0A1A2 = 4, /* Completed: A0, A1, A2 */ |
| 1740 | ECI_A0A1A2B0 = 5, /* Completed: A0, A1, A2, B0 */ |
| 1741 | /* All other values reserved */ |
| 1742 | }; |
| 1743 | |
| 1744 | /* Definitions for the PMU registers */ |
| 1745 | #define PMCRN_MASK 0xf800 |
| 1746 | #define PMCRN_SHIFT 11 |
| 1747 | #define PMCRLP 0x80 |
| 1748 | #define PMCRLC 0x40 |
| 1749 | #define PMCRDP 0x20 |
| 1750 | #define PMCRX 0x10 |
| 1751 | #define PMCRD 0x8 |
| 1752 | #define PMCRC 0x4 |
| 1753 | #define PMCRP 0x2 |
| 1754 | #define PMCRE 0x1 |
| 1755 | /* |
| 1756 | * Mask of PMCR bits writable by guest (not including WO bits like C, P, |
| 1757 | * which can be written as 1 to trigger behaviour but which stay RAZ). |
| 1758 | */ |
| 1759 | #define PMCR_WRITABLE_MASK (PMCRLP | PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) |
| 1760 | |
| 1761 | #define PMXEVTYPER_P 0x80000000 |
| 1762 | #define PMXEVTYPER_U 0x40000000 |
| 1763 | #define PMXEVTYPER_NSK 0x20000000 |
| 1764 | #define PMXEVTYPER_NSU 0x10000000 |
| 1765 | #define PMXEVTYPER_NSH 0x08000000 |
| 1766 | #define PMXEVTYPER_M 0x04000000 |
| 1767 | #define PMXEVTYPER_MT 0x02000000 |
| 1768 | #define PMXEVTYPER_EVTCOUNT 0x0000ffff |
| 1769 | #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ |
| 1770 | PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ |
| 1771 | PMXEVTYPER_M | PMXEVTYPER_MT | \ |
| 1772 | PMXEVTYPER_EVTCOUNT) |
| 1773 | |
| 1774 | #define PMCCFILTR 0xf8000000 |
| 1775 | #define PMCCFILTR_M PMXEVTYPER_M |
| 1776 | #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) |
| 1777 | |
| 1778 | static inline uint32_t pmu_num_counters(CPUARMState *env) |
| 1779 | { |
| 1780 | ARMCPU *cpu = env_archcpu(env); |
| 1781 | |
| 1782 | return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT; |
| 1783 | } |
| 1784 | |
| 1785 | /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ |
| 1786 | static inline uint64_t pmu_counter_mask(CPUARMState *env) |
| 1787 | { |
| 1788 | return (1ULL << 31) | ((1ULL << pmu_num_counters(env)) - 1); |
| 1789 | } |
| 1790 | |
| 1791 | GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); |
| 1792 | GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cpu, int base_reg); |
| 1793 | GDBFeature *arm_gen_dynamic_tls_feature(CPUState *cpu, int base_reg); |
| 1794 | int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); |
| 1795 | int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); |
| 1796 | int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg); |
| 1797 | int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg); |
| 1798 | int aarch64_gdb_get_sme2_reg(CPUState *cs, GByteArray *buf, int reg); |
| 1799 | int aarch64_gdb_set_sme2_reg(CPUState *cs, uint8_t *buf, int reg); |
| 1800 | int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg); |
| 1801 | int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg); |
| 1802 | int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg); |
| 1803 | int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg); |
| 1804 | int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg); |
| 1805 | int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg); |
| 1806 | int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg); |
| 1807 | int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg); |
| 1808 | void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp); |
| 1809 | void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp); |
| 1810 | void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); |
| 1811 | void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); |
| 1812 | void aarch64_max_v8_tcg_initfn(Object *obj); |
| 1813 | void aarch64_max_v9_tcg_initfn(Object *obj); |
| 1814 | void aarch64_add_pauth_properties(Object *obj); |
| 1815 | void aarch64_add_sve_properties(Object *obj); |
| 1816 | void aarch64_add_sme_properties(Object *obj); |
| 1817 | void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa64_enabled); |
| 1818 | void aarch64_host_initfn(Object *obj); |
| 1819 | |
| 1820 | /* Return true if the gdbstub is presenting an AArch64 CPU */ |
| 1821 | static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu) |
| 1822 | { |
| 1823 | return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); |
| 1824 | } |
| 1825 | |
| 1826 | /* Read the CONTROL register as the MRS instruction would. */ |
| 1827 | uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); |
| 1828 | |
| 1829 | /* |
| 1830 | * Return a pointer to the location where we currently store the |
| 1831 | * stack pointer for the requested security state and thread mode. |
| 1832 | * This pointer will become invalid if the CPU state is updated |
| 1833 | * such that the stack pointers are switched around (eg changing |
| 1834 | * the SPSEL control bit). |
| 1835 | */ |
| 1836 | uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, |
| 1837 | bool threadmode, bool spsel); |
| 1838 | |
| 1839 | bool el_is_in_host(CPUARMState *env, int el); |
| 1840 | |
| 1841 | void aa32_max_features(ARMCPU *cpu); |
| 1842 | void aarch32_max_v8_tcg_initfn(Object *obj); |
| 1843 | int exception_target_el(CPUARMState *env); |
| 1844 | bool arm_singlestep_active(CPUARMState *env); |
| 1845 | bool arm_generate_debug_exceptions(CPUARMState *env); |
| 1846 | |
| 1847 | /** |
| 1848 | * pauth_ptr_mask: |
| 1849 | * @param: parameters defining the MMU setup |
| 1850 | * |
| 1851 | * Return a mask of the address bits that contain the authentication code, |
| 1852 | * given the MMU config defined by @param. |
| 1853 | */ |
| 1854 | static inline uint64_t pauth_ptr_mask(ARMVAParameters param) |
| 1855 | { |
| 1856 | int bot_pac_bit = 64 - param.tsz; |
| 1857 | int top_pac_bit = 64 - 8 * param.tbi; |
| 1858 | |
| 1859 | uint64_t mask = MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit); |
| 1860 | |
| 1861 | /* |
| 1862 | * If mtx is enabled, second nibble is not part of PAC. See |
| 1863 | * InsertPAC(). |
| 1864 | */ |
| 1865 | if (param.mtx) { |
| 1866 | mask &= ~MAKE_64BIT_MASK(56, 4); |
| 1867 | } |
| 1868 | |
| 1869 | return mask; |
| 1870 | } |
| 1871 | |
| 1872 | /* Add the cpreg definitions for debug related system registers */ |
| 1873 | void define_debug_regs(ARMCPU *cpu); |
| 1874 | |
| 1875 | /* Add the cpreg definitions for TLBI instructions */ |
| 1876 | void define_tlb_insn_regs(ARMCPU *cpu); |
| 1877 | /* Add the cpreg definitions for AT instructions */ |
| 1878 | void define_at_insn_regs(ARMCPU *cpu); |
| 1879 | /* Add the cpreg definitions for PM cpregs */ |
| 1880 | void define_pm_cpregs(ARMCPU *cpu); |
| 1881 | /* Add the cpreg definitions for GCS cpregs */ |
| 1882 | void define_gcs_cpregs(ARMCPU *cpu); |
| 1883 | /* Add the cpreg definitions for OMAP CP15 regs */ |
| 1884 | void define_omap_cp_regs(ARMCPU *cpu); |
| 1885 | |
| 1886 | /* Add the cpreg definitions for the GICv5 CPU interface */ |
| 1887 | void define_gicv5_cpuif_regs(ARMCPU *cpu); |
| 1888 | |
| 1889 | /* |
| 1890 | * Update the state of the given GICv5 PPI for this CPU. Does nothing |
| 1891 | * if the GICv5 is not present. |
| 1892 | */ |
| 1893 | void gicv5_update_ppi_state(CPUARMState *env, int ppi, bool level); |
| 1894 | |
| 1895 | /* Effective value of MDCR_EL2 */ |
| 1896 | static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) |
| 1897 | { |
| 1898 | return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; |
| 1899 | } |
| 1900 | |
| 1901 | /* Powers of 2 for sve_vq_map et al. */ |
| 1902 | #define SVE_VQ_POW2_MAP \ |
| 1903 | ((1 << (1 - 1)) | (1 << (2 - 1)) | \ |
| 1904 | (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) |
| 1905 | |
| 1906 | /* |
| 1907 | * Return the maximum SVE/SME VQ for this CPU. This defines |
| 1908 | * the maximum possible size of the Zn vector registers. |
| 1909 | */ |
| 1910 | static inline int arm_max_vq(ARMCPU *cpu) |
| 1911 | { |
| 1912 | return MAX(cpu->sve_max_vq, cpu->sme_max_vq); |
| 1913 | } |
| 1914 | |
| 1915 | /* |
| 1916 | * Return true if it is possible to take a fine-grained-trap to EL2. |
| 1917 | */ |
| 1918 | static inline bool arm_fgt_active(CPUARMState *env, int el) |
| 1919 | { |
| 1920 | /* |
| 1921 | * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps |
| 1922 | * that can affect EL0, but it is harmless to do the test also for |
| 1923 | * traps on registers that are only accessible at EL1 because if the test |
| 1924 | * returns true then we can't be executing at EL1 anyway. |
| 1925 | * FGT traps only happen when EL2 is enabled and EL1 is AArch64; |
| 1926 | * traps from AArch32 only happen for the EL0 is AArch32 case. |
| 1927 | */ |
| 1928 | return cpu_isar_feature(aa64_fgt, env_archcpu(env)) && |
| 1929 | el < 2 && arm_is_el2_enabled(env) && |
| 1930 | arm_el_is_aa64(env, 1) && |
| 1931 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE) && |
| 1932 | (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN)); |
| 1933 | } |
| 1934 | |
| 1935 | /* |
| 1936 | * Although the ARM implementation of hardware assisted debugging |
| 1937 | * allows for different breakpoints per-core, the current GDB |
| 1938 | * interface treats them as a global pool of registers (which seems to |
| 1939 | * be the case for x86, ppc and s390). As a result we store one copy |
| 1940 | * of registers which is used for all active cores. |
| 1941 | * |
| 1942 | * Write access is serialised by virtue of the GDB protocol which |
| 1943 | * updates things. Read access (i.e. when the values are copied to the |
| 1944 | * vCPU) is also gated by GDB's run control. |
| 1945 | * |
| 1946 | * This is not unreasonable as most of the time debugging kernels you |
| 1947 | * never know which core will eventually execute your function. |
| 1948 | */ |
| 1949 | |
| 1950 | typedef struct { |
| 1951 | uint64_t bcr; |
| 1952 | uint64_t bvr; |
| 1953 | } HWBreakpoint; |
| 1954 | |
| 1955 | /* |
| 1956 | * The watchpoint registers can cover more area than the requested |
| 1957 | * watchpoint so we need to store the additional information |
| 1958 | * somewhere. We also need to supply a CPUWatchpoint to the GDB stub |
| 1959 | * when the watchpoint is hit. |
| 1960 | */ |
| 1961 | typedef struct { |
| 1962 | uint64_t wcr; |
| 1963 | uint64_t wvr; |
| 1964 | CPUWatchpoint details; |
| 1965 | } HWWatchpoint; |
| 1966 | |
| 1967 | /* Maximum and current break/watch point counts */ |
| 1968 | extern int max_hw_bps, max_hw_wps; |
| 1969 | extern GArray *hw_breakpoints, *hw_watchpoints; |
| 1970 | |
| 1971 | #define cur_hw_wps (hw_watchpoints->len) |
| 1972 | #define cur_hw_bps (hw_breakpoints->len) |
| 1973 | #define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i)) |
| 1974 | #define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i)) |
| 1975 | |
| 1976 | bool find_hw_breakpoint(CPUState *cpu, vaddr pc); |
| 1977 | int insert_hw_breakpoint(vaddr pc); |
| 1978 | int delete_hw_breakpoint(vaddr pc); |
| 1979 | |
| 1980 | bool check_watchpoint_in_range(int i, vaddr addr); |
| 1981 | CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, vaddr addr); |
| 1982 | int insert_gdbstub_hw_watchpoint(vaddr addr, vaddr len, GdbBreakpointType type); |
| 1983 | int delete_gdbstub_hw_watchpoint(vaddr addr, vaddr len, GdbBreakpointType type); |
| 1984 | |
| 1985 | /* Return the current value of the system counter in ticks */ |
| 1986 | uint64_t gt_get_countervalue(CPUARMState *env); |
| 1987 | /* |
| 1988 | * Return the currently applicable offset between the system counter |
| 1989 | * and the counter for the specified timer, as used for direct register |
| 1990 | * accesses. |
| 1991 | */ |
| 1992 | uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx); |
| 1993 | |
| 1994 | /* |
| 1995 | * Return mask of ARMMMUIdxBit values corresponding to an "invalidate |
| 1996 | * all EL1" scope; this covers stage 1 and stage 2. |
| 1997 | */ |
| 1998 | int alle1_tlbmask(CPUARMState *env); |
| 1999 | /* |
| 2000 | * Return mask of ARMMMUIdxBit values corresponding to an "invalidate |
| 2001 | * all EL2&0" scope. |
| 2002 | */ |
| 2003 | int alle2_tlbmask(void); |
| 2004 | |
| 2005 | /* Set the float_status behaviour to match the Arm defaults */ |
| 2006 | void arm_set_default_fp_behaviours(float_status *s); |
| 2007 | /* Set the float_status behaviour to match Arm FPCR.AH=1 behaviour */ |
| 2008 | void arm_set_ah_fp_behaviours(float_status *s); |
| 2009 | /* Read the float_status info and return the appropriate FPSR value */ |
| 2010 | uint32_t vfp_get_fpsr_from_host(CPUARMState *env); |
| 2011 | /* Clear the exception status flags from all float_status fields */ |
| 2012 | void vfp_clear_float_status_exc_flags(CPUARMState *env); |
| 2013 | /* |
| 2014 | * Update float_status fields to handle the bits of the FPCR |
| 2015 | * specified by mask changing to the values in val. |
| 2016 | */ |
| 2017 | void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask); |
| 2018 | bool arm_pan_enabled(CPUARMState *env); |
| 2019 | uint32_t cpsr_read_for_spsr_elx(CPUARMState *env); |
| 2020 | void cpsr_write_from_spsr_elx(CPUARMState *env, uint32_t val); |
| 2021 | |
| 2022 | /* Compare uint64_t for qsort and bsearch. */ |
| 2023 | int compare_u64(const void *a, const void *b); |
| 2024 | |
| 2025 | /* Used in FEAT_MEC to set the MECIDWidthm1 field in the MECIDR_EL2 register. */ |
| 2026 | #define MECID_WIDTH 16 |
| 2027 | |
| 2028 | typedef enum { |
| 2029 | ToleranceNotOnBothEnds, |
| 2030 | ToleranceOnlySrcTestValue, |
| 2031 | ToleranceDiffInMask, |
| 2032 | ToleranceFieldLT, |
| 2033 | ToleranceFieldGT, |
| 2034 | } ARMCPRegMigToleranceType; |
| 2035 | |
| 2036 | typedef struct ARMCPRegMigTolerance { |
| 2037 | uint64_t kvmidx; |
| 2038 | uint64_t mask; |
| 2039 | uint64_t value; |
| 2040 | ARMCPRegMigToleranceType type; |
| 2041 | QLIST_ENTRY(ARMCPRegMigTolerance) node; |
| 2042 | } ARMCPRegMigTolerance; |
| 2043 | |
| 2044 | /** |
| 2045 | * arm_register_cpreg_mig_tolerance: |
| 2046 | * Register a migration tolerance wrt one given cpreg identified by its |
| 2047 | * @kvmidx. Calling this function twice for the same @kvmidx is a |
| 2048 | * programming error and will cause an assertion failure. |
| 2049 | * |
| 2050 | * @cpu: vcpu to apply the migration tolerance on |
| 2051 | * @kvmidx: kvm index of the cpreg the tolerance applies to |
| 2052 | * @mask: bitmask where a difference is tolerated |
| 2053 | * (relevant with ToleranceDiffInMask) |
| 2054 | * @value: value the bitmask field is compared with |
| 2055 | * (relevant with ToleranceFieldLT and ToleranceFieldGT) |
| 2056 | * @type: type of the migration tolerance: |
| 2057 | * - ToleranceNotOnBothEnds (cpreg index is allowed to be only present |
| 2058 | * on one end) |
| 2059 | * - ToleranceOnlySrcTestValue (cpreg index is allowed to be only |
| 2060 | * present in source if its value @mask field matches @value) |
| 2061 | * - ToleranceDiffInMask (mismatch in cpreg values are only tolerated |
| 2062 | * if differences are within @mask) |
| 2063 | * - ToleranceFieldLT (mismatch in cpreg values are only tolerated |
| 2064 | * if incoming @bitmask field value is less than @value) |
| 2065 | * - ToleranceFieldGT (mismatch in cpreg values are only tolerated |
| 2066 | * if incoming @bitmask field value is greater than @value) |
| 2067 | */ |
| 2068 | void arm_register_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx, |
| 2069 | uint64_t mask, uint64_t value, |
| 2070 | ARMCPRegMigToleranceType type); |
| 2071 | |
| 2072 | /** |
| 2073 | * arm_cpu_match_cpreg_mig_tolerance: |
| 2074 | * Check whether a tolerance of type @type exists for a given @kvmidx |
| 2075 | * and the tolerance criterion is satisfied |
| 2076 | */ |
| 2077 | bool arm_cpu_match_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx, |
| 2078 | uint64_t vmstate_value, uint64_t local_value, |
| 2079 | ARMCPRegMigToleranceType type); |
| 2080 | |
| 2081 | |
| 2082 | /** |
| 2083 | * arm_set_cpu_power_state() - set power state synced with halt_reason |
| 2084 | */ |
| 2085 | static inline void arm_set_cpu_power_state(ARMCPU *cpu, ARMPSCIState state) |
| 2086 | { |
| 2087 | CPUARMState *env = &cpu->env; |
| 2088 | |
| 2089 | cpu->power_state = state; |
| 2090 | env->halt_reason = state == PSCI_OFF ? HALT_PSCI : NOT_HALTED; |
| 2091 | } |
| 2092 | |
| 2093 | #endif |