| 1 | /* |
| 2 | * KVM ARM ABI constant definitions |
| 3 | * |
| 4 | * Copyright (c) 2013 Linaro Limited |
| 5 | * |
| 6 | * Provide versions of KVM constant defines that can be used even |
| 7 | * when CONFIG_KVM is not set and we don't have access to the |
| 8 | * KVM headers. If CONFIG_KVM is set, we do a compile-time check |
| 9 | * that we haven't got out of sync somehow. |
| 10 | * |
| 11 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 12 | * See the COPYING file in the top-level directory. |
| 13 | */ |
| 14 | #ifndef ARM_KVM_CONSTS_H |
| 15 | #define ARM_KVM_CONSTS_H |
| 16 | |
| 17 | #ifdef COMPILING_PER_TARGET |
| 18 | #ifdef CONFIG_KVM |
| 19 | #include <linux/kvm.h> |
| 20 | #include <linux/psci.h> |
| 21 | #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y) |
| 22 | #endif |
| 23 | #endif /* COMPILING_PER_TARGET */ |
| 24 | |
| 25 | #ifndef MISMATCH_CHECK |
| 26 | #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0) |
| 27 | #endif |
| 28 | |
| 29 | #define CP_REG_SIZE_SHIFT 52 |
| 30 | #define CP_REG_SIZE_MASK 0x00f0000000000000ULL |
| 31 | #define CP_REG_SIZE_U32 0x0020000000000000ULL |
| 32 | #define CP_REG_SIZE_U64 0x0030000000000000ULL |
| 33 | #define CP_REG_ARM 0x4000000000000000ULL |
| 34 | #define CP_REG_ARCH_MASK 0xff00000000000000ULL |
| 35 | |
| 36 | MISMATCH_CHECK(CP_REG_SIZE_SHIFT, KVM_REG_SIZE_SHIFT); |
| 37 | MISMATCH_CHECK(CP_REG_SIZE_MASK, KVM_REG_SIZE_MASK); |
| 38 | MISMATCH_CHECK(CP_REG_SIZE_U32, KVM_REG_SIZE_U32); |
| 39 | MISMATCH_CHECK(CP_REG_SIZE_U64, KVM_REG_SIZE_U64); |
| 40 | MISMATCH_CHECK(CP_REG_ARM, KVM_REG_ARM); |
| 41 | MISMATCH_CHECK(CP_REG_ARCH_MASK, KVM_REG_ARCH_MASK); |
| 42 | |
| 43 | #define QEMU_PSCI_0_1_FN_BASE 0x95c1ba5e |
| 44 | #define QEMU_PSCI_0_1_FN(n) (QEMU_PSCI_0_1_FN_BASE + (n)) |
| 45 | #define QEMU_PSCI_0_1_FN_CPU_SUSPEND QEMU_PSCI_0_1_FN(0) |
| 46 | #define QEMU_PSCI_0_1_FN_CPU_OFF QEMU_PSCI_0_1_FN(1) |
| 47 | #define QEMU_PSCI_0_1_FN_CPU_ON QEMU_PSCI_0_1_FN(2) |
| 48 | #define QEMU_PSCI_0_1_FN_MIGRATE QEMU_PSCI_0_1_FN(3) |
| 49 | |
| 50 | MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_SUSPEND, KVM_PSCI_FN_CPU_SUSPEND); |
| 51 | MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_OFF, KVM_PSCI_FN_CPU_OFF); |
| 52 | MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_ON, KVM_PSCI_FN_CPU_ON); |
| 53 | MISMATCH_CHECK(QEMU_PSCI_0_1_FN_MIGRATE, KVM_PSCI_FN_MIGRATE); |
| 54 | |
| 55 | #define QEMU_PSCI_0_2_FN_BASE 0x84000000 |
| 56 | #define QEMU_PSCI_0_2_FN(n) (QEMU_PSCI_0_2_FN_BASE + (n)) |
| 57 | |
| 58 | #define QEMU_PSCI_0_2_64BIT 0x40000000 |
| 59 | #define QEMU_PSCI_0_2_FN64_BASE \ |
| 60 | (QEMU_PSCI_0_2_FN_BASE + QEMU_PSCI_0_2_64BIT) |
| 61 | #define QEMU_PSCI_0_2_FN64(n) (QEMU_PSCI_0_2_FN64_BASE + (n)) |
| 62 | |
| 63 | #define QEMU_PSCI_0_2_FN_PSCI_VERSION QEMU_PSCI_0_2_FN(0) |
| 64 | #define QEMU_PSCI_0_2_FN_CPU_SUSPEND QEMU_PSCI_0_2_FN(1) |
| 65 | #define QEMU_PSCI_0_2_FN_CPU_OFF QEMU_PSCI_0_2_FN(2) |
| 66 | #define QEMU_PSCI_0_2_FN_CPU_ON QEMU_PSCI_0_2_FN(3) |
| 67 | #define QEMU_PSCI_0_2_FN_AFFINITY_INFO QEMU_PSCI_0_2_FN(4) |
| 68 | #define QEMU_PSCI_0_2_FN_MIGRATE QEMU_PSCI_0_2_FN(5) |
| 69 | #define QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE QEMU_PSCI_0_2_FN(6) |
| 70 | #define QEMU_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU QEMU_PSCI_0_2_FN(7) |
| 71 | #define QEMU_PSCI_0_2_FN_SYSTEM_OFF QEMU_PSCI_0_2_FN(8) |
| 72 | #define QEMU_PSCI_0_2_FN_SYSTEM_RESET QEMU_PSCI_0_2_FN(9) |
| 73 | |
| 74 | #define QEMU_PSCI_0_2_FN64_CPU_SUSPEND QEMU_PSCI_0_2_FN64(1) |
| 75 | #define QEMU_PSCI_0_2_FN64_CPU_OFF QEMU_PSCI_0_2_FN64(2) |
| 76 | #define QEMU_PSCI_0_2_FN64_CPU_ON QEMU_PSCI_0_2_FN64(3) |
| 77 | #define QEMU_PSCI_0_2_FN64_AFFINITY_INFO QEMU_PSCI_0_2_FN64(4) |
| 78 | #define QEMU_PSCI_0_2_FN64_MIGRATE QEMU_PSCI_0_2_FN64(5) |
| 79 | |
| 80 | #define QEMU_PSCI_1_0_FN_PSCI_FEATURES QEMU_PSCI_0_2_FN(10) |
| 81 | |
| 82 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_SUSPEND, PSCI_0_2_FN_CPU_SUSPEND); |
| 83 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_OFF, PSCI_0_2_FN_CPU_OFF); |
| 84 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_ON, PSCI_0_2_FN_CPU_ON); |
| 85 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE, PSCI_0_2_FN_MIGRATE); |
| 86 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_SUSPEND, PSCI_0_2_FN64_CPU_SUSPEND); |
| 87 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_ON, PSCI_0_2_FN64_CPU_ON); |
| 88 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE, PSCI_0_2_FN64_MIGRATE); |
| 89 | MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_FN_PSCI_FEATURES); |
| 90 | |
| 91 | /* PSCI v0.2 return values used by TCG emulation of PSCI */ |
| 92 | |
| 93 | /* No Trusted OS migration to worry about when offlining CPUs */ |
| 94 | #define QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED 2 |
| 95 | |
| 96 | #define QEMU_PSCI_VERSION_0_1 0x00001 |
| 97 | #define QEMU_PSCI_VERSION_0_2 0x00002 |
| 98 | #define QEMU_PSCI_VERSION_1_0 0x10000 |
| 99 | #define QEMU_PSCI_VERSION_1_1 0x10001 |
| 100 | #define QEMU_PSCI_VERSION_1_2 0x10002 |
| 101 | #define QEMU_PSCI_VERSION_1_3 0x10003 |
| 102 | |
| 103 | MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP); |
| 104 | /* We don't bother to check every possible version value */ |
| 105 | MISMATCH_CHECK(QEMU_PSCI_VERSION_0_2, PSCI_VERSION(0, 2)); |
| 106 | MISMATCH_CHECK(QEMU_PSCI_VERSION_1_1, PSCI_VERSION(1, 1)); |
| 107 | |
| 108 | /* PSCI return values (inclusive of all PSCI versions) */ |
| 109 | #define QEMU_PSCI_RET_SUCCESS 0 |
| 110 | #define QEMU_PSCI_RET_NOT_SUPPORTED -1 |
| 111 | #define QEMU_PSCI_RET_INVALID_PARAMS -2 |
| 112 | #define QEMU_PSCI_RET_DENIED -3 |
| 113 | #define QEMU_PSCI_RET_ALREADY_ON -4 |
| 114 | #define QEMU_PSCI_RET_ON_PENDING -5 |
| 115 | #define QEMU_PSCI_RET_INTERNAL_FAILURE -6 |
| 116 | #define QEMU_PSCI_RET_NOT_PRESENT -7 |
| 117 | #define QEMU_PSCI_RET_DISABLED -8 |
| 118 | |
| 119 | MISMATCH_CHECK(QEMU_PSCI_RET_SUCCESS, PSCI_RET_SUCCESS); |
| 120 | MISMATCH_CHECK(QEMU_PSCI_RET_NOT_SUPPORTED, PSCI_RET_NOT_SUPPORTED); |
| 121 | MISMATCH_CHECK(QEMU_PSCI_RET_INVALID_PARAMS, PSCI_RET_INVALID_PARAMS); |
| 122 | MISMATCH_CHECK(QEMU_PSCI_RET_DENIED, PSCI_RET_DENIED); |
| 123 | MISMATCH_CHECK(QEMU_PSCI_RET_ALREADY_ON, PSCI_RET_ALREADY_ON); |
| 124 | MISMATCH_CHECK(QEMU_PSCI_RET_ON_PENDING, PSCI_RET_ON_PENDING); |
| 125 | MISMATCH_CHECK(QEMU_PSCI_RET_INTERNAL_FAILURE, PSCI_RET_INTERNAL_FAILURE); |
| 126 | MISMATCH_CHECK(QEMU_PSCI_RET_NOT_PRESENT, PSCI_RET_NOT_PRESENT); |
| 127 | MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED); |
| 128 | |
| 129 | /* |
| 130 | * Note that KVM uses overlapping values for AArch32 and AArch64 |
| 131 | * target CPU numbers. AArch64 targets: |
| 132 | */ |
| 133 | #define QEMU_KVM_ARM_TARGET_AEM_V8 0 |
| 134 | #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1 |
| 135 | #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 |
| 136 | #define QEMU_KVM_ARM_TARGET_XGENE_POTENZA 3 |
| 137 | #define QEMU_KVM_ARM_TARGET_CORTEX_A53 4 |
| 138 | |
| 139 | /* There's no kernel define for this: sentinel value which |
| 140 | * matches no KVM target value for either 64 or 32 bit |
| 141 | */ |
| 142 | #define QEMU_KVM_ARM_TARGET_NONE UINT_MAX |
| 143 | |
| 144 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8); |
| 145 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8); |
| 146 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57); |
| 147 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA); |
| 148 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53); |
| 149 | |
| 150 | #define CP_REG_ARM64 0x6000000000000000ULL |
| 151 | #define CP_REG_ARM_COPROC_MASK 0x000000000FFF0000 |
| 152 | #define CP_REG_ARM_COPROC_SHIFT 16 |
| 153 | #define CP_REG_ARM64_SYSREG (0x0013 << CP_REG_ARM_COPROC_SHIFT) |
| 154 | #define CP_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 |
| 155 | #define CP_REG_ARM64_SYSREG_OP0_SHIFT 14 |
| 156 | #define CP_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 |
| 157 | #define CP_REG_ARM64_SYSREG_OP1_SHIFT 11 |
| 158 | #define CP_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 |
| 159 | #define CP_REG_ARM64_SYSREG_CRN_SHIFT 7 |
| 160 | #define CP_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 |
| 161 | #define CP_REG_ARM64_SYSREG_CRM_SHIFT 3 |
| 162 | #define CP_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 |
| 163 | #define CP_REG_ARM64_SYSREG_OP2_SHIFT 0 |
| 164 | |
| 165 | MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64); |
| 166 | MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK); |
| 167 | MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT); |
| 168 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG, KVM_REG_ARM64_SYSREG); |
| 169 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_MASK); |
| 170 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_SHIFT, KVM_REG_ARM64_SYSREG_OP0_SHIFT); |
| 171 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_MASK, KVM_REG_ARM64_SYSREG_OP1_MASK); |
| 172 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_SHIFT, KVM_REG_ARM64_SYSREG_OP1_SHIFT); |
| 173 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_MASK, KVM_REG_ARM64_SYSREG_CRN_MASK); |
| 174 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_SHIFT, KVM_REG_ARM64_SYSREG_CRN_SHIFT); |
| 175 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_MASK, KVM_REG_ARM64_SYSREG_CRM_MASK); |
| 176 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRM_SHIFT); |
| 177 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_MASK); |
| 178 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_ARM64_SYSREG_OP2_SHIFT); |
| 179 | |
| 180 | #undef MISMATCH_CHECK |
| 181 | |
| 182 | #define KVMID_AA64_SYS_REG_(op0, op1, crn, crm, op2) \ |
| 183 | (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \ |
| 184 | ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ |
| 185 | ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ |
| 186 | ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ |
| 187 | ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ |
| 188 | ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) |
| 189 | |
| 190 | #define KVMID_AA64_SYS_REG64(op0, op1, crn, crm, op2) \ |
| 191 | (KVMID_AA64_SYS_REG_(op0, op1, crn, crm, op2) | CP_REG_SIZE_U64) |
| 192 | |
| 193 | #endif |