| 1 | #include "qemu/osdep.h" |
| 2 | #include "cpu.h" |
| 3 | #include "cpregs.h" |
| 4 | #include "trace.h" |
| 5 | #include "qemu/error-report.h" |
| 6 | #include "system/hvf.h" |
| 7 | #include "system/tcg.h" |
| 8 | #include "kvm_arm.h" |
| 9 | #include "internals.h" |
| 10 | #include "cpu-features.h" |
| 11 | #include "migration/qemu-file-types.h" |
| 12 | #include "migration/vmstate.h" |
| 13 | #include "target/arm/gtimer.h" |
| 14 | #include "hw/arm/machines-qom.h" |
| 15 | |
| 16 | static bool vfp_needed(void *opaque) |
| 17 | { |
| 18 | ARMCPU *cpu = opaque; |
| 19 | |
| 20 | return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) |
| 21 | ? cpu_isar_feature(aa64_fp_simd, cpu) |
| 22 | : cpu_isar_feature(aa32_vfp_simd, cpu)); |
| 23 | } |
| 24 | |
| 25 | static bool vfp_fpcr_fpsr_needed(void *opaque) |
| 26 | { |
| 27 | /* |
| 28 | * If either the FPCR or the FPSR include set bits that are not |
| 29 | * visible in the AArch32 FPSCR view of floating point control/status |
| 30 | * then we must send the FPCR and FPSR as two separate fields in the |
| 31 | * cpu/vfp/fpcr_fpsr subsection, and we will send a 0 for the old |
| 32 | * FPSCR field in cpu/vfp. |
| 33 | * |
| 34 | * If all the set bits are representable in an AArch32 FPSCR then we |
| 35 | * send that value as the cpu/vfp FPSCR field, and don't send the |
| 36 | * cpu/vfp/fpcr_fpsr subsection. |
| 37 | * |
| 38 | * On incoming migration, if the cpu/vfp FPSCR field is non-zero we |
| 39 | * use it, and if the fpcr_fpsr subsection is present we use that. |
| 40 | * (The subsection will never be present with a non-zero FPSCR field, |
| 41 | * and if FPSCR is zero and the subsection is not present that means |
| 42 | * that FPSCR/FPSR/FPCR are zero.) |
| 43 | * |
| 44 | * This preserves migration compatibility with older QEMU versions, |
| 45 | * in both directions. |
| 46 | */ |
| 47 | ARMCPU *cpu = opaque; |
| 48 | CPUARMState *env = &cpu->env; |
| 49 | |
| 50 | return (vfp_get_fpcr(env) & ~FPSCR_FPCR_MASK) || |
| 51 | (vfp_get_fpsr(env) & ~FPSCR_FPSR_MASK); |
| 52 | } |
| 53 | |
| 54 | static int get_fpscr(QEMUFile *f, void *opaque, size_t size, |
| 55 | const VMStateField *field) |
| 56 | { |
| 57 | ARMCPU *cpu = opaque; |
| 58 | CPUARMState *env = &cpu->env; |
| 59 | uint32_t val = qemu_get_be32(f); |
| 60 | |
| 61 | if (val) { |
| 62 | /* 0 means we might have the data in the fpcr_fpsr subsection */ |
| 63 | vfp_set_fpscr(env, val); |
| 64 | } |
| 65 | return 0; |
| 66 | } |
| 67 | |
| 68 | static int put_fpscr(QEMUFile *f, void *opaque, size_t size, |
| 69 | const VMStateField *field, JSONWriter *vmdesc) |
| 70 | { |
| 71 | ARMCPU *cpu = opaque; |
| 72 | CPUARMState *env = &cpu->env; |
| 73 | uint32_t fpscr = vfp_fpcr_fpsr_needed(opaque) ? 0 : vfp_get_fpscr(env); |
| 74 | |
| 75 | qemu_put_be32(f, fpscr); |
| 76 | return 0; |
| 77 | } |
| 78 | |
| 79 | static const VMStateInfo vmstate_fpscr = { |
| 80 | .name = "fpscr", |
| 81 | .get = get_fpscr, |
| 82 | .put = put_fpscr, |
| 83 | }; |
| 84 | |
| 85 | static int get_fpcr(QEMUFile *f, void *opaque, size_t size, |
| 86 | const VMStateField *field) |
| 87 | { |
| 88 | ARMCPU *cpu = opaque; |
| 89 | CPUARMState *env = &cpu->env; |
| 90 | uint64_t val = qemu_get_be64(f); |
| 91 | |
| 92 | vfp_set_fpcr(env, val); |
| 93 | return 0; |
| 94 | } |
| 95 | |
| 96 | static int put_fpcr(QEMUFile *f, void *opaque, size_t size, |
| 97 | const VMStateField *field, JSONWriter *vmdesc) |
| 98 | { |
| 99 | ARMCPU *cpu = opaque; |
| 100 | CPUARMState *env = &cpu->env; |
| 101 | |
| 102 | qemu_put_be64(f, vfp_get_fpcr(env)); |
| 103 | return 0; |
| 104 | } |
| 105 | |
| 106 | static const VMStateInfo vmstate_fpcr = { |
| 107 | .name = "fpcr", |
| 108 | .get = get_fpcr, |
| 109 | .put = put_fpcr, |
| 110 | }; |
| 111 | |
| 112 | static int get_fpsr(QEMUFile *f, void *opaque, size_t size, |
| 113 | const VMStateField *field) |
| 114 | { |
| 115 | ARMCPU *cpu = opaque; |
| 116 | CPUARMState *env = &cpu->env; |
| 117 | uint64_t val = qemu_get_be64(f); |
| 118 | |
| 119 | vfp_set_fpsr(env, val); |
| 120 | return 0; |
| 121 | } |
| 122 | |
| 123 | static int put_fpsr(QEMUFile *f, void *opaque, size_t size, |
| 124 | const VMStateField *field, JSONWriter *vmdesc) |
| 125 | { |
| 126 | ARMCPU *cpu = opaque; |
| 127 | CPUARMState *env = &cpu->env; |
| 128 | |
| 129 | qemu_put_be64(f, vfp_get_fpsr(env)); |
| 130 | return 0; |
| 131 | } |
| 132 | |
| 133 | static const VMStateInfo vmstate_fpsr = { |
| 134 | .name = "fpsr", |
| 135 | .get = get_fpsr, |
| 136 | .put = put_fpsr, |
| 137 | }; |
| 138 | |
| 139 | static const VMStateDescription vmstate_vfp_fpcr_fpsr = { |
| 140 | .name = "cpu/vfp/fpcr_fpsr", |
| 141 | .version_id = 1, |
| 142 | .minimum_version_id = 1, |
| 143 | .needed = vfp_fpcr_fpsr_needed, |
| 144 | .fields = (const VMStateField[]) { |
| 145 | { |
| 146 | .name = "fpcr", |
| 147 | .version_id = 0, |
| 148 | .size = sizeof(uint64_t), |
| 149 | .info = &vmstate_fpcr, |
| 150 | .flags = VMS_SINGLE, |
| 151 | .offset = 0, |
| 152 | }, |
| 153 | { |
| 154 | .name = "fpsr", |
| 155 | .version_id = 0, |
| 156 | .size = sizeof(uint64_t), |
| 157 | .info = &vmstate_fpsr, |
| 158 | .flags = VMS_SINGLE, |
| 159 | .offset = 0, |
| 160 | }, |
| 161 | VMSTATE_END_OF_LIST() |
| 162 | }, |
| 163 | }; |
| 164 | |
| 165 | static const VMStateDescription vmstate_vfp = { |
| 166 | .name = "cpu/vfp", |
| 167 | .version_id = 3, |
| 168 | .minimum_version_id = 3, |
| 169 | .needed = vfp_needed, |
| 170 | .fields = (const VMStateField[]) { |
| 171 | /* For compatibility, store Qn out of Zn here. */ |
| 172 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2), |
| 173 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[1].d, ARMCPU, 0, 2), |
| 174 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[2].d, ARMCPU, 0, 2), |
| 175 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[3].d, ARMCPU, 0, 2), |
| 176 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[4].d, ARMCPU, 0, 2), |
| 177 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[5].d, ARMCPU, 0, 2), |
| 178 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[6].d, ARMCPU, 0, 2), |
| 179 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[7].d, ARMCPU, 0, 2), |
| 180 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[8].d, ARMCPU, 0, 2), |
| 181 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[9].d, ARMCPU, 0, 2), |
| 182 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[10].d, ARMCPU, 0, 2), |
| 183 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[11].d, ARMCPU, 0, 2), |
| 184 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[12].d, ARMCPU, 0, 2), |
| 185 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[13].d, ARMCPU, 0, 2), |
| 186 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[14].d, ARMCPU, 0, 2), |
| 187 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[15].d, ARMCPU, 0, 2), |
| 188 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[16].d, ARMCPU, 0, 2), |
| 189 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[17].d, ARMCPU, 0, 2), |
| 190 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[18].d, ARMCPU, 0, 2), |
| 191 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[19].d, ARMCPU, 0, 2), |
| 192 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[20].d, ARMCPU, 0, 2), |
| 193 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[21].d, ARMCPU, 0, 2), |
| 194 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[22].d, ARMCPU, 0, 2), |
| 195 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[23].d, ARMCPU, 0, 2), |
| 196 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[24].d, ARMCPU, 0, 2), |
| 197 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[25].d, ARMCPU, 0, 2), |
| 198 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[26].d, ARMCPU, 0, 2), |
| 199 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[27].d, ARMCPU, 0, 2), |
| 200 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[28].d, ARMCPU, 0, 2), |
| 201 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[29].d, ARMCPU, 0, 2), |
| 202 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[30].d, ARMCPU, 0, 2), |
| 203 | VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[31].d, ARMCPU, 0, 2), |
| 204 | |
| 205 | /* The xregs array is a little awkward because element 1 (FPSCR) |
| 206 | * requires a specific accessor, so we have to split it up in |
| 207 | * the vmstate: |
| 208 | */ |
| 209 | VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), |
| 210 | VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), |
| 211 | { |
| 212 | .name = "fpscr", |
| 213 | .version_id = 0, |
| 214 | .size = sizeof(uint32_t), |
| 215 | .info = &vmstate_fpscr, |
| 216 | .flags = VMS_SINGLE, |
| 217 | .offset = 0, |
| 218 | }, |
| 219 | VMSTATE_END_OF_LIST() |
| 220 | }, |
| 221 | .subsections = (const VMStateDescription * const []) { |
| 222 | &vmstate_vfp_fpcr_fpsr, |
| 223 | NULL |
| 224 | } |
| 225 | }; |
| 226 | |
| 227 | /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, |
| 228 | * and ARMPredicateReg is actively empty. This triggers errors |
| 229 | * in the expansion of the VMSTATE macros. |
| 230 | */ |
| 231 | |
| 232 | static bool sve_needed(void *opaque) |
| 233 | { |
| 234 | ARMCPU *cpu = opaque; |
| 235 | |
| 236 | return cpu_isar_feature(aa64_sve, cpu) || cpu_isar_feature(aa64_sme, cpu); |
| 237 | } |
| 238 | |
| 239 | /* The first two words of each Zreg is stored in VFP state. */ |
| 240 | static const VMStateDescription vmstate_zreg_hi_reg = { |
| 241 | .name = "cpu/sve/zreg_hi", |
| 242 | .version_id = 1, |
| 243 | .minimum_version_id = 1, |
| 244 | .fields = (const VMStateField[]) { |
| 245 | VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2), |
| 246 | VMSTATE_END_OF_LIST() |
| 247 | } |
| 248 | }; |
| 249 | |
| 250 | static const VMStateDescription vmstate_preg_reg = { |
| 251 | .name = "cpu/sve/preg", |
| 252 | .version_id = 1, |
| 253 | .minimum_version_id = 1, |
| 254 | .fields = (const VMStateField[]) { |
| 255 | VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8), |
| 256 | VMSTATE_END_OF_LIST() |
| 257 | } |
| 258 | }; |
| 259 | |
| 260 | static const VMStateDescription vmstate_sve = { |
| 261 | .name = "cpu/sve", |
| 262 | .version_id = 1, |
| 263 | .minimum_version_id = 1, |
| 264 | .needed = sve_needed, |
| 265 | .fields = (const VMStateField[]) { |
| 266 | VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0, |
| 267 | vmstate_zreg_hi_reg, ARMVectorReg), |
| 268 | VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0, |
| 269 | vmstate_preg_reg, ARMPredicateReg), |
| 270 | VMSTATE_END_OF_LIST() |
| 271 | } |
| 272 | }; |
| 273 | |
| 274 | static const VMStateDescription vmstate_vreg = { |
| 275 | .name = "vreg", |
| 276 | .version_id = 1, |
| 277 | .minimum_version_id = 1, |
| 278 | .fields = (const VMStateField[]) { |
| 279 | VMSTATE_UINT64_ARRAY(d, ARMVectorReg, ARM_MAX_VQ * 2), |
| 280 | VMSTATE_END_OF_LIST() |
| 281 | } |
| 282 | }; |
| 283 | |
| 284 | static bool za_needed(void *opaque) |
| 285 | { |
| 286 | ARMCPU *cpu = opaque; |
| 287 | |
| 288 | /* |
| 289 | * When ZA storage is disabled, its contents are discarded. |
| 290 | * It will be zeroed when ZA storage is re-enabled. |
| 291 | */ |
| 292 | return FIELD_EX64(cpu->env.svcr, SVCR, ZA); |
| 293 | } |
| 294 | |
| 295 | static const VMStateDescription vmstate_za = { |
| 296 | .name = "cpu/sme", |
| 297 | .version_id = 1, |
| 298 | .minimum_version_id = 1, |
| 299 | .needed = za_needed, |
| 300 | .fields = (const VMStateField[]) { |
| 301 | VMSTATE_STRUCT_ARRAY(env.za_state.za, ARMCPU, ARM_MAX_VQ * 16, 0, |
| 302 | vmstate_vreg, ARMVectorReg), |
| 303 | VMSTATE_END_OF_LIST() |
| 304 | } |
| 305 | }; |
| 306 | |
| 307 | static bool zt0_needed(void *opaque) |
| 308 | { |
| 309 | ARMCPU *cpu = opaque; |
| 310 | |
| 311 | return za_needed(cpu) && cpu_isar_feature(aa64_sme2, cpu); |
| 312 | } |
| 313 | |
| 314 | static const VMStateDescription vmstate_zt0 = { |
| 315 | .name = "cpu/zt0", |
| 316 | .version_id = 1, |
| 317 | .minimum_version_id = 1, |
| 318 | .needed = zt0_needed, |
| 319 | .fields = (VMStateField[]) { |
| 320 | VMSTATE_UINT64_ARRAY(env.za_state.zt0, ARMCPU, |
| 321 | ARRAY_SIZE(((CPUARMState *)0)->za_state.zt0)), |
| 322 | VMSTATE_END_OF_LIST() |
| 323 | } |
| 324 | }; |
| 325 | |
| 326 | static bool serror_needed(void *opaque) |
| 327 | { |
| 328 | ARMCPU *cpu = opaque; |
| 329 | CPUARMState *env = &cpu->env; |
| 330 | |
| 331 | return env->serror.pending != 0; |
| 332 | } |
| 333 | |
| 334 | static const VMStateDescription vmstate_serror = { |
| 335 | .name = "cpu/serror", |
| 336 | .version_id = 1, |
| 337 | .minimum_version_id = 1, |
| 338 | .needed = serror_needed, |
| 339 | .fields = (const VMStateField[]) { |
| 340 | VMSTATE_UINT8(env.serror.pending, ARMCPU), |
| 341 | VMSTATE_UINT8(env.serror.has_esr, ARMCPU), |
| 342 | VMSTATE_UINT64(env.serror.esr, ARMCPU), |
| 343 | VMSTATE_END_OF_LIST() |
| 344 | } |
| 345 | }; |
| 346 | |
| 347 | static bool irq_line_state_needed(void *opaque) |
| 348 | { |
| 349 | return true; |
| 350 | } |
| 351 | |
| 352 | static const VMStateDescription vmstate_irq_line_state = { |
| 353 | .name = "cpu/irq-line-state", |
| 354 | .version_id = 1, |
| 355 | .minimum_version_id = 1, |
| 356 | .needed = irq_line_state_needed, |
| 357 | .fields = (const VMStateField[]) { |
| 358 | VMSTATE_UINT32(env.irq_line_state, ARMCPU), |
| 359 | VMSTATE_END_OF_LIST() |
| 360 | } |
| 361 | }; |
| 362 | |
| 363 | static bool wfxt_timer_needed(void *opaque) |
| 364 | { |
| 365 | ARMCPU *cpu = opaque; |
| 366 | |
| 367 | /* We'll only have the timer object if FEAT_WFxT is implemented */ |
| 368 | return cpu->wfxt_timer; |
| 369 | } |
| 370 | |
| 371 | static const VMStateDescription vmstate_wfxt_timer = { |
| 372 | .name = "cpu/wfxt-timer", |
| 373 | .version_id = 1, |
| 374 | .minimum_version_id = 1, |
| 375 | .needed = wfxt_timer_needed, |
| 376 | .fields = (const VMStateField[]) { |
| 377 | VMSTATE_TIMER_PTR(wfxt_timer, ARMCPU), |
| 378 | VMSTATE_END_OF_LIST() |
| 379 | } |
| 380 | }; |
| 381 | |
| 382 | static bool m_needed(void *opaque) |
| 383 | { |
| 384 | ARMCPU *cpu = opaque; |
| 385 | CPUARMState *env = &cpu->env; |
| 386 | |
| 387 | return arm_feature(env, ARM_FEATURE_M); |
| 388 | } |
| 389 | |
| 390 | static const VMStateDescription vmstate_m_faultmask_primask = { |
| 391 | .name = "cpu/m/faultmask-primask", |
| 392 | .version_id = 1, |
| 393 | .minimum_version_id = 1, |
| 394 | .needed = m_needed, |
| 395 | .fields = (const VMStateField[]) { |
| 396 | VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), |
| 397 | VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), |
| 398 | VMSTATE_END_OF_LIST() |
| 399 | } |
| 400 | }; |
| 401 | |
| 402 | /* CSSELR is in a subsection because we didn't implement it previously. |
| 403 | * Migration from an old implementation will leave it at zero, which |
| 404 | * is OK since the only CPUs in the old implementation make the |
| 405 | * register RAZ/WI. |
| 406 | * Since there was no version of QEMU which implemented the CSSELR for |
| 407 | * just non-secure, we transfer both banks here rather than putting |
| 408 | * the secure banked version in the m-security subsection. |
| 409 | */ |
| 410 | static bool csselr_vmstate_validate(void *opaque, int version_id) |
| 411 | { |
| 412 | ARMCPU *cpu = opaque; |
| 413 | |
| 414 | return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK |
| 415 | && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK; |
| 416 | } |
| 417 | |
| 418 | static bool m_csselr_needed(void *opaque) |
| 419 | { |
| 420 | ARMCPU *cpu = opaque; |
| 421 | |
| 422 | return !arm_v7m_csselr_razwi(cpu); |
| 423 | } |
| 424 | |
| 425 | static const VMStateDescription vmstate_m_csselr = { |
| 426 | .name = "cpu/m/csselr", |
| 427 | .version_id = 1, |
| 428 | .minimum_version_id = 1, |
| 429 | .needed = m_csselr_needed, |
| 430 | .fields = (const VMStateField[]) { |
| 431 | VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS), |
| 432 | VMSTATE_VALIDATE("CSSELR is valid", csselr_vmstate_validate), |
| 433 | VMSTATE_END_OF_LIST() |
| 434 | } |
| 435 | }; |
| 436 | |
| 437 | static const VMStateDescription vmstate_m_scr = { |
| 438 | .name = "cpu/m/scr", |
| 439 | .version_id = 1, |
| 440 | .minimum_version_id = 1, |
| 441 | .needed = m_needed, |
| 442 | .fields = (const VMStateField[]) { |
| 443 | VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU), |
| 444 | VMSTATE_END_OF_LIST() |
| 445 | } |
| 446 | }; |
| 447 | |
| 448 | static const VMStateDescription vmstate_m_other_sp = { |
| 449 | .name = "cpu/m/other-sp", |
| 450 | .version_id = 1, |
| 451 | .minimum_version_id = 1, |
| 452 | .needed = m_needed, |
| 453 | .fields = (const VMStateField[]) { |
| 454 | VMSTATE_UINT32(env.v7m.other_sp, ARMCPU), |
| 455 | VMSTATE_END_OF_LIST() |
| 456 | } |
| 457 | }; |
| 458 | |
| 459 | static bool m_v8m_needed(void *opaque) |
| 460 | { |
| 461 | ARMCPU *cpu = opaque; |
| 462 | CPUARMState *env = &cpu->env; |
| 463 | |
| 464 | return arm_feature(env, ARM_FEATURE_M) && arm_feature(env, ARM_FEATURE_V8); |
| 465 | } |
| 466 | |
| 467 | static const VMStateDescription vmstate_m_v8m = { |
| 468 | .name = "cpu/m/v8m", |
| 469 | .version_id = 1, |
| 470 | .minimum_version_id = 1, |
| 471 | .needed = m_v8m_needed, |
| 472 | .fields = (const VMStateField[]) { |
| 473 | VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS), |
| 474 | VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS), |
| 475 | VMSTATE_END_OF_LIST() |
| 476 | } |
| 477 | }; |
| 478 | |
| 479 | static const VMStateDescription vmstate_m_fp = { |
| 480 | .name = "cpu/m/fp", |
| 481 | .version_id = 1, |
| 482 | .minimum_version_id = 1, |
| 483 | .needed = vfp_needed, |
| 484 | .fields = (const VMStateField[]) { |
| 485 | VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS), |
| 486 | VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS), |
| 487 | VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS), |
| 488 | VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS), |
| 489 | VMSTATE_UINT32(env.v7m.nsacr, ARMCPU), |
| 490 | VMSTATE_END_OF_LIST() |
| 491 | } |
| 492 | }; |
| 493 | |
| 494 | static bool mve_needed(void *opaque) |
| 495 | { |
| 496 | ARMCPU *cpu = opaque; |
| 497 | |
| 498 | return cpu_isar_feature(aa32_mve, cpu); |
| 499 | } |
| 500 | |
| 501 | static const VMStateDescription vmstate_m_mve = { |
| 502 | .name = "cpu/m/mve", |
| 503 | .version_id = 1, |
| 504 | .minimum_version_id = 1, |
| 505 | .needed = mve_needed, |
| 506 | .fields = (const VMStateField[]) { |
| 507 | VMSTATE_UINT32(env.v7m.vpr, ARMCPU), |
| 508 | VMSTATE_UINT32(env.v7m.ltpsize, ARMCPU), |
| 509 | VMSTATE_END_OF_LIST() |
| 510 | }, |
| 511 | }; |
| 512 | |
| 513 | static bool event_needed(void *opaque) |
| 514 | { |
| 515 | ARMCPU *cpu = opaque; |
| 516 | |
| 517 | return cpu->env.event_register; |
| 518 | } |
| 519 | |
| 520 | static const VMStateDescription vmstate_event = { |
| 521 | .name = "cpu/event", |
| 522 | .version_id = 1, |
| 523 | .minimum_version_id = 1, |
| 524 | .needed = event_needed, |
| 525 | .fields = (const VMStateField[]) { |
| 526 | VMSTATE_BOOL(env.event_register, ARMCPU), |
| 527 | VMSTATE_END_OF_LIST() |
| 528 | } |
| 529 | }; |
| 530 | |
| 531 | static const VMStateDescription vmstate_m = { |
| 532 | .name = "cpu/m", |
| 533 | .version_id = 4, |
| 534 | .minimum_version_id = 4, |
| 535 | .needed = m_needed, |
| 536 | .fields = (const VMStateField[]) { |
| 537 | VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), |
| 538 | VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), |
| 539 | VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), |
| 540 | VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), |
| 541 | VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU), |
| 542 | VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), |
| 543 | VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), |
| 544 | VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), |
| 545 | VMSTATE_UINT32(env.v7m.bfar, ARMCPU), |
| 546 | VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), |
| 547 | VMSTATE_INT32(env.v7m.exception, ARMCPU), |
| 548 | VMSTATE_END_OF_LIST() |
| 549 | }, |
| 550 | .subsections = (const VMStateDescription * const []) { |
| 551 | &vmstate_m_faultmask_primask, |
| 552 | &vmstate_m_csselr, |
| 553 | &vmstate_m_scr, |
| 554 | &vmstate_m_other_sp, |
| 555 | &vmstate_m_v8m, |
| 556 | &vmstate_m_fp, |
| 557 | &vmstate_m_mve, |
| 558 | NULL |
| 559 | } |
| 560 | }; |
| 561 | |
| 562 | static bool thumb2ee_needed(void *opaque) |
| 563 | { |
| 564 | ARMCPU *cpu = opaque; |
| 565 | CPUARMState *env = &cpu->env; |
| 566 | |
| 567 | return arm_feature(env, ARM_FEATURE_THUMB2EE); |
| 568 | } |
| 569 | |
| 570 | static const VMStateDescription vmstate_thumb2ee = { |
| 571 | .name = "cpu/thumb2ee", |
| 572 | .version_id = 1, |
| 573 | .minimum_version_id = 1, |
| 574 | .needed = thumb2ee_needed, |
| 575 | .fields = (const VMStateField[]) { |
| 576 | VMSTATE_UINT32(env.teecr, ARMCPU), |
| 577 | VMSTATE_UINT32(env.teehbr, ARMCPU), |
| 578 | VMSTATE_END_OF_LIST() |
| 579 | } |
| 580 | }; |
| 581 | |
| 582 | static bool pmsav7_needed(void *opaque) |
| 583 | { |
| 584 | ARMCPU *cpu = opaque; |
| 585 | CPUARMState *env = &cpu->env; |
| 586 | |
| 587 | return arm_feature(env, ARM_FEATURE_PMSA) && |
| 588 | arm_feature(env, ARM_FEATURE_V7) && |
| 589 | !arm_feature(env, ARM_FEATURE_V8); |
| 590 | } |
| 591 | |
| 592 | static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) |
| 593 | { |
| 594 | ARMCPU *cpu = opaque; |
| 595 | |
| 596 | return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion; |
| 597 | } |
| 598 | |
| 599 | static const VMStateDescription vmstate_pmsav7 = { |
| 600 | .name = "cpu/pmsav7", |
| 601 | .version_id = 1, |
| 602 | .minimum_version_id = 1, |
| 603 | .needed = pmsav7_needed, |
| 604 | .fields = (const VMStateField[]) { |
| 605 | VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, |
| 606 | vmstate_info_uint32, uint32_t), |
| 607 | VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, |
| 608 | vmstate_info_uint32, uint32_t), |
| 609 | VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, |
| 610 | vmstate_info_uint32, uint32_t), |
| 611 | VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), |
| 612 | VMSTATE_END_OF_LIST() |
| 613 | } |
| 614 | }; |
| 615 | |
| 616 | static bool pmsav7_rnr_needed(void *opaque) |
| 617 | { |
| 618 | ARMCPU *cpu = opaque; |
| 619 | CPUARMState *env = &cpu->env; |
| 620 | |
| 621 | /* For R profile cores pmsav7.rnr is migrated via the cpreg |
| 622 | * "RGNR" definition in helper.h. For M profile we have to |
| 623 | * migrate it separately. |
| 624 | */ |
| 625 | return arm_feature(env, ARM_FEATURE_M); |
| 626 | } |
| 627 | |
| 628 | static const VMStateDescription vmstate_pmsav7_rnr = { |
| 629 | .name = "cpu/pmsav7-rnr", |
| 630 | .version_id = 1, |
| 631 | .minimum_version_id = 1, |
| 632 | .needed = pmsav7_rnr_needed, |
| 633 | .fields = (const VMStateField[]) { |
| 634 | VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU), |
| 635 | VMSTATE_END_OF_LIST() |
| 636 | } |
| 637 | }; |
| 638 | |
| 639 | static bool pmsav8_needed(void *opaque) |
| 640 | { |
| 641 | ARMCPU *cpu = opaque; |
| 642 | CPUARMState *env = &cpu->env; |
| 643 | |
| 644 | return arm_feature(env, ARM_FEATURE_PMSA) && |
| 645 | arm_feature(env, ARM_FEATURE_V8); |
| 646 | } |
| 647 | |
| 648 | static bool pmsav8r_needed(void *opaque) |
| 649 | { |
| 650 | ARMCPU *cpu = opaque; |
| 651 | CPUARMState *env = &cpu->env; |
| 652 | |
| 653 | return arm_feature(env, ARM_FEATURE_PMSA) && |
| 654 | arm_feature(env, ARM_FEATURE_V8) && |
| 655 | !arm_feature(env, ARM_FEATURE_M); |
| 656 | } |
| 657 | |
| 658 | static const VMStateDescription vmstate_pmsav8r = { |
| 659 | .name = "cpu/pmsav8/pmsav8r", |
| 660 | .version_id = 1, |
| 661 | .minimum_version_id = 1, |
| 662 | .needed = pmsav8r_needed, |
| 663 | .fields = (const VMStateField[]) { |
| 664 | VMSTATE_VARRAY_UINT32(env.pmsav8.hprbar, ARMCPU, |
| 665 | pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t), |
| 666 | VMSTATE_VARRAY_UINT32(env.pmsav8.hprlar, ARMCPU, |
| 667 | pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t), |
| 668 | VMSTATE_END_OF_LIST() |
| 669 | }, |
| 670 | }; |
| 671 | |
| 672 | static const VMStateDescription vmstate_pmsav8 = { |
| 673 | .name = "cpu/pmsav8", |
| 674 | .version_id = 1, |
| 675 | .minimum_version_id = 1, |
| 676 | .needed = pmsav8_needed, |
| 677 | .fields = (const VMStateField[]) { |
| 678 | VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion, |
| 679 | 0, vmstate_info_uint32, uint32_t), |
| 680 | VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion, |
| 681 | 0, vmstate_info_uint32, uint32_t), |
| 682 | VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), |
| 683 | VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), |
| 684 | VMSTATE_END_OF_LIST() |
| 685 | }, |
| 686 | .subsections = (const VMStateDescription * const []) { |
| 687 | &vmstate_pmsav8r, |
| 688 | NULL |
| 689 | } |
| 690 | }; |
| 691 | |
| 692 | static bool s_rnr_vmstate_validate(void *opaque, int version_id) |
| 693 | { |
| 694 | ARMCPU *cpu = opaque; |
| 695 | |
| 696 | return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; |
| 697 | } |
| 698 | |
| 699 | static bool sau_rnr_vmstate_validate(void *opaque, int version_id) |
| 700 | { |
| 701 | ARMCPU *cpu = opaque; |
| 702 | |
| 703 | return cpu->env.sau.rnr < cpu->sau_sregion; |
| 704 | } |
| 705 | |
| 706 | static bool m_security_needed(void *opaque) |
| 707 | { |
| 708 | ARMCPU *cpu = opaque; |
| 709 | CPUARMState *env = &cpu->env; |
| 710 | |
| 711 | return arm_feature(env, ARM_FEATURE_M_SECURITY); |
| 712 | } |
| 713 | |
| 714 | static const VMStateDescription vmstate_m_security = { |
| 715 | .name = "cpu/m-security", |
| 716 | .version_id = 1, |
| 717 | .minimum_version_id = 1, |
| 718 | .needed = m_security_needed, |
| 719 | .fields = (const VMStateField[]) { |
| 720 | VMSTATE_UINT32(env.v7m.secure, ARMCPU), |
| 721 | VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU), |
| 722 | VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU), |
| 723 | VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), |
| 724 | VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), |
| 725 | VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), |
| 726 | VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), |
| 727 | VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), |
| 728 | VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), |
| 729 | VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), |
| 730 | VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion, |
| 731 | 0, vmstate_info_uint32, uint32_t), |
| 732 | VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, |
| 733 | 0, vmstate_info_uint32, uint32_t), |
| 734 | VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), |
| 735 | VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), |
| 736 | VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), |
| 737 | VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), |
| 738 | VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), |
| 739 | VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU), |
| 740 | VMSTATE_UINT32(env.v7m.sfsr, ARMCPU), |
| 741 | VMSTATE_UINT32(env.v7m.sfar, ARMCPU), |
| 742 | VMSTATE_VARRAY_UINT32(env.sau.rbar, ARMCPU, sau_sregion, 0, |
| 743 | vmstate_info_uint32, uint32_t), |
| 744 | VMSTATE_VARRAY_UINT32(env.sau.rlar, ARMCPU, sau_sregion, 0, |
| 745 | vmstate_info_uint32, uint32_t), |
| 746 | VMSTATE_UINT32(env.sau.rnr, ARMCPU), |
| 747 | VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate), |
| 748 | VMSTATE_UINT32(env.sau.ctrl, ARMCPU), |
| 749 | VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU), |
| 750 | /* AIRCR is not secure-only, but our implementation is R/O if the |
| 751 | * security extension is unimplemented, so we migrate it here. |
| 752 | */ |
| 753 | VMSTATE_UINT32(env.v7m.aircr, ARMCPU), |
| 754 | VMSTATE_END_OF_LIST() |
| 755 | } |
| 756 | }; |
| 757 | |
| 758 | static int get_cpsr(QEMUFile *f, void *opaque, size_t size, |
| 759 | const VMStateField *field) |
| 760 | { |
| 761 | ARMCPU *cpu = opaque; |
| 762 | CPUARMState *env = &cpu->env; |
| 763 | uint32_t val = qemu_get_be32(f); |
| 764 | |
| 765 | if (arm_feature(env, ARM_FEATURE_M)) { |
| 766 | if (val & XPSR_EXCP) { |
| 767 | /* This is a CPSR format value from an older QEMU. (We can tell |
| 768 | * because values transferred in XPSR format always have zero |
| 769 | * for the EXCP field, and CPSR format will always have bit 4 |
| 770 | * set in CPSR_M.) Rearrange it into XPSR format. The significant |
| 771 | * differences are that the T bit is not in the same place, the |
| 772 | * primask/faultmask info may be in the CPSR I and F bits, and |
| 773 | * we do not want the mode bits. |
| 774 | * We know that this cleanup happened before v8M, so there |
| 775 | * is no complication with banked primask/faultmask. |
| 776 | */ |
| 777 | uint32_t newval = val; |
| 778 | |
| 779 | assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); |
| 780 | |
| 781 | newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); |
| 782 | if (val & CPSR_T) { |
| 783 | newval |= XPSR_T; |
| 784 | } |
| 785 | /* If the I or F bits are set then this is a migration from |
| 786 | * an old QEMU which still stored the M profile FAULTMASK |
| 787 | * and PRIMASK in env->daif. For a new QEMU, the data is |
| 788 | * transferred using the vmstate_m_faultmask_primask subsection. |
| 789 | */ |
| 790 | if (val & CPSR_F) { |
| 791 | env->v7m.faultmask[M_REG_NS] = 1; |
| 792 | } |
| 793 | if (val & CPSR_I) { |
| 794 | env->v7m.primask[M_REG_NS] = 1; |
| 795 | } |
| 796 | val = newval; |
| 797 | } |
| 798 | /* Ignore the low bits, they are handled by vmstate_m. */ |
| 799 | xpsr_write(env, val, ~XPSR_EXCP); |
| 800 | return 0; |
| 801 | } |
| 802 | |
| 803 | env->aarch64 = ((val & PSTATE_nRW) == 0); |
| 804 | |
| 805 | if (is_a64(env)) { |
| 806 | pstate_write(env, val); |
| 807 | return 0; |
| 808 | } |
| 809 | |
| 810 | cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); |
| 811 | return 0; |
| 812 | } |
| 813 | |
| 814 | static int put_cpsr(QEMUFile *f, void *opaque, size_t size, |
| 815 | const VMStateField *field, JSONWriter *vmdesc) |
| 816 | { |
| 817 | ARMCPU *cpu = opaque; |
| 818 | CPUARMState *env = &cpu->env; |
| 819 | uint32_t val; |
| 820 | |
| 821 | if (arm_feature(env, ARM_FEATURE_M)) { |
| 822 | /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ |
| 823 | val = xpsr_read(env) & ~XPSR_EXCP; |
| 824 | } else if (is_a64(env)) { |
| 825 | val = pstate_read(env); |
| 826 | } else { |
| 827 | val = cpsr_read(env); |
| 828 | } |
| 829 | |
| 830 | qemu_put_be32(f, val); |
| 831 | return 0; |
| 832 | } |
| 833 | |
| 834 | static const VMStateInfo vmstate_cpsr = { |
| 835 | .name = "cpsr", |
| 836 | .get = get_cpsr, |
| 837 | .put = put_cpsr, |
| 838 | }; |
| 839 | |
| 840 | static int get_pstate64(QEMUFile *f, void *opaque, size_t size, |
| 841 | const VMStateField *field) |
| 842 | { |
| 843 | ARMCPU *cpu = opaque; |
| 844 | CPUARMState *env = &cpu->env; |
| 845 | uint64_t val = qemu_get_be64(f); |
| 846 | |
| 847 | env->aarch64 = ((val & PSTATE_nRW) == 0); |
| 848 | if (is_a64(env)) { |
| 849 | pstate_write(env, val); |
| 850 | } else { |
| 851 | cpsr_write_from_spsr_elx(env, val); |
| 852 | } |
| 853 | return 0; |
| 854 | } |
| 855 | |
| 856 | static int put_pstate64(QEMUFile *f, void *opaque, size_t size, |
| 857 | const VMStateField *field, JSONWriter *vmdesc) |
| 858 | { |
| 859 | ARMCPU *cpu = opaque; |
| 860 | CPUARMState *env = &cpu->env; |
| 861 | uint64_t val; |
| 862 | |
| 863 | if (is_a64(env)) { |
| 864 | val = pstate_read(env); |
| 865 | } else { |
| 866 | val = cpsr_read_for_spsr_elx(env); |
| 867 | } |
| 868 | qemu_put_be64(f, val); |
| 869 | return 0; |
| 870 | } |
| 871 | |
| 872 | static bool pstate64_needed(void *opaque) |
| 873 | { |
| 874 | ARMCPU *cpu = opaque; |
| 875 | CPUARMState *env = &cpu->env; |
| 876 | uint64_t val; |
| 877 | |
| 878 | if (arm_feature(env, ARM_FEATURE_M)) { |
| 879 | return false; |
| 880 | } |
| 881 | if (is_a64(env)) { |
| 882 | val = pstate_read(env); |
| 883 | } else { |
| 884 | val = cpsr_read_for_spsr_elx(env); |
| 885 | if (val & PSTATE_SS) { |
| 886 | return true; |
| 887 | } |
| 888 | } |
| 889 | return val > UINT32_MAX; |
| 890 | } |
| 891 | |
| 892 | static const VMStateDescription vmstate_pstate64 = { |
| 893 | .name = "cpu/pstate64", |
| 894 | .version_id = 1, |
| 895 | .minimum_version_id = 1, |
| 896 | .needed = pstate64_needed, |
| 897 | .fields = (const VMStateField[]) { |
| 898 | { |
| 899 | .name = "pstate64", |
| 900 | .version_id = 0, |
| 901 | .size = sizeof(uint64_t), |
| 902 | .info = &(const VMStateInfo) { |
| 903 | .name = "pstate64", |
| 904 | .get = get_pstate64, |
| 905 | .put = put_pstate64, |
| 906 | }, |
| 907 | .flags = VMS_SINGLE, |
| 908 | .offset = 0, |
| 909 | }, |
| 910 | VMSTATE_END_OF_LIST() |
| 911 | }, |
| 912 | }; |
| 913 | |
| 914 | static int get_power(QEMUFile *f, void *opaque, size_t size, |
| 915 | const VMStateField *field) |
| 916 | { |
| 917 | ARMCPU *cpu = opaque; |
| 918 | bool powered_off = qemu_get_byte(f); |
| 919 | arm_set_cpu_power_state(cpu, powered_off ? PSCI_OFF : PSCI_ON); |
| 920 | return 0; |
| 921 | } |
| 922 | |
| 923 | static int put_power(QEMUFile *f, void *opaque, size_t size, |
| 924 | const VMStateField *field, JSONWriter *vmdesc) |
| 925 | { |
| 926 | ARMCPU *cpu = opaque; |
| 927 | |
| 928 | /* Migration should never happen while we transition power states */ |
| 929 | |
| 930 | if (cpu->power_state == PSCI_ON || |
| 931 | cpu->power_state == PSCI_OFF) { |
| 932 | bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; |
| 933 | qemu_put_byte(f, powered_off); |
| 934 | return 0; |
| 935 | } else { |
| 936 | return 1; |
| 937 | } |
| 938 | } |
| 939 | |
| 940 | static const VMStateInfo vmstate_powered_off = { |
| 941 | .name = "powered_off", |
| 942 | .get = get_power, |
| 943 | .put = put_power, |
| 944 | }; |
| 945 | |
| 946 | static bool syndrome64_needed(void *opaque) |
| 947 | { |
| 948 | ARMCPU *cpu = opaque; |
| 949 | return cpu->env.exception.syndrome > UINT32_MAX; |
| 950 | } |
| 951 | |
| 952 | static const VMStateDescription vmstate_syndrome64 = { |
| 953 | .name = "cpu/syndrome64", |
| 954 | .version_id = 1, |
| 955 | .minimum_version_id = 1, |
| 956 | .needed = syndrome64_needed, |
| 957 | .fields = (const VMStateField[]) { |
| 958 | VMSTATE_UINT64(env.exception.syndrome, ARMCPU), |
| 959 | VMSTATE_END_OF_LIST() |
| 960 | }, |
| 961 | }; |
| 962 | |
| 963 | static bool fpmr_needed(void *opaque) |
| 964 | { |
| 965 | ARMCPU *cpu = opaque; |
| 966 | |
| 967 | return arm_feature(&cpu->env, ARM_FEATURE_AARCH64) |
| 968 | && cpu_isar_feature(aa64_fpmr, cpu); |
| 969 | } |
| 970 | |
| 971 | static const VMStateDescription vmstate_fpmr = { |
| 972 | .name = "cpu/fpmr", |
| 973 | .version_id = 1, |
| 974 | .minimum_version_id = 1, |
| 975 | .needed = fpmr_needed, |
| 976 | .fields = (const VMStateField[]) { |
| 977 | VMSTATE_UINT64(env.vfp.fpmr, ARMCPU), |
| 978 | VMSTATE_END_OF_LIST() |
| 979 | }, |
| 980 | }; |
| 981 | |
| 982 | static int cpu_pre_save(void *opaque) |
| 983 | { |
| 984 | ARMCPU *cpu = opaque; |
| 985 | |
| 986 | if (tcg_enabled() || hvf_enabled()) { |
| 987 | pmu_op_start(&cpu->env); |
| 988 | } |
| 989 | |
| 990 | if (kvm_enabled()) { |
| 991 | if (!write_kvmstate_to_list(cpu)) { |
| 992 | /* This should never fail */ |
| 993 | g_assert_not_reached(); |
| 994 | } |
| 995 | |
| 996 | /* |
| 997 | * kvm_arm_cpu_pre_save() must be called after |
| 998 | * write_kvmstate_to_list() |
| 999 | */ |
| 1000 | kvm_arm_cpu_pre_save(cpu); |
| 1001 | } else { |
| 1002 | if (!write_cpustate_to_list(cpu, false)) { |
| 1003 | /* This should never fail. */ |
| 1004 | g_assert_not_reached(); |
| 1005 | } |
| 1006 | } |
| 1007 | |
| 1008 | /* |
| 1009 | * On outbound migration, send the data in our cpreg_{values,indexes} |
| 1010 | * arrays. The migration code will not allocate anything, but just |
| 1011 | * reads the data pointed to by the VMSTATE_VARRAY_INT32_ALLOC() fields. |
| 1012 | */ |
| 1013 | cpu->cpreg_vmstate_indexes = cpu->cpreg_indexes; |
| 1014 | cpu->cpreg_vmstate_values = cpu->cpreg_values; |
| 1015 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; |
| 1016 | |
| 1017 | return 0; |
| 1018 | } |
| 1019 | |
| 1020 | static void cpu_post_save(void *opaque) |
| 1021 | { |
| 1022 | ARMCPU *cpu = opaque; |
| 1023 | |
| 1024 | if (tcg_enabled() || hvf_enabled()) { |
| 1025 | pmu_op_finish(&cpu->env); |
| 1026 | } |
| 1027 | |
| 1028 | cpu->cpreg_vmstate_indexes = NULL; |
| 1029 | cpu->cpreg_vmstate_values = NULL; |
| 1030 | } |
| 1031 | |
| 1032 | static int cpu_pre_load(void *opaque) |
| 1033 | { |
| 1034 | ARMCPU *cpu = opaque; |
| 1035 | CPUARMState *env = &cpu->env; |
| 1036 | |
| 1037 | /* |
| 1038 | * In an inbound migration where on the source FPSCR/FPSR/FPCR are 0, |
| 1039 | * there will be no fpcr_fpsr subsection so we won't call vfp_set_fpcr() |
| 1040 | * and vfp_set_fpsr() from get_fpcr() and get_fpsr(); also the get_fpscr() |
| 1041 | * function will not call vfp_set_fpscr() because it will see a 0 in the |
| 1042 | * inbound data. Ensure that in this case we have a correctly set up |
| 1043 | * zero FPSCR/FPCR/FPSR. |
| 1044 | * |
| 1045 | * This is not strictly needed because FPSCR is zero out of reset, but |
| 1046 | * it avoids the possibility of future confusing migration bugs if some |
| 1047 | * future architecture change makes the reset value non-zero. |
| 1048 | */ |
| 1049 | vfp_set_fpscr(env, 0); |
| 1050 | |
| 1051 | /* |
| 1052 | * Pre-initialize irq_line_state to a value that's never valid as |
| 1053 | * real data, so cpu_post_load() can tell whether we've seen the |
| 1054 | * irq-line-state subsection in the incoming migration state. |
| 1055 | */ |
| 1056 | env->irq_line_state = UINT32_MAX; |
| 1057 | |
| 1058 | if (tcg_enabled() || hvf_enabled()) { |
| 1059 | pmu_op_start(env); |
| 1060 | } |
| 1061 | |
| 1062 | g_assert(!cpu->cpreg_vmstate_indexes); |
| 1063 | g_assert(!cpu->cpreg_vmstate_values); |
| 1064 | |
| 1065 | return 0; |
| 1066 | } |
| 1067 | |
| 1068 | static gchar *print_register_name(uint64_t kvm_regidx) |
| 1069 | { |
| 1070 | if (kvm_enabled()) { |
| 1071 | return kvm_print_register_name(kvm_regidx); |
| 1072 | } else { |
| 1073 | return g_strdup_printf("system register 0x%x", kvm_to_cpreg_id(kvm_regidx)); |
| 1074 | } |
| 1075 | } |
| 1076 | |
| 1077 | /* |
| 1078 | * Handle the situation where @kvmidx is on destination but not |
| 1079 | * in the incoming stream. This never fails the migration. |
| 1080 | */ |
| 1081 | static void handle_cpreg_missing_in_incoming_stream(ARMCPU *cpu, uint64_t kvmidx) |
| 1082 | { |
| 1083 | g_autofree gchar *name = print_register_name(kvmidx); |
| 1084 | |
| 1085 | if (arm_cpu_match_cpreg_mig_tolerance(cpu, kvmidx, |
| 1086 | 0, 0, ToleranceNotOnBothEnds)) { |
| 1087 | trace_tolerate_cpreg_missing_in_incoming_stream(name); |
| 1088 | return; |
| 1089 | } |
| 1090 | warn_report("%s: %s " |
| 1091 | "expected by the destination but not in the incoming stream: " |
| 1092 | "skip it", __func__, name); |
| 1093 | } |
| 1094 | |
| 1095 | /* |
| 1096 | * Handle the situation where @kvmidx is in the incoming |
| 1097 | * stream but not on destination. This fails the migration if |
| 1098 | * no cpreg mig tolerance is matched for this @kvmidx |
| 1099 | * Return true if the migration should eventually fail |
| 1100 | */ |
| 1101 | static bool |
| 1102 | handle_cpreg_only_in_incoming_stream(ARMCPU *cpu, uint64_t kvmidx, uint64_t value) |
| 1103 | { |
| 1104 | g_autofree gchar *name = print_register_name(kvmidx); |
| 1105 | |
| 1106 | if (arm_cpu_match_cpreg_mig_tolerance(cpu, kvmidx, |
| 1107 | 0, 0, ToleranceNotOnBothEnds) || |
| 1108 | arm_cpu_match_cpreg_mig_tolerance(cpu, kvmidx, |
| 1109 | value, 0, ToleranceOnlySrcTestValue)) { |
| 1110 | trace_tolerate_cpreg_only_in_incoming_stream(name); |
| 1111 | return false; |
| 1112 | } |
| 1113 | error_report("%s: %s in the incoming stream but unknown on the " |
| 1114 | "destination: fail migration", __func__, name); |
| 1115 | return true; |
| 1116 | } |
| 1117 | |
| 1118 | static int cpu_post_load(void *opaque, int version_id) |
| 1119 | { |
| 1120 | ARMCPU *cpu = opaque; |
| 1121 | CPUARMState *env = &cpu->env; |
| 1122 | bool fail = false; |
| 1123 | int i, v; |
| 1124 | |
| 1125 | trace_cpu_post_load(cpu->cpreg_vmstate_array_len, |
| 1126 | cpu->cpreg_array_len); |
| 1127 | |
| 1128 | /* |
| 1129 | * Handle migration compatibility from old QEMU which didn't |
| 1130 | * send the irq-line-state subsection. A QEMU without it did not |
| 1131 | * implement the HCR_EL2.{VI,VF} bits as generating interrupts, |
| 1132 | * so for TCG the line state matches the bits set in cs->interrupt_request. |
| 1133 | * For KVM the line state is not stored in cs->interrupt_request |
| 1134 | * and so this will leave irq_line_state as 0, but this is OK because |
| 1135 | * we only need to care about it for TCG. |
| 1136 | */ |
| 1137 | if (env->irq_line_state == UINT32_MAX) { |
| 1138 | CPUState *cs = CPU(cpu); |
| 1139 | |
| 1140 | env->irq_line_state = cs->interrupt_request & |
| 1141 | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ | |
| 1142 | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VFIQ); |
| 1143 | } |
| 1144 | |
| 1145 | /* Update the values list from the incoming migration data. |
| 1146 | * Anything in the incoming data which we don't know about is |
| 1147 | * a migration failure; anything we know about but the incoming |
| 1148 | * data doesn't specify retains its current (reset) value. |
| 1149 | * The indexes list remains untouched -- we only inspect the |
| 1150 | * incoming migration index list so we can match the values array |
| 1151 | * entries with the right slots in our own values array. |
| 1152 | */ |
| 1153 | |
| 1154 | for (i = 0, v = 0; i < cpu->cpreg_array_len |
| 1155 | && v < cpu->cpreg_vmstate_array_len;) { |
| 1156 | if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { |
| 1157 | handle_cpreg_missing_in_incoming_stream(cpu, cpu->cpreg_indexes[i++]); |
| 1158 | continue; |
| 1159 | } |
| 1160 | if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { |
| 1161 | fail = handle_cpreg_only_in_incoming_stream(cpu, |
| 1162 | cpu->cpreg_vmstate_indexes[v], |
| 1163 | cpu->cpreg_vmstate_values[v]); |
| 1164 | v++; |
| 1165 | continue; |
| 1166 | } |
| 1167 | /* matching register, copy the value over */ |
| 1168 | cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; |
| 1169 | i++; |
| 1170 | v++; |
| 1171 | } |
| 1172 | |
| 1173 | /* |
| 1174 | * if we have reached the end of the incoming array but there are |
| 1175 | * still regs in cpreg, continue parsing the regs which are missing |
| 1176 | * in the input stream |
| 1177 | */ |
| 1178 | for ( ; i < cpu->cpreg_array_len; i++) { |
| 1179 | handle_cpreg_missing_in_incoming_stream(cpu, cpu->cpreg_indexes[i]); |
| 1180 | } |
| 1181 | /* |
| 1182 | * if we have reached the end of the cpreg array but there are |
| 1183 | * still regs in the input stream, continue parsing the vmstate array |
| 1184 | */ |
| 1185 | for ( ; v < cpu->cpreg_vmstate_array_len; v++) { |
| 1186 | fail = handle_cpreg_only_in_incoming_stream(cpu, |
| 1187 | cpu->cpreg_vmstate_indexes[v], |
| 1188 | cpu->cpreg_vmstate_values[v]); |
| 1189 | } |
| 1190 | if (fail) { |
| 1191 | return -1; |
| 1192 | } |
| 1193 | |
| 1194 | if (kvm_enabled()) { |
| 1195 | if (!kvm_arm_cpu_post_load(cpu)) { |
| 1196 | return -1; |
| 1197 | } |
| 1198 | } else { |
| 1199 | if (!write_list_to_cpustate(cpu)) { |
| 1200 | return -1; |
| 1201 | } |
| 1202 | } |
| 1203 | |
| 1204 | g_free(cpu->cpreg_vmstate_indexes); |
| 1205 | g_free(cpu->cpreg_vmstate_values); |
| 1206 | cpu->cpreg_vmstate_indexes = NULL; |
| 1207 | cpu->cpreg_vmstate_values = NULL; |
| 1208 | |
| 1209 | /* |
| 1210 | * Misaligned thumb pc is architecturally impossible. Fail the |
| 1211 | * incoming migration. For TCG it would trigger the assert in |
| 1212 | * thumb_tr_translate_insn(). |
| 1213 | */ |
| 1214 | if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { |
| 1215 | return -1; |
| 1216 | } |
| 1217 | |
| 1218 | if (tcg_enabled()) { |
| 1219 | hw_breakpoint_update_all(cpu); |
| 1220 | hw_watchpoint_update_all(cpu); |
| 1221 | } |
| 1222 | |
| 1223 | /* |
| 1224 | * TCG gen_update_fp_context() relies on the invariant that |
| 1225 | * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension; |
| 1226 | * forbid bogus incoming data with some other value. |
| 1227 | */ |
| 1228 | if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)) { |
| 1229 | if (extract32(env->v7m.fpdscr[M_REG_NS], |
| 1230 | FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4 || |
| 1231 | extract32(env->v7m.fpdscr[M_REG_S], |
| 1232 | FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4) { |
| 1233 | return -1; |
| 1234 | } |
| 1235 | } |
| 1236 | |
| 1237 | if (tcg_enabled() || hvf_enabled()) { |
| 1238 | pmu_op_finish(env); |
| 1239 | } |
| 1240 | |
| 1241 | if (tcg_enabled()) { |
| 1242 | arm_rebuild_hflags(env); |
| 1243 | } |
| 1244 | |
| 1245 | return 0; |
| 1246 | } |
| 1247 | |
| 1248 | const VMStateDescription vmstate_arm_cpu = { |
| 1249 | .name = "cpu", |
| 1250 | .version_id = 22, |
| 1251 | .minimum_version_id = 22, |
| 1252 | .pre_save = cpu_pre_save, |
| 1253 | .post_save = cpu_post_save, |
| 1254 | .pre_load = cpu_pre_load, |
| 1255 | .post_load = cpu_post_load, |
| 1256 | .fields = (const VMStateField[]) { |
| 1257 | VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), |
| 1258 | VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), |
| 1259 | VMSTATE_UINT64(env.pc, ARMCPU), |
| 1260 | /* |
| 1261 | * If any bits are set in the upper 32 bits of cpsr/pstate, |
| 1262 | * or if the cpu is in aa32 mode and PSTATE.SS is set, then |
| 1263 | * the cpu/pstate64 subsection will override this with the |
| 1264 | * full 64 bit state. |
| 1265 | */ |
| 1266 | { |
| 1267 | .name = "cpsr", |
| 1268 | .version_id = 0, |
| 1269 | .size = sizeof(uint32_t), |
| 1270 | .info = &vmstate_cpsr, |
| 1271 | .flags = VMS_SINGLE, |
| 1272 | .offset = 0, |
| 1273 | }, |
| 1274 | VMSTATE_UINT32(env.spsr, ARMCPU), |
| 1275 | VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), |
| 1276 | VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), |
| 1277 | VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), |
| 1278 | VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), |
| 1279 | VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), |
| 1280 | VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), |
| 1281 | VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), |
| 1282 | /* |
| 1283 | * The length must come before the arrays so we can |
| 1284 | * allocate the arrays before their data arrives |
| 1285 | */ |
| 1286 | VMSTATE_INT32(cpreg_vmstate_array_len, ARMCPU), |
| 1287 | VMSTATE_VARRAY_INT32_ALLOC(cpreg_vmstate_indexes, ARMCPU, |
| 1288 | cpreg_vmstate_array_len, |
| 1289 | 0, vmstate_info_uint64, uint64_t), |
| 1290 | VMSTATE_VARRAY_INT32_ALLOC(cpreg_vmstate_values, ARMCPU, |
| 1291 | cpreg_vmstate_array_len, |
| 1292 | 0, vmstate_info_uint64, uint64_t), |
| 1293 | VMSTATE_UINT64(env.exclusive_addr, ARMCPU), |
| 1294 | VMSTATE_UINT64(env.exclusive_val, ARMCPU), |
| 1295 | VMSTATE_UINT64(env.exclusive_high, ARMCPU), |
| 1296 | VMSTATE_UNUSED(sizeof(uint64_t)), |
| 1297 | /* |
| 1298 | * If any bits are set in the upper 32 bits of syndrome, |
| 1299 | * then the cpu/syndrome64 subsection will override this |
| 1300 | * with the full 64 bit state. |
| 1301 | */ |
| 1302 | { |
| 1303 | .name = "env.exception.syndrome", |
| 1304 | .version_id = 0, |
| 1305 | .size = sizeof(uint32_t), |
| 1306 | .info = &vmstate_info_uint32, |
| 1307 | .flags = VMS_SINGLE, |
| 1308 | .offset = offsetoflow32(ARMCPU, env.exception.syndrome), |
| 1309 | }, |
| 1310 | VMSTATE_UINT32(env.exception.fsr, ARMCPU), |
| 1311 | VMSTATE_UINT64(env.exception.vaddress, ARMCPU), |
| 1312 | VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), |
| 1313 | VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), |
| 1314 | { |
| 1315 | .name = "power_state", |
| 1316 | .version_id = 0, |
| 1317 | .size = sizeof(bool), |
| 1318 | .info = &vmstate_powered_off, |
| 1319 | .flags = VMS_SINGLE, |
| 1320 | .offset = 0, |
| 1321 | }, |
| 1322 | VMSTATE_END_OF_LIST() |
| 1323 | }, |
| 1324 | .subsections = (const VMStateDescription * const []) { |
| 1325 | &vmstate_vfp, |
| 1326 | &vmstate_m, |
| 1327 | &vmstate_thumb2ee, |
| 1328 | /* pmsav7_rnr must come before pmsav7 so that we have the |
| 1329 | * region number before we test it in the VMSTATE_VALIDATE |
| 1330 | * in vmstate_pmsav7. |
| 1331 | */ |
| 1332 | &vmstate_pmsav7_rnr, |
| 1333 | &vmstate_pmsav7, |
| 1334 | &vmstate_pmsav8, |
| 1335 | &vmstate_m_security, |
| 1336 | &vmstate_sve, |
| 1337 | &vmstate_za, |
| 1338 | &vmstate_zt0, |
| 1339 | &vmstate_serror, |
| 1340 | &vmstate_irq_line_state, |
| 1341 | &vmstate_wfxt_timer, |
| 1342 | &vmstate_syndrome64, |
| 1343 | &vmstate_pstate64, |
| 1344 | &vmstate_event, |
| 1345 | &vmstate_fpmr, |
| 1346 | NULL |
| 1347 | } |
| 1348 | }; |
| 1349 | |
| 1350 | const InterfaceInfo arm_machine_interfaces[] = { |
| 1351 | { TYPE_TARGET_ARM_MACHINE }, |
| 1352 | { TYPE_TARGET_AARCH64_MACHINE }, |
| 1353 | { } |
| 1354 | }; |
| 1355 | |
| 1356 | const InterfaceInfo arm_aarch64_machine_interfaces[] = { |
| 1357 | { TYPE_TARGET_ARM_MACHINE }, |
| 1358 | { TYPE_TARGET_AARCH64_MACHINE }, |
| 1359 | { } |
| 1360 | }; |
| 1361 | |
| 1362 | const InterfaceInfo aarch64_machine_interfaces[] = { |
| 1363 | { TYPE_TARGET_AARCH64_MACHINE }, |
| 1364 | { } |
| 1365 | }; |