| 1 | /* |
| 2 | * QEMU Arm software mmu index definitions |
| 3 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 4 | */ |
| 5 | |
| 6 | #ifndef TARGET_ARM_MMUIDX_H |
| 7 | #define TARGET_ARM_MMUIDX_H |
| 8 | |
| 9 | /* |
| 10 | * Arm has the following "translation regimes" (as the Arm ARM calls them): |
| 11 | * |
| 12 | * If EL3 is 64-bit: |
| 13 | * + NonSecure EL1 & 0 stage 1 |
| 14 | * + NonSecure EL1 & 0 stage 2 |
| 15 | * + NonSecure EL2 |
| 16 | * + NonSecure EL2 & 0 (ARMv8.1-VHE) |
| 17 | * + Secure EL1 & 0 stage 1 |
| 18 | * + Secure EL1 & 0 stage 2 (FEAT_SEL2) |
| 19 | * + Secure EL2 (FEAT_SEL2) |
| 20 | * + Secure EL2 & 0 (FEAT_SEL2) |
| 21 | * + Realm EL1 & 0 stage 1 (FEAT_RME) |
| 22 | * + Realm EL1 & 0 stage 2 (FEAT_RME) |
| 23 | * + Realm EL2 (FEAT_RME) |
| 24 | * + EL3 |
| 25 | * If EL3 is 32-bit: |
| 26 | * + NonSecure PL1 & 0 stage 1 |
| 27 | * + NonSecure PL1 & 0 stage 2 |
| 28 | * + NonSecure PL2 |
| 29 | * + Secure PL1 & 0 |
| 30 | * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) |
| 31 | * |
| 32 | * For QEMU, an mmu_idx is not quite the same as a translation regime because: |
| 33 | * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, |
| 34 | * because they may differ in access permissions even if the VA->PA map is |
| 35 | * the same |
| 36 | * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 |
| 37 | * translation, which means that we have one mmu_idx that deals with two |
| 38 | * concatenated translation regimes [this sort of combined s1+2 TLB is |
| 39 | * architecturally permitted] |
| 40 | * 3. we don't need to allocate an mmu_idx to translations that we won't be |
| 41 | * handling via the TLB. The only way to do a stage 1 translation without |
| 42 | * the immediate stage 2 translation is via the ATS or AT system insns, |
| 43 | * which can be slow-pathed and always do a page table walk. |
| 44 | * The only use of stage 2 translations is either as part of an s1+2 |
| 45 | * lookup or when loading the descriptors during a stage 1 page table walk, |
| 46 | * and in both those cases we don't use the TLB. |
| 47 | * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" |
| 48 | * translation regimes, because they map reasonably well to each other |
| 49 | * and they can't both be active at the same time. |
| 50 | * 5. we want to be able to use the TLB for accesses done as part of a |
| 51 | * stage1 page table walk, rather than having to walk the stage2 page |
| 52 | * table over and over. |
| 53 | * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access |
| 54 | * Never (PAN) bit within PSTATE. |
| 55 | * 7. we fold together most secure and non-secure regimes for A-profile, |
| 56 | * because there are no banked system registers for aarch64, so the |
| 57 | * process of switching between secure and non-secure is |
| 58 | * already heavyweight. |
| 59 | * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, |
| 60 | * because both are in use simultaneously for Secure EL2. |
| 61 | * 9. we need separate indexes for handling AccessType_GCS. |
| 62 | * |
| 63 | * This gives us the following list of cases: |
| 64 | * |
| 65 | * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2) |
| 66 | * EL0 EL1&0 stage 1+2 +GCS |
| 67 | * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2) |
| 68 | * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN) |
| 69 | * EL1 EL1&0 stage 1+2 +GCS |
| 70 | * EL0 EL2&0 |
| 71 | * EL0 EL2&0 +GCS |
| 72 | * EL2 EL2&0 |
| 73 | * EL2 EL2&0 +PAN |
| 74 | * EL2 EL2&0 +GCS |
| 75 | * EL2 (aka NS PL2) |
| 76 | * EL2 +GCS |
| 77 | * EL3 (aka AArch32 S PL1 PL1&0) |
| 78 | * EL3 +GCS |
| 79 | * AArch32 S PL0 PL1&0 (we call this EL30_0) |
| 80 | * AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN) |
| 81 | * Stage2 Secure |
| 82 | * Stage2 NonSecure |
| 83 | * plus one TLB per Physical address space: S, NS, Realm, Root |
| 84 | * |
| 85 | * for a total of 22 different mmu_idx. |
| 86 | * |
| 87 | * R profile CPUs have an MPU, but can use the same set of MMU indexes |
| 88 | * as A profile. They only need to distinguish EL0 and EL1 (and |
| 89 | * EL2 for cores like the Cortex-R52). |
| 90 | * |
| 91 | * M profile CPUs are rather different as they do not have a true MMU. |
| 92 | * They have the following different MMU indexes: |
| 93 | * User |
| 94 | * Privileged |
| 95 | * User, execution priority negative (ie the MPU HFNMIENA bit may apply) |
| 96 | * Privileged, execution priority negative (ditto) |
| 97 | * If the CPU supports the v8M Security Extension then there are also: |
| 98 | * Secure User |
| 99 | * Secure Privileged |
| 100 | * Secure User, execution priority negative |
| 101 | * Secure Privileged, execution priority negative |
| 102 | * |
| 103 | * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code |
| 104 | * are not quite the same -- different CPU types (most notably M profile |
| 105 | * vs A/R profile) would like to use MMU indexes with different semantics, |
| 106 | * but since we don't ever need to use all of those in a single CPU we |
| 107 | * can avoid having to set NB_MMU_MODES to "total number of A profile MMU |
| 108 | * modes + total number of M profile MMU modes". The lower bits of |
| 109 | * ARMMMUIdx are the core TLB mmu index, and the higher bits are always |
| 110 | * the same for any particular CPU. |
| 111 | * Variables of type ARMMUIdx are always full values, and the core |
| 112 | * index values are in variables of type 'int'. |
| 113 | * |
| 114 | * Our enumeration includes at the end some entries which are not "true" |
| 115 | * mmu_idx values in that they don't have corresponding TLBs and are only |
| 116 | * valid for doing slow path page table walks. |
| 117 | * |
| 118 | * The constant names here are patterned after the general style of the names |
| 119 | * of the AT/ATS operations. |
| 120 | * The values used are carefully arranged to make mmu_idx => EL lookup easy. |
| 121 | * For M profile we arrange them to have a bit for priv, a bit for negpri |
| 122 | * and a bit for secure. |
| 123 | */ |
| 124 | #define ARM_MMU_IDX_A 0x20 /* A profile */ |
| 125 | #define ARM_MMU_IDX_NOTLB 0x40 /* does not have a TLB */ |
| 126 | #define ARM_MMU_IDX_M 0x80 /* M profile */ |
| 127 | |
| 128 | /* Meanings of the bits for M profile mmu idx values */ |
| 129 | #define ARM_MMU_IDX_M_PRIV 0x1 |
| 130 | #define ARM_MMU_IDX_M_NEGPRI 0x2 |
| 131 | #define ARM_MMU_IDX_M_S 0x4 /* Secure */ |
| 132 | |
| 133 | #define ARM_MMU_IDX_TYPE_MASK \ |
| 134 | (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) |
| 135 | #define ARM_MMU_IDX_COREIDX_MASK 0x1f |
| 136 | |
| 137 | typedef enum ARMMMUIdx { |
| 138 | /* |
| 139 | * A-profile. |
| 140 | */ |
| 141 | |
| 142 | ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, |
| 143 | ARMMMUIdx_E10_0_GCS = 1 | ARM_MMU_IDX_A, |
| 144 | ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, |
| 145 | ARMMMUIdx_E10_1_PAN = 3 | ARM_MMU_IDX_A, |
| 146 | ARMMMUIdx_E10_1_GCS = 4 | ARM_MMU_IDX_A, |
| 147 | |
| 148 | ARMMMUIdx_E20_0 = 5 | ARM_MMU_IDX_A, |
| 149 | ARMMMUIdx_E20_0_GCS = 6 | ARM_MMU_IDX_A, |
| 150 | ARMMMUIdx_E20_2 = 7 | ARM_MMU_IDX_A, |
| 151 | ARMMMUIdx_E20_2_PAN = 8 | ARM_MMU_IDX_A, |
| 152 | ARMMMUIdx_E20_2_GCS = 9 | ARM_MMU_IDX_A, |
| 153 | |
| 154 | ARMMMUIdx_E2 = 10 | ARM_MMU_IDX_A, |
| 155 | ARMMMUIdx_E2_GCS = 11 | ARM_MMU_IDX_A, |
| 156 | |
| 157 | ARMMMUIdx_E3 = 12 | ARM_MMU_IDX_A, |
| 158 | ARMMMUIdx_E3_GCS = 13 | ARM_MMU_IDX_A, |
| 159 | ARMMMUIdx_E30_0 = 14 | ARM_MMU_IDX_A, |
| 160 | ARMMMUIdx_E30_3_PAN = 15 | ARM_MMU_IDX_A, |
| 161 | |
| 162 | /* |
| 163 | * Used for second stage of an S12 page table walk, or for descriptor |
| 164 | * loads during first stage of an S1 page table walk. Note that both |
| 165 | * are in use simultaneously for SecureEL2: the security state for |
| 166 | * the S2 ptw is selected by the NS bit from the S1 ptw. |
| 167 | */ |
| 168 | ARMMMUIdx_Stage2_S = 16 | ARM_MMU_IDX_A, |
| 169 | ARMMMUIdx_Stage2 = 17 | ARM_MMU_IDX_A, |
| 170 | |
| 171 | /* TLBs with 1-1 mapping to the physical address spaces. */ |
| 172 | ARMMMUIdx_Phys_S = 18 | ARM_MMU_IDX_A, |
| 173 | ARMMMUIdx_Phys_NS = 19 | ARM_MMU_IDX_A, |
| 174 | ARMMMUIdx_Phys_Root = 20 | ARM_MMU_IDX_A, |
| 175 | ARMMMUIdx_Phys_Realm = 21 | ARM_MMU_IDX_A, |
| 176 | |
| 177 | /* |
| 178 | * These are not allocated TLBs and are used only for AT system |
| 179 | * instructions or for the first stage of an S12 page table walk. |
| 180 | */ |
| 181 | ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, |
| 182 | ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, |
| 183 | ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, |
| 184 | ARMMMUIdx_Stage1_E0_GCS = 3 | ARM_MMU_IDX_NOTLB, |
| 185 | ARMMMUIdx_Stage1_E1_GCS = 4 | ARM_MMU_IDX_NOTLB, |
| 186 | |
| 187 | /* |
| 188 | * M-profile. |
| 189 | */ |
| 190 | ARMMMUIdx_MUser = ARM_MMU_IDX_M, |
| 191 | ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, |
| 192 | ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, |
| 193 | ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, |
| 194 | ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, |
| 195 | ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, |
| 196 | ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, |
| 197 | ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, |
| 198 | } ARMMMUIdx; |
| 199 | |
| 200 | /* |
| 201 | * Bit macros for the core-mmu-index values for each index, |
| 202 | * for use when calling tlb_flush_by_mmuidx() and friends. |
| 203 | */ |
| 204 | #define TO_CORE_BIT(NAME) \ |
| 205 | ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) |
| 206 | |
| 207 | typedef enum ARMMMUIdxBit { |
| 208 | TO_CORE_BIT(E10_0), |
| 209 | TO_CORE_BIT(E10_0_GCS), |
| 210 | TO_CORE_BIT(E10_1), |
| 211 | TO_CORE_BIT(E10_1_PAN), |
| 212 | TO_CORE_BIT(E10_1_GCS), |
| 213 | TO_CORE_BIT(E20_0), |
| 214 | TO_CORE_BIT(E20_0_GCS), |
| 215 | TO_CORE_BIT(E20_2), |
| 216 | TO_CORE_BIT(E20_2_PAN), |
| 217 | TO_CORE_BIT(E20_2_GCS), |
| 218 | TO_CORE_BIT(E2), |
| 219 | TO_CORE_BIT(E2_GCS), |
| 220 | TO_CORE_BIT(E3), |
| 221 | TO_CORE_BIT(E3_GCS), |
| 222 | TO_CORE_BIT(E30_0), |
| 223 | TO_CORE_BIT(E30_3_PAN), |
| 224 | TO_CORE_BIT(Stage2), |
| 225 | TO_CORE_BIT(Stage2_S), |
| 226 | |
| 227 | TO_CORE_BIT(MUser), |
| 228 | TO_CORE_BIT(MPriv), |
| 229 | TO_CORE_BIT(MUserNegPri), |
| 230 | TO_CORE_BIT(MPrivNegPri), |
| 231 | TO_CORE_BIT(MSUser), |
| 232 | TO_CORE_BIT(MSPriv), |
| 233 | TO_CORE_BIT(MSUserNegPri), |
| 234 | TO_CORE_BIT(MSPrivNegPri), |
| 235 | } ARMMMUIdxBit; |
| 236 | |
| 237 | #undef TO_CORE_BIT |
| 238 | |
| 239 | #define MMU_USER_IDX 0 |
| 240 | |
| 241 | #endif /* TARGET_ARM_MMUIDX_H */ |