| 1 | /* |
| 2 | * QEMU AArch64 TCG CPUs |
| 3 | * |
| 4 | * Copyright (c) 2013 Linaro Ltd |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, see |
| 18 | * <http://www.gnu.org/licenses/gpl-2.0.html> |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qapi/error.h" |
| 23 | #include "cpu.h" |
| 24 | #include "qemu/module.h" |
| 25 | #include "qapi/visitor.h" |
| 26 | #include "hw/core/qdev-properties.h" |
| 27 | #include "qemu/units.h" |
| 28 | #include "internals.h" |
| 29 | #include "cpu-features.h" |
| 30 | #include "cpregs.h" |
| 31 | |
| 32 | static void aarch64_a35_initfn(Object *obj) |
| 33 | { |
| 34 | ARMCPU *cpu = ARM_CPU(obj); |
| 35 | ARMISARegisters *isar = &cpu->isar; |
| 36 | |
| 37 | cpu->dtb_compatible = "arm,cortex-a35"; |
| 38 | set_feature(&cpu->env, ARM_FEATURE_V8); |
| 39 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 40 | set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); |
| 41 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
| 42 | set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); |
| 43 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
| 44 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
| 45 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
| 46 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
| 47 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
| 48 | |
| 49 | /* From B2.2 AArch64 identification registers. */ |
| 50 | cpu->midr = 0x411fd040; |
| 51 | cpu->revidr = 0; |
| 52 | cpu->ctr = 0x84448004; |
| 53 | SET_IDREG(isar, ID_PFR0, 0x00000131); |
| 54 | SET_IDREG(isar, ID_PFR1, 0x00011011); |
| 55 | SET_IDREG(isar, ID_DFR0, 0x03010066); |
| 56 | SET_IDREG(isar, ID_AFR0, 0); |
| 57 | SET_IDREG(isar, ID_MMFR0, 0x10201105); |
| 58 | SET_IDREG(isar, ID_MMFR1, 0x40000000); |
| 59 | SET_IDREG(isar, ID_MMFR2, 0x01260000); |
| 60 | SET_IDREG(isar, ID_MMFR3, 0x02102211); |
| 61 | SET_IDREG(isar, ID_ISAR0, 0x02101110); |
| 62 | SET_IDREG(isar, ID_ISAR1, 0x13112111); |
| 63 | SET_IDREG(isar, ID_ISAR2, 0x21232042); |
| 64 | SET_IDREG(isar, ID_ISAR3, 0x01112131); |
| 65 | SET_IDREG(isar, ID_ISAR4, 0x00011142); |
| 66 | SET_IDREG(isar, ID_ISAR5, 0x00011121); |
| 67 | SET_IDREG(isar, ID_AA64PFR0, 0x00002222); |
| 68 | SET_IDREG(isar, ID_AA64PFR1, 0); |
| 69 | SET_IDREG(isar, ID_AA64DFR0, 0x10305106); |
| 70 | SET_IDREG(isar, ID_AA64DFR1, 0); |
| 71 | SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); |
| 72 | SET_IDREG(isar, ID_AA64ISAR1, 0); |
| 73 | SET_IDREG(isar, ID_AA64MMFR0, 0x00101122); |
| 74 | SET_IDREG(isar, ID_AA64MMFR1, 0); |
| 75 | SET_IDREG(isar, CLIDR, 0x0a200023); |
| 76 | set_dczid_bs(cpu, 4); |
| 77 | |
| 78 | /* From B2.4 AArch64 Virtual Memory control registers */ |
| 79 | cpu->reset_sctlr = 0x00c50838; |
| 80 | |
| 81 | /* From B2.10 AArch64 performance monitor registers */ |
| 82 | cpu->isar.reset_pmcr_el0 = 0x410a3000; |
| 83 | |
| 84 | /* From B2.29 Cache ID registers */ |
| 85 | /* 32KB L1 dcache */ |
| 86 | cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); |
| 87 | /* 32KB L1 icache */ |
| 88 | cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2); |
| 89 | /* 512KB L2 cache */ |
| 90 | cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7); |
| 91 | |
| 92 | /* From B3.5 VGIC Type register */ |
| 93 | cpu->gic_num_lrs = 4; |
| 94 | cpu->gic_vpribits = 5; |
| 95 | cpu->gic_vprebits = 5; |
| 96 | cpu->gic_pribits = 5; |
| 97 | |
| 98 | /* From C6.4 Debug ID Register */ |
| 99 | cpu->isar.dbgdidr = 0x3516d000; |
| 100 | /* From C6.5 Debug Device ID Register */ |
| 101 | cpu->isar.dbgdevid = 0x00110f13; |
| 102 | /* From C6.6 Debug Device ID Register 1 */ |
| 103 | cpu->isar.dbgdevid1 = 0x2; |
| 104 | |
| 105 | /* From Cortex-A35 SIMD and Floating-point Support r1p0 */ |
| 106 | /* From 3.2 AArch32 register summary */ |
| 107 | cpu->reset_fpsid = 0x41034043; |
| 108 | |
| 109 | /* From 2.2 AArch64 register summary */ |
| 110 | cpu->isar.mvfr0 = 0x10110222; |
| 111 | cpu->isar.mvfr1 = 0x12111111; |
| 112 | cpu->isar.mvfr2 = 0x00000043; |
| 113 | |
| 114 | /* These values are the same with A53/A57/A72. */ |
| 115 | define_cortex_a72_a57_a53_cp_reginfo(cpu); |
| 116 | } |
| 117 | |
| 118 | static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, |
| 119 | void *opaque, Error **errp) |
| 120 | { |
| 121 | ARMCPU *cpu = ARM_CPU(obj); |
| 122 | uint32_t value; |
| 123 | |
| 124 | /* All vector lengths are disabled when SVE is off. */ |
| 125 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
| 126 | value = 0; |
| 127 | } else { |
| 128 | value = cpu->sve_max_vq; |
| 129 | } |
| 130 | visit_type_uint32(v, name, &value, errp); |
| 131 | } |
| 132 | |
| 133 | static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, |
| 134 | void *opaque, Error **errp) |
| 135 | { |
| 136 | ARMCPU *cpu = ARM_CPU(obj); |
| 137 | uint32_t max_vq; |
| 138 | |
| 139 | if (!visit_type_uint32(v, name, &max_vq, errp)) { |
| 140 | return; |
| 141 | } |
| 142 | |
| 143 | if (max_vq == 0 || max_vq > ARM_MAX_VQ) { |
| 144 | error_setg(errp, "unsupported SVE vector length"); |
| 145 | error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", |
| 146 | ARM_MAX_VQ); |
| 147 | return; |
| 148 | } |
| 149 | |
| 150 | cpu->sve_max_vq = max_vq; |
| 151 | } |
| 152 | |
| 153 | static bool cpu_arm_get_rme(Object *obj, Error **errp) |
| 154 | { |
| 155 | ARMCPU *cpu = ARM_CPU(obj); |
| 156 | return cpu_isar_feature(aa64_rme, cpu); |
| 157 | } |
| 158 | |
| 159 | static void cpu_arm_set_rme(Object *obj, bool value, Error **errp) |
| 160 | { |
| 161 | ARMCPU *cpu = ARM_CPU(obj); |
| 162 | |
| 163 | /* Enable FEAT_RME_GPC3 */ |
| 164 | FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, RME, value ? 3 : 0); |
| 165 | } |
| 166 | |
| 167 | static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, |
| 168 | void *opaque, Error **errp) |
| 169 | { |
| 170 | ARMCPU *cpu = ARM_CPU(obj); |
| 171 | uint32_t value; |
| 172 | |
| 173 | if (!visit_type_uint32(v, name, &value, errp)) { |
| 174 | return; |
| 175 | } |
| 176 | |
| 177 | /* Encode the value for the GPCCR_EL3 field. */ |
| 178 | switch (value) { |
| 179 | case 30: |
| 180 | case 34: |
| 181 | case 36: |
| 182 | case 39: |
| 183 | cpu->reset_l0gptsz = value - 30; |
| 184 | break; |
| 185 | default: |
| 186 | error_setg(errp, "invalid value for l0gptsz"); |
| 187 | error_append_hint(errp, "valid values are 30, 34, 36, 39\n"); |
| 188 | break; |
| 189 | } |
| 190 | } |
| 191 | |
| 192 | static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name, |
| 193 | void *opaque, Error **errp) |
| 194 | { |
| 195 | ARMCPU *cpu = ARM_CPU(obj); |
| 196 | uint32_t value = cpu->reset_l0gptsz + 30; |
| 197 | |
| 198 | visit_type_uint32(v, name, &value, errp); |
| 199 | } |
| 200 | |
| 201 | static const Property arm_cpu_lpa2_property = |
| 202 | DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); |
| 203 | |
| 204 | static void aarch64_a55_initfn(Object *obj) |
| 205 | { |
| 206 | ARMCPU *cpu = ARM_CPU(obj); |
| 207 | ARMISARegisters *isar = &cpu->isar; |
| 208 | |
| 209 | cpu->dtb_compatible = "arm,cortex-a55"; |
| 210 | set_feature(&cpu->env, ARM_FEATURE_V8); |
| 211 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 212 | set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); |
| 213 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
| 214 | set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); |
| 215 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
| 216 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
| 217 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
| 218 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
| 219 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
| 220 | |
| 221 | /* Ordered by B2.4 AArch64 registers by functional group */ |
| 222 | SET_IDREG(isar, CLIDR, 0x82000023); |
| 223 | cpu->ctr = 0x84448004; /* L1Ip = VIPT */ |
| 224 | set_dczid_bs(cpu, 4); /* 64 bytes */ |
| 225 | SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull); |
| 226 | SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); |
| 227 | SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); |
| 228 | SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); |
| 229 | SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); |
| 230 | SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); |
| 231 | SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull); |
| 232 | SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); |
| 233 | SET_IDREG(isar, ID_AFR0, 0x00000000); |
| 234 | SET_IDREG(isar, ID_DFR0, 0x04010088); |
| 235 | SET_IDREG(isar, ID_ISAR0, 0x02101110); |
| 236 | SET_IDREG(isar, ID_ISAR1, 0x13112111); |
| 237 | SET_IDREG(isar, ID_ISAR2, 0x21232042); |
| 238 | SET_IDREG(isar, ID_ISAR3, 0x01112131); |
| 239 | SET_IDREG(isar, ID_ISAR4, 0x00011142); |
| 240 | SET_IDREG(isar, ID_ISAR5, 0x01011121); |
| 241 | SET_IDREG(isar, ID_ISAR6, 0x00000010); |
| 242 | SET_IDREG(isar, ID_MMFR0, 0x10201105); |
| 243 | SET_IDREG(isar, ID_MMFR1, 0x40000000); |
| 244 | SET_IDREG(isar, ID_MMFR2, 0x01260000); |
| 245 | SET_IDREG(isar, ID_MMFR3, 0x02122211); |
| 246 | SET_IDREG(isar, ID_MMFR4, 0x00021110); |
| 247 | SET_IDREG(isar, ID_PFR0, 0x10010131); |
| 248 | SET_IDREG(isar, ID_PFR1, 0x00011011); |
| 249 | SET_IDREG(isar, ID_PFR2, 0x00000011); |
| 250 | cpu->midr = 0x412FD050; /* r2p0 */ |
| 251 | cpu->revidr = 0; |
| 252 | |
| 253 | /* From B2.23 CCSIDR_EL1 */ |
| 254 | /* 32KB L1 dcache */ |
| 255 | cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); |
| 256 | /* 32KB L1 icache */ |
| 257 | cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2); |
| 258 | /* 512KB L2 cache */ |
| 259 | cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7); |
| 260 | |
| 261 | /* From B2.96 SCTLR_EL3 */ |
| 262 | cpu->reset_sctlr = 0x30c50838; |
| 263 | |
| 264 | /* From B4.45 ICH_VTR_EL2 */ |
| 265 | cpu->gic_num_lrs = 4; |
| 266 | cpu->gic_vpribits = 5; |
| 267 | cpu->gic_vprebits = 5; |
| 268 | cpu->gic_pribits = 5; |
| 269 | |
| 270 | cpu->isar.mvfr0 = 0x10110222; |
| 271 | cpu->isar.mvfr1 = 0x13211111; |
| 272 | cpu->isar.mvfr2 = 0x00000043; |
| 273 | |
| 274 | /* From D5.4 AArch64 PMU register summary */ |
| 275 | cpu->isar.reset_pmcr_el0 = 0x410b3000; |
| 276 | } |
| 277 | |
| 278 | static void aarch64_a72_initfn(Object *obj) |
| 279 | { |
| 280 | ARMCPU *cpu = ARM_CPU(obj); |
| 281 | ARMISARegisters *isar = &cpu->isar; |
| 282 | |
| 283 | cpu->dtb_compatible = "arm,cortex-a72"; |
| 284 | set_feature(&cpu->env, ARM_FEATURE_V8); |
| 285 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 286 | set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); |
| 287 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
| 288 | set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); |
| 289 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
| 290 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
| 291 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
| 292 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
| 293 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
| 294 | cpu->midr = 0x410fd083; |
| 295 | cpu->revidr = 0x00000000; |
| 296 | cpu->reset_fpsid = 0x41034080; |
| 297 | cpu->isar.mvfr0 = 0x10110222; |
| 298 | cpu->isar.mvfr1 = 0x12111111; |
| 299 | cpu->isar.mvfr2 = 0x00000043; |
| 300 | cpu->ctr = 0x8444c004; |
| 301 | cpu->reset_sctlr = 0x00c50838; |
| 302 | SET_IDREG(isar, ID_PFR0, 0x00000131); |
| 303 | SET_IDREG(isar, ID_PFR1, 0x00011011); |
| 304 | SET_IDREG(isar, ID_DFR0, 0x03010066); |
| 305 | SET_IDREG(isar, ID_AFR0, 0x00000000); |
| 306 | SET_IDREG(isar, ID_MMFR0, 0x10201105); |
| 307 | SET_IDREG(isar, ID_MMFR1, 0x40000000); |
| 308 | SET_IDREG(isar, ID_MMFR2, 0x01260000); |
| 309 | SET_IDREG(isar, ID_MMFR3, 0x02102211); |
| 310 | SET_IDREG(isar, ID_ISAR0, 0x02101110); |
| 311 | SET_IDREG(isar, ID_ISAR1, 0x13112111); |
| 312 | SET_IDREG(isar, ID_ISAR2, 0x21232042); |
| 313 | SET_IDREG(isar, ID_ISAR3, 0x01112131); |
| 314 | SET_IDREG(isar, ID_ISAR4, 0x00011142); |
| 315 | SET_IDREG(isar, ID_ISAR5, 0x00011121); |
| 316 | SET_IDREG(isar, ID_AA64PFR0, 0x00002222); |
| 317 | SET_IDREG(isar, ID_AA64DFR0, 0x10305106); |
| 318 | SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); |
| 319 | SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); |
| 320 | cpu->isar.dbgdidr = 0x3516d000; |
| 321 | cpu->isar.dbgdevid = 0x01110f13; |
| 322 | cpu->isar.dbgdevid1 = 0x2; |
| 323 | cpu->isar.reset_pmcr_el0 = 0x41023000; |
| 324 | SET_IDREG(isar, CLIDR, 0x0a200023); |
| 325 | /* 32KB L1 dcache */ |
| 326 | cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); |
| 327 | /* 48KB L1 dcache */ |
| 328 | cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2); |
| 329 | /* 1MB L2 cache */ |
| 330 | cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7); |
| 331 | set_dczid_bs(cpu, 4); /* 64 bytes */ |
| 332 | cpu->gic_num_lrs = 4; |
| 333 | cpu->gic_vpribits = 5; |
| 334 | cpu->gic_vprebits = 5; |
| 335 | cpu->gic_pribits = 5; |
| 336 | define_cortex_a72_a57_a53_cp_reginfo(cpu); |
| 337 | } |
| 338 | |
| 339 | static void aarch64_a76_initfn(Object *obj) |
| 340 | { |
| 341 | ARMCPU *cpu = ARM_CPU(obj); |
| 342 | ARMISARegisters *isar = &cpu->isar; |
| 343 | |
| 344 | cpu->dtb_compatible = "arm,cortex-a76"; |
| 345 | set_feature(&cpu->env, ARM_FEATURE_V8); |
| 346 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 347 | set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); |
| 348 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
| 349 | set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); |
| 350 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
| 351 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
| 352 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
| 353 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
| 354 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
| 355 | |
| 356 | /* Ordered by B2.4 AArch64 registers by functional group */ |
| 357 | SET_IDREG(isar, CLIDR, 0x82000023); |
| 358 | cpu->ctr = 0x8444C004; |
| 359 | set_dczid_bs(cpu, 4); |
| 360 | SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull); |
| 361 | SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); |
| 362 | SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); |
| 363 | SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); |
| 364 | SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); |
| 365 | SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); |
| 366 | SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */ |
| 367 | SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); |
| 368 | SET_IDREG(isar, ID_AFR0, 0x00000000); |
| 369 | SET_IDREG(isar, ID_DFR0, 0x04010088); |
| 370 | SET_IDREG(isar, ID_ISAR0, 0x02101110); |
| 371 | SET_IDREG(isar, ID_ISAR1, 0x13112111); |
| 372 | SET_IDREG(isar, ID_ISAR2, 0x21232042); |
| 373 | SET_IDREG(isar, ID_ISAR3, 0x01112131); |
| 374 | SET_IDREG(isar, ID_ISAR4, 0x00010142); |
| 375 | SET_IDREG(isar, ID_ISAR5, 0x01011121); |
| 376 | SET_IDREG(isar, ID_ISAR6, 0x00000010); |
| 377 | SET_IDREG(isar, ID_MMFR0, 0x10201105); |
| 378 | SET_IDREG(isar, ID_MMFR1, 0x40000000); |
| 379 | SET_IDREG(isar, ID_MMFR2, 0x01260000); |
| 380 | SET_IDREG(isar, ID_MMFR3, 0x02122211); |
| 381 | SET_IDREG(isar, ID_MMFR4, 0x00021110); |
| 382 | SET_IDREG(isar, ID_PFR0, 0x10010131); |
| 383 | SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ |
| 384 | SET_IDREG(isar, ID_PFR2, 0x00000011); |
| 385 | cpu->midr = 0x414fd0b1; /* r4p1 */ |
| 386 | cpu->revidr = 0; |
| 387 | |
| 388 | /* From B2.18 CCSIDR_EL1 */ |
| 389 | /* 64KB L1 dcache */ |
| 390 | cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); |
| 391 | /* 64KB L1 icache */ |
| 392 | cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); |
| 393 | /* 512KB L2 cache */ |
| 394 | cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7); |
| 395 | |
| 396 | /* From B2.93 SCTLR_EL3 */ |
| 397 | cpu->reset_sctlr = 0x30c50838; |
| 398 | |
| 399 | /* From B4.23 ICH_VTR_EL2 */ |
| 400 | cpu->gic_num_lrs = 4; |
| 401 | cpu->gic_vpribits = 5; |
| 402 | cpu->gic_vprebits = 5; |
| 403 | cpu->gic_pribits = 5; |
| 404 | |
| 405 | /* From B5.1 AdvSIMD AArch64 register summary */ |
| 406 | cpu->isar.mvfr0 = 0x10110222; |
| 407 | cpu->isar.mvfr1 = 0x13211111; |
| 408 | cpu->isar.mvfr2 = 0x00000043; |
| 409 | |
| 410 | /* From D5.1 AArch64 PMU register summary */ |
| 411 | cpu->isar.reset_pmcr_el0 = 0x410b3000; |
| 412 | } |
| 413 | |
| 414 | static void aarch64_a78ae_initfn(Object *obj) |
| 415 | { |
| 416 | ARMCPU *cpu = ARM_CPU(obj); |
| 417 | ARMISARegisters *isar = &cpu->isar; |
| 418 | |
| 419 | cpu->dtb_compatible = "arm,cortex-a78ae"; |
| 420 | set_feature(&cpu->env, ARM_FEATURE_V8); |
| 421 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 422 | set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); |
| 423 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
| 424 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
| 425 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
| 426 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
| 427 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
| 428 | |
| 429 | /* Ordered by 3.2.4 AArch64 registers by functional group */ |
| 430 | SET_IDREG(isar, CLIDR, 0x82000023); |
| 431 | cpu->ctr = 0x9444c004; |
| 432 | set_dczid_bs(cpu, 4); |
| 433 | SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull); |
| 434 | SET_IDREG(isar, ID_AA64ISAR0, 0x0010100010211120ull); |
| 435 | SET_IDREG(isar, ID_AA64ISAR1, 0x0000000001200031ull); |
| 436 | SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); |
| 437 | SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); |
| 438 | SET_IDREG(isar, ID_AA64MMFR2, 0x0000000100001011ull); |
| 439 | SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */ |
| 440 | SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); |
| 441 | SET_IDREG(isar, ID_AFR0, 0x00000000); |
| 442 | SET_IDREG(isar, ID_DFR0, 0x04010088); |
| 443 | SET_IDREG(isar, ID_ISAR0, 0x02101110); |
| 444 | SET_IDREG(isar, ID_ISAR1, 0x13112111); |
| 445 | SET_IDREG(isar, ID_ISAR2, 0x21232042); |
| 446 | SET_IDREG(isar, ID_ISAR3, 0x01112131); |
| 447 | SET_IDREG(isar, ID_ISAR4, 0x00010142); |
| 448 | SET_IDREG(isar, ID_ISAR5, 0x01011121); |
| 449 | SET_IDREG(isar, ID_ISAR6, 0x00000010); |
| 450 | SET_IDREG(isar, ID_MMFR0, 0x10201105); |
| 451 | SET_IDREG(isar, ID_MMFR1, 0x40000000); |
| 452 | SET_IDREG(isar, ID_MMFR2, 0x01260000); |
| 453 | SET_IDREG(isar, ID_MMFR3, 0x02122211); |
| 454 | SET_IDREG(isar, ID_MMFR4, 0x00021110); |
| 455 | SET_IDREG(isar, ID_PFR0, 0x10010131); |
| 456 | SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ |
| 457 | SET_IDREG(isar, ID_PFR2, 0x00000011); |
| 458 | cpu->midr = 0x410fd423; /* r0p3 */ |
| 459 | cpu->revidr = 0; |
| 460 | |
| 461 | /* From 3.2.33 CCSIDR_EL1 */ |
| 462 | /* 64KB L1 dcache */ |
| 463 | cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); |
| 464 | /* 64KB L1 icache */ |
| 465 | cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); |
| 466 | /* 512KB L2 cache */ |
| 467 | cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7); |
| 468 | |
| 469 | /* From 3.2.118 SCTLR_EL3 */ |
| 470 | cpu->reset_sctlr = 0x30c50838; |
| 471 | |
| 472 | /* From 3.4.23 ICH_VTR_EL2 */ |
| 473 | cpu->gic_num_lrs = 4; |
| 474 | cpu->gic_vpribits = 5; |
| 475 | cpu->gic_vprebits = 5; |
| 476 | /* From 3.4.8 ICC_CTLR_EL3 */ |
| 477 | cpu->gic_pribits = 5; |
| 478 | |
| 479 | /* From 3.5.1 AdvSIMD AArch64 register summary */ |
| 480 | cpu->isar.mvfr0 = 0x10110222; |
| 481 | cpu->isar.mvfr1 = 0x13211111; |
| 482 | cpu->isar.mvfr2 = 0x00000043; |
| 483 | |
| 484 | /* From 5.5.1 AArch64 PMU register summary */ |
| 485 | cpu->isar.reset_pmcr_el0 = 0x41223000; |
| 486 | } |
| 487 | |
| 488 | static void aarch64_a64fx_initfn(Object *obj) |
| 489 | { |
| 490 | ARMCPU *cpu = ARM_CPU(obj); |
| 491 | ARMISARegisters *isar = &cpu->isar; |
| 492 | |
| 493 | cpu->dtb_compatible = "arm,a64fx"; |
| 494 | set_feature(&cpu->env, ARM_FEATURE_V8); |
| 495 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 496 | set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); |
| 497 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
| 498 | set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); |
| 499 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
| 500 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
| 501 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
| 502 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
| 503 | cpu->midr = 0x461f0010; |
| 504 | cpu->revidr = 0x00000000; |
| 505 | cpu->ctr = 0x86668006; |
| 506 | cpu->reset_sctlr = 0x30000180; |
| 507 | SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions */ |
| 508 | SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000); |
| 509 | SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408); |
| 510 | SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000); |
| 511 | SET_IDREG(isar, ID_AA64AFR0, 0x0000000000000000); |
| 512 | SET_IDREG(isar, ID_AA64AFR1, 0x0000000000000000); |
| 513 | SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122); |
| 514 | SET_IDREG(isar, ID_AA64MMFR1, 0x0000000011212100); |
| 515 | SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011); |
| 516 | SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120); |
| 517 | SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000010001); |
| 518 | SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000); |
| 519 | SET_IDREG(isar, CLIDR, 0x0000000080000023); |
| 520 | /* 64KB L1 dcache */ |
| 521 | cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 7); |
| 522 | /* 64KB L1 icache */ |
| 523 | cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 2); |
| 524 | /* 8MB L2 cache */ |
| 525 | cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 256, 8 * MiB, 7); |
| 526 | set_dczid_bs(cpu, 6); /* 256 bytes */ |
| 527 | cpu->gic_num_lrs = 4; |
| 528 | cpu->gic_vpribits = 5; |
| 529 | cpu->gic_vprebits = 5; |
| 530 | cpu->gic_pribits = 5; |
| 531 | |
| 532 | /* The A64FX supports only 128, 256 and 512 bit vector lengths */ |
| 533 | cpu->sve_vq.supported = (1 << 0) /* 128bit */ |
| 534 | | (1 << 1) /* 256bit */ |
| 535 | | (1 << 3); /* 512bit */ |
| 536 | aarch64_add_sve_properties(obj); |
| 537 | |
| 538 | cpu->isar.reset_pmcr_el0 = 0x46014040; |
| 539 | |
| 540 | /* TODO: Add A64FX specific HPC extension registers */ |
| 541 | } |
| 542 | |
| 543 | static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r, |
| 544 | bool read) |
| 545 | { |
| 546 | if (!read) { |
| 547 | int el = arm_current_el(env); |
| 548 | |
| 549 | /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */ |
| 550 | if (el < 2 && arm_is_el2_enabled(env)) { |
| 551 | return CP_ACCESS_TRAP_EL2; |
| 552 | } |
| 553 | /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */ |
| 554 | if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { |
| 555 | return CP_ACCESS_TRAP_EL3; |
| 556 | } |
| 557 | } |
| 558 | return CP_ACCESS_OK; |
| 559 | } |
| 560 | |
| 561 | static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { |
| 562 | { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64, |
| 563 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0, |
| 564 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 565 | /* Traps and enables are the same as for TCR_EL1. */ |
| 566 | .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, }, |
| 567 | { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64, |
| 568 | .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0, |
| 569 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 570 | { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64, |
| 571 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0, |
| 572 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 573 | { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64, |
| 574 | .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0, |
| 575 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 576 | { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64, |
| 577 | .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1, |
| 578 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 579 | { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, |
| 580 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0, |
| 581 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 582 | .accessfn = access_actlr_w }, |
| 583 | { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, |
| 584 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1, |
| 585 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 586 | .accessfn = access_actlr_w }, |
| 587 | { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, |
| 588 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2, |
| 589 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 590 | .accessfn = access_actlr_w }, |
| 591 | /* |
| 592 | * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU |
| 593 | * (and in particular its system registers). |
| 594 | */ |
| 595 | { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64, |
| 596 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0, |
| 597 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, |
| 598 | { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, |
| 599 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4, |
| 600 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010, |
| 601 | .accessfn = access_actlr_w }, |
| 602 | { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64, |
| 603 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1, |
| 604 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 605 | { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64, |
| 606 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3, |
| 607 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 608 | { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64, |
| 609 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2, |
| 610 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 611 | { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64, |
| 612 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0, |
| 613 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 614 | { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64, |
| 615 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, |
| 616 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 617 | .accessfn = access_actlr_w }, |
| 618 | { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64, |
| 619 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2, |
| 620 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 621 | .accessfn = access_actlr_w }, |
| 622 | { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64, |
| 623 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1, |
| 624 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 625 | .accessfn = access_actlr_w }, |
| 626 | { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64, |
| 627 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, |
| 628 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 629 | .accessfn = access_actlr_w }, |
| 630 | }; |
| 631 | |
| 632 | static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) |
| 633 | { |
| 634 | define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); |
| 635 | } |
| 636 | |
| 637 | static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = { |
| 638 | { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64, |
| 639 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5, |
| 640 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 641 | .accessfn = access_actlr_w }, |
| 642 | { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, |
| 643 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0, |
| 644 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 645 | { .name = "CPUPPMCR2_EL3", .state = ARM_CP_STATE_AA64, |
| 646 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 1, |
| 647 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 648 | { .name = "CPUPPMCR3_EL3", .state = ARM_CP_STATE_AA64, |
| 649 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 6, |
| 650 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 651 | }; |
| 652 | |
| 653 | static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) |
| 654 | { |
| 655 | /* |
| 656 | * The Neoverse V1 has all of the Neoverse N1's IMPDEF |
| 657 | * registers and a few more of its own. |
| 658 | */ |
| 659 | define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); |
| 660 | define_arm_cp_regs(cpu, neoverse_v1_cp_reginfo); |
| 661 | } |
| 662 | |
| 663 | static void aarch64_neoverse_n1_initfn(Object *obj) |
| 664 | { |
| 665 | ARMCPU *cpu = ARM_CPU(obj); |
| 666 | ARMISARegisters *isar = &cpu->isar; |
| 667 | |
| 668 | cpu->dtb_compatible = "arm,neoverse-n1"; |
| 669 | set_feature(&cpu->env, ARM_FEATURE_V8); |
| 670 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 671 | set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); |
| 672 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
| 673 | set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); |
| 674 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
| 675 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
| 676 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
| 677 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
| 678 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
| 679 | |
| 680 | /* Ordered by B2.4 AArch64 registers by functional group */ |
| 681 | SET_IDREG(isar, CLIDR, 0x82000023); |
| 682 | cpu->ctr = 0x8444c004; |
| 683 | set_dczid_bs(cpu, 4); |
| 684 | SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull); |
| 685 | SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); |
| 686 | SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); |
| 687 | SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); |
| 688 | SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); |
| 689 | SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); |
| 690 | SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */ |
| 691 | SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); |
| 692 | SET_IDREG(isar, ID_AFR0, 0x00000000); |
| 693 | SET_IDREG(isar, ID_DFR0, 0x04010088); |
| 694 | SET_IDREG(isar, ID_ISAR0, 0x02101110); |
| 695 | SET_IDREG(isar, ID_ISAR1, 0x13112111); |
| 696 | SET_IDREG(isar, ID_ISAR2, 0x21232042); |
| 697 | SET_IDREG(isar, ID_ISAR3, 0x01112131); |
| 698 | SET_IDREG(isar, ID_ISAR4, 0x00010142); |
| 699 | SET_IDREG(isar, ID_ISAR5, 0x01011121); |
| 700 | SET_IDREG(isar, ID_ISAR6, 0x00000010); |
| 701 | SET_IDREG(isar, ID_MMFR0, 0x10201105); |
| 702 | SET_IDREG(isar, ID_MMFR1, 0x40000000); |
| 703 | SET_IDREG(isar, ID_MMFR2, 0x01260000); |
| 704 | SET_IDREG(isar, ID_MMFR3, 0x02122211); |
| 705 | SET_IDREG(isar, ID_MMFR4, 0x00021110); |
| 706 | SET_IDREG(isar, ID_PFR0, 0x10010131); |
| 707 | SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ |
| 708 | SET_IDREG(isar, ID_PFR2, 0x00000011); |
| 709 | cpu->midr = 0x414fd0c1; /* r4p1 */ |
| 710 | cpu->revidr = 0; |
| 711 | |
| 712 | /* From B2.23 CCSIDR_EL1 */ |
| 713 | /* 64KB L1 dcache */ |
| 714 | cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); |
| 715 | /* 64KB L1 icache */ |
| 716 | cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); |
| 717 | /* 1MB L2 dcache */ |
| 718 | cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); |
| 719 | |
| 720 | /* From B2.98 SCTLR_EL3 */ |
| 721 | cpu->reset_sctlr = 0x30c50838; |
| 722 | |
| 723 | /* From B4.23 ICH_VTR_EL2 */ |
| 724 | cpu->gic_num_lrs = 4; |
| 725 | cpu->gic_vpribits = 5; |
| 726 | cpu->gic_vprebits = 5; |
| 727 | cpu->gic_pribits = 5; |
| 728 | |
| 729 | /* From B5.1 AdvSIMD AArch64 register summary */ |
| 730 | cpu->isar.mvfr0 = 0x10110222; |
| 731 | cpu->isar.mvfr1 = 0x13211111; |
| 732 | cpu->isar.mvfr2 = 0x00000043; |
| 733 | |
| 734 | /* From D5.1 AArch64 PMU register summary */ |
| 735 | cpu->isar.reset_pmcr_el0 = 0x410c3000; |
| 736 | |
| 737 | define_neoverse_n1_cp_reginfo(cpu); |
| 738 | } |
| 739 | |
| 740 | static void aarch64_neoverse_v1_initfn(Object *obj) |
| 741 | { |
| 742 | ARMCPU *cpu = ARM_CPU(obj); |
| 743 | ARMISARegisters *isar = &cpu->isar; |
| 744 | |
| 745 | cpu->dtb_compatible = "arm,neoverse-v1"; |
| 746 | set_feature(&cpu->env, ARM_FEATURE_V8); |
| 747 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 748 | set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); |
| 749 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
| 750 | set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); |
| 751 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
| 752 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
| 753 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
| 754 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
| 755 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
| 756 | |
| 757 | /* Ordered by 3.2.4 AArch64 registers by functional group */ |
| 758 | SET_IDREG(isar, CLIDR, 0x82000023); |
| 759 | cpu->ctr = 0xb444c004; /* With DIC and IDC set */ |
| 760 | set_dczid_bs(cpu, 4); |
| 761 | SET_IDREG(isar, ID_AA64AFR0, 0x00000000); |
| 762 | SET_IDREG(isar, ID_AA64AFR1, 0x00000000); |
| 763 | SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull); |
| 764 | SET_IDREG(isar, ID_AA64DFR1, 0x00000000); |
| 765 | SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */ |
| 766 | SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull); |
| 767 | SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); |
| 768 | SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); |
| 769 | SET_IDREG(isar, ID_AA64MMFR2, 0x0220011102101011ull); |
| 770 | SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in later */ |
| 771 | SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); |
| 772 | SET_IDREG(isar, ID_AFR0, 0x00000000); |
| 773 | SET_IDREG(isar, ID_DFR0, 0x15011099); |
| 774 | SET_IDREG(isar, ID_ISAR0, 0x02101110); |
| 775 | SET_IDREG(isar, ID_ISAR1, 0x13112111); |
| 776 | SET_IDREG(isar, ID_ISAR2, 0x21232042); |
| 777 | SET_IDREG(isar, ID_ISAR3, 0x01112131); |
| 778 | SET_IDREG(isar, ID_ISAR4, 0x00010142); |
| 779 | SET_IDREG(isar, ID_ISAR5, 0x11011121); |
| 780 | SET_IDREG(isar, ID_ISAR6, 0x01100111); |
| 781 | SET_IDREG(isar, ID_MMFR0, 0x10201105); |
| 782 | SET_IDREG(isar, ID_MMFR1, 0x40000000); |
| 783 | SET_IDREG(isar, ID_MMFR2, 0x01260000); |
| 784 | SET_IDREG(isar, ID_MMFR3, 0x02122211); |
| 785 | SET_IDREG(isar, ID_MMFR4, 0x01021110); |
| 786 | SET_IDREG(isar, ID_PFR0, 0x21110131); |
| 787 | SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ |
| 788 | SET_IDREG(isar, ID_PFR2, 0x00000011); |
| 789 | cpu->midr = 0x411FD402; /* r1p2 */ |
| 790 | cpu->revidr = 0; |
| 791 | |
| 792 | /* |
| 793 | * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values, |
| 794 | * but also says it implements CCIDX, which means they should be |
| 795 | * 64-bit format. So we here use values which are based on the textual |
| 796 | * information in chapter 2 of the TRM: |
| 797 | * |
| 798 | * L1: 4-way set associative 64-byte line size, total size 64K. |
| 799 | * L2: 8-way set associative, 64 byte line size, either 512K or 1MB. |
| 800 | * L3: No L3 (this matches the CLIDR_EL1 value). |
| 801 | */ |
| 802 | /* 64KB L1 dcache */ |
| 803 | cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); |
| 804 | /* 64KB L1 icache */ |
| 805 | cpu->ccsidr[1] = cpu->ccsidr[0]; |
| 806 | /* 1MB L2 cache */ |
| 807 | cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 1 * MiB, 0); |
| 808 | |
| 809 | /* From 3.2.115 SCTLR_EL3 */ |
| 810 | cpu->reset_sctlr = 0x30c50838; |
| 811 | |
| 812 | /* From 3.4.8 ICC_CTLR_EL3 and 3.4.23 ICH_VTR_EL2 */ |
| 813 | cpu->gic_num_lrs = 4; |
| 814 | cpu->gic_vpribits = 5; |
| 815 | cpu->gic_vprebits = 5; |
| 816 | cpu->gic_pribits = 5; |
| 817 | |
| 818 | /* From 3.5.1 AdvSIMD AArch64 register summary */ |
| 819 | cpu->isar.mvfr0 = 0x10110222; |
| 820 | cpu->isar.mvfr1 = 0x13211111; |
| 821 | cpu->isar.mvfr2 = 0x00000043; |
| 822 | |
| 823 | /* From 3.7.5 ID_AA64ZFR0_EL1 */ |
| 824 | SET_IDREG(isar, ID_AA64ZFR0, 0x0000100000100000); |
| 825 | cpu->sve_vq.supported = (1 << 0) /* 128bit */ |
| 826 | | (1 << 1); /* 256bit */ |
| 827 | |
| 828 | /* From 5.5.1 AArch64 PMU register summary */ |
| 829 | cpu->isar.reset_pmcr_el0 = 0x41213000; |
| 830 | |
| 831 | define_neoverse_v1_cp_reginfo(cpu); |
| 832 | |
| 833 | aarch64_add_pauth_properties(obj); |
| 834 | aarch64_add_sve_properties(obj); |
| 835 | } |
| 836 | |
| 837 | static const ARMCPRegInfo cortex_a710_cp_reginfo[] = { |
| 838 | { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, |
| 839 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0, |
| 840 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 841 | .accessfn = access_actlr_w }, |
| 842 | { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, |
| 843 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1, |
| 844 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 845 | .accessfn = access_actlr_w }, |
| 846 | { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, |
| 847 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2, |
| 848 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 849 | .accessfn = access_actlr_w }, |
| 850 | { .name = "CPUACTLR4_EL1", .state = ARM_CP_STATE_AA64, |
| 851 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 3, |
| 852 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 853 | .accessfn = access_actlr_w }, |
| 854 | { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, |
| 855 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4, |
| 856 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 857 | .accessfn = access_actlr_w }, |
| 858 | { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64, |
| 859 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5, |
| 860 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 861 | .accessfn = access_actlr_w }, |
| 862 | { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, |
| 863 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 4, |
| 864 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 865 | { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64, |
| 866 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, |
| 867 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 868 | .accessfn = access_actlr_w }, |
| 869 | { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64, |
| 870 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0, |
| 871 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 872 | { .name = "CPUACTLR5_EL1", .state = ARM_CP_STATE_AA64, |
| 873 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 0, |
| 874 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 875 | .accessfn = access_actlr_w }, |
| 876 | { .name = "CPUACTLR6_EL1", .state = ARM_CP_STATE_AA64, |
| 877 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 1, |
| 878 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 879 | .accessfn = access_actlr_w }, |
| 880 | { .name = "CPUACTLR7_EL1", .state = ARM_CP_STATE_AA64, |
| 881 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 2, |
| 882 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
| 883 | .accessfn = access_actlr_w }, |
| 884 | { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64, |
| 885 | .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0, |
| 886 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 887 | { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64, |
| 888 | .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1, |
| 889 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 890 | { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, |
| 891 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0, |
| 892 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 893 | { .name = "CPUPPMCR2_EL3", .state = ARM_CP_STATE_AA64, |
| 894 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 1, |
| 895 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 896 | { .name = "CPUPPMCR4_EL3", .state = ARM_CP_STATE_AA64, |
| 897 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 4, |
| 898 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 899 | { .name = "CPUPPMCR5_EL3", .state = ARM_CP_STATE_AA64, |
| 900 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 5, |
| 901 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 902 | { .name = "CPUPPMCR6_EL3", .state = ARM_CP_STATE_AA64, |
| 903 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 6, |
| 904 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 905 | { .name = "CPUACTLR_EL3", .state = ARM_CP_STATE_AA64, |
| 906 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 4, .opc2 = 0, |
| 907 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 908 | { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64, |
| 909 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0, |
| 910 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 911 | { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64, |
| 912 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0, |
| 913 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 914 | { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64, |
| 915 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1, |
| 916 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 917 | { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64, |
| 918 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2, |
| 919 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 920 | { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64, |
| 921 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3, |
| 922 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 923 | { .name = "CPUPOR2_EL3", .state = ARM_CP_STATE_AA64, |
| 924 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 4, |
| 925 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 926 | { .name = "CPUPMR2_EL3", .state = ARM_CP_STATE_AA64, |
| 927 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 5, |
| 928 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 929 | { .name = "CPUPFR_EL3", .state = ARM_CP_STATE_AA64, |
| 930 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 6, |
| 931 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 932 | /* |
| 933 | * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU |
| 934 | * (and in particular its system registers). |
| 935 | */ |
| 936 | { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64, |
| 937 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0, |
| 938 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, |
| 939 | |
| 940 | /* |
| 941 | * Stub RAMINDEX, as we don't actually implement caches, BTB, |
| 942 | * or anything else with cpu internal memory. |
| 943 | * "Read" zeros into the IDATA* and DDATA* output registers. |
| 944 | */ |
| 945 | { .name = "RAMINDEX_EL3", .state = ARM_CP_STATE_AA64, |
| 946 | .opc0 = 1, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0, |
| 947 | .access = PL3_W, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 948 | { .name = "IDATA0_EL3", .state = ARM_CP_STATE_AA64, |
| 949 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0, |
| 950 | .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 951 | { .name = "IDATA1_EL3", .state = ARM_CP_STATE_AA64, |
| 952 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 1, |
| 953 | .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 954 | { .name = "IDATA2_EL3", .state = ARM_CP_STATE_AA64, |
| 955 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 2, |
| 956 | .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 957 | { .name = "DDATA0_EL3", .state = ARM_CP_STATE_AA64, |
| 958 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 0, |
| 959 | .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 960 | { .name = "DDATA1_EL3", .state = ARM_CP_STATE_AA64, |
| 961 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 1, |
| 962 | .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 963 | { .name = "DDATA2_EL3", .state = ARM_CP_STATE_AA64, |
| 964 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 2, |
| 965 | .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 966 | }; |
| 967 | |
| 968 | static void aarch64_a710_initfn(Object *obj) |
| 969 | { |
| 970 | ARMCPU *cpu = ARM_CPU(obj); |
| 971 | ARMISARegisters *isar = &cpu->isar; |
| 972 | |
| 973 | cpu->dtb_compatible = "arm,cortex-a710"; |
| 974 | set_feature(&cpu->env, ARM_FEATURE_V8); |
| 975 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 976 | set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); |
| 977 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
| 978 | set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); |
| 979 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
| 980 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
| 981 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
| 982 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
| 983 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
| 984 | |
| 985 | /* Ordered by Section B.4: AArch64 registers */ |
| 986 | cpu->midr = 0x412FD471; /* r2p1 */ |
| 987 | cpu->revidr = 0; |
| 988 | SET_IDREG(isar, ID_PFR0, 0x21110131); |
| 989 | SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ |
| 990 | SET_IDREG(isar, ID_DFR0, 0x16011099); |
| 991 | SET_IDREG(isar, ID_AFR0, 0); |
| 992 | SET_IDREG(isar, ID_MMFR0, 0x10201105); |
| 993 | SET_IDREG(isar, ID_MMFR1, 0x40000000); |
| 994 | SET_IDREG(isar, ID_MMFR2, 0x01260000); |
| 995 | SET_IDREG(isar, ID_MMFR3, 0x02122211); |
| 996 | SET_IDREG(isar, ID_ISAR0, 0x02101110); |
| 997 | SET_IDREG(isar, ID_ISAR1, 0x13112111); |
| 998 | SET_IDREG(isar, ID_ISAR2, 0x21232042); |
| 999 | SET_IDREG(isar, ID_ISAR3, 0x01112131); |
| 1000 | SET_IDREG(isar, ID_ISAR4, 0x00010142); |
| 1001 | SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */ |
| 1002 | SET_IDREG(isar, ID_MMFR4, 0x21021110); |
| 1003 | SET_IDREG(isar, ID_ISAR6, 0x01111111); |
| 1004 | cpu->isar.mvfr0 = 0x10110222; |
| 1005 | cpu->isar.mvfr1 = 0x13211111; |
| 1006 | cpu->isar.mvfr2 = 0x00000043; |
| 1007 | SET_IDREG(isar, ID_PFR2, 0x00000011); |
| 1008 | SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */ |
| 1009 | SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); |
| 1010 | SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ |
| 1011 | SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull); |
| 1012 | SET_IDREG(isar, ID_AA64DFR1, 0); |
| 1013 | SET_IDREG(isar, ID_AA64AFR0, 0); |
| 1014 | SET_IDREG(isar, ID_AA64AFR1, 0); |
| 1015 | SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ |
| 1016 | SET_IDREG(isar, ID_AA64ISAR1, 0x0010111101211052ull); |
| 1017 | SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101122ull); |
| 1018 | SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); |
| 1019 | SET_IDREG(isar, ID_AA64MMFR2, 0x1221011110101011ull); |
| 1020 | SET_IDREG(isar, CLIDR, 0x0000001482000023ull); |
| 1021 | cpu->gm_blocksize = 4; |
| 1022 | cpu->ctr = 0x000000049444c004ull; |
| 1023 | set_dczid_bs(cpu, 4); |
| 1024 | /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_0006_003f */ |
| 1025 | |
| 1026 | /* Section B.5.2: PMCR_EL0 */ |
| 1027 | cpu->isar.reset_pmcr_el0 = 0xa000; /* with 20 counters */ |
| 1028 | |
| 1029 | /* Section B.6.7: ICH_VTR_EL2 */ |
| 1030 | cpu->gic_num_lrs = 4; |
| 1031 | cpu->gic_vpribits = 5; |
| 1032 | cpu->gic_vprebits = 5; |
| 1033 | cpu->gic_pribits = 5; |
| 1034 | |
| 1035 | /* Section 14: Scalable Vector Extensions support */ |
| 1036 | cpu->sve_vq.supported = 1 << 0; /* 128bit */ |
| 1037 | |
| 1038 | /* |
| 1039 | * The cortex-a710 TRM does not list CCSIDR values. The layout of |
| 1040 | * the caches are in text in Table 7-1, Table 8-1, and Table 9-1. |
| 1041 | * |
| 1042 | * L1: 4-way set associative 64-byte line size, total either 32K or 64K. |
| 1043 | * L2: 8-way set associative 64 byte line size, total either 256K or 512K. |
| 1044 | */ |
| 1045 | /* L1 dcache */ |
| 1046 | cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); |
| 1047 | /* L1 icache */ |
| 1048 | cpu->ccsidr[1] = cpu->ccsidr[0]; |
| 1049 | /* L2 cache */ |
| 1050 | cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0); |
| 1051 | |
| 1052 | /* FIXME: Not documented -- copied from neoverse-v1 */ |
| 1053 | cpu->reset_sctlr = 0x30c50838; |
| 1054 | |
| 1055 | define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); |
| 1056 | |
| 1057 | aarch64_add_pauth_properties(obj); |
| 1058 | aarch64_add_sve_properties(obj); |
| 1059 | } |
| 1060 | |
| 1061 | /* Extra IMPDEF regs in the N2 beyond those in the A710 */ |
| 1062 | static const ARMCPRegInfo neoverse_n2_cp_reginfo[] = { |
| 1063 | { .name = "CPURNDBR_EL3", .state = ARM_CP_STATE_AA64, |
| 1064 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 0, |
| 1065 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 1066 | { .name = "CPURNDPEID_EL3", .state = ARM_CP_STATE_AA64, |
| 1067 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 1, |
| 1068 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 1069 | }; |
| 1070 | |
| 1071 | static void aarch64_neoverse_n2_initfn(Object *obj) |
| 1072 | { |
| 1073 | ARMCPU *cpu = ARM_CPU(obj); |
| 1074 | ARMISARegisters *isar = &cpu->isar; |
| 1075 | |
| 1076 | cpu->dtb_compatible = "arm,neoverse-n2"; |
| 1077 | set_feature(&cpu->env, ARM_FEATURE_V8); |
| 1078 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 1079 | set_feature(&cpu->env, ARM_FEATURE_NEON_TRAPS); |
| 1080 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
| 1081 | set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); |
| 1082 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
| 1083 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
| 1084 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
| 1085 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
| 1086 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
| 1087 | |
| 1088 | /* Ordered by Section B.5: AArch64 ID registers */ |
| 1089 | cpu->midr = 0x410FD493; /* r0p3 */ |
| 1090 | cpu->revidr = 0; |
| 1091 | SET_IDREG(isar, ID_PFR0, 0x21110131); |
| 1092 | SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ |
| 1093 | SET_IDREG(isar, ID_DFR0, 0x16011099); |
| 1094 | SET_IDREG(isar, ID_AFR0, 0); |
| 1095 | SET_IDREG(isar, ID_MMFR0, 0x10201105); |
| 1096 | SET_IDREG(isar, ID_MMFR1, 0x40000000); |
| 1097 | SET_IDREG(isar, ID_MMFR2, 0x01260000); |
| 1098 | SET_IDREG(isar, ID_MMFR3, 0x02122211); |
| 1099 | SET_IDREG(isar, ID_ISAR0, 0x02101110); |
| 1100 | SET_IDREG(isar, ID_ISAR1, 0x13112111); |
| 1101 | SET_IDREG(isar, ID_ISAR2, 0x21232042); |
| 1102 | SET_IDREG(isar, ID_ISAR3, 0x01112131); |
| 1103 | SET_IDREG(isar, ID_ISAR4, 0x00010142); |
| 1104 | SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */ |
| 1105 | SET_IDREG(isar, ID_MMFR4, 0x01021110); |
| 1106 | SET_IDREG(isar, ID_ISAR6, 0x01111111); |
| 1107 | cpu->isar.mvfr0 = 0x10110222; |
| 1108 | cpu->isar.mvfr1 = 0x13211111; |
| 1109 | cpu->isar.mvfr2 = 0x00000043; |
| 1110 | SET_IDREG(isar, ID_PFR2, 0x00000011); |
| 1111 | SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */ |
| 1112 | SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); |
| 1113 | SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ |
| 1114 | SET_IDREG(isar, ID_AA64DFR0, 0x000011f210305619ull); |
| 1115 | SET_IDREG(isar, ID_AA64DFR1, 0); |
| 1116 | SET_IDREG(isar, ID_AA64AFR0, 0); |
| 1117 | SET_IDREG(isar, ID_AA64AFR1, 0); |
| 1118 | SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */ |
| 1119 | SET_IDREG(isar, ID_AA64ISAR1, 0x0011111101211052ull); |
| 1120 | SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101125ull); |
| 1121 | SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); |
| 1122 | SET_IDREG(isar, ID_AA64MMFR2, 0x1221011112101011ull); |
| 1123 | SET_IDREG(isar, CLIDR, 0x0000001482000023ull); |
| 1124 | cpu->gm_blocksize = 4; |
| 1125 | cpu->ctr = 0x00000004b444c004ull; |
| 1126 | set_dczid_bs(cpu, 4); |
| 1127 | /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_001e_01ff */ |
| 1128 | |
| 1129 | /* Section B.7.2: PMCR_EL0 */ |
| 1130 | cpu->isar.reset_pmcr_el0 = 0x3000; /* with 6 counters */ |
| 1131 | |
| 1132 | /* Section B.8.9: ICH_VTR_EL2 */ |
| 1133 | cpu->gic_num_lrs = 4; |
| 1134 | cpu->gic_vpribits = 5; |
| 1135 | cpu->gic_vprebits = 5; |
| 1136 | cpu->gic_pribits = 5; |
| 1137 | |
| 1138 | /* Section 14: Scalable Vector Extensions support */ |
| 1139 | cpu->sve_vq.supported = 1 << 0; /* 128bit */ |
| 1140 | |
| 1141 | /* |
| 1142 | * The Neoverse N2 TRM does not list CCSIDR values. The layout of |
| 1143 | * the caches are in text in Table 7-1, Table 8-1, and Table 9-1. |
| 1144 | * |
| 1145 | * L1: 4-way set associative 64-byte line size, total 64K. |
| 1146 | * L2: 8-way set associative 64 byte line size, total either 512K or 1024K. |
| 1147 | */ |
| 1148 | /* L1 dcache */ |
| 1149 | cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); |
| 1150 | /* L1 icache */ |
| 1151 | cpu->ccsidr[1] = cpu->ccsidr[0]; |
| 1152 | /* L2 cache */ |
| 1153 | cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0); |
| 1154 | /* FIXME: Not documented -- copied from neoverse-v1 */ |
| 1155 | cpu->reset_sctlr = 0x30c50838; |
| 1156 | |
| 1157 | /* |
| 1158 | * The Neoverse N2 has all of the Cortex-A710 IMPDEF registers, |
| 1159 | * and a few more RNG related ones. |
| 1160 | */ |
| 1161 | define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); |
| 1162 | define_arm_cp_regs(cpu, neoverse_n2_cp_reginfo); |
| 1163 | |
| 1164 | aarch64_add_pauth_properties(obj); |
| 1165 | aarch64_add_sve_properties(obj); |
| 1166 | } |
| 1167 | |
| 1168 | /* |
| 1169 | * -cpu max-v8: an ARMv8 CPU with as many features enabled as |
| 1170 | * our emulation supports. |
| 1171 | */ |
| 1172 | void aarch64_max_v8_tcg_initfn(Object *obj) |
| 1173 | { |
| 1174 | ARMCPU *cpu = ARM_CPU(obj); |
| 1175 | ARMISARegisters *isar = &cpu->isar; |
| 1176 | uint64_t t; |
| 1177 | uint32_t u; |
| 1178 | |
| 1179 | aarch64_aa32_a57_init(cpu, true); |
| 1180 | |
| 1181 | SET_IDREG(isar, CLIDR, 0x8200123); |
| 1182 | /* 64KB L1 dcache */ |
| 1183 | cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); |
| 1184 | /* 64KB L1 icache */ |
| 1185 | cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); |
| 1186 | /* 1MB L2 unified cache */ |
| 1187 | cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); |
| 1188 | /* 2MB L3 unified cache */ |
| 1189 | cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7); |
| 1190 | |
| 1191 | /* |
| 1192 | * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default |
| 1193 | * to because we started with aarch64_a57_initfn(). A 'max' CPU might |
| 1194 | * be a v8.6-or-later one, in which case the cntfrq must be 1GHz; and |
| 1195 | * because it is our "may change" CPU type we are OK with it not being |
| 1196 | * backwards-compatible with how it worked in old QEMU. |
| 1197 | */ |
| 1198 | unset_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); |
| 1199 | |
| 1200 | /* |
| 1201 | * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real |
| 1202 | * one and try to apply errata workarounds or use impdef features we |
| 1203 | * don't provide. |
| 1204 | * An IMPLEMENTER field of 0 means "reserved for software use"; |
| 1205 | * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers |
| 1206 | * to see which features are present"; |
| 1207 | * the VARIANT, PARTNUM and REVISION fields are all implementation |
| 1208 | * defined and we choose to define PARTNUM just in case guest |
| 1209 | * code needs to distinguish this QEMU CPU from other software |
| 1210 | * implementations, though this shouldn't be needed. |
| 1211 | */ |
| 1212 | t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); |
| 1213 | t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); |
| 1214 | t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); |
| 1215 | t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); |
| 1216 | t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); |
| 1217 | cpu->midr = t; |
| 1218 | |
| 1219 | /* |
| 1220 | * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS} |
| 1221 | * are zero. |
| 1222 | */ |
| 1223 | u = GET_IDREG(isar, CLIDR); |
| 1224 | u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); |
| 1225 | u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0); |
| 1226 | SET_IDREG(isar, CLIDR, u); |
| 1227 | |
| 1228 | /* |
| 1229 | * Set CTR_EL0.DIC and IDC to tell the guest it doesnt' need to |
| 1230 | * do any cache maintenance for data-to-instruction or |
| 1231 | * instruction-to-guest coherence. (Our cache ops are nops.) |
| 1232 | */ |
| 1233 | t = cpu->ctr; |
| 1234 | t = FIELD_DP64(t, CTR_EL0, IDC, 1); |
| 1235 | t = FIELD_DP64(t, CTR_EL0, DIC, 1); |
| 1236 | cpu->ctr = t; |
| 1237 | |
| 1238 | /* |
| 1239 | * Below, note the revision from which the feature is OPTIONAL. |
| 1240 | */ |
| 1241 | t = GET_IDREG(isar, ID_AA64ISAR0); |
| 1242 | t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* v8.0: FEAT_PMULL */ |
| 1243 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* v8.0: FEAT_SHA1 */ |
| 1244 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* v8.1: FEAT_SHA512 */ |
| 1245 | t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* v8.0: FEAT_CRC32 */ |
| 1246 | t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* v8.0: FEAT_LSE */ |
| 1247 | t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* v8.0: FEAT_RDM */ |
| 1248 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* v8.1: FEAT_SHA3 */ |
| 1249 | t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* v8.1: FEAT_SM3 */ |
| 1250 | t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* v8.1: FEAT_SM4 */ |
| 1251 | t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* v8.1: FEAT_DotProd */ |
| 1252 | t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* v8.1: FEAT_FHM */ |
| 1253 | t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.4: FEAT_FlagM2 */ |
| 1254 | t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* v8.3: FEAT_TLBIRANGE */ |
| 1255 | t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* v8.4: FEAT_RNG */ |
| 1256 | SET_IDREG(isar, ID_AA64ISAR0, t); |
| 1257 | |
| 1258 | t = GET_IDREG(isar, ID_AA64ISAR1); |
| 1259 | t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* v8.1: FEAT_DPB2 */ |
| 1260 | t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED); /* v8.2 */ |
| 1261 | t = FIELD_DP64(t, ID_AA64ISAR1, API, 1); |
| 1262 | t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* v8.2: FEAT_JSCVT */ |
| 1263 | t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* v8.2: FEAT_FCMA */ |
| 1264 | t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* v8.2: FEAT_LRCPC2 */ |
| 1265 | t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* v8.4: FEAT_FRINTTS */ |
| 1266 | t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* v8.0: FEAT_SB */ |
| 1267 | t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* v8.0: FEAT_SPECRES */ |
| 1268 | t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* v8.2: FEAT_EBF16 */ |
| 1269 | t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* v8.0: FEAT_DGH */ |
| 1270 | t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* v8.1: FEAT_I8MM */ |
| 1271 | t = FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* v8.6: FEAT_XS */ |
| 1272 | SET_IDREG(isar, ID_AA64ISAR1, t); |
| 1273 | |
| 1274 | t = GET_IDREG(isar, ID_AA64ISAR2); |
| 1275 | t = FIELD_DP64(t, ID_AA64ISAR2, RPRES, 1); /* v8.6: FEAT_RPRES */ |
| 1276 | t = FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* v8.7: FEAT_MOPS */ |
| 1277 | t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* v8.7: FEAT_HBC */ |
| 1278 | t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* v8.6: FEAT_WFxT */ |
| 1279 | t = FIELD_DP64(t, ID_AA64ISAR2, CSSC, 1); /* v8.7: FEAT_CSSC */ |
| 1280 | t = FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* v8.8: FEAT_ATS1A */ |
| 1281 | SET_IDREG(isar, ID_AA64ISAR2, t); |
| 1282 | |
| 1283 | t = GET_IDREG(isar, ID_AA64PFR0); |
| 1284 | t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* v8.2: FEAT_FP16 */ |
| 1285 | t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* v8.2: FEAT_FP16 */ |
| 1286 | t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* v8.3: FEAT_DoubleFault */ |
| 1287 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); /* v8.2: FEAT_SVE */ |
| 1288 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* v8.3: FEAT_SEL2 */ |
| 1289 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* v8.3: FEAT_DIT */ |
| 1290 | t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* v8.0: FEAT_CSV2_3 */ |
| 1291 | t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* v8.0: FEAT_CSV3 */ |
| 1292 | SET_IDREG(isar, ID_AA64PFR0, t); |
| 1293 | |
| 1294 | t = GET_IDREG(isar, ID_AA64PFR1); |
| 1295 | t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* v8.4: FEAT_BTI */ |
| 1296 | t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* v8.0: FEAT_SSBS2 */ |
| 1297 | /* |
| 1298 | * Begin with full support for MTE. This will be downgraded to MTE=0 |
| 1299 | * during realize if the board provides no tag memory, much like |
| 1300 | * we do for EL2 with the virtualization=on property. |
| 1301 | */ |
| 1302 | t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* v8.5: FEAT_MTE3 */ |
| 1303 | t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* v8.3: FEAT_DoubleFault */ |
| 1304 | t = FIELD_DP64(t, ID_AA64PFR1, RNDR_TRAP, 1); /* v8.4: FEAT_RNG_TRAP */ |
| 1305 | t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* v8.0: FEAT_CSV2_3 */ |
| 1306 | t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* v8.7: FEAT_NMI */ |
| 1307 | /* v8.7: FEAT_MTE_NO_ADDRESS_TAGS + FEAT_MTE_CANONICAL_TAGS */ |
| 1308 | t = FIELD_DP64(t, ID_AA64PFR1, MTEX, 1); |
| 1309 | SET_IDREG(isar, ID_AA64PFR1, t); |
| 1310 | |
| 1311 | t = GET_IDREG(isar, ID_AA64PFR2); |
| 1312 | t = FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 1); /* v8.7: FEAT_MTE_TAGGED_FAR */ |
| 1313 | t = FIELD_DP64(t, ID_AA64PFR2, MTESTOREONLY, 1); /* v8.7: FEAT_MTE_STORE_ONLY */ |
| 1314 | t = FIELD_DP64(t, ID_AA64PFR2, MTEPERM, 1); /* v8.7: FEAT_MTE_PERM */ |
| 1315 | SET_IDREG(isar, ID_AA64PFR2, t); |
| 1316 | |
| 1317 | t = GET_IDREG(isar, ID_AA64MMFR0); |
| 1318 | t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* v8.1: FEAT_LPA: 52 bits */ |
| 1319 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* v8.0: FEAT_TGran16K */ |
| 1320 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* v8.0: FEAT_S2TGran16K */ |
| 1321 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* v8.0: FEAT_S2TGran64K */ |
| 1322 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* v8.0: FEAT_S2TGran4K */ |
| 1323 | t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* v8.5: FEAT_FGT */ |
| 1324 | t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* v8.5: FEAT_ECV_POFF */ |
| 1325 | SET_IDREG(isar, ID_AA64MMFR0, t); |
| 1326 | |
| 1327 | t = GET_IDREG(isar, ID_AA64MMFR1); |
| 1328 | t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* v8.0: FEAT_HAFDBS */ |
| 1329 | t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* v8.0: FEAT_VMID16 */ |
| 1330 | t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* v8.0: FEAT_VHE */ |
| 1331 | t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* v8.1: FEAT_HPDS2 */ |
| 1332 | t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* v8.0: FEAT_LOR */ |
| 1333 | t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* v8.1: FEAT_PAN3 */ |
| 1334 | t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* v8.1: FEAT_XNX */ |
| 1335 | t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* v8.0: FEAT_ETS2 */ |
| 1336 | t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* v8.6: FEAT_HCX */ |
| 1337 | t = FIELD_DP64(t, ID_AA64MMFR1, AFP, 1); /* v8.6: FEAT_AFP */ |
| 1338 | t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* v8.7: FEAT_TIDCP1 */ |
| 1339 | t = FIELD_DP64(t, ID_AA64MMFR1, CMOW, 1); /* v8.7: FEAT_CMOW */ |
| 1340 | SET_IDREG(isar, ID_AA64MMFR1, t); |
| 1341 | |
| 1342 | t = GET_IDREG(isar, ID_AA64MMFR2); |
| 1343 | t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* v8.1: FEAT_TTCNP */ |
| 1344 | t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* v8.1: FEAT_UAO */ |
| 1345 | t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* v8.1: FEAT_IESB */ |
| 1346 | t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* v8.1: FEAT_LVA */ |
| 1347 | t = FIELD_DP64(t, ID_AA64MMFR2, NV, 2); /* v8.3: FEAT_NV2 */ |
| 1348 | t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* v8.3: FEAT_TTST */ |
| 1349 | t = FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* v8.2: FEAT_LSE2 */ |
| 1350 | t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* v8.3: FEAT_IDST */ |
| 1351 | t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* v8.3: FEAT_S2FWB */ |
| 1352 | t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* v8.3: FEAT_TTL */ |
| 1353 | t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* v8.3: FEAT_BBML2 */ |
| 1354 | t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* v8.2: FEAT_EVT2 */ |
| 1355 | t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* v8.4: FEAT_E0PD */ |
| 1356 | SET_IDREG(isar, ID_AA64MMFR2, t); |
| 1357 | |
| 1358 | t = GET_IDREG(isar, ID_AA64MMFR3); |
| 1359 | t = FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* v8.0: FEAT_TCR2 */ |
| 1360 | t = FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* v8.0: FEAT_SCTLR2 */ |
| 1361 | t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* v8.2: FEAT_FPACC_SPEC */ |
| 1362 | t = FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* v8.8: FEAT_S1PIE */ |
| 1363 | t = FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* v8.8: FEAT_S2PIE */ |
| 1364 | t = FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* v8.8: FEAT_AIE */ |
| 1365 | SET_IDREG(isar, ID_AA64MMFR3, t); |
| 1366 | |
| 1367 | t = GET_IDREG(isar, ID_AA64ZFR0); |
| 1368 | t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 2); /* v8.2: FEAT_EBF16 */ |
| 1369 | t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* v8.1: FEAT_I8MM */ |
| 1370 | t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* v8.2: FEAT_F32MM */ |
| 1371 | t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* v8.2: FEAT_F64MM */ |
| 1372 | SET_IDREG(isar, ID_AA64ZFR0, t); |
| 1373 | |
| 1374 | t = GET_IDREG(isar, ID_AA64DFR0); |
| 1375 | t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* v8.7: FEAT_Debugv8p8 */ |
| 1376 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* v8.4: FEAT_PMUv3p5 */ |
| 1377 | t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* v8.5: FEAT_HPMN0 */ |
| 1378 | SET_IDREG(isar, ID_AA64DFR0, t); |
| 1379 | |
| 1380 | /* Replicate the same data to the 32-bit id registers. */ |
| 1381 | aa32_max_features(cpu); |
| 1382 | |
| 1383 | #ifdef CONFIG_USER_ONLY |
| 1384 | /* |
| 1385 | * For usermode -cpu max we can use a larger and more efficient DCZ |
| 1386 | * blocksize since we don't have to follow what the hardware does. |
| 1387 | */ |
| 1388 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ |
| 1389 | set_dczid_bs(cpu, 7); /* 512 bytes */ |
| 1390 | #endif |
| 1391 | |
| 1392 | /* v8.2: FEAT_SVE */ |
| 1393 | cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); |
| 1394 | aarch64_add_sve_properties(OBJECT(cpu)); |
| 1395 | object_property_add(OBJECT(cpu), "sve-max-vq", "uint32", |
| 1396 | cpu_max_get_sve_max_vq, cpu_max_set_sve_max_vq, |
| 1397 | NULL, NULL); |
| 1398 | |
| 1399 | /* v8.2: FEAT_PAuth2 */ |
| 1400 | aarch64_add_pauth_properties(OBJECT(cpu)); |
| 1401 | |
| 1402 | /* v8.4: FEAT_MTE2 */ |
| 1403 | cpu->gm_blocksize = 6; /* 256 bytes */ |
| 1404 | |
| 1405 | /* v8.6: FEAT_LPA2 */ |
| 1406 | qdev_property_add_static(DEVICE(cpu), &arm_cpu_lpa2_property); |
| 1407 | } |
| 1408 | |
| 1409 | /* |
| 1410 | * -cpu max-v9: an ARMv9 CPU with as many features enabled as |
| 1411 | * our emulation supports. |
| 1412 | */ |
| 1413 | void aarch64_max_v9_tcg_initfn(Object *obj) |
| 1414 | { |
| 1415 | ARMCPU *cpu = ARM_CPU(obj); |
| 1416 | ARMISARegisters *isar = &cpu->isar; |
| 1417 | uint64_t t; |
| 1418 | |
| 1419 | /* Armv9.0 is based on a minimum of Armv8.5. */ |
| 1420 | aarch64_max_v8_tcg_initfn(obj); |
| 1421 | |
| 1422 | /* |
| 1423 | * Armv9.0 does not support AArch32 except at EL0, |
| 1424 | * therefore indicate EL1 through EL3 are AArch64-only. |
| 1425 | */ |
| 1426 | t = GET_IDREG(isar, ID_AA64PFR0); |
| 1427 | t = FIELD_DP64(t, ID_AA64PFR0, EL1, 1); |
| 1428 | t = FIELD_DP64(t, ID_AA64PFR0, EL2, 1); |
| 1429 | t = FIELD_DP64(t, ID_AA64PFR0, EL3, 1); |
| 1430 | SET_IDREG(isar, ID_AA64PFR0, t); |
| 1431 | |
| 1432 | /* v9.0 prohibits FEAT_DoubleLock. */ |
| 1433 | FIELD_DP64_IDREG(isar, ID_AA64DFR0, DOUBLELOCK, -1); |
| 1434 | FIELD_DP64_IDREG(isar, ID_AA64PFR0, RAS, 1); |
| 1435 | isar->dbgdevid = FIELD_DP32(isar->dbgdevid, DBGDEVID, DOUBLELOCK, 0); |
| 1436 | |
| 1437 | /* |
| 1438 | * Below, note the revision from which the feature is OPTIONAL. |
| 1439 | */ |
| 1440 | t = GET_IDREG(isar, ID_AA64ISAR0); |
| 1441 | t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 3); /* v9.3: FEAT_LSE128 */ |
| 1442 | SET_IDREG(isar, ID_AA64ISAR0, t); |
| 1443 | |
| 1444 | t = GET_IDREG(isar, ID_AA64ISAR2); |
| 1445 | t = FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* v9.3: FEAT_CMPBR */ |
| 1446 | t = FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* v9.2: FEAT_LUT */ |
| 1447 | SET_IDREG(isar, ID_AA64ISAR2, t); |
| 1448 | |
| 1449 | t = GET_IDREG(isar, ID_AA64ISAR3); |
| 1450 | t = FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* v9.2: FEAT_FAMINMAX */ |
| 1451 | t = FIELD_DP64(t, ID_AA64ISAR3, FPRCVT, 1); /* v9.5: FEAT_FPRCVT */ |
| 1452 | SET_IDREG(isar, ID_AA64ISAR3, t); |
| 1453 | |
| 1454 | t = GET_IDREG(isar, ID_AA64PFR1); |
| 1455 | t = FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* v9.2: FEAT_SME2 */ |
| 1456 | t = FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* v9.3: FEAT_GCS */ |
| 1457 | SET_IDREG(isar, ID_AA64PFR1, t); |
| 1458 | |
| 1459 | t = GET_IDREG(isar, ID_AA64PFR2); |
| 1460 | t = FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* v9.2: FEAT_FPMR */ |
| 1461 | SET_IDREG(isar, ID_AA64PFR2, t); |
| 1462 | |
| 1463 | t = GET_IDREG(isar, ID_AA64MMFR3); |
| 1464 | t = FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* v9.2: FEAT_MEC */ |
| 1465 | SET_IDREG(isar, ID_AA64MMFR3, t); |
| 1466 | |
| 1467 | t = GET_IDREG(isar, ID_AA64MMFR4); |
| 1468 | t = FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* v9.4: FEAT_ASID2 */ |
| 1469 | t = FIELD_DP64(t, ID_AA64MMFR4, FGWTE3, 1); /* v9.4: FEAT_FGWTE3 */ |
| 1470 | SET_IDREG(isar, ID_AA64MMFR4, t); |
| 1471 | |
| 1472 | t = GET_IDREG(isar, ID_AA64ZFR0); |
| 1473 | t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 3); /* v9.4: FEAT_SVE2p2 */ |
| 1474 | t = FIELD_DP64(t, ID_AA64ZFR0, AES, 3); /* v9.5: FEAT_SVE_AES2 */ |
| 1475 | t = FIELD_DP64(t, ID_AA64ZFR0, ELTPERM, 1); /* v9.4: FEAT_SVE2p2 */ |
| 1476 | t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitPerm */ |
| 1477 | t = FIELD_DP64(t, ID_AA64ZFR0, B16B16, 2); /* v9.2: FEAT_SVE_BFSCALE */ |
| 1478 | t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3 */ |
| 1479 | t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* v9.0: FEAT_SVE_SM4 */ |
| 1480 | SET_IDREG(isar, ID_AA64ZFR0, t); |
| 1481 | |
| 1482 | t = GET_IDREG(isar, ID_AA64SMFR0); |
| 1483 | t = FIELD_DP64(t, ID_AA64SMFR0, SMOP4, 1); /* v9.4: FEAT_SME_MOP4 */ |
| 1484 | t = FIELD_DP64(t, ID_AA64SMFR0, STMOP, 1); /* v9.4: FEAT_SME_TMOP */ |
| 1485 | t = FIELD_DP64(t, ID_AA64SMFR0, SFEXPA, 1); /* v9.4: FEAT_SSVE_FEXPA */ |
| 1486 | t = FIELD_DP64(t, ID_AA64SMFR0, AES, 1); /* v9.5: FEAT_SSVE_AES */ |
| 1487 | t = FIELD_DP64(t, ID_AA64SMFR0, SBITPERM, 1); /* v9.4: FEAT_SSVE_BitPerm */ |
| 1488 | t = FIELD_DP64(t, ID_AA64SMFR0, SF8DP2, 1); /* v9.2: FEAT_SSVE_FP8DOT2 */ |
| 1489 | t = FIELD_DP64(t, ID_AA64SMFR0, SF8DP4, 1); /* v9.2: FEAT_SSVE_FP8DOT4 */ |
| 1490 | t = FIELD_DP64(t, ID_AA64SMFR0, SF8FMA, 1); /* v9.2: FEAT_SSVE_FP8FMA */ |
| 1491 | t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* v9.2: FEAT_SME */ |
| 1492 | t = FIELD_DP64(t, ID_AA64SMFR0, BI32I32, 1); /* v9.2: FEAT_SME2 */ |
| 1493 | t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* v9.2: FEAT_SME */ |
| 1494 | t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* v9.2: FEAT_SME */ |
| 1495 | t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* v9.2: FEAT_SME */ |
| 1496 | t = FIELD_DP64(t, ID_AA64SMFR0, F8F32, 1); /* v9.2: FEAT_SME_F8F32 */ |
| 1497 | t = FIELD_DP64(t, ID_AA64SMFR0, F8F16, 1); /* v9.2: FEAT_SME_F8F16 */ |
| 1498 | t = FIELD_DP64(t, ID_AA64SMFR0, F16F16, 1); /* v9.2: FEAT_SME_F16F16 */ |
| 1499 | t = FIELD_DP64(t, ID_AA64SMFR0, B16B16, 1); /* v9.2: FEAT_SME_B16B16 */ |
| 1500 | t = FIELD_DP64(t, ID_AA64SMFR0, I16I32, 5); /* v9.2: FEAT_SME2 */ |
| 1501 | t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* v9.2: FEAT_SME_F64F64 */ |
| 1502 | t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* v9.2: FEAT_SME_I16I64 */ |
| 1503 | t = FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 3); /* v9.4: FEAT_SME2p2 */ |
| 1504 | t = FIELD_DP64(t, ID_AA64SMFR0, LUTv2, 1); /* v9.2: FEAT_SME_LUTv2 */ |
| 1505 | t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* v9.2: FEAT_SME_FA64 */ |
| 1506 | SET_IDREG(isar, ID_AA64SMFR0, t); |
| 1507 | |
| 1508 | t = GET_IDREG(isar, ID_AA64FPFR0); |
| 1509 | t = FIELD_DP64(t, ID_AA64FPFR0, F8E5M2, 1); /* v9.2: FEAT_FP8 */ |
| 1510 | t = FIELD_DP64(t, ID_AA64FPFR0, F8E4M3, 1); /* v9.2: FEAT_FP8 */ |
| 1511 | t = FIELD_DP64(t, ID_AA64FPFR0, F8MM4, 1); /* v9.2: FEAT_F8F16MM */ |
| 1512 | t = FIELD_DP64(t, ID_AA64FPFR0, F8MM8, 1); /* v9.2: FEAT_F8F32MM */ |
| 1513 | t = FIELD_DP64(t, ID_AA64FPFR0, F8DP2, 1); /* v9.2: FEAT_FP8DOT2 */ |
| 1514 | t = FIELD_DP64(t, ID_AA64FPFR0, F8DP4, 1); /* v9.2: FEAT_FP8DOT4 */ |
| 1515 | t = FIELD_DP64(t, ID_AA64FPFR0, F8FMA, 1); /* v9.2: FEAT_FP8FMA */ |
| 1516 | t = FIELD_DP64(t, ID_AA64FPFR0, F8CVT, 1); /* v9.2: FEAT_FP8 */ |
| 1517 | SET_IDREG(isar, ID_AA64FPFR0, t); |
| 1518 | |
| 1519 | /* v9.2: FEAT_SME */ |
| 1520 | cpu->sme_vq.supported = SVE_VQ_POW2_MAP; |
| 1521 | aarch64_add_sme_properties(obj); |
| 1522 | |
| 1523 | /* v9.1: FEAT_RME */ |
| 1524 | object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rme); |
| 1525 | |
| 1526 | /* v9.4: FEAT_RME_GPC2 */ |
| 1527 | object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz, |
| 1528 | cpu_max_set_l0gptsz, NULL, NULL); |
| 1529 | } |
| 1530 | |
| 1531 | static const ARMCPUInfo aarch64_cpus[] = { |
| 1532 | { .name = "cortex-a35", .initfn = aarch64_a35_initfn }, |
| 1533 | { .name = "cortex-a55", .initfn = aarch64_a55_initfn }, |
| 1534 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, |
| 1535 | { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, |
| 1536 | /* |
| 1537 | * The Cortex-A78AE differs slightly from the plain Cortex-A78. We don't |
| 1538 | * currently model the latter. |
| 1539 | */ |
| 1540 | { .name = "cortex-a78ae", .initfn = aarch64_a78ae_initfn }, |
| 1541 | { .name = "cortex-a710", .initfn = aarch64_a710_initfn }, |
| 1542 | { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, |
| 1543 | { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, |
| 1544 | { .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn }, |
| 1545 | { .name = "neoverse-n2", .initfn = aarch64_neoverse_n2_initfn }, |
| 1546 | { .name = "max-v9", .initfn = aarch64_max_v9_tcg_initfn }, |
| 1547 | }; |
| 1548 | |
| 1549 | static void aarch64_cpu_register_types(void) |
| 1550 | { |
| 1551 | size_t i; |
| 1552 | |
| 1553 | for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { |
| 1554 | arm_cpu_register(&aarch64_cpus[i]); |
| 1555 | } |
| 1556 | } |
| 1557 | |
| 1558 | type_init(aarch64_cpu_register_types) |