| 1 | /* |
| 2 | * AArch64 generic vector expansion |
| 3 | * |
| 4 | * Copyright (c) 2013 Alexander Graf <agraf@suse.de> |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "cpu.h" |
| 22 | #include "helper-sve.h" |
| 23 | #include "translate.h" |
| 24 | #include "translate-a64.h" |
| 25 | |
| 26 | static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) |
| 27 | { |
| 28 | tcg_gen_rotli_i64(d, m, 1); |
| 29 | tcg_gen_xor_i64(d, d, n); |
| 30 | } |
| 31 | |
| 32 | static void gen_rax1_vec(unsigned vece, TCGv_vec d, TCGv_vec n, TCGv_vec m) |
| 33 | { |
| 34 | tcg_gen_rotli_vec(vece, d, m, 1); |
| 35 | tcg_gen_xor_vec(vece, d, d, n); |
| 36 | } |
| 37 | |
| 38 | void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 39 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz) |
| 40 | { |
| 41 | static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 }; |
| 42 | static const GVecGen3 op = { |
| 43 | .fni8 = gen_rax1_i64, |
| 44 | .fniv = gen_rax1_vec, |
| 45 | .opt_opc = vecop_list, |
| 46 | .fno = gen_helper_crypto_rax1, |
| 47 | .vece = MO_64, |
| 48 | }; |
| 49 | tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &op); |
| 50 | } |
| 51 | |
| 52 | static void gen_xar8_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh) |
| 53 | { |
| 54 | TCGv_i64 t = tcg_temp_new_i64(); |
| 55 | uint64_t mask = dup_const(MO_8, 0xff >> sh); |
| 56 | |
| 57 | tcg_gen_xor_i64(t, n, m); |
| 58 | tcg_gen_shri_i64(d, t, sh); |
| 59 | tcg_gen_shli_i64(t, t, 8 - sh); |
| 60 | tcg_gen_andi_i64(d, d, mask); |
| 61 | tcg_gen_andi_i64(t, t, ~mask); |
| 62 | tcg_gen_or_i64(d, d, t); |
| 63 | } |
| 64 | |
| 65 | static void gen_xar16_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh) |
| 66 | { |
| 67 | TCGv_i64 t = tcg_temp_new_i64(); |
| 68 | uint64_t mask = dup_const(MO_16, 0xffff >> sh); |
| 69 | |
| 70 | tcg_gen_xor_i64(t, n, m); |
| 71 | tcg_gen_shri_i64(d, t, sh); |
| 72 | tcg_gen_shli_i64(t, t, 16 - sh); |
| 73 | tcg_gen_andi_i64(d, d, mask); |
| 74 | tcg_gen_andi_i64(t, t, ~mask); |
| 75 | tcg_gen_or_i64(d, d, t); |
| 76 | } |
| 77 | |
| 78 | static void gen_xar_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, int32_t sh) |
| 79 | { |
| 80 | tcg_gen_xor_i32(d, n, m); |
| 81 | tcg_gen_rotri_i32(d, d, sh); |
| 82 | } |
| 83 | |
| 84 | static void gen_xar_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh) |
| 85 | { |
| 86 | tcg_gen_xor_i64(d, n, m); |
| 87 | tcg_gen_rotri_i64(d, d, sh); |
| 88 | } |
| 89 | |
| 90 | static void gen_xar_vec(unsigned vece, TCGv_vec d, TCGv_vec n, |
| 91 | TCGv_vec m, int64_t sh) |
| 92 | { |
| 93 | tcg_gen_xor_vec(vece, d, n, m); |
| 94 | tcg_gen_rotri_vec(vece, d, d, sh); |
| 95 | } |
| 96 | |
| 97 | void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 98 | uint32_t rm_ofs, int64_t shift, |
| 99 | uint32_t opr_sz, uint32_t max_sz) |
| 100 | { |
| 101 | static const TCGOpcode vecop[] = { INDEX_op_rotli_vec, 0 }; |
| 102 | static const GVecGen3i ops[4] = { |
| 103 | { .fni8 = gen_xar8_i64, |
| 104 | .fniv = gen_xar_vec, |
| 105 | .fno = gen_helper_sve2_xar_b, |
| 106 | .opt_opc = vecop, |
| 107 | .vece = MO_8 }, |
| 108 | { .fni8 = gen_xar16_i64, |
| 109 | .fniv = gen_xar_vec, |
| 110 | .fno = gen_helper_sve2_xar_h, |
| 111 | .opt_opc = vecop, |
| 112 | .vece = MO_16 }, |
| 113 | { .fni4 = gen_xar_i32, |
| 114 | .fniv = gen_xar_vec, |
| 115 | .fno = gen_helper_sve2_xar_s, |
| 116 | .opt_opc = vecop, |
| 117 | .vece = MO_32 }, |
| 118 | { .fni8 = gen_xar_i64, |
| 119 | .fniv = gen_xar_vec, |
| 120 | .fno = gen_helper_gvec_xar_d, |
| 121 | .opt_opc = vecop, |
| 122 | .vece = MO_64 } |
| 123 | }; |
| 124 | int esize = 8 << vece; |
| 125 | |
| 126 | /* The SVE2 range is 1 .. esize; the AdvSIMD range is 0 .. esize-1. */ |
| 127 | tcg_debug_assert(shift >= 0); |
| 128 | tcg_debug_assert(shift <= esize); |
| 129 | shift &= esize - 1; |
| 130 | |
| 131 | if (shift == 0) { |
| 132 | /* xar with no rotate devolves to xor. */ |
| 133 | tcg_gen_gvec_xor(vece, rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz); |
| 134 | } else { |
| 135 | tcg_gen_gvec_3i(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, |
| 136 | shift, &ops[vece]); |
| 137 | } |
| 138 | } |
| 139 | |
| 140 | static void gen_eor3_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) |
| 141 | { |
| 142 | tcg_gen_xor_i64(d, n, m); |
| 143 | tcg_gen_xor_i64(d, d, k); |
| 144 | } |
| 145 | |
| 146 | static void gen_eor3_vec(unsigned vece, TCGv_vec d, TCGv_vec n, |
| 147 | TCGv_vec m, TCGv_vec k) |
| 148 | { |
| 149 | tcg_gen_xor_vec(vece, d, n, m); |
| 150 | tcg_gen_xor_vec(vece, d, d, k); |
| 151 | } |
| 152 | |
| 153 | void gen_gvec_eor3(unsigned vece, uint32_t d, uint32_t n, uint32_t m, |
| 154 | uint32_t a, uint32_t oprsz, uint32_t maxsz) |
| 155 | { |
| 156 | static const GVecGen4 op = { |
| 157 | .fni8 = gen_eor3_i64, |
| 158 | .fniv = gen_eor3_vec, |
| 159 | .fno = gen_helper_sve2_eor3, |
| 160 | .vece = MO_64, |
| 161 | .prefer_i64 = true, |
| 162 | }; |
| 163 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); |
| 164 | } |
| 165 | |
| 166 | static void gen_bcax_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) |
| 167 | { |
| 168 | tcg_gen_andc_i64(d, m, k); |
| 169 | tcg_gen_xor_i64(d, d, n); |
| 170 | } |
| 171 | |
| 172 | static void gen_bcax_vec(unsigned vece, TCGv_vec d, TCGv_vec n, |
| 173 | TCGv_vec m, TCGv_vec k) |
| 174 | { |
| 175 | tcg_gen_andc_vec(vece, d, m, k); |
| 176 | tcg_gen_xor_vec(vece, d, d, n); |
| 177 | } |
| 178 | |
| 179 | void gen_gvec_bcax(unsigned vece, uint32_t d, uint32_t n, uint32_t m, |
| 180 | uint32_t a, uint32_t oprsz, uint32_t maxsz) |
| 181 | { |
| 182 | static const GVecGen4 op = { |
| 183 | .fni8 = gen_bcax_i64, |
| 184 | .fniv = gen_bcax_vec, |
| 185 | .fno = gen_helper_sve2_bcax, |
| 186 | .vece = MO_64, |
| 187 | .prefer_i64 = true, |
| 188 | }; |
| 189 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); |
| 190 | } |
| 191 | |
| 192 | /* |
| 193 | * Set @res to the correctly saturated result. |
| 194 | * Set @qc non-zero if saturation occured. |
| 195 | */ |
| 196 | void gen_suqadd_bhs(TCGv_i64 res, TCGv_i64 qc, |
| 197 | TCGv_i64 a, TCGv_i64 b, MemOp esz) |
| 198 | { |
| 199 | TCGv_i64 max = tcg_constant_i64((1ull << ((8 << esz) - 1)) - 1); |
| 200 | TCGv_i64 t = tcg_temp_new_i64(); |
| 201 | |
| 202 | tcg_gen_add_i64(t, a, b); |
| 203 | tcg_gen_smin_i64(res, t, max); |
| 204 | tcg_gen_xor_i64(t, t, res); |
| 205 | tcg_gen_or_i64(qc, qc, t); |
| 206 | } |
| 207 | |
| 208 | void gen_suqadd_d(TCGv_i64 res, TCGv_i64 qc, TCGv_i64 a, TCGv_i64 b) |
| 209 | { |
| 210 | TCGv_i64 max = tcg_constant_i64(INT64_MAX); |
| 211 | TCGv_i64 t = tcg_temp_new_i64(); |
| 212 | |
| 213 | /* Maximum value that can be added to @a without overflow. */ |
| 214 | tcg_gen_sub_i64(t, max, a); |
| 215 | |
| 216 | /* Constrain addend so that the next addition never overflows. */ |
| 217 | tcg_gen_umin_i64(t, t, b); |
| 218 | tcg_gen_add_i64(res, a, t); |
| 219 | |
| 220 | tcg_gen_xor_i64(t, t, b); |
| 221 | tcg_gen_or_i64(qc, qc, t); |
| 222 | } |
| 223 | |
| 224 | static void gen_suqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec qc, |
| 225 | TCGv_vec a, TCGv_vec b) |
| 226 | { |
| 227 | TCGv_vec max = |
| 228 | tcg_constant_vec_matching(t, vece, (1ull << ((8 << vece) - 1)) - 1); |
| 229 | TCGv_vec u = tcg_temp_new_vec_matching(t); |
| 230 | |
| 231 | /* Maximum value that can be added to @a without overflow. */ |
| 232 | tcg_gen_sub_vec(vece, u, max, a); |
| 233 | |
| 234 | /* Constrain addend so that the next addition never overflows. */ |
| 235 | tcg_gen_umin_vec(vece, u, u, b); |
| 236 | tcg_gen_add_vec(vece, t, u, a); |
| 237 | |
| 238 | /* Compute QC by comparing the adjusted @b. */ |
| 239 | tcg_gen_xor_vec(vece, u, u, b); |
| 240 | tcg_gen_or_vec(vece, qc, qc, u); |
| 241 | } |
| 242 | |
| 243 | void gen_gvec_suqadd_qc(unsigned vece, uint32_t rd_ofs, |
| 244 | uint32_t rn_ofs, uint32_t rm_ofs, |
| 245 | uint32_t opr_sz, uint32_t max_sz) |
| 246 | { |
| 247 | static const TCGOpcode vecop_list[] = { |
| 248 | INDEX_op_add_vec, INDEX_op_sub_vec, INDEX_op_umin_vec, 0 |
| 249 | }; |
| 250 | static const GVecGen4 ops[4] = { |
| 251 | { .fniv = gen_suqadd_vec, |
| 252 | .fno = gen_helper_gvec_suqadd_b, |
| 253 | .opt_opc = vecop_list, |
| 254 | .write_aofs = true, |
| 255 | .vece = MO_8 }, |
| 256 | { .fniv = gen_suqadd_vec, |
| 257 | .fno = gen_helper_gvec_suqadd_h, |
| 258 | .opt_opc = vecop_list, |
| 259 | .write_aofs = true, |
| 260 | .vece = MO_16 }, |
| 261 | { .fniv = gen_suqadd_vec, |
| 262 | .fno = gen_helper_gvec_suqadd_s, |
| 263 | .opt_opc = vecop_list, |
| 264 | .write_aofs = true, |
| 265 | .vece = MO_32 }, |
| 266 | { .fniv = gen_suqadd_vec, |
| 267 | .fni8 = gen_suqadd_d, |
| 268 | .fno = gen_helper_gvec_suqadd_d, |
| 269 | .opt_opc = vecop_list, |
| 270 | .write_aofs = true, |
| 271 | .vece = MO_64 }, |
| 272 | }; |
| 273 | |
| 274 | tcg_debug_assert(opr_sz <= sizeof_field(CPUARMState, vfp.qc)); |
| 275 | tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), |
| 276 | rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]); |
| 277 | } |
| 278 | |
| 279 | void gen_usqadd_bhs(TCGv_i64 res, TCGv_i64 qc, |
| 280 | TCGv_i64 a, TCGv_i64 b, MemOp esz) |
| 281 | { |
| 282 | TCGv_i64 max = tcg_constant_i64(MAKE_64BIT_MASK(0, 8 << esz)); |
| 283 | TCGv_i64 zero = tcg_constant_i64(0); |
| 284 | TCGv_i64 tmp = tcg_temp_new_i64(); |
| 285 | |
| 286 | tcg_gen_add_i64(tmp, a, b); |
| 287 | tcg_gen_smin_i64(res, tmp, max); |
| 288 | tcg_gen_smax_i64(res, res, zero); |
| 289 | tcg_gen_xor_i64(tmp, tmp, res); |
| 290 | tcg_gen_or_i64(qc, qc, tmp); |
| 291 | } |
| 292 | |
| 293 | void gen_usqadd_d(TCGv_i64 res, TCGv_i64 qc, TCGv_i64 a, TCGv_i64 b) |
| 294 | { |
| 295 | TCGv_i64 tmp = tcg_temp_new_i64(); |
| 296 | TCGv_i64 tneg = tcg_temp_new_i64(); |
| 297 | TCGv_i64 tpos = tcg_temp_new_i64(); |
| 298 | TCGv_i64 max = tcg_constant_i64(UINT64_MAX); |
| 299 | TCGv_i64 zero = tcg_constant_i64(0); |
| 300 | |
| 301 | tcg_gen_add_i64(tmp, a, b); |
| 302 | |
| 303 | /* If @b is positive, saturate if (a + b) < a, aka unsigned overflow. */ |
| 304 | tcg_gen_movcond_i64(TCG_COND_LTU, tpos, tmp, a, max, tmp); |
| 305 | |
| 306 | /* If @b is negative, saturate if a < -b, ie subtraction is negative. */ |
| 307 | tcg_gen_neg_i64(tneg, b); |
| 308 | tcg_gen_movcond_i64(TCG_COND_LTU, tneg, a, tneg, zero, tmp); |
| 309 | |
| 310 | /* Select correct result from sign of @b. */ |
| 311 | tcg_gen_movcond_i64(TCG_COND_LT, res, b, zero, tneg, tpos); |
| 312 | tcg_gen_xor_i64(tmp, tmp, res); |
| 313 | tcg_gen_or_i64(qc, qc, tmp); |
| 314 | } |
| 315 | |
| 316 | static void gen_usqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec qc, |
| 317 | TCGv_vec a, TCGv_vec b) |
| 318 | { |
| 319 | TCGv_vec u = tcg_temp_new_vec_matching(t); |
| 320 | TCGv_vec z = tcg_constant_vec_matching(t, vece, 0); |
| 321 | |
| 322 | /* Compute unsigned saturation of add for +b and sub for -b. */ |
| 323 | tcg_gen_neg_vec(vece, t, b); |
| 324 | tcg_gen_usadd_vec(vece, u, a, b); |
| 325 | tcg_gen_ussub_vec(vece, t, a, t); |
| 326 | |
| 327 | /* Select the correct result depending on the sign of b. */ |
| 328 | tcg_gen_cmpsel_vec(TCG_COND_LT, vece, t, b, z, t, u); |
| 329 | |
| 330 | /* Compute QC by comparing against the non-saturated result. */ |
| 331 | tcg_gen_add_vec(vece, u, a, b); |
| 332 | tcg_gen_xor_vec(vece, u, u, t); |
| 333 | tcg_gen_or_vec(vece, qc, qc, u); |
| 334 | } |
| 335 | |
| 336 | void gen_gvec_usqadd_qc(unsigned vece, uint32_t rd_ofs, |
| 337 | uint32_t rn_ofs, uint32_t rm_ofs, |
| 338 | uint32_t opr_sz, uint32_t max_sz) |
| 339 | { |
| 340 | static const TCGOpcode vecop_list[] = { |
| 341 | INDEX_op_neg_vec, INDEX_op_add_vec, |
| 342 | INDEX_op_usadd_vec, INDEX_op_ussub_vec, |
| 343 | INDEX_op_cmpsel_vec, 0 |
| 344 | }; |
| 345 | static const GVecGen4 ops[4] = { |
| 346 | { .fniv = gen_usqadd_vec, |
| 347 | .fno = gen_helper_gvec_usqadd_b, |
| 348 | .opt_opc = vecop_list, |
| 349 | .write_aofs = true, |
| 350 | .vece = MO_8 }, |
| 351 | { .fniv = gen_usqadd_vec, |
| 352 | .fno = gen_helper_gvec_usqadd_h, |
| 353 | .opt_opc = vecop_list, |
| 354 | .write_aofs = true, |
| 355 | .vece = MO_16 }, |
| 356 | { .fniv = gen_usqadd_vec, |
| 357 | .fno = gen_helper_gvec_usqadd_s, |
| 358 | .opt_opc = vecop_list, |
| 359 | .write_aofs = true, |
| 360 | .vece = MO_32 }, |
| 361 | { .fniv = gen_usqadd_vec, |
| 362 | .fni8 = gen_usqadd_d, |
| 363 | .fno = gen_helper_gvec_usqadd_d, |
| 364 | .opt_opc = vecop_list, |
| 365 | .write_aofs = true, |
| 366 | .vece = MO_64 }, |
| 367 | }; |
| 368 | |
| 369 | tcg_debug_assert(opr_sz <= sizeof_field(CPUARMState, vfp.qc)); |
| 370 | tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), |
| 371 | rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]); |
| 372 | } |
| 373 | |
| 374 | void gen_gvec_sve2_sqdmulh(unsigned vece, uint32_t rd_ofs, |
| 375 | uint32_t rn_ofs, uint32_t rm_ofs, |
| 376 | uint32_t opr_sz, uint32_t max_sz) |
| 377 | { |
| 378 | static gen_helper_gvec_3 * const fns[4] = { |
| 379 | gen_helper_sve2_sqdmulh_b, gen_helper_sve2_sqdmulh_h, |
| 380 | gen_helper_sve2_sqdmulh_s, gen_helper_sve2_sqdmulh_d, |
| 381 | }; |
| 382 | tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, 0, fns[vece]); |
| 383 | } |