| 1 | /* |
| 2 | * GICv5 CPU interface |
| 3 | * |
| 4 | * Copyright (c) 2025 Linaro Limited |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | * |
| 8 | * The cpu interface is defined in IHI 111701 |
| 9 | * (ARM Generic Interrupt Controller Architecture Specification, |
| 10 | * GIC architecture version 5): |
| 11 | * https://developer.arm.com/documentation/111701/latest |
| 12 | */ |
| 13 | |
| 14 | #include "qemu/osdep.h" |
| 15 | #include "cpu.h" |
| 16 | #include "internals.h" |
| 17 | #include "cpregs.h" |
| 18 | #include "hw/intc/arm_gicv5_stream.h" |
| 19 | #include "trace.h" |
| 20 | |
| 21 | FIELD(GIC_CDPRI, ID, 0, 24) |
| 22 | FIELD(GIC_CDPRI, TYPE, 29, 3) |
| 23 | FIELD(GIC_CDPRI, PRIORITY, 35, 5) |
| 24 | |
| 25 | FIELD(GIC_CDDI, ID, 0, 24) |
| 26 | FIELD(GIC_CDDI, TYPE, 29, 3) |
| 27 | |
| 28 | FIELD(GIC_CDDIS, ID, 0, 24) |
| 29 | FIELD(GIC_CDDIS, TYPE, 29, 3) |
| 30 | |
| 31 | FIELD(GIC_CDEN, ID, 0, 24) |
| 32 | FIELD(GIC_CDEN, TYPE, 29, 3) |
| 33 | |
| 34 | FIELD(GIC_CDAFF, ID, 0, 24) |
| 35 | FIELD(GIC_CDAFF, IRM, 28, 1) |
| 36 | FIELD(GIC_CDAFF, TYPE, 29, 3) |
| 37 | FIELD(GIC_CDAFF, IAFFID, 32, 16) |
| 38 | |
| 39 | FIELD(GIC_CDPEND, ID, 0, 24) |
| 40 | FIELD(GIC_CDPEND, TYPE, 29, 3) |
| 41 | FIELD(GIC_CDPEND, PENDING, 32, 1) |
| 42 | |
| 43 | FIELD(GIC_CDHM, ID, 0, 24) |
| 44 | FIELD(GIC_CDHM, TYPE, 29, 3) |
| 45 | FIELD(GIC_CDHM, HM, 32, 1) |
| 46 | |
| 47 | FIELD(GIC_CDRCFG, ID, 0, 24) |
| 48 | FIELD(GIC_CDRCFG, TYPE, 29, 3) |
| 49 | |
| 50 | FIELD(GICR_CDIA, ID, 0, 24) |
| 51 | FIELD(GICR_CDIA, TYPE, 29, 3) |
| 52 | FIELD(GICR_CDIA, VALID, 32, 1) |
| 53 | |
| 54 | FIELD(ICC_IDR0_EL1, ID_BITS, 0, 4) |
| 55 | FIELD(ICC_IDR0_EL1, PRI_BITS, 4, 4) |
| 56 | FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4) |
| 57 | |
| 58 | FIELD(ICC_CR0, EN, 0, 1) |
| 59 | FIELD(ICC_CR0, LINK, 1, 1) |
| 60 | FIELD(ICC_CR0, LINK_IDLE, 2, 1) |
| 61 | FIELD(ICC_CR0, IPPT, 32, 6) |
| 62 | FIELD(ICC_CR0, PID, 38, 1) |
| 63 | |
| 64 | FIELD(ICC_PCR, PRIORITY, 0, 5) |
| 65 | |
| 66 | FIELD(ICC_HPPIR_EL1, ID, 0, 24) |
| 67 | FIELD(ICC_HPPIR_EL1, TYPE, 29, 3) |
| 68 | FIELD(ICC_HPPIR_EL1, HPPIV, 32, 1) |
| 69 | |
| 70 | /* |
| 71 | * We implement 24 bits of interrupt ID, the mandated 5 bits of priority, |
| 72 | * and no legacy GICv3.3 vcpu interface (yet) |
| 73 | */ |
| 74 | #define QEMU_ICC_IDR0 \ |
| 75 | ((4 << R_ICC_IDR0_EL1_PRI_BITS_SHIFT) | \ |
| 76 | (1 << R_ICC_IDR0_EL1_ID_BITS_SHIFT)) |
| 77 | |
| 78 | /* |
| 79 | * PPI handling modes are fixed and not software configurable. |
| 80 | * R_CFSKX defines them for the architected PPIs: they are all Level, |
| 81 | * except that PPI 24 (CTIIRQ) is IMPDEF and PPI 3 (SW_PPI) is Edge. |
| 82 | * For unimplemented PPIs the field is RES0. The PPI register bits |
| 83 | * are 1 for Level and 0 for Edge. |
| 84 | */ |
| 85 | #define PPI_HMR0_RESET (~(1ULL << GICV5_PPI_SW_PPI)) |
| 86 | #define PPI_HMR1_RESET (~0ULL) |
| 87 | |
| 88 | static GICv5Common *gicv5_get_gic(CPUARMState *env) |
| 89 | { |
| 90 | return env->gicv5state; |
| 91 | } |
| 92 | |
| 93 | static GICv5Domain gicv5_logical_domain(CPUARMState *env) |
| 94 | { |
| 95 | /* |
| 96 | * Return the Logical Interrupt Domain, which is the one associated |
| 97 | * with the security state selected by the SCR_EL3.{NS,NSE} bits |
| 98 | */ |
| 99 | switch (arm_security_space_below_el3(env)) { |
| 100 | case ARMSS_Secure: |
| 101 | return GICV5_ID_S; |
| 102 | case ARMSS_NonSecure: |
| 103 | return GICV5_ID_NS; |
| 104 | case ARMSS_Realm: |
| 105 | return GICV5_ID_REALM; |
| 106 | default: |
| 107 | g_assert_not_reached(); |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | static GICv5Domain gicv5_current_phys_domain(CPUARMState *env) |
| 112 | { |
| 113 | /* |
| 114 | * Return the Current Physical Interrupt Domain as |
| 115 | * defined by R_ZFCXM. |
| 116 | */ |
| 117 | if (arm_current_el(env) == 3) { |
| 118 | return GICV5_ID_EL3; |
| 119 | } |
| 120 | return gicv5_logical_domain(env); |
| 121 | } |
| 122 | |
| 123 | static uint64_t gic_running_prio(CPUARMState *env, GICv5Domain domain) |
| 124 | { |
| 125 | /* |
| 126 | * Return the current running priority; this is the lowest set bit in |
| 127 | * the Active Priority Register, or the idle priority if none (D_XMBQZ) |
| 128 | */ |
| 129 | uint64_t hap = ctz64(env->gicv5_cpuif.icc_apr[domain]); |
| 130 | return hap < 32 ? hap : PRIO_IDLE; |
| 131 | } |
| 132 | |
| 133 | static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv5Domain domain) |
| 134 | { |
| 135 | /* |
| 136 | * Return the current highest priority pending interrupt for the |
| 137 | * specified domain, if it has sufficient priority to preempt. |
| 138 | * If there is no interrupt that can preempt we signal this by |
| 139 | * returning a struct with prio == PRIO_IDLE. |
| 140 | */ |
| 141 | |
| 142 | GICv5Common *gic = gicv5_get_gic(env); |
| 143 | GICv5PendingIrq best, irs_hppi; |
| 144 | |
| 145 | if (!(env->gicv5_cpuif.icc_cr0[domain] & R_ICC_CR0_EN_MASK)) { |
| 146 | /* If cpuif is disabled there is no HPPI */ |
| 147 | return GICV5_PENDING_IRQ_NONE; |
| 148 | } |
| 149 | |
| 150 | irs_hppi = gicv5_get_hppi(gic, domain, env->gicv5_iaffid); |
| 151 | |
| 152 | /* |
| 153 | * If the best PPI and the best interrupt from the IRS have the |
| 154 | * same priority, it's IMPDEF which we pick (R_VVBPS). We choose |
| 155 | * the PPI. |
| 156 | */ |
| 157 | if (env->gicv5_cpuif.ppi_hppi[domain].prio <= irs_hppi.prio) { |
| 158 | best = env->gicv5_cpuif.ppi_hppi[domain]; |
| 159 | } else { |
| 160 | best = irs_hppi; |
| 161 | } |
| 162 | |
| 163 | /* |
| 164 | * D_MSQKF: an interrupt has sufficient priority if its priority |
| 165 | * is higher than the current running priority and equal to or |
| 166 | * higher than the priority mask. |
| 167 | */ |
| 168 | if (best.prio == PRIO_IDLE || |
| 169 | best.prio > env->gicv5_cpuif.icc_pcr[domain] || |
| 170 | best.prio >= gic_running_prio(env, domain)) { |
| 171 | return GICV5_PENDING_IRQ_NONE; |
| 172 | } |
| 173 | return best; |
| 174 | } |
| 175 | |
| 176 | static void cpu_interrupt_update(CPUARMState *env, int irqtype, bool new_state) |
| 177 | { |
| 178 | CPUState *cs = env_cpu(env); |
| 179 | |
| 180 | /* |
| 181 | * OPT: calling cpu_interrupt() and cpu_reset_interrupt() has the |
| 182 | * correct behaviour, but is not optimal for the case where we're |
| 183 | * setting the interrupt line to the same level it already has. |
| 184 | * |
| 185 | * Clearing an already clear interrupt is free (it's just doing an |
| 186 | * atomic AND operation). Signalling an already set interrupt is a |
| 187 | * bit less ideal (it might unnecessarily kick the CPU). |
| 188 | * |
| 189 | * We could potentially use cpu_test_interrupt(), like |
| 190 | * arm_cpu_update_{virq,vfiq,vinmi,vserr}, since we always hold |
| 191 | * the BQL here; or perhaps there is an abstraction we could |
| 192 | * provide in the core code that all these places could call. |
| 193 | * |
| 194 | * For now, this is simple and definitely correct. |
| 195 | */ |
| 196 | if (new_state) { |
| 197 | cpu_interrupt(cs, irqtype); |
| 198 | } else { |
| 199 | cpu_reset_interrupt(cs, irqtype); |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | static void gicv5_update_irq_fiq(CPUARMState *env) |
| 204 | { |
| 205 | /* |
| 206 | * Update whether we are signalling IRQ or FIQ based on the |
| 207 | * current state of the CPU interface (and in particular on the |
| 208 | * HPPI information from the IRS and for the PPIs for each |
| 209 | * interrupt domain); |
| 210 | * |
| 211 | * The logic here for IRQ and FIQ is defined by rules R_QLGBG and |
| 212 | * R_ZGHMN; whether to signal with superpriority is defined by |
| 213 | * rule R_CSBDX. |
| 214 | * |
| 215 | * For the moment, we do not consider preemptive interrupts, |
| 216 | * because these only occur when there is a HPPI of sufficient |
| 217 | * priority for another interrupt domain, and we only support EL1 |
| 218 | * and the NonSecure interrupt domain currently. |
| 219 | * |
| 220 | * NB: when we handle more than just EL1 we will need to arrange |
| 221 | * to call this function to re-evaluate the IRQ and FIQ state when |
| 222 | * we change EL. |
| 223 | */ |
| 224 | GICv5PendingIrq current_hppi; |
| 225 | bool irq, fiq, superpriority; |
| 226 | |
| 227 | /* |
| 228 | * We will never signal FIQ because FIQ is for preemptive |
| 229 | * interrupts or for EL3 HPPIs. |
| 230 | */ |
| 231 | fiq = false; |
| 232 | |
| 233 | /* |
| 234 | * We signal IRQ when we are not signalling FIQ and there is a |
| 235 | * HPPI of sufficient priority for the current domain. It has |
| 236 | * Superpriority if its priority is 0 (in which case it is |
| 237 | * CPU_INTERRUPT_NMI rather than CPU_INTERRUPT_HARD). |
| 238 | */ |
| 239 | current_hppi = gic_hppi(env, gicv5_current_phys_domain(env)); |
| 240 | superpriority = current_hppi.prio == 0; |
| 241 | irq = current_hppi.prio != PRIO_IDLE && !superpriority; |
| 242 | |
| 243 | /* |
| 244 | * Unlike a GICv3 or GICv2, there is no external IRQ or FIQ line |
| 245 | * to the CPU. Instead we directly signal the interrupt via |
| 246 | * cpu_interrupt()/cpu_reset_interrupt(). |
| 247 | */ |
| 248 | trace_gicv5_update_irq_fiq(irq, fiq, superpriority); |
| 249 | cpu_interrupt_update(env, CPU_INTERRUPT_HARD, irq); |
| 250 | cpu_interrupt_update(env, CPU_INTERRUPT_FIQ, fiq); |
| 251 | cpu_interrupt_update(env, CPU_INTERRUPT_NMI, superpriority); |
| 252 | } |
| 253 | |
| 254 | static void gic_recalc_ppi_hppi(CPUARMState *env) |
| 255 | { |
| 256 | /* |
| 257 | * Recalculate the HPPI PPI: this is the best PPI which is |
| 258 | * enabled, pending and not active. |
| 259 | */ |
| 260 | for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_hppi); i++) { |
| 261 | env->gicv5_cpuif.ppi_hppi[i] = GICV5_PENDING_IRQ_NONE; |
| 262 | }; |
| 263 | |
| 264 | for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_active); i++) { |
| 265 | uint64_t en_pend_nact = env->gicv5_cpuif.ppi_enable[i] & |
| 266 | env->gicv5_cpuif.ppi_pend[i] & |
| 267 | ~env->gicv5_cpuif.ppi_active[i]; |
| 268 | |
| 269 | while (en_pend_nact) { |
| 270 | /* |
| 271 | * When EL3 is supported ICC_PPI_DOMAINR<n>_EL3 tells us |
| 272 | * the domain of each PPI. While we only support EL1, the |
| 273 | * domain is always NS. |
| 274 | */ |
| 275 | GICv5Domain ppi_domain = GICV5_ID_NS; |
| 276 | uint8_t prio; |
| 277 | int ppi; |
| 278 | int bit = ctz64(en_pend_nact); |
| 279 | |
| 280 | en_pend_nact &= ~(1ULL << bit); |
| 281 | |
| 282 | ppi = i * 64 + bit; |
| 283 | prio = extract64(env->gicv5_cpuif.ppi_priority[ppi / 8], |
| 284 | (ppi & 7) * 8, 5); |
| 285 | |
| 286 | if (prio < env->gicv5_cpuif.ppi_hppi[ppi_domain].prio) { |
| 287 | uint32_t intid = 0; |
| 288 | |
| 289 | intid = FIELD_DP32(intid, INTID, ID, ppi); |
| 290 | intid = FIELD_DP32(intid, INTID, TYPE, GICV5_PPI); |
| 291 | env->gicv5_cpuif.ppi_hppi[ppi_domain].intid = intid; |
| 292 | env->gicv5_cpuif.ppi_hppi[ppi_domain].prio = prio; |
| 293 | } |
| 294 | } |
| 295 | } |
| 296 | |
| 297 | for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_hppi); i++) { |
| 298 | trace_gicv5_recalc_ppi_hppi(i, |
| 299 | env->gicv5_cpuif.ppi_hppi[i].intid, |
| 300 | env->gicv5_cpuif.ppi_hppi[i].prio); |
| 301 | } |
| 302 | gicv5_update_irq_fiq(env); |
| 303 | } |
| 304 | |
| 305 | void gicv5_forward_interrupt(ARMCPU *cpu, GICv5Domain domain) |
| 306 | { |
| 307 | /* |
| 308 | * IRS HPPI has changed: recalculate the IRQ/FIQ levels by |
| 309 | * combining the IRS HPPI with the PPI HPPI. |
| 310 | */ |
| 311 | gicv5_update_irq_fiq(&cpu->env); |
| 312 | } |
| 313 | |
| 314 | void gicv5_update_ppi_state(CPUARMState *env, int ppi, bool level) |
| 315 | { |
| 316 | /* |
| 317 | * Update the state of the given PPI (which is connected to some |
| 318 | * CPU-internal source of interrupts, like the timers). We can |
| 319 | * assume that the PPI is fixed as level-triggered, which means |
| 320 | * that its pending state exactly tracks the input (and the guest |
| 321 | * cannot separately change the pending state, because the pending |
| 322 | * bits are RO). |
| 323 | */ |
| 324 | int oldlevel; |
| 325 | |
| 326 | if (!cpu_isar_feature(aa64_gcie, env_archcpu(env))) { |
| 327 | return; |
| 328 | } |
| 329 | |
| 330 | /* The architected PPIs are 0..63, so in the first PPI register. */ |
| 331 | assert(ppi >= 0 && ppi < 64); |
| 332 | oldlevel = extract64(env->gicv5_cpuif.ppi_pend[0], ppi, 1); |
| 333 | if (oldlevel != level) { |
| 334 | trace_gicv5_update_ppi_state(ppi, level); |
| 335 | |
| 336 | env->gicv5_cpuif.ppi_pend[0] = |
| 337 | deposit64(env->gicv5_cpuif.ppi_pend[0], ppi, 1, level); |
| 338 | gic_recalc_ppi_hppi(env); |
| 339 | } |
| 340 | } |
| 341 | |
| 342 | static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 343 | uint64_t value) |
| 344 | { |
| 345 | GICv5Common *gic = gicv5_get_gic(env); |
| 346 | GICv5IntType type = FIELD_EX64(value, GIC_CDDIS, TYPE); |
| 347 | uint32_t id = FIELD_EX64(value, GIC_CDDIS, ID); |
| 348 | bool virtual = false; |
| 349 | GICv5Domain domain = gicv5_current_phys_domain(env); |
| 350 | |
| 351 | gicv5_set_enabled(gic, id, false, domain, type, virtual); |
| 352 | } |
| 353 | |
| 354 | static void gic_cden_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 355 | uint64_t value) |
| 356 | { |
| 357 | GICv5Common *gic = gicv5_get_gic(env); |
| 358 | GICv5IntType type = FIELD_EX64(value, GIC_CDEN, TYPE); |
| 359 | uint32_t id = FIELD_EX64(value, GIC_CDEN, ID); |
| 360 | bool virtual = false; |
| 361 | GICv5Domain domain = gicv5_current_phys_domain(env); |
| 362 | |
| 363 | gicv5_set_enabled(gic, id, true, domain, type, virtual); |
| 364 | } |
| 365 | |
| 366 | static void gic_cdpri_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 367 | uint64_t value) |
| 368 | { |
| 369 | GICv5Common *gic = gicv5_get_gic(env); |
| 370 | uint8_t priority = FIELD_EX64(value, GIC_CDPRI, PRIORITY); |
| 371 | GICv5IntType type = FIELD_EX64(value, GIC_CDPRI, TYPE); |
| 372 | uint32_t id = FIELD_EX64(value, GIC_CDPRI, ID); |
| 373 | bool virtual = false; |
| 374 | GICv5Domain domain = gicv5_current_phys_domain(env); |
| 375 | |
| 376 | gicv5_set_priority(gic, id, priority, domain, type, virtual); |
| 377 | } |
| 378 | |
| 379 | static void gic_cdaff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 380 | uint64_t value) |
| 381 | { |
| 382 | GICv5Common *gic = gicv5_get_gic(env); |
| 383 | uint32_t iaffid = FIELD_EX64(value, GIC_CDAFF, IAFFID); |
| 384 | GICv5RoutingMode irm = FIELD_EX64(value, GIC_CDAFF, IRM); |
| 385 | GICv5IntType type = FIELD_EX64(value, GIC_CDAFF, TYPE); |
| 386 | uint32_t id = FIELD_EX64(value, GIC_CDAFF, ID); |
| 387 | bool virtual = false; |
| 388 | GICv5Domain domain = gicv5_current_phys_domain(env); |
| 389 | |
| 390 | gicv5_set_target(gic, id, iaffid, irm, domain, type, virtual); |
| 391 | } |
| 392 | |
| 393 | static void gic_cdpend_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 394 | uint64_t value) |
| 395 | { |
| 396 | GICv5Common *gic = gicv5_get_gic(env); |
| 397 | bool pending = FIELD_EX64(value, GIC_CDPEND, PENDING); |
| 398 | GICv5IntType type = FIELD_EX64(value, GIC_CDPEND, TYPE); |
| 399 | uint32_t id = FIELD_EX64(value, GIC_CDPEND, ID); |
| 400 | bool virtual = false; |
| 401 | GICv5Domain domain = gicv5_current_phys_domain(env); |
| 402 | |
| 403 | gicv5_set_pending(gic, id, pending, domain, type, virtual); |
| 404 | } |
| 405 | |
| 406 | static void gic_cdrcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 407 | uint64_t value) |
| 408 | { |
| 409 | GICv5Common *gic = gicv5_get_gic(env); |
| 410 | GICv5IntType type = FIELD_EX64(value, GIC_CDRCFG, TYPE); |
| 411 | uint32_t id = FIELD_EX64(value, GIC_CDRCFG, ID); |
| 412 | bool virtual = false; |
| 413 | GICv5Domain domain = gicv5_current_phys_domain(env); |
| 414 | |
| 415 | env->gicv5_cpuif.icc_icsr_el1 = |
| 416 | gicv5_request_config(gic, id, domain, type, virtual); |
| 417 | } |
| 418 | |
| 419 | static void gic_cdhm_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 420 | uint64_t value) |
| 421 | { |
| 422 | GICv5Common *gic = gicv5_get_gic(env); |
| 423 | GICv5HandlingMode hm = FIELD_EX64(value, GIC_CDHM, HM); |
| 424 | GICv5IntType type = FIELD_EX64(value, GIC_CDAFF, TYPE); |
| 425 | uint32_t id = FIELD_EX64(value, GIC_CDAFF, ID); |
| 426 | bool virtual = false; |
| 427 | GICv5Domain domain = gicv5_current_phys_domain(env); |
| 428 | |
| 429 | gicv5_set_handling(gic, id, hm, domain, type, virtual); |
| 430 | } |
| 431 | |
| 432 | static void gic_ppi_cactive_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 433 | uint64_t value) |
| 434 | { |
| 435 | uint64_t old = raw_read(env, ri); |
| 436 | raw_write(env, ri, old & ~value); |
| 437 | gic_recalc_ppi_hppi(env); |
| 438 | } |
| 439 | |
| 440 | static void gic_ppi_sactive_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 441 | uint64_t value) |
| 442 | { |
| 443 | uint64_t old = raw_read(env, ri); |
| 444 | raw_write(env, ri, old | value); |
| 445 | gic_recalc_ppi_hppi(env); |
| 446 | } |
| 447 | |
| 448 | static void gic_ppi_cpend_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 449 | uint64_t value) |
| 450 | { |
| 451 | uint64_t old = raw_read(env, ri); |
| 452 | /* If ICC_PPI_HMR_EL1[n].HM is 1, PEND bits are RO */ |
| 453 | uint64_t hm = env->gicv5_cpuif.ppi_hm[ri->opc2 & 1]; |
| 454 | value &= ~hm; |
| 455 | raw_write(env, ri, old & ~value); |
| 456 | gic_recalc_ppi_hppi(env); |
| 457 | } |
| 458 | |
| 459 | static void gic_ppi_spend_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 460 | uint64_t value) |
| 461 | { |
| 462 | uint64_t old = raw_read(env, ri); |
| 463 | /* If ICC_PPI_HMR_EL1[n].HM is 1, PEND bits are RO */ |
| 464 | uint64_t hm = env->gicv5_cpuif.ppi_hm[ri->opc2 & 1]; |
| 465 | value &= ~hm; |
| 466 | raw_write(env, ri, old | value); |
| 467 | gic_recalc_ppi_hppi(env); |
| 468 | } |
| 469 | |
| 470 | static void gic_ppi_enable_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 471 | uint64_t value) |
| 472 | { |
| 473 | raw_write(env, ri, value); |
| 474 | gic_recalc_ppi_hppi(env); |
| 475 | } |
| 476 | |
| 477 | static void gic_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 478 | uint64_t value) |
| 479 | { |
| 480 | raw_write(env, ri, value); |
| 481 | gic_recalc_ppi_hppi(env); |
| 482 | } |
| 483 | |
| 484 | /* |
| 485 | * ICC_APR_EL1 is banked and reads/writes as the version for the |
| 486 | * current logical interrupt domain. |
| 487 | */ |
| 488 | static void gic_icc_apr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 489 | uint64_t value) |
| 490 | { |
| 491 | /* |
| 492 | * With an architectural 5 bits of priority, this register has 32 |
| 493 | * non-RES0 bits |
| 494 | */ |
| 495 | GICv5Domain domain = gicv5_logical_domain(env); |
| 496 | value &= 0xffffffff; |
| 497 | env->gicv5_cpuif.icc_apr[domain] = value; |
| 498 | gicv5_update_irq_fiq(env); |
| 499 | } |
| 500 | |
| 501 | static uint64_t gic_icc_apr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri) |
| 502 | { |
| 503 | GICv5Domain domain = gicv5_logical_domain(env); |
| 504 | return env->gicv5_cpuif.icc_apr[domain]; |
| 505 | } |
| 506 | |
| 507 | static void gic_icc_apr_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
| 508 | { |
| 509 | for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_apr); i++) { |
| 510 | env->gicv5_cpuif.icc_apr[i] = 0; |
| 511 | } |
| 512 | } |
| 513 | |
| 514 | /* ICC_CR0_EL1 is also banked */ |
| 515 | static uint64_t gic_icc_cr0_el1_read(CPUARMState *env, const ARMCPRegInfo *ri) |
| 516 | { |
| 517 | GICv5Domain domain = gicv5_logical_domain(env); |
| 518 | return env->gicv5_cpuif.icc_cr0[domain]; |
| 519 | } |
| 520 | |
| 521 | static void gic_icc_cr0_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 522 | uint64_t value) |
| 523 | { |
| 524 | /* |
| 525 | * For our implementation the link to the IRI is always connected, |
| 526 | * so LINK and LINK_IDLE are always 1. Without EL3, PID and IPPT |
| 527 | * are RAZ/WI, so the only writeable bit is the main enable bit EN. |
| 528 | */ |
| 529 | GICv5Domain domain = gicv5_logical_domain(env); |
| 530 | value &= R_ICC_CR0_EN_MASK; |
| 531 | value |= R_ICC_CR0_LINK_MASK | R_ICC_CR0_LINK_IDLE_MASK; |
| 532 | |
| 533 | env->gicv5_cpuif.icc_cr0[domain] = value; |
| 534 | gicv5_update_irq_fiq(env); |
| 535 | } |
| 536 | |
| 537 | static void gic_icc_cr0_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
| 538 | { |
| 539 | /* The link is always connected so we reset with LINK and LINK_IDLE set */ |
| 540 | for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_cr0); i++) { |
| 541 | env->gicv5_cpuif.icc_cr0[i] = |
| 542 | R_ICC_CR0_LINK_MASK | R_ICC_CR0_LINK_IDLE_MASK; |
| 543 | } |
| 544 | } |
| 545 | |
| 546 | static uint64_t gic_icc_pcr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri) |
| 547 | { |
| 548 | GICv5Domain domain = gicv5_logical_domain(env); |
| 549 | return env->gicv5_cpuif.icc_pcr[domain]; |
| 550 | } |
| 551 | |
| 552 | static void gic_icc_pcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 553 | uint64_t value) |
| 554 | { |
| 555 | GICv5Domain domain = gicv5_logical_domain(env); |
| 556 | |
| 557 | value &= R_ICC_PCR_PRIORITY_MASK; |
| 558 | env->gicv5_cpuif.icc_pcr[domain] = value; |
| 559 | gicv5_update_irq_fiq(env); |
| 560 | } |
| 561 | |
| 562 | static void gic_icc_pcr_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
| 563 | { |
| 564 | for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_pcr); i++) { |
| 565 | env->gicv5_cpuif.icc_pcr[i] = 0; |
| 566 | } |
| 567 | } |
| 568 | |
| 569 | static uint64_t gic_icc_hppir_el1_read(CPUARMState *env, const ARMCPRegInfo *ri) |
| 570 | { |
| 571 | GICv5Domain domain = gicv5_logical_domain(env); |
| 572 | GICv5PendingIrq hppi = gic_hppi(env, domain); |
| 573 | |
| 574 | if (hppi.prio == PRIO_IDLE) { |
| 575 | /* No valid interrupt */ |
| 576 | return 0; |
| 577 | } |
| 578 | return hppi.intid | R_ICC_HPPIR_EL1_HPPIV_MASK; |
| 579 | } |
| 580 | |
| 581 | static bool gic_hppi_is_nmi(CPUARMState *env, GICv5PendingIrq hppi, |
| 582 | GICv5Domain domain) |
| 583 | { |
| 584 | /* |
| 585 | * For GICv5 an interrupt is an NMI if it is signaled with |
| 586 | * Superpriority and SCTLR_ELx.NMI for the current EL is 1. GICR |
| 587 | * CDIA/CDNMIA always work on the current interrupt domain, so we |
| 588 | * do not need to consider preemptive interrupts. This means that |
| 589 | * the interrupt has Superpriority if and only if it has priority 0. |
| 590 | */ |
| 591 | return hppi.prio == 0 && arm_sctlr(env, arm_current_el(env)) & SCTLR_NMI; |
| 592 | } |
| 593 | |
| 594 | static uint64_t gicr_cdia_read(CPUARMState *env, const ARMCPRegInfo *ri) |
| 595 | { |
| 596 | /* Acknowledge HPPI in the current interrupt domain */ |
| 597 | GICv5Common *gic = gicv5_get_gic(env); |
| 598 | GICv5Domain domain = gicv5_current_phys_domain(env); |
| 599 | GICv5PendingIrq hppi = gic_hppi(env, domain); |
| 600 | GICv5IntType type = FIELD_EX64(hppi.intid, INTID, TYPE); |
| 601 | uint32_t id = FIELD_EX64(hppi.intid, INTID, ID); |
| 602 | |
| 603 | bool cdnmia = ri->opc2 == 1; |
| 604 | |
| 605 | if (hppi.prio == PRIO_IDLE) { |
| 606 | /* No interrupt available to acknowledge */ |
| 607 | trace_gicv5_gicr_cdia_fail(domain, |
| 608 | "no available interrupt to acknowledge"); |
| 609 | return 0; |
| 610 | } |
| 611 | |
| 612 | if (gic_hppi_is_nmi(env, hppi, domain) != cdnmia) { |
| 613 | /* GICR CDIA only acknowledges non-NMI; GICR CDNMIA only NMI */ |
| 614 | trace_gicv5_gicr_cdia_fail(domain, |
| 615 | cdnmia ? "CDNMIA but HPPI is not NMI" : |
| 616 | "CDIA but HPPI is NMI"); |
| 617 | return 0; |
| 618 | } |
| 619 | |
| 620 | trace_gicv5_gicr_cdia(domain, hppi.intid); |
| 621 | |
| 622 | /* |
| 623 | * The interrupt becomes Active. If the handling mode of the |
| 624 | * interrupt is Edge then we also clear the pending state. |
| 625 | */ |
| 626 | |
| 627 | /* |
| 628 | * Set the appropriate bit in the APR to track active priorities. |
| 629 | * We do this now so that when gic_recalc_ppi_hppi() or |
| 630 | * gicv5_activate() cause a re-evaluation of HPPIs they use the |
| 631 | * right (new) running priority. |
| 632 | */ |
| 633 | env->gicv5_cpuif.icc_apr[domain] |= (1ULL << hppi.prio); |
| 634 | switch (type) { |
| 635 | case GICV5_PPI: |
| 636 | { |
| 637 | uint32_t ppireg; |
| 638 | uint64_t ppibit; |
| 639 | |
| 640 | assert(id < GICV5_NUM_PPIS); |
| 641 | ppireg = id / 64; |
| 642 | ppibit = 1ULL << (id % 64); |
| 643 | |
| 644 | env->gicv5_cpuif.ppi_active[ppireg] |= ppibit; |
| 645 | if (!(env->gicv5_cpuif.ppi_hm[ppireg] & ppibit)) { |
| 646 | /* handling mode is Edge: clear pending */ |
| 647 | env->gicv5_cpuif.ppi_pend[ppireg] &= ~ppibit; |
| 648 | } |
| 649 | gic_recalc_ppi_hppi(env); |
| 650 | break; |
| 651 | } |
| 652 | case GICV5_LPI: |
| 653 | case GICV5_SPI: |
| 654 | /* |
| 655 | * Send an Activate command to the IRS, which, despite the |
| 656 | * name of the stream command, does both "set Active" and |
| 657 | * "maybe set not Pending" as a single atomic action. |
| 658 | */ |
| 659 | gicv5_activate(gic, id, domain, type, false); |
| 660 | break; |
| 661 | default: |
| 662 | g_assert_not_reached(); |
| 663 | } |
| 664 | |
| 665 | return hppi.intid | R_GICR_CDIA_VALID_MASK; |
| 666 | } |
| 667 | |
| 668 | static void gic_cdeoi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 669 | uint64_t value) |
| 670 | { |
| 671 | /* |
| 672 | * Perform Priority Drop in the current interrupt domain. |
| 673 | * This is just clearing the lowest set bit in the APR. |
| 674 | */ |
| 675 | GICv5Domain domain = gicv5_current_phys_domain(env); |
| 676 | uint64_t *apr = &env->gicv5_cpuif.icc_apr[domain]; |
| 677 | |
| 678 | trace_gicv5_cdeoi(domain); |
| 679 | |
| 680 | /* clear lowest bit, doing nothing if already zero */ |
| 681 | *apr &= *apr - 1; |
| 682 | gicv5_update_irq_fiq(env); |
| 683 | } |
| 684 | |
| 685 | static void gic_cddi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 686 | uint64_t value) |
| 687 | { |
| 688 | /* |
| 689 | * Clear the Active state of the specified interrupt in the |
| 690 | * current interrupt domain. |
| 691 | */ |
| 692 | GICv5Common *gic = gicv5_get_gic(env); |
| 693 | GICv5Domain domain = gicv5_current_phys_domain(env); |
| 694 | GICv5IntType type = FIELD_EX64(value, GIC_CDDI, TYPE); |
| 695 | uint32_t id = FIELD_EX64(value, GIC_CDDI, ID); |
| 696 | bool virtual = false; |
| 697 | |
| 698 | trace_gicv5_cddi(domain, value); |
| 699 | |
| 700 | switch (type) { |
| 701 | case GICV5_PPI: |
| 702 | { |
| 703 | uint32_t ppireg, ppibit; |
| 704 | |
| 705 | if (id >= GICV5_NUM_PPIS) { |
| 706 | break; |
| 707 | } |
| 708 | |
| 709 | ppireg = id / 64; |
| 710 | ppibit = 1ULL << (id % 64); |
| 711 | |
| 712 | env->gicv5_cpuif.ppi_active[ppireg] &= ~ppibit; |
| 713 | gic_recalc_ppi_hppi(env); |
| 714 | break; |
| 715 | } |
| 716 | case GICV5_LPI: |
| 717 | case GICV5_SPI: |
| 718 | /* Tell the IRS to deactivate this interrupt */ |
| 719 | gicv5_deactivate(gic, id, domain, type, virtual); |
| 720 | break; |
| 721 | default: |
| 722 | break; |
| 723 | } |
| 724 | } |
| 725 | |
| 726 | static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { |
| 727 | /* |
| 728 | * Barrier: wait until the effects of a cpuif system register |
| 729 | * write have definitely made it to the IRS (and will thus show up |
| 730 | * in cpuif reads from the IRS by this or other CPUs and in the |
| 731 | * status of IRQ, FIQ etc). For QEMU we do all interaction with |
| 732 | * the IRS synchronously, so we can make this a nop. |
| 733 | */ |
| 734 | { .name = "GSB_SYS", .state = ARM_CP_STATE_AA64, |
| 735 | .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 0, |
| 736 | .access = PL1_W, .type = ARM_CP_NOP, |
| 737 | }, |
| 738 | /* |
| 739 | * Barrier: wait until the effects of acknowledging an interrupt |
| 740 | * (via GICR CDIA or GICR CDNMIA) are visible, including the |
| 741 | * effect on the {IRQ,FIQ,vIRQ,vFIQ} pending state. This is a |
| 742 | * weaker version of GSB SYS. Again, for QEMU this is a nop. |
| 743 | */ |
| 744 | { .name = "GSB_ACK", .state = ARM_CP_STATE_AA64, |
| 745 | .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
| 746 | .access = PL1_W, .type = ARM_CP_NOP, |
| 747 | }, |
| 748 | { .name = "GIC_CDDIS", .state = ARM_CP_STATE_AA64, |
| 749 | .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, |
| 750 | .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 751 | .writefn = gic_cddis_write, |
| 752 | }, |
| 753 | { .name = "GIC_CDEN", .state = ARM_CP_STATE_AA64, |
| 754 | .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1, |
| 755 | .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 756 | .writefn = gic_cden_write, |
| 757 | }, |
| 758 | { .name = "GIC_CDPRI", .state = ARM_CP_STATE_AA64, |
| 759 | .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 2, |
| 760 | .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 761 | .writefn = gic_cdpri_write, |
| 762 | }, |
| 763 | { .name = "GIC_CDAFF", .state = ARM_CP_STATE_AA64, |
| 764 | .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 3, |
| 765 | .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 766 | .writefn = gic_cdaff_write, |
| 767 | }, |
| 768 | { .name = "GIC_CDPEND", .state = ARM_CP_STATE_AA64, |
| 769 | .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 4, |
| 770 | .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 771 | .writefn = gic_cdpend_write, |
| 772 | }, |
| 773 | { .name = "GIC_CDRCFG", .state = ARM_CP_STATE_AA64, |
| 774 | .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 5, |
| 775 | .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 776 | .writefn = gic_cdrcfg_write, |
| 777 | }, |
| 778 | { .name = "GIC_CDEOI", .state = ARM_CP_STATE_AA64, |
| 779 | .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 7, |
| 780 | .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 781 | .writefn = gic_cdeoi_write, |
| 782 | }, |
| 783 | { .name = "GIC_CDDI", .state = ARM_CP_STATE_AA64, |
| 784 | .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 2, .opc2 = 0, |
| 785 | .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 786 | .writefn = gic_cddi_write, |
| 787 | }, |
| 788 | { .name = "GIC_CDHM", .state = ARM_CP_STATE_AA64, |
| 789 | .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 2, .opc2 = 1, |
| 790 | .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 791 | .writefn = gic_cdhm_write, |
| 792 | }, |
| 793 | { .name = "GICR_CDIA", .state = ARM_CP_STATE_AA64, |
| 794 | .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 3, .opc2 = 0, |
| 795 | .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 796 | .readfn = gicr_cdia_read, |
| 797 | }, |
| 798 | { .name = "GICR_CDNMIA", .state = ARM_CP_STATE_AA64, |
| 799 | .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 3, .opc2 = 1, |
| 800 | .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 801 | .readfn = gicr_cdia_read, |
| 802 | }, |
| 803 | { .name = "ICC_IDR0_EL1", .state = ARM_CP_STATE_AA64, |
| 804 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 2, |
| 805 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
| 806 | .resetvalue = QEMU_ICC_IDR0, |
| 807 | }, |
| 808 | { .name = "ICC_ICSR_EL1", .state = ARM_CP_STATE_AA64, |
| 809 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 4, |
| 810 | .access = PL1_RW, .type = ARM_CP_NO_RAW, |
| 811 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.icc_icsr_el1), |
| 812 | .resetvalue = 0, |
| 813 | }, |
| 814 | { .name = "ICC_IAFFIDR_EL1", .state = ARM_CP_STATE_AA64, |
| 815 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 5, |
| 816 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
| 817 | /* ICC_IAFFIDR_EL1 holds the IAFFID only, in its low bits */ |
| 818 | .fieldoffset = offsetof(CPUARMState, gicv5_iaffid), |
| 819 | /* |
| 820 | * The field is a constant value set in gicv5_set_gicv5state(), |
| 821 | * so don't allow it to be overwritten by reset. |
| 822 | */ |
| 823 | .resetfn = arm_cp_reset_ignore, |
| 824 | }, |
| 825 | { .name = "ICC_PPI_CACTIVER0_EL1", .state = ARM_CP_STATE_AA64, |
| 826 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 0, |
| 827 | .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
| 828 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[0]), |
| 829 | .writefn = gic_ppi_cactive_write, |
| 830 | }, |
| 831 | { .name = "ICC_PPI_CACTIVER1_EL1", .state = ARM_CP_STATE_AA64, |
| 832 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 1, |
| 833 | .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
| 834 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]), |
| 835 | .writefn = gic_ppi_cactive_write, |
| 836 | }, |
| 837 | { .name = "ICC_PPI_SACTIVER0_EL1", .state = ARM_CP_STATE_AA64, |
| 838 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 2, |
| 839 | .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 840 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[0]), |
| 841 | .writefn = gic_ppi_sactive_write, |
| 842 | }, |
| 843 | { .name = "ICC_PPI_SACTIVER1_EL1", .state = ARM_CP_STATE_AA64, |
| 844 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 3, |
| 845 | .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 846 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]), |
| 847 | .writefn = gic_ppi_sactive_write, |
| 848 | }, |
| 849 | { .name = "ICC_PPI_HMR0_EL1", .state = ARM_CP_STATE_AA64, |
| 850 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 0, |
| 851 | .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 852 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[0]), |
| 853 | .resetvalue = PPI_HMR0_RESET, |
| 854 | }, |
| 855 | { .name = "ICC_PPI_HMR1_EL1", .state = ARM_CP_STATE_AA64, |
| 856 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 1, |
| 857 | .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 858 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]), |
| 859 | .resetvalue = PPI_HMR1_RESET, |
| 860 | }, |
| 861 | { .name = "ICC_HPPIR_EL1", .state = ARM_CP_STATE_AA64, |
| 862 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 3, |
| 863 | .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 864 | .readfn = gic_icc_hppir_el1_read, |
| 865 | }, |
| 866 | { .name = "ICC_PPI_ENABLER0_EL1", .state = ARM_CP_STATE_AA64, |
| 867 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 6, |
| 868 | .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 869 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_enable[0]), |
| 870 | .writefn = gic_ppi_enable_write, |
| 871 | }, |
| 872 | { .name = "ICC_PPI_ENABLER1_EL1", .state = ARM_CP_STATE_AA64, |
| 873 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 7, |
| 874 | .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 875 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_enable[1]), |
| 876 | .writefn = gic_ppi_enable_write, |
| 877 | }, |
| 878 | { .name = "ICC_PPI_CPENDR0_EL1", .state = ARM_CP_STATE_AA64, |
| 879 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 4, |
| 880 | .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
| 881 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[0]), |
| 882 | .writefn = gic_ppi_cpend_write, |
| 883 | }, |
| 884 | { .name = "ICC_PPI_CPENDR1_EL1", .state = ARM_CP_STATE_AA64, |
| 885 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 5, |
| 886 | .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
| 887 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]), |
| 888 | .writefn = gic_ppi_cpend_write, |
| 889 | }, |
| 890 | { .name = "ICC_PPI_SPENDR0_EL1", .state = ARM_CP_STATE_AA64, |
| 891 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 6, |
| 892 | .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 893 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[0]), |
| 894 | .writefn = gic_ppi_spend_write, |
| 895 | }, |
| 896 | { .name = "ICC_PPI_SPENDR0_EL1", .state = ARM_CP_STATE_AA64, |
| 897 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 7, |
| 898 | .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 899 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]), |
| 900 | .writefn = gic_ppi_spend_write, |
| 901 | }, |
| 902 | { .name = "ICC_APR_EL1", .state = ARM_CP_STATE_AA64, |
| 903 | .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 0, |
| 904 | .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 905 | .readfn = gic_icc_apr_el1_read, |
| 906 | .writefn = gic_icc_apr_el1_write, |
| 907 | .resetfn = gic_icc_apr_el1_reset, |
| 908 | }, |
| 909 | { .name = "ICC_CR0_EL1", .state = ARM_CP_STATE_AA64, |
| 910 | .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 1, |
| 911 | .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 912 | .readfn = gic_icc_cr0_el1_read, |
| 913 | .writefn = gic_icc_cr0_el1_write, |
| 914 | .resetfn = gic_icc_cr0_el1_reset, |
| 915 | }, |
| 916 | { .name = "ICC_PCR_EL1", .state = ARM_CP_STATE_AA64, |
| 917 | .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 2, |
| 918 | .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 919 | .readfn = gic_icc_pcr_el1_read, |
| 920 | .writefn = gic_icc_pcr_el1_write, |
| 921 | .resetfn = gic_icc_pcr_el1_reset, |
| 922 | }, |
| 923 | }; |
| 924 | |
| 925 | void define_gicv5_cpuif_regs(ARMCPU *cpu) |
| 926 | { |
| 927 | if (cpu_isar_feature(aa64_gcie, cpu)) { |
| 928 | define_arm_cp_regs(cpu, gicv5_cpuif_reginfo); |
| 929 | |
| 930 | /* |
| 931 | * There are 16 ICC_PPI_PRIORITYR<n>_EL1 regs, so define them |
| 932 | * programmatically rather than listing them all statically. |
| 933 | */ |
| 934 | for (int i = 0; i < 16; i++) { |
| 935 | g_autofree char *name = g_strdup_printf("ICC_PPI_PRIORITYR%d_EL1", i); |
| 936 | ARMCPRegInfo ppi_prio = { |
| 937 | .name = name, .state = ARM_CP_STATE_AA64, |
| 938 | .opc0 = 3, .opc1 = 0, .crn = 12, |
| 939 | .crm = 14 + (i >> 3), .opc2 = i & 7, |
| 940 | .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, |
| 941 | .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_priority[i]), |
| 942 | .writefn = gic_ppi_priority_write, .raw_writefn = raw_write, |
| 943 | }; |
| 944 | define_one_arm_cp_reg(cpu, &ppi_prio); |
| 945 | } |
| 946 | } |
| 947 | } |