| 1 | /* |
| 2 | * ARM v8.5-MemTag Operations |
| 3 | * |
| 4 | * Copyright (c) 2020 Linaro, Ltd. |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "qemu/log.h" |
| 22 | #include "cpu.h" |
| 23 | #include "helper.h" |
| 24 | #include "internals.h" |
| 25 | #include "exec/target_page.h" |
| 26 | #include "exec/page-protection.h" |
| 27 | #ifdef CONFIG_USER_ONLY |
| 28 | #include "user/cpu_loop.h" |
| 29 | #include "user/page-protection.h" |
| 30 | #else |
| 31 | #include "system/physmem.h" |
| 32 | #endif |
| 33 | #include "accel/tcg/cpu-ldst.h" |
| 34 | #include "accel/tcg/probe.h" |
| 35 | #include "helper-a64.h" |
| 36 | #include "exec/tlb-flags.h" |
| 37 | #include "accel/tcg/cpu-ops.h" |
| 38 | #include "qapi/error.h" |
| 39 | #include "qemu/guest-random.h" |
| 40 | #include "mte_helper.h" |
| 41 | |
| 42 | static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) |
| 43 | { |
| 44 | if (exclude == 0xffff) { |
| 45 | return 0; |
| 46 | } |
| 47 | if (offset == 0) { |
| 48 | while (exclude & (1 << tag)) { |
| 49 | tag = (tag + 1) & 15; |
| 50 | } |
| 51 | } else { |
| 52 | do { |
| 53 | do { |
| 54 | tag = (tag + 1) & 15; |
| 55 | } while (exclude & (1 << tag)); |
| 56 | } while (--offset > 0); |
| 57 | } |
| 58 | return tag; |
| 59 | } |
| 60 | |
| 61 | #ifndef CONFIG_USER_ONLY |
| 62 | /* |
| 63 | * Constructs S2 Permission Fault as described in ARM ARM "Stage 2 Memory |
| 64 | * Tagging Attributes". |
| 65 | */ |
| 66 | static void mte_perm_check_fail(CPUARMState *env, uint64_t dirty_ptr, |
| 67 | uintptr_t ra, bool is_write) |
| 68 | { |
| 69 | uint64_t syn; |
| 70 | |
| 71 | env->exception.vaddress = dirty_ptr; |
| 72 | |
| 73 | syn = syn_data_abort_no_iss(0, 0, 0, 0, 0, is_write, 0); |
| 74 | |
| 75 | syn |= BIT_ULL(41); /* TagAccess is bit 41 */ |
| 76 | |
| 77 | raise_exception_ra(env, EXCP_DATA_ABORT, syn, 2, ra); |
| 78 | g_assert_not_reached(); |
| 79 | } |
| 80 | #endif |
| 81 | |
| 82 | uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx, |
| 83 | uint64_t ptr, MMUAccessType ptr_access, |
| 84 | int ptr_size, MMUAccessType tag_access, |
| 85 | bool probe, uintptr_t ra) |
| 86 | { |
| 87 | #ifdef CONFIG_USER_ONLY |
| 88 | const size_t page_data_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); |
| 89 | uint64_t clean_ptr = useronly_clean_ptr(ptr); |
| 90 | int flags = page_get_flags(clean_ptr); |
| 91 | uint8_t *tags; |
| 92 | uintptr_t index; |
| 93 | |
| 94 | assert(!(probe && ra)); |
| 95 | |
| 96 | if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) { |
| 97 | if (probe) { |
| 98 | return NULL; |
| 99 | } |
| 100 | cpu_loop_exit_sigsegv(env_cpu(env), ptr, ptr_access, |
| 101 | !(flags & PAGE_VALID), ra); |
| 102 | } |
| 103 | |
| 104 | /* Require both MAP_ANON and PROT_MTE for the page. */ |
| 105 | if (!(flags & PAGE_ANON) || !(flags & PAGE_MTE)) { |
| 106 | return NULL; |
| 107 | } |
| 108 | |
| 109 | tags = page_get_target_data(clean_ptr, page_data_size); |
| 110 | |
| 111 | index = extract32(ptr, LOG2_TAG_GRANULE + 1, |
| 112 | TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); |
| 113 | return tags + index; |
| 114 | #else |
| 115 | CPUTLBEntryFull *full; |
| 116 | MemTxAttrs attrs; |
| 117 | int in_page, flags; |
| 118 | hwaddr ptr_paddr, tag_paddr, xlat; |
| 119 | MemoryRegion *mr; |
| 120 | ARMASIdx tag_asi; |
| 121 | AddressSpace *tag_as; |
| 122 | void *host; |
| 123 | |
| 124 | /* |
| 125 | * Probe the first byte of the virtual address. This raises an |
| 126 | * exception for inaccessible pages, and resolves the virtual address |
| 127 | * into the softmmu tlb. |
| 128 | * |
| 129 | * When RA == 0, this is either a pure probe or a no-fault-expected probe. |
| 130 | * Indicate to probe_access_flags no-fault, then either return NULL |
| 131 | * for the pure probe, or assert that we received a valid page for the |
| 132 | * no-fault-expected probe. |
| 133 | */ |
| 134 | flags = probe_access_full(env, ptr, 0, ptr_access, ptr_mmu_idx, |
| 135 | ra == 0, &host, &full, ra); |
| 136 | if (probe && (flags & TLB_INVALID_MASK)) { |
| 137 | return NULL; |
| 138 | } |
| 139 | assert(!(flags & TLB_INVALID_MASK)); |
| 140 | |
| 141 | switch (full->extra.arm.pte_attrs) { |
| 142 | case 0xf0: /* Tagged */ |
| 143 | break; |
| 144 | |
| 145 | case 0xe0: /* NoTagAccess */ |
| 146 | if (cpu_isar_feature(aa64_mteperm, env_archcpu(env))) { |
| 147 | if (probe) { |
| 148 | return NULL; |
| 149 | } |
| 150 | assert(ra); |
| 151 | mte_perm_check_fail(env, ptr, ra, tag_access == MMU_DATA_STORE); |
| 152 | } |
| 153 | /* fall through */ |
| 154 | |
| 155 | default: /* Not Tagged */ |
| 156 | return NULL; |
| 157 | } |
| 158 | |
| 159 | /* |
| 160 | * If not backed by host ram, there is no tag storage: access unchecked. |
| 161 | * This is probably a guest os bug though, so log it. |
| 162 | */ |
| 163 | if (unlikely(flags & TLB_MMIO)) { |
| 164 | qemu_log_mask(LOG_GUEST_ERROR, |
| 165 | "Page @ 0x%" PRIx64 " indicates Tagged Normal memory " |
| 166 | "but is not backed by host ram\n", ptr); |
| 167 | return NULL; |
| 168 | } |
| 169 | |
| 170 | /* |
| 171 | * Remember these values across the second lookup below, |
| 172 | * which may invalidate this pointer via tlb resize. |
| 173 | */ |
| 174 | ptr_paddr = full->phys_addr | (ptr & ~TARGET_PAGE_MASK); |
| 175 | attrs = full->attrs; |
| 176 | full = NULL; |
| 177 | |
| 178 | /* |
| 179 | * The Normal memory access can extend to the next page. E.g. a single |
| 180 | * 8-byte access to the last byte of a page will check only the last |
| 181 | * tag on the first page. |
| 182 | * Any page access exception has priority over tag check exception. |
| 183 | */ |
| 184 | in_page = -(ptr | TARGET_PAGE_MASK); |
| 185 | if (unlikely(ptr_size > in_page)) { |
| 186 | flags |= probe_access_full(env, ptr + in_page, 0, ptr_access, |
| 187 | ptr_mmu_idx, ra == 0, &host, &full, ra); |
| 188 | assert(!(flags & TLB_INVALID_MASK)); |
| 189 | } |
| 190 | |
| 191 | /* Any debug exception has priority over a tag check exception. */ |
| 192 | if (!probe && unlikely(flags & TLB_WATCHPOINT)) { |
| 193 | int wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_WRITE; |
| 194 | assert(ra != 0); |
| 195 | cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, attrs, wp, ra); |
| 196 | } |
| 197 | |
| 198 | /* Convert to the physical address in tag space. */ |
| 199 | tag_paddr = ptr_paddr >> (LOG2_TAG_GRANULE + 1); |
| 200 | |
| 201 | /* Look up the address in tag space. */ |
| 202 | tag_asi = attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; |
| 203 | tag_as = cpu_get_address_space(env_cpu(env), tag_asi); |
| 204 | mr = address_space_translate(tag_as, tag_paddr, &xlat, NULL, |
| 205 | tag_access == MMU_DATA_STORE, attrs); |
| 206 | |
| 207 | /* |
| 208 | * Note that @mr will never be NULL. If there is nothing in the address |
| 209 | * space at @tag_paddr, the translation will return the unallocated memory |
| 210 | * region. For our purposes, the result must be ram. |
| 211 | */ |
| 212 | if (unlikely(!memory_region_is_ram(mr))) { |
| 213 | /* ??? Failure is a board configuration error. */ |
| 214 | qemu_log_mask(LOG_UNIMP, |
| 215 | "Tag Memory @ 0x%" HWADDR_PRIx " not found for " |
| 216 | "Normal Memory @ 0x%" HWADDR_PRIx "\n", |
| 217 | tag_paddr, ptr_paddr); |
| 218 | return NULL; |
| 219 | } |
| 220 | |
| 221 | /* |
| 222 | * Ensure the tag memory is dirty on write, for migration. |
| 223 | * Tag memory can never contain code or display memory (vga). |
| 224 | */ |
| 225 | if (tag_access == MMU_DATA_STORE) { |
| 226 | ram_addr_t tag_ra = memory_region_get_ram_addr(mr) + xlat; |
| 227 | physical_memory_set_dirty_flag(tag_ra, DIRTY_MEMORY_MIGRATION); |
| 228 | } |
| 229 | |
| 230 | return memory_region_get_ram_ptr(mr) + xlat; |
| 231 | #endif |
| 232 | } |
| 233 | |
| 234 | static G_NORETURN void canonical_tag_write_fail(CPUARMState *env, |
| 235 | uint64_t dirty_ptr, uintptr_t ra) |
| 236 | { |
| 237 | uint64_t syn; |
| 238 | |
| 239 | env->exception.vaddress = dirty_ptr; |
| 240 | |
| 241 | syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0, 1, 0); |
| 242 | syn |= BIT_ULL(42); /* TnD is bit 42 */ |
| 243 | |
| 244 | raise_exception_ra(env, EXCP_DATA_ABORT, syn, exception_target_el(env), ra); |
| 245 | } |
| 246 | |
| 247 | static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, |
| 248 | uint64_t ptr, MMUAccessType ptr_access, |
| 249 | int ptr_size, MMUAccessType tag_access, |
| 250 | uintptr_t ra) |
| 251 | { |
| 252 | return allocation_tag_mem_probe(env, ptr_mmu_idx, ptr, ptr_access, |
| 253 | ptr_size, tag_access, false, ra); |
| 254 | } |
| 255 | |
| 256 | uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) |
| 257 | { |
| 258 | uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16); |
| 259 | int rrnd = extract32(env->cp15.gcr_el1, 16, 1); |
| 260 | int start = extract32(env->cp15.rgsr_el1, 0, 4); |
| 261 | int seed = extract32(env->cp15.rgsr_el1, 8, 16); |
| 262 | int offset, i, rtag; |
| 263 | |
| 264 | /* |
| 265 | * Our IMPDEF choice for GCR_EL1.RRND==1 is to continue to use the |
| 266 | * deterministic algorithm. Except that with RRND==1 the kernel is |
| 267 | * not required to have set RGSR_EL1.SEED != 0, which is required for |
| 268 | * the deterministic algorithm to function. So we force a non-zero |
| 269 | * SEED for that case. |
| 270 | */ |
| 271 | if (unlikely(seed == 0) && rrnd) { |
| 272 | do { |
| 273 | Error *err = NULL; |
| 274 | uint16_t two; |
| 275 | |
| 276 | if (qemu_guest_getrandom(&two, sizeof(two), &err) < 0) { |
| 277 | /* |
| 278 | * Failed, for unknown reasons in the crypto subsystem. |
| 279 | * Best we can do is log the reason and use a constant seed. |
| 280 | */ |
| 281 | qemu_log_mask(LOG_UNIMP, "IRG: Crypto failure: %s\n", |
| 282 | error_get_pretty(err)); |
| 283 | error_free(err); |
| 284 | two = 1; |
| 285 | } |
| 286 | seed = two; |
| 287 | } while (seed == 0); |
| 288 | } |
| 289 | |
| 290 | /* RandomTag */ |
| 291 | for (i = offset = 0; i < 4; ++i) { |
| 292 | /* NextRandomTagBit */ |
| 293 | int top = (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^ |
| 294 | extract32(seed, 2, 1) ^ extract32(seed, 0, 1)); |
| 295 | seed = (top << 15) | (seed >> 1); |
| 296 | offset |= top << i; |
| 297 | } |
| 298 | rtag = choose_nonexcluded_tag(start, offset, exclude); |
| 299 | env->cp15.rgsr_el1 = rtag | (seed << 8); |
| 300 | |
| 301 | return address_with_allocation_tag(rn, rtag); |
| 302 | } |
| 303 | |
| 304 | uint64_t HELPER(addsubg)(CPUARMState *env, uint64_t ptr, |
| 305 | int32_t offset, uint32_t tag_offset) |
| 306 | { |
| 307 | int start_tag = allocation_tag_from_addr(ptr); |
| 308 | uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16); |
| 309 | int rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude); |
| 310 | |
| 311 | return address_with_allocation_tag(ptr + offset, rtag); |
| 312 | } |
| 313 | |
| 314 | int load_tag1(uint64_t ptr, uint8_t *mem) |
| 315 | { |
| 316 | int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; |
| 317 | return extract32(*mem, ofs, 4); |
| 318 | } |
| 319 | |
| 320 | /* Like mtx_check, but simple mtx bit pair instead of MTEDESC. */ |
| 321 | static bool raw_mtx_check(unsigned mtx, unsigned bit55) |
| 322 | { |
| 323 | return (mtx >> bit55) & 1; |
| 324 | } |
| 325 | |
| 326 | uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt, uint32_t mtx) |
| 327 | { |
| 328 | int mmu_idx = arm_env_mmu_index(env); |
| 329 | uint8_t *mem; |
| 330 | int rtag = 0; |
| 331 | |
| 332 | /* Trap if accessing an invalid page. */ |
| 333 | mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, 1, |
| 334 | MMU_DATA_LOAD, GETPC()); |
| 335 | |
| 336 | /* Load if page supports tags. */ |
| 337 | if (mem) { |
| 338 | rtag = load_tag1(ptr, mem); |
| 339 | } else { |
| 340 | bool bit55 = extract64(ptr, 55, 1); |
| 341 | if (raw_mtx_check(mtx, bit55)) { |
| 342 | rtag = 0xF * bit55; |
| 343 | } |
| 344 | } |
| 345 | |
| 346 | return address_with_allocation_tag(xt, rtag); |
| 347 | } |
| 348 | |
| 349 | static void check_tag_aligned(CPUARMState *env, uint64_t ptr, uintptr_t ra) |
| 350 | { |
| 351 | if (unlikely(!QEMU_IS_ALIGNED(ptr, TAG_GRANULE))) { |
| 352 | arm_cpu_do_unaligned_access(env_cpu(env), ptr, MMU_DATA_STORE, |
| 353 | arm_env_mmu_index(env), ra); |
| 354 | g_assert_not_reached(); |
| 355 | } |
| 356 | } |
| 357 | |
| 358 | /* For use in a non-parallel context, store to the given nibble. */ |
| 359 | void store_tag1(uint64_t ptr, uint8_t *mem, int tag) |
| 360 | { |
| 361 | int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; |
| 362 | *mem = deposit32(*mem, ofs, 4, tag); |
| 363 | } |
| 364 | |
| 365 | /* For use in a parallel context, atomically store to the given nibble. */ |
| 366 | static void store_tag1_parallel(uint64_t ptr, uint8_t *mem, int tag) |
| 367 | { |
| 368 | int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; |
| 369 | uint8_t old = qatomic_read(mem); |
| 370 | |
| 371 | while (1) { |
| 372 | uint8_t new = deposit32(old, ofs, 4, tag); |
| 373 | uint8_t cmp = qatomic_cmpxchg(mem, old, new); |
| 374 | if (likely(cmp == old)) { |
| 375 | return; |
| 376 | } |
| 377 | old = cmp; |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | typedef void stg_store1(uint64_t, uint8_t *, int); |
| 382 | |
| 383 | static inline void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt, |
| 384 | uint32_t mtx, uintptr_t ra, stg_store1 store1) |
| 385 | { |
| 386 | int mmu_idx = arm_env_mmu_index(env); |
| 387 | uint8_t *mem; |
| 388 | |
| 389 | check_tag_aligned(env, ptr, ra); |
| 390 | |
| 391 | /* Trap if accessing an invalid page. */ |
| 392 | mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, TAG_GRANULE, |
| 393 | MMU_DATA_STORE, ra); |
| 394 | |
| 395 | /* Store if page supports tags. */ |
| 396 | if (mem) { |
| 397 | store1(ptr, mem, allocation_tag_from_addr(xt)); |
| 398 | } else if (raw_mtx_check(mtx, extract64(ptr, 55, 1))) { |
| 399 | canonical_tag_write_fail(env, ptr, ra); |
| 400 | } |
| 401 | } |
| 402 | |
| 403 | void HELPER(stg)(CPUARMState *env, uint64_t ptr, uint64_t xt, uint32_t mtx) |
| 404 | { |
| 405 | do_stg(env, ptr, xt, mtx, GETPC(), store_tag1); |
| 406 | } |
| 407 | |
| 408 | void HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt, |
| 409 | uint32_t mtx) |
| 410 | { |
| 411 | do_stg(env, ptr, xt, mtx, GETPC(), store_tag1_parallel); |
| 412 | } |
| 413 | |
| 414 | void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr) |
| 415 | { |
| 416 | int mmu_idx = arm_env_mmu_index(env); |
| 417 | uintptr_t ra = GETPC(); |
| 418 | |
| 419 | check_tag_aligned(env, ptr, ra); |
| 420 | probe_write(env, ptr, TAG_GRANULE, mmu_idx, ra); |
| 421 | } |
| 422 | |
| 423 | static inline void do_st2g(CPUARMState *env, uint64_t ptr, uint64_t xt, |
| 424 | uint32_t mtx, uintptr_t ra, stg_store1 store1) |
| 425 | { |
| 426 | int mmu_idx = arm_env_mmu_index(env); |
| 427 | int tag = allocation_tag_from_addr(xt); |
| 428 | uint8_t *mem1, *mem2; |
| 429 | |
| 430 | check_tag_aligned(env, ptr, ra); |
| 431 | mtx = raw_mtx_check(mtx, extract64(ptr, 55, 1)); |
| 432 | |
| 433 | /* |
| 434 | * Trap if accessing an invalid page(s). |
| 435 | * This takes priority over !allocation_tag_access_enabled. |
| 436 | */ |
| 437 | if (ptr & TAG_GRANULE) { |
| 438 | /* Two stores unaligned mod TAG_GRANULE*2 -- modify two bytes. */ |
| 439 | mem1 = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, |
| 440 | TAG_GRANULE, MMU_DATA_STORE, ra); |
| 441 | mem2 = allocation_tag_mem(env, mmu_idx, ptr + TAG_GRANULE, |
| 442 | MMU_DATA_STORE, TAG_GRANULE, |
| 443 | MMU_DATA_STORE, ra); |
| 444 | |
| 445 | /* Store if page(s) support tags. */ |
| 446 | if (mem1) { |
| 447 | store1(TAG_GRANULE, mem1, tag); |
| 448 | } else if (mtx) { |
| 449 | canonical_tag_write_fail(env, ptr, ra); |
| 450 | } |
| 451 | if (mem2) { |
| 452 | store1(0, mem2, tag); |
| 453 | } else if (mtx) { |
| 454 | canonical_tag_write_fail(env, ptr + TAG_GRANULE, ra); |
| 455 | } |
| 456 | } else { |
| 457 | /* Two stores aligned mod TAG_GRANULE*2 -- modify one byte. */ |
| 458 | mem1 = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, |
| 459 | 2 * TAG_GRANULE, MMU_DATA_STORE, ra); |
| 460 | if (mem1) { |
| 461 | tag |= tag << 4; |
| 462 | qatomic_set(mem1, tag); |
| 463 | } else if (mtx) { |
| 464 | /* Writing tags to canonically tagged memory region: faults */ |
| 465 | canonical_tag_write_fail(env, ptr, ra); |
| 466 | } |
| 467 | } |
| 468 | } |
| 469 | |
| 470 | void HELPER(st2g)(CPUARMState *env, uint64_t ptr, uint64_t xt, uint32_t mtx) |
| 471 | { |
| 472 | do_st2g(env, ptr, xt, mtx, GETPC(), store_tag1); |
| 473 | } |
| 474 | |
| 475 | void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt, |
| 476 | uint32_t mtx) |
| 477 | { |
| 478 | do_st2g(env, ptr, xt, mtx, GETPC(), store_tag1_parallel); |
| 479 | } |
| 480 | |
| 481 | void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) |
| 482 | { |
| 483 | int mmu_idx = arm_env_mmu_index(env); |
| 484 | uintptr_t ra = GETPC(); |
| 485 | int in_page = -(ptr | TARGET_PAGE_MASK); |
| 486 | |
| 487 | check_tag_aligned(env, ptr, ra); |
| 488 | |
| 489 | if (likely(in_page >= 2 * TAG_GRANULE)) { |
| 490 | probe_write(env, ptr, 2 * TAG_GRANULE, mmu_idx, ra); |
| 491 | } else { |
| 492 | probe_write(env, ptr, TAG_GRANULE, mmu_idx, ra); |
| 493 | probe_write(env, ptr + TAG_GRANULE, TAG_GRANULE, mmu_idx, ra); |
| 494 | } |
| 495 | } |
| 496 | |
| 497 | uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr, uint32_t mtx) |
| 498 | { |
| 499 | int mmu_idx = arm_env_mmu_index(env); |
| 500 | uintptr_t ra = GETPC(); |
| 501 | int gm_bs = env_archcpu(env)->gm_blocksize; |
| 502 | int gm_bs_bytes = 4 << gm_bs; |
| 503 | void *tag_mem; |
| 504 | uint64_t ret; |
| 505 | int shift; |
| 506 | |
| 507 | ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); |
| 508 | |
| 509 | /* Trap if accessing an invalid page. */ |
| 510 | tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, |
| 511 | gm_bs_bytes, MMU_DATA_LOAD, ra); |
| 512 | |
| 513 | /* The tag is squashed to zero if the page does not support tags. */ |
| 514 | if (!tag_mem) { |
| 515 | /* Load canonical value if mtx is set (untagged memory region) */ |
| 516 | bool bit55 = extract64(ptr, 55, 1); |
| 517 | if (raw_mtx_check(mtx, bit55)) { |
| 518 | ret = extract64(-bit55, 0, 1 << gm_bs); |
| 519 | shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; |
| 520 | return ret << shift; |
| 521 | } |
| 522 | return 0; |
| 523 | } |
| 524 | |
| 525 | /* |
| 526 | * The ordering of elements within the word corresponds to |
| 527 | * a little-endian operation. Computation of shift comes from |
| 528 | * |
| 529 | * index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE> |
| 530 | * data<index*4+3:index*4> = tag |
| 531 | * |
| 532 | * Because of the alignment of ptr above, BS=6 has shift=0. |
| 533 | * All memory operations are aligned. Defer support for BS=2, |
| 534 | * requiring insertion or extraction of a nibble, until we |
| 535 | * support a cpu that requires it. |
| 536 | */ |
| 537 | switch (gm_bs) { |
| 538 | case 3: |
| 539 | /* 32 bytes -> 2 tags -> 8 result bits */ |
| 540 | ret = *(uint8_t *)tag_mem; |
| 541 | break; |
| 542 | case 4: |
| 543 | /* 64 bytes -> 4 tags -> 16 result bits */ |
| 544 | ret = cpu_to_le16(*(uint16_t *)tag_mem); |
| 545 | break; |
| 546 | case 5: |
| 547 | /* 128 bytes -> 8 tags -> 32 result bits */ |
| 548 | ret = cpu_to_le32(*(uint32_t *)tag_mem); |
| 549 | break; |
| 550 | case 6: |
| 551 | /* 256 bytes -> 16 tags -> 64 result bits */ |
| 552 | return cpu_to_le64(*(uint64_t *)tag_mem); |
| 553 | default: |
| 554 | /* |
| 555 | * CPU configured with unsupported/invalid gm blocksize. |
| 556 | * This is detected early in arm_cpu_realizefn. |
| 557 | */ |
| 558 | g_assert_not_reached(); |
| 559 | } |
| 560 | shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; |
| 561 | return ret << shift; |
| 562 | } |
| 563 | |
| 564 | void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val, uint32_t mtx) |
| 565 | { |
| 566 | int mmu_idx = arm_env_mmu_index(env); |
| 567 | uintptr_t ra = GETPC(); |
| 568 | int gm_bs = env_archcpu(env)->gm_blocksize; |
| 569 | int gm_bs_bytes = 4 << gm_bs; |
| 570 | void *tag_mem; |
| 571 | int shift; |
| 572 | |
| 573 | ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); |
| 574 | |
| 575 | /* Trap if accessing an invalid page. */ |
| 576 | tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, |
| 577 | gm_bs_bytes, MMU_DATA_LOAD, ra); |
| 578 | |
| 579 | /* |
| 580 | * Tag store only happens if the page support tags, |
| 581 | * and if the OS has enabled access to the tags. |
| 582 | */ |
| 583 | if (!tag_mem) { |
| 584 | /* Storing tags to canonically tagged region: fault. */ |
| 585 | if (raw_mtx_check(mtx, extract64(ptr, 55, 1))) { |
| 586 | canonical_tag_write_fail(env, ptr, ra); |
| 587 | } |
| 588 | return; |
| 589 | } |
| 590 | |
| 591 | /* See LDGM for comments on BS and on shift. */ |
| 592 | shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; |
| 593 | val >>= shift; |
| 594 | switch (gm_bs) { |
| 595 | case 3: |
| 596 | /* 32 bytes -> 2 tags -> 8 result bits */ |
| 597 | *(uint8_t *)tag_mem = val; |
| 598 | break; |
| 599 | case 4: |
| 600 | /* 64 bytes -> 4 tags -> 16 result bits */ |
| 601 | *(uint16_t *)tag_mem = cpu_to_le16(val); |
| 602 | break; |
| 603 | case 5: |
| 604 | /* 128 bytes -> 8 tags -> 32 result bits */ |
| 605 | *(uint32_t *)tag_mem = cpu_to_le32(val); |
| 606 | break; |
| 607 | case 6: |
| 608 | /* 256 bytes -> 16 tags -> 64 result bits */ |
| 609 | *(uint64_t *)tag_mem = cpu_to_le64(val); |
| 610 | break; |
| 611 | default: |
| 612 | /* cpu configured with unsupported gm blocksize. */ |
| 613 | g_assert_not_reached(); |
| 614 | } |
| 615 | } |
| 616 | |
| 617 | void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val, |
| 618 | uint32_t mtx) |
| 619 | { |
| 620 | uintptr_t ra = GETPC(); |
| 621 | int mmu_idx = arm_env_mmu_index(env); |
| 622 | int log2_dcz_bytes, log2_tag_bytes; |
| 623 | intptr_t dcz_bytes, tag_bytes; |
| 624 | uint8_t *mem; |
| 625 | |
| 626 | /* |
| 627 | * In arm_cpu_realizefn, we assert that dcz > LOG2_TAG_GRANULE+1, |
| 628 | * i.e. 32 bytes, which is an unreasonably small dcz anyway, |
| 629 | * to make sure that we can access one complete tag byte here. |
| 630 | */ |
| 631 | log2_dcz_bytes = get_dczid_bs(env_archcpu(env)) + 2; |
| 632 | log2_tag_bytes = log2_dcz_bytes - (LOG2_TAG_GRANULE + 1); |
| 633 | dcz_bytes = (intptr_t)1 << log2_dcz_bytes; |
| 634 | tag_bytes = (intptr_t)1 << log2_tag_bytes; |
| 635 | ptr &= -dcz_bytes; |
| 636 | |
| 637 | mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, dcz_bytes, |
| 638 | MMU_DATA_STORE, ra); |
| 639 | if (mem) { |
| 640 | int tag_pair = (val & 0xf) * 0x11; |
| 641 | memset(mem, tag_pair, tag_bytes); |
| 642 | } else if (raw_mtx_check(mtx, extract64(ptr, 55, 1))) { |
| 643 | canonical_tag_write_fail(env, ptr, ra); |
| 644 | } |
| 645 | } |
| 646 | |
| 647 | static void mte_sync_check_fail(CPUARMState *env, uint32_t desc, |
| 648 | uint64_t dirty_ptr, uintptr_t ra) |
| 649 | { |
| 650 | int is_write, syn; |
| 651 | |
| 652 | env->exception.vaddress = dirty_ptr; |
| 653 | |
| 654 | is_write = FIELD_EX32(desc, MTEDESC, WRITE); |
| 655 | syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0, is_write, |
| 656 | 0x11); |
| 657 | raise_exception_ra(env, EXCP_DATA_ABORT, syn, exception_target_el(env), ra); |
| 658 | g_assert_not_reached(); |
| 659 | } |
| 660 | |
| 661 | static void mte_async_check_fail(CPUARMState *env, uint64_t dirty_ptr, |
| 662 | uintptr_t ra, ARMMMUIdx arm_mmu_idx, int el) |
| 663 | { |
| 664 | int select; |
| 665 | |
| 666 | if (regime_has_2_ranges(arm_mmu_idx)) { |
| 667 | select = extract64(dirty_ptr, 55, 1); |
| 668 | } else { |
| 669 | select = 0; |
| 670 | } |
| 671 | env->cp15.tfsr_el[el] |= 1 << select; |
| 672 | #ifdef CONFIG_USER_ONLY |
| 673 | /* |
| 674 | * Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT, |
| 675 | * which then sends a SIGSEGV when the thread is next scheduled. |
| 676 | * This cpu will return to the main loop at the end of the TB, |
| 677 | * which is rather sooner than "normal". But the alternative |
| 678 | * is waiting until the next syscall. |
| 679 | */ |
| 680 | cpu_exit(env_cpu(env)); |
| 681 | #endif |
| 682 | } |
| 683 | |
| 684 | /* Record a tag check failure. */ |
| 685 | void mte_check_fail(CPUARMState *env, uint32_t desc, |
| 686 | uint64_t dirty_ptr, uintptr_t ra) |
| 687 | { |
| 688 | int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); |
| 689 | ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx); |
| 690 | int el, reg_el, tcf; |
| 691 | uint64_t sctlr; |
| 692 | |
| 693 | reg_el = regime_el(arm_mmu_idx); |
| 694 | sctlr = env->cp15.sctlr_el[reg_el]; |
| 695 | |
| 696 | switch (arm_mmu_idx) { |
| 697 | case ARMMMUIdx_E10_0: |
| 698 | case ARMMMUIdx_E20_0: |
| 699 | el = 0; |
| 700 | tcf = extract64(sctlr, 38, 2); |
| 701 | break; |
| 702 | default: |
| 703 | el = reg_el; |
| 704 | tcf = extract64(sctlr, 40, 2); |
| 705 | } |
| 706 | |
| 707 | switch (tcf) { |
| 708 | case 1: |
| 709 | /* Tag check fail causes a synchronous exception. */ |
| 710 | mte_sync_check_fail(env, desc, dirty_ptr, ra); |
| 711 | break; |
| 712 | |
| 713 | case 0: |
| 714 | /* |
| 715 | * Tag check fail does not affect the PE. |
| 716 | * We eliminate this case by not setting MTE_ACTIVE |
| 717 | * in tb_flags, so that we never make this runtime call. |
| 718 | */ |
| 719 | g_assert_not_reached(); |
| 720 | |
| 721 | case 2: |
| 722 | /* Tag check fail causes asynchronous flag set. */ |
| 723 | mte_async_check_fail(env, dirty_ptr, ra, arm_mmu_idx, el); |
| 724 | break; |
| 725 | |
| 726 | case 3: |
| 727 | /* |
| 728 | * Tag check fail causes asynchronous flag set for stores, or |
| 729 | * a synchronous exception for loads. |
| 730 | */ |
| 731 | if (FIELD_EX32(desc, MTEDESC, WRITE)) { |
| 732 | mte_async_check_fail(env, dirty_ptr, ra, arm_mmu_idx, el); |
| 733 | } else { |
| 734 | mte_sync_check_fail(env, desc, dirty_ptr, ra); |
| 735 | } |
| 736 | break; |
| 737 | } |
| 738 | } |
| 739 | |
| 740 | /** |
| 741 | * checkN: |
| 742 | * @tag: tag memory to test |
| 743 | * @odd: true to begin testing at tags at odd nibble |
| 744 | * @cmp: the tag to compare against |
| 745 | * @count: number of tags to test |
| 746 | * |
| 747 | * Return the number of successful tests. |
| 748 | * Thus a return value < @count indicates a failure. |
| 749 | * |
| 750 | * A note about sizes: count is expected to be small. |
| 751 | * |
| 752 | * The most common use will be LDP/STP of two integer registers, |
| 753 | * which means 16 bytes of memory touching at most 2 tags, but |
| 754 | * often the access is aligned and thus just 1 tag. |
| 755 | * |
| 756 | * Using AdvSIMD LD/ST (multiple), one can access 64 bytes of memory, |
| 757 | * touching at most 5 tags. SVE LDR/STR (vector) with the default |
| 758 | * vector length is also 64 bytes; the maximum architectural length |
| 759 | * is 256 bytes touching at most 9 tags. |
| 760 | * |
| 761 | * The loop below uses 7 logical operations and 1 memory operation |
| 762 | * per tag pair. An implementation that loads an aligned word and |
| 763 | * uses masking to ignore adjacent tags requires 18 logical operations |
| 764 | * and thus does not begin to pay off until 6 tags. |
| 765 | * Which, according to the survey above, is unlikely to be common. |
| 766 | */ |
| 767 | static int checkN(uint8_t *mem, int odd, int cmp, int count) |
| 768 | { |
| 769 | int n = 0, diff; |
| 770 | |
| 771 | /* Replicate the test tag and compare. */ |
| 772 | cmp *= 0x11; |
| 773 | diff = *mem++ ^ cmp; |
| 774 | |
| 775 | if (odd) { |
| 776 | goto start_odd; |
| 777 | } |
| 778 | |
| 779 | while (1) { |
| 780 | /* Test even tag. */ |
| 781 | if (unlikely((diff) & 0x0f)) { |
| 782 | break; |
| 783 | } |
| 784 | if (++n == count) { |
| 785 | break; |
| 786 | } |
| 787 | |
| 788 | start_odd: |
| 789 | /* Test odd tag. */ |
| 790 | if (unlikely((diff) & 0xf0)) { |
| 791 | break; |
| 792 | } |
| 793 | if (++n == count) { |
| 794 | break; |
| 795 | } |
| 796 | |
| 797 | diff = *mem++ ^ cmp; |
| 798 | } |
| 799 | return n; |
| 800 | } |
| 801 | |
| 802 | /** |
| 803 | * checkNrev: |
| 804 | * @tag: tag memory to test |
| 805 | * @odd: true to begin testing at tags at odd nibble |
| 806 | * @cmp: the tag to compare against |
| 807 | * @count: number of tags to test |
| 808 | * |
| 809 | * Return the number of successful tests. |
| 810 | * Thus a return value < @count indicates a failure. |
| 811 | * |
| 812 | * This is like checkN, but it runs backwards, checking the |
| 813 | * tags starting with @tag and then the tags preceding it. |
| 814 | * This is needed by the backwards-memory-copying operations. |
| 815 | */ |
| 816 | static int checkNrev(uint8_t *mem, int odd, int cmp, int count) |
| 817 | { |
| 818 | int n = 0, diff; |
| 819 | |
| 820 | /* Replicate the test tag and compare. */ |
| 821 | cmp *= 0x11; |
| 822 | diff = *mem-- ^ cmp; |
| 823 | |
| 824 | if (!odd) { |
| 825 | goto start_even; |
| 826 | } |
| 827 | |
| 828 | while (1) { |
| 829 | /* Test odd tag. */ |
| 830 | if (unlikely((diff) & 0xf0)) { |
| 831 | break; |
| 832 | } |
| 833 | if (++n == count) { |
| 834 | break; |
| 835 | } |
| 836 | |
| 837 | start_even: |
| 838 | /* Test even tag. */ |
| 839 | if (unlikely((diff) & 0x0f)) { |
| 840 | break; |
| 841 | } |
| 842 | if (++n == count) { |
| 843 | break; |
| 844 | } |
| 845 | |
| 846 | diff = *mem-- ^ cmp; |
| 847 | } |
| 848 | return n; |
| 849 | } |
| 850 | |
| 851 | /** |
| 852 | * mte_probe_int() - helper for mte_probe and mte_check |
| 853 | * @env: CPU environment |
| 854 | * @desc: MTEDESC descriptor |
| 855 | * @ptr: virtual address of the base of the access |
| 856 | * @fault: return virtual address of the first check failure |
| 857 | * |
| 858 | * Internal routine for both mte_probe and mte_check. |
| 859 | * Return zero on failure, filling in *fault. |
| 860 | * Return negative on trivial success for tbi disabled. |
| 861 | * Return positive on success with tbi enabled. |
| 862 | */ |
| 863 | static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr, |
| 864 | uintptr_t ra, uint64_t *fault) |
| 865 | { |
| 866 | int mmu_idx, ptr_tag, bit55; |
| 867 | uint64_t ptr_last, prev_page, next_page; |
| 868 | uint64_t tag_first, tag_last; |
| 869 | uint32_t sizem1, tag_count, n, c; |
| 870 | uint8_t *mem1, *mem2; |
| 871 | MMUAccessType type; |
| 872 | |
| 873 | bit55 = extract64(ptr, 55, 1); |
| 874 | *fault = ptr; |
| 875 | |
| 876 | /* |
| 877 | * If TBI and MTX are disabled, the access is unchecked, and ptr is not |
| 878 | * dirty. |
| 879 | */ |
| 880 | if (unlikely(!tbi_or_mtx_check(desc, bit55))) { |
| 881 | return -1; |
| 882 | } |
| 883 | |
| 884 | ptr_tag = allocation_tag_from_addr(ptr); |
| 885 | |
| 886 | if (tcma_check(desc, bit55, ptr_tag)) { |
| 887 | return 1; |
| 888 | } |
| 889 | |
| 890 | mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); |
| 891 | type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD; |
| 892 | sizem1 = FIELD_EX32(desc, MTEDESC, SIZEM1); |
| 893 | |
| 894 | /* Find the addr of the end of the access */ |
| 895 | ptr_last = ptr + sizem1; |
| 896 | |
| 897 | /* Round the bounds to the tag granule, and compute the number of tags. */ |
| 898 | tag_first = QEMU_ALIGN_DOWN(ptr, TAG_GRANULE); |
| 899 | tag_last = QEMU_ALIGN_DOWN(ptr_last, TAG_GRANULE); |
| 900 | tag_count = ((tag_last - tag_first) / TAG_GRANULE) + 1; |
| 901 | |
| 902 | /* Locate the page boundaries. */ |
| 903 | prev_page = ptr & TARGET_PAGE_MASK; |
| 904 | next_page = prev_page + TARGET_PAGE_SIZE; |
| 905 | |
| 906 | if (likely(tag_last - prev_page < TARGET_PAGE_SIZE)) { |
| 907 | /* Memory access stays on one page. */ |
| 908 | mem1 = allocation_tag_mem(env, mmu_idx, ptr, type, sizem1 + 1, |
| 909 | MMU_DATA_LOAD, ra); |
| 910 | if (!mem1) { |
| 911 | /* |
| 912 | * If mtx is enabled, then the access is MemTag_CanonicallyTagged, |
| 913 | * otherwise it is Untagged. See AArch64.S1DecodeMemAttrs and |
| 914 | * AArch64.S1DisabledOutput. |
| 915 | */ |
| 916 | if (mtx_check(desc, bit55)) { |
| 917 | return tag_is_canonical(ptr_tag, bit55); |
| 918 | } |
| 919 | return 1; |
| 920 | } |
| 921 | /* Perform all of the comparisons. */ |
| 922 | n = checkN(mem1, ptr & TAG_GRANULE, ptr_tag, tag_count); |
| 923 | } else { |
| 924 | /* Memory access crosses to next page. */ |
| 925 | mem1 = allocation_tag_mem(env, mmu_idx, ptr, type, next_page - ptr, |
| 926 | MMU_DATA_LOAD, ra); |
| 927 | |
| 928 | mem2 = allocation_tag_mem(env, mmu_idx, next_page, type, |
| 929 | ptr_last - next_page + 1, |
| 930 | MMU_DATA_LOAD, ra); |
| 931 | |
| 932 | /* |
| 933 | * Perform all of the comparisons. |
| 934 | * Note the possible but unlikely case of the operation spanning two |
| 935 | * pages that do not both have allocation tagging enabled. This can |
| 936 | * happen with or without mtx (canonical tagging) enabled. |
| 937 | */ |
| 938 | n = c = (next_page - tag_first) / TAG_GRANULE; |
| 939 | if (mem1) { |
| 940 | n = checkN(mem1, ptr & TAG_GRANULE, ptr_tag, c); |
| 941 | } else if (mtx_check(desc, bit55) && |
| 942 | !tag_is_canonical(ptr_tag, bit55)) { |
| 943 | return 0; |
| 944 | } |
| 945 | if (n == c) { |
| 946 | if (mem2) { |
| 947 | n += checkN(mem2, 0, ptr_tag, tag_count - c); |
| 948 | } else if (!mtx_check(desc, bit55) || |
| 949 | tag_is_canonical(ptr_tag, bit55)) { |
| 950 | return 1; |
| 951 | } |
| 952 | } |
| 953 | } |
| 954 | |
| 955 | if (likely(n == tag_count)) { |
| 956 | return 1; |
| 957 | } |
| 958 | |
| 959 | /* |
| 960 | * If we failed, we know which granule. For the first granule, the |
| 961 | * failure address is @ptr, the first byte accessed. Otherwise the |
| 962 | * failure address is the first byte of the nth granule. |
| 963 | */ |
| 964 | if (n > 0) { |
| 965 | *fault = tag_first + n * TAG_GRANULE; |
| 966 | } |
| 967 | return 0; |
| 968 | } |
| 969 | |
| 970 | uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra) |
| 971 | { |
| 972 | uint64_t fault; |
| 973 | int ret = mte_probe_int(env, desc, ptr, ra, &fault); |
| 974 | |
| 975 | if (unlikely(ret == 0)) { |
| 976 | mte_check_fail(env, desc, fault, ra); |
| 977 | } else if (ret < 0) { |
| 978 | return ptr; |
| 979 | } |
| 980 | return useronly_clean_ptr(ptr); |
| 981 | } |
| 982 | |
| 983 | uint64_t HELPER(mte_check)(CPUARMState *env, uint32_t desc, uint64_t ptr) |
| 984 | { |
| 985 | /* |
| 986 | * R_XCHFJ: Alignment check not caused by memory type is priority 1, |
| 987 | * higher than any translation fault. When MTE is disabled, tcg |
| 988 | * performs the alignment check during the code generated for the |
| 989 | * memory access. With MTE enabled, we must check this here before |
| 990 | * raising any translation fault in allocation_tag_mem. |
| 991 | */ |
| 992 | unsigned align = FIELD_EX32(desc, MTEDESC, ALIGN); |
| 993 | if (unlikely(align)) { |
| 994 | align = (1u << align) - 1; |
| 995 | if (unlikely(ptr & align)) { |
| 996 | int idx = FIELD_EX32(desc, MTEDESC, MIDX); |
| 997 | bool w = FIELD_EX32(desc, MTEDESC, WRITE); |
| 998 | MMUAccessType type = w ? MMU_DATA_STORE : MMU_DATA_LOAD; |
| 999 | arm_cpu_do_unaligned_access(env_cpu(env), ptr, type, idx, GETPC()); |
| 1000 | } |
| 1001 | } |
| 1002 | |
| 1003 | return mte_check(env, desc, ptr, GETPC()); |
| 1004 | } |
| 1005 | |
| 1006 | /* |
| 1007 | * No-fault version of mte_check, to be used by SVE for MemSingleNF. |
| 1008 | * Returns false if the access is Checked and the check failed. This |
| 1009 | * is only intended to probe the tag -- the validity of the page must |
| 1010 | * be checked beforehand. |
| 1011 | */ |
| 1012 | bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr) |
| 1013 | { |
| 1014 | uint64_t fault; |
| 1015 | int ret = mte_probe_int(env, desc, ptr, 0, &fault); |
| 1016 | |
| 1017 | return ret != 0; |
| 1018 | } |
| 1019 | |
| 1020 | /* |
| 1021 | * Perform an MTE checked access for DC_ZVA. |
| 1022 | */ |
| 1023 | uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32_t desc, uint64_t ptr) |
| 1024 | { |
| 1025 | uintptr_t ra = GETPC(); |
| 1026 | int log2_dcz_bytes, log2_tag_bytes; |
| 1027 | int mmu_idx, bit55; |
| 1028 | intptr_t dcz_bytes, tag_bytes, i; |
| 1029 | void *mem; |
| 1030 | uint64_t ptr_tag, mem_tag, align_ptr; |
| 1031 | |
| 1032 | bit55 = extract64(ptr, 55, 1); |
| 1033 | |
| 1034 | /* If TBI is disabled, the access is unchecked, and ptr is not dirty. */ |
| 1035 | if (unlikely(!tbi_or_mtx_check(desc, bit55))) { |
| 1036 | return ptr; |
| 1037 | } |
| 1038 | |
| 1039 | ptr_tag = allocation_tag_from_addr(ptr); |
| 1040 | |
| 1041 | if (tcma_check(desc, bit55, ptr_tag)) { |
| 1042 | goto done; |
| 1043 | } |
| 1044 | |
| 1045 | /* |
| 1046 | * In arm_cpu_realizefn, we asserted that dcz > LOG2_TAG_GRANULE+1, |
| 1047 | * i.e. 32 bytes, which is an unreasonably small dcz anyway, to make |
| 1048 | * sure that we can access one complete tag byte here. |
| 1049 | */ |
| 1050 | log2_dcz_bytes = get_dczid_bs(env_archcpu(env)) + 2; |
| 1051 | log2_tag_bytes = log2_dcz_bytes - (LOG2_TAG_GRANULE + 1); |
| 1052 | dcz_bytes = (intptr_t)1 << log2_dcz_bytes; |
| 1053 | tag_bytes = (intptr_t)1 << log2_tag_bytes; |
| 1054 | align_ptr = ptr & -dcz_bytes; |
| 1055 | |
| 1056 | /* |
| 1057 | * Trap if accessing an invalid page. DC_ZVA requires that we supply |
| 1058 | * the original pointer for an invalid page. But watchpoints require |
| 1059 | * that we probe the actual space. So do both. |
| 1060 | */ |
| 1061 | mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); |
| 1062 | (void) probe_write(env, ptr, 1, mmu_idx, ra); |
| 1063 | mem = allocation_tag_mem(env, mmu_idx, align_ptr, MMU_DATA_STORE, |
| 1064 | dcz_bytes, MMU_DATA_LOAD, ra); |
| 1065 | if (!mem) { |
| 1066 | /* |
| 1067 | * If mtx is enabled, then the access is MemTag_CanonicallyTagged, |
| 1068 | * otherwise it is Untagged. See AArch64.S1DecodeMemAttrs and |
| 1069 | * AArch64.S1DisabledOutput. |
| 1070 | */ |
| 1071 | if (mtx_check(desc, bit55) && !tag_is_canonical(ptr_tag, bit55)) { |
| 1072 | mte_check_fail(env, desc, ptr, ra); |
| 1073 | } |
| 1074 | goto done; |
| 1075 | } |
| 1076 | |
| 1077 | /* |
| 1078 | * Unlike the reasoning for checkN, DC_ZVA is always aligned, and thus |
| 1079 | * it is quite easy to perform all of the comparisons at once without |
| 1080 | * any extra masking. |
| 1081 | * |
| 1082 | * The most common zva block size is 64; some of the thunderx cpus use |
| 1083 | * a block size of 128. For user-only, aarch64_max_initfn will set the |
| 1084 | * block size to 512. Fill out the other cases for future-proofing. |
| 1085 | * |
| 1086 | * In order to be able to find the first miscompare later, we want the |
| 1087 | * tag bytes to be in little-endian order. |
| 1088 | */ |
| 1089 | switch (log2_tag_bytes) { |
| 1090 | case 0: /* zva_blocksize 32 */ |
| 1091 | mem_tag = *(uint8_t *)mem; |
| 1092 | ptr_tag *= 0x11u; |
| 1093 | break; |
| 1094 | case 1: /* zva_blocksize 64 */ |
| 1095 | mem_tag = cpu_to_le16(*(uint16_t *)mem); |
| 1096 | ptr_tag *= 0x1111u; |
| 1097 | break; |
| 1098 | case 2: /* zva_blocksize 128 */ |
| 1099 | mem_tag = cpu_to_le32(*(uint32_t *)mem); |
| 1100 | ptr_tag *= 0x11111111u; |
| 1101 | break; |
| 1102 | case 3: /* zva_blocksize 256 */ |
| 1103 | mem_tag = cpu_to_le64(*(uint64_t *)mem); |
| 1104 | ptr_tag *= 0x1111111111111111ull; |
| 1105 | break; |
| 1106 | |
| 1107 | default: /* zva_blocksize 512, 1024, 2048 */ |
| 1108 | ptr_tag *= 0x1111111111111111ull; |
| 1109 | i = 0; |
| 1110 | do { |
| 1111 | mem_tag = cpu_to_le64(*(uint64_t *)(mem + i)); |
| 1112 | if (unlikely(mem_tag != ptr_tag)) { |
| 1113 | goto fail; |
| 1114 | } |
| 1115 | i += 8; |
| 1116 | align_ptr += 16 * TAG_GRANULE; |
| 1117 | } while (i < tag_bytes); |
| 1118 | goto done; |
| 1119 | } |
| 1120 | |
| 1121 | if (likely(mem_tag == ptr_tag)) { |
| 1122 | goto done; |
| 1123 | } |
| 1124 | |
| 1125 | fail: |
| 1126 | /* Locate the first nibble that differs. */ |
| 1127 | i = ctz64(mem_tag ^ ptr_tag) >> 4; |
| 1128 | mte_check_fail(env, desc, align_ptr + i * TAG_GRANULE, ra); |
| 1129 | |
| 1130 | done: |
| 1131 | return useronly_clean_ptr(ptr); |
| 1132 | } |
| 1133 | |
| 1134 | uint64_t mte_mops_probe(CPUARMState *env, uint64_t ptr, uint64_t size, |
| 1135 | uint32_t desc) |
| 1136 | { |
| 1137 | int mmu_idx, tag_count; |
| 1138 | uint64_t ptr_tag, tag_first, tag_last; |
| 1139 | void *mem; |
| 1140 | bool w = FIELD_EX32(desc, MTEDESC, WRITE); |
| 1141 | uint32_t n; |
| 1142 | |
| 1143 | mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); |
| 1144 | /* True probe; this will never fault */ |
| 1145 | mem = allocation_tag_mem_probe(env, mmu_idx, ptr, |
| 1146 | w ? MMU_DATA_STORE : MMU_DATA_LOAD, |
| 1147 | size, MMU_DATA_LOAD, true, 0); |
| 1148 | if (!mem) { |
| 1149 | return size; |
| 1150 | } |
| 1151 | |
| 1152 | /* |
| 1153 | * TODO: checkN() is not designed for checks of the size we expect |
| 1154 | * for FEAT_MOPS operations, so we should implement this differently. |
| 1155 | * Maybe we should do something like |
| 1156 | * if (region start and size are aligned nicely) { |
| 1157 | * do direct loads of 64 tag bits at a time; |
| 1158 | * } else { |
| 1159 | * call checkN() |
| 1160 | * } |
| 1161 | */ |
| 1162 | /* Round the bounds to the tag granule, and compute the number of tags. */ |
| 1163 | ptr_tag = allocation_tag_from_addr(ptr); |
| 1164 | tag_first = QEMU_ALIGN_DOWN(ptr, TAG_GRANULE); |
| 1165 | tag_last = QEMU_ALIGN_DOWN(ptr + size - 1, TAG_GRANULE); |
| 1166 | tag_count = ((tag_last - tag_first) / TAG_GRANULE) + 1; |
| 1167 | n = checkN(mem, ptr & TAG_GRANULE, ptr_tag, tag_count); |
| 1168 | if (likely(n == tag_count)) { |
| 1169 | return size; |
| 1170 | } |
| 1171 | |
| 1172 | /* |
| 1173 | * Failure; for the first granule, it's at @ptr. Otherwise |
| 1174 | * it's at the first byte of the nth granule. Calculate how |
| 1175 | * many bytes we can access without hitting that failure. |
| 1176 | */ |
| 1177 | if (n == 0) { |
| 1178 | return 0; |
| 1179 | } else { |
| 1180 | return n * TAG_GRANULE - (ptr - tag_first); |
| 1181 | } |
| 1182 | } |
| 1183 | |
| 1184 | uint64_t mte_mops_probe_rev(CPUARMState *env, uint64_t ptr, uint64_t size, |
| 1185 | uint32_t desc) |
| 1186 | { |
| 1187 | int mmu_idx, tag_count; |
| 1188 | uint64_t ptr_tag, tag_first, tag_last; |
| 1189 | void *mem; |
| 1190 | bool w = FIELD_EX32(desc, MTEDESC, WRITE); |
| 1191 | uint32_t n; |
| 1192 | |
| 1193 | mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); |
| 1194 | /* |
| 1195 | * True probe; this will never fault. Note that our caller passes |
| 1196 | * us a pointer to the end of the region, but allocation_tag_mem_probe() |
| 1197 | * wants a pointer to the start. Because we know we don't span a page |
| 1198 | * boundary and that allocation_tag_mem_probe() doesn't otherwise care |
| 1199 | * about the size, pass in a size of 1 byte. This is simpler than |
| 1200 | * adjusting the ptr to point to the start of the region and then having |
| 1201 | * to adjust the returned 'mem' to get the end of the tag memory. |
| 1202 | */ |
| 1203 | mem = allocation_tag_mem_probe(env, mmu_idx, ptr, |
| 1204 | w ? MMU_DATA_STORE : MMU_DATA_LOAD, |
| 1205 | 1, MMU_DATA_LOAD, true, 0); |
| 1206 | if (!mem) { |
| 1207 | return size; |
| 1208 | } |
| 1209 | |
| 1210 | /* |
| 1211 | * TODO: checkNrev() is not designed for checks of the size we expect |
| 1212 | * for FEAT_MOPS operations, so we should implement this differently. |
| 1213 | * Maybe we should do something like |
| 1214 | * if (region start and size are aligned nicely) { |
| 1215 | * do direct loads of 64 tag bits at a time; |
| 1216 | * } else { |
| 1217 | * call checkN() |
| 1218 | * } |
| 1219 | */ |
| 1220 | /* Round the bounds to the tag granule, and compute the number of tags. */ |
| 1221 | ptr_tag = allocation_tag_from_addr(ptr); |
| 1222 | tag_first = QEMU_ALIGN_DOWN(ptr - (size - 1), TAG_GRANULE); |
| 1223 | tag_last = QEMU_ALIGN_DOWN(ptr, TAG_GRANULE); |
| 1224 | tag_count = ((tag_last - tag_first) / TAG_GRANULE) + 1; |
| 1225 | n = checkNrev(mem, ptr & TAG_GRANULE, ptr_tag, tag_count); |
| 1226 | if (likely(n == tag_count)) { |
| 1227 | return size; |
| 1228 | } |
| 1229 | |
| 1230 | /* |
| 1231 | * Failure; for the first granule, it's at @ptr. Otherwise |
| 1232 | * it's at the last byte of the nth granule. Calculate how |
| 1233 | * many bytes we can access without hitting that failure. |
| 1234 | */ |
| 1235 | if (n == 0) { |
| 1236 | return 0; |
| 1237 | } else { |
| 1238 | return (n - 1) * TAG_GRANULE + ((ptr + 1) - tag_last); |
| 1239 | } |
| 1240 | } |
| 1241 | |
| 1242 | void mte_mops_set_tags(CPUARMState *env, uint64_t ptr, uint64_t size, |
| 1243 | uint32_t desc) |
| 1244 | { |
| 1245 | int mmu_idx, tag_count; |
| 1246 | uint64_t ptr_tag; |
| 1247 | void *mem; |
| 1248 | |
| 1249 | if (!desc) { |
| 1250 | /* Tags not actually enabled */ |
| 1251 | return; |
| 1252 | } |
| 1253 | |
| 1254 | mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); |
| 1255 | /* True probe: this will never fault */ |
| 1256 | mem = allocation_tag_mem_probe(env, mmu_idx, ptr, MMU_DATA_STORE, size, |
| 1257 | MMU_DATA_STORE, true, 0); |
| 1258 | if (!mem) { |
| 1259 | return; |
| 1260 | } |
| 1261 | |
| 1262 | /* |
| 1263 | * We know that ptr and size are both TAG_GRANULE aligned; store |
| 1264 | * the tag from the pointer value into the tag memory. |
| 1265 | */ |
| 1266 | ptr_tag = allocation_tag_from_addr(ptr); |
| 1267 | tag_count = size / TAG_GRANULE; |
| 1268 | if (ptr & TAG_GRANULE) { |
| 1269 | /* Not 2*TAG_GRANULE-aligned: store tag to first nibble */ |
| 1270 | store_tag1_parallel(TAG_GRANULE, mem, ptr_tag); |
| 1271 | mem++; |
| 1272 | tag_count--; |
| 1273 | } |
| 1274 | memset(mem, ptr_tag | (ptr_tag << 4), tag_count / 2); |
| 1275 | if (tag_count & 1) { |
| 1276 | /* Final trailing unaligned nibble */ |
| 1277 | mem += tag_count / 2; |
| 1278 | store_tag1_parallel(0, mem, ptr_tag); |
| 1279 | } |
| 1280 | } |