| 1 | # M-profile MVE instruction descriptions |
| 2 | # |
| 3 | # Copyright (c) 2021 Linaro, Ltd |
| 4 | # |
| 5 | # This library is free software; you can redistribute it and/or |
| 6 | # modify it under the terms of the GNU Lesser General Public |
| 7 | # License as published by the Free Software Foundation; either |
| 8 | # version 2.1 of the License, or (at your option) any later version. |
| 9 | # |
| 10 | # This library is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 13 | # Lesser General Public License for more details. |
| 14 | # |
| 15 | # You should have received a copy of the GNU Lesser General Public |
| 16 | # License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 17 | |
| 18 | # |
| 19 | # This file is processed by scripts/decodetree.py |
| 20 | # |
| 21 | |
| 22 | %qd 22:1 13:3 |
| 23 | %qm 5:1 1:3 |
| 24 | %qn 7:1 17:3 |
| 25 | |
| 26 | # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit |
| 27 | %size_28 28:1 !function=plus_1 |
| 28 | |
| 29 | # 2 operand fp insns have size in bit 20: 1 for 16 bit, 0 for 32 bit, |
| 30 | # like Neon FP insns. |
| 31 | %2op_fp_size 20:1 !function=neon_3same_fp_size |
| 32 | # VCADD is an exception, where bit 20 is 0 for 16 bit and 1 for 32 bit |
| 33 | %2op_fp_size_rev 20:1 !function=plus_1 |
| 34 | # FP scalars have size in bit 28, 1 for 16 bit, 0 for 32 bit |
| 35 | %2op_fp_scalar_size 28:1 !function=neon_3same_fp_size |
| 36 | |
| 37 | # 1imm format immediate |
| 38 | %imm_28_16_0 28:1 16:3 0:4 |
| 39 | |
| 40 | &vldr_vstr rn qd imm p a w size l u |
| 41 | &1op qd qm size |
| 42 | &2op qd qm qn size |
| 43 | &2scalar qd qn rm size |
| 44 | &1imm qd imm cmode op |
| 45 | &2shift qd qm shift size |
| 46 | &vidup qd rn size imm |
| 47 | &viwdup qd rn rm size imm |
| 48 | &vcmp qm qn size mask |
| 49 | &vcmp_scalar qn rm size mask |
| 50 | &shl_scalar qda rm size |
| 51 | &vmaxv qm rda size |
| 52 | &vabav qn qm rda size |
| 53 | &vldst_sg qd qm rn size msize os |
| 54 | &vldst_sg_imm qd qm a w imm |
| 55 | &vldst_il qd rn size pat w |
| 56 | |
| 57 | # scatter-gather memory size is in bits 6:4 |
| 58 | %sg_msize 6:1 4:1 |
| 59 | |
| 60 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 |
| 61 | # Note that both Rn and Qd are 3 bits only (no D bit) |
| 62 | @vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr |
| 63 | |
| 64 | @vldst_sg .... .... .... rn:4 .... ... size:2 ... ... os:1 &vldst_sg \ |
| 65 | qd=%qd qm=%qm msize=%sg_msize |
| 66 | |
| 67 | # Qm is in the fields usually labeled Qn |
| 68 | @vldst_sg_imm .... .... a:1 . w:1 . .... .... .... . imm:7 &vldst_sg_imm \ |
| 69 | qd=%qd qm=%qn |
| 70 | |
| 71 | # Deinterleaving load/interleaving store |
| 72 | @vldst_il .... .... .. w:1 . rn:4 .... ... size:2 pat:2 ..... &vldst_il \ |
| 73 | qd=%qd |
| 74 | |
| 75 | @1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm |
| 76 | @1op_nosz .... .... .... .... .... .... .... .... &1op qd=%qd qm=%qm size=0 |
| 77 | @2op .... .... .. size:2 .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn |
| 78 | @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0 |
| 79 | @2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \ |
| 80 | size=%size_28 |
| 81 | @1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0 |
| 82 | |
| 83 | # The _rev suffix indicates that Vn and Vm are reversed. This is |
| 84 | # the case for shifts. In the Arm ARM these insns are documented |
| 85 | # with the Vm and Vn fields in their usual places, but in the |
| 86 | # assembly the operands are listed "backwards", ie in the order |
| 87 | # Qd, Qm, Qn where other insns use Qd, Qn, Qm. For QEMU we choose |
| 88 | # to consider Vm and Vn as being in different fields in the insn. |
| 89 | # This gives us consistency with A64 and Neon. |
| 90 | @2op_rev .... .... .. size:2 .... .... .... .... .... &2op qd=%qd qm=%qn qn=%qm |
| 91 | |
| 92 | @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn |
| 93 | @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn |
| 94 | |
| 95 | @2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0 |
| 96 | @2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 |
| 97 | @2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 |
| 98 | |
| 99 | @2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0 |
| 100 | @2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 |
| 101 | # VSHLL encoding T2 where shift == esize |
| 102 | @2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \ |
| 103 | qd=%qd qm=%qm size=0 shift=8 |
| 104 | @2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \ |
| 105 | qd=%qd qm=%qm size=1 shift=16 |
| 106 | |
| 107 | # Right shifts are encoded as N - shift, where N is the element size in bits. |
| 108 | %rshift_i5 16:5 !function=rsub_32 |
| 109 | %rshift_i4 16:4 !function=rsub_16 |
| 110 | %rshift_i3 16:3 !function=rsub_8 |
| 111 | |
| 112 | @2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \ |
| 113 | size=0 shift=%rshift_i3 |
| 114 | @2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \ |
| 115 | size=1 shift=%rshift_i4 |
| 116 | @2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \ |
| 117 | size=2 shift=%rshift_i5 |
| 118 | |
| 119 | @shl_scalar .... .... .... size:2 .. .... .... .... rm:4 &shl_scalar qda=%qd |
| 120 | |
| 121 | # Vector comparison; 4-bit Qm but 3-bit Qn |
| 122 | %mask_22_13 22:1 13:3 |
| 123 | @vcmp .... .... .. size:2 qn:3 . .... .... .... .... &vcmp qm=%qm mask=%mask_22_13 |
| 124 | @vcmp_scalar .... .... .. size:2 qn:3 . .... .... .... rm:4 &vcmp_scalar \ |
| 125 | mask=%mask_22_13 |
| 126 | |
| 127 | @vcmp_fp .... .... .... qn:3 . .... .... .... .... &vcmp \ |
| 128 | qm=%qm size=%2op_fp_scalar_size mask=%mask_22_13 |
| 129 | |
| 130 | # Bit 28 is a 2op_fp_scalar_size bit, but we do not decode it in this |
| 131 | # format to avoid complicated overlapping-instruction-groups |
| 132 | @vcmp_fp_scalar .... .... .... qn:3 . .... .... .... rm:4 &vcmp_scalar \ |
| 133 | mask=%mask_22_13 |
| 134 | |
| 135 | @vmaxv .... .... .... size:2 .. rda:4 .... .... .... &vmaxv qm=%qm |
| 136 | |
| 137 | @2op_fp .... .... .... .... .... .... .... .... &2op \ |
| 138 | qd=%qd qn=%qn qm=%qm size=%2op_fp_size |
| 139 | |
| 140 | @2op_fp_size_rev .... .... .... .... .... .... .... .... &2op \ |
| 141 | qd=%qd qn=%qn qm=%qm size=%2op_fp_size_rev |
| 142 | |
| 143 | # 2-operand, but Qd and Qn share a field. Size is in bit 28, but we |
| 144 | # don't decode it in this format |
| 145 | @vmaxnma .... .... .... .... .... .... .... .... &2op \ |
| 146 | qd=%qd qn=%qd qm=%qm |
| 147 | |
| 148 | # Here also we don't decode the bit 28 size in the format to avoid |
| 149 | # awkward nested overlap groups |
| 150 | @vmaxnmv .... .... .... .... rda:4 .... .... .... &vmaxv qm=%qm |
| 151 | |
| 152 | @2op_fp_scalar .... .... .... .... .... .... .... rm:4 &2scalar \ |
| 153 | qd=%qd qn=%qn size=%2op_fp_scalar_size |
| 154 | |
| 155 | # Vector loads and stores |
| 156 | |
| 157 | # Widening loads and narrowing stores: |
| 158 | # for these P=0 W=0 is 'related encoding'; sz=11 is 'related encoding' |
| 159 | # This means we need to expand out to multiple patterns for P, W, SZ. |
| 160 | # For stores the U bit must be 0 but we catch that in the trans_ function. |
| 161 | # The naming scheme here is "VLDSTB_H == in-memory byte load/store to/from |
| 162 | # signed halfword element in register", etc. |
| 163 | VLDSTB_H 111 . 110 0 a:1 0 1 . 0 ... ... 0 111 01 ....... @vldst_wn \ |
| 164 | p=0 w=1 size=1 |
| 165 | VLDSTB_H 111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 01 ....... @vldst_wn \ |
| 166 | p=1 size=1 |
| 167 | VLDSTB_W 111 . 110 0 a:1 0 1 . 0 ... ... 0 111 10 ....... @vldst_wn \ |
| 168 | p=0 w=1 size=2 |
| 169 | VLDSTB_W 111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 10 ....... @vldst_wn \ |
| 170 | p=1 size=2 |
| 171 | VLDSTH_W 111 . 110 0 a:1 0 1 . 1 ... ... 0 111 10 ....... @vldst_wn \ |
| 172 | p=0 w=1 size=2 |
| 173 | VLDSTH_W 111 . 110 1 a:1 0 w:1 . 1 ... ... 0 111 10 ....... @vldst_wn \ |
| 174 | p=1 size=2 |
| 175 | |
| 176 | # Non-widening loads/stores (P=0 W=0 is 'related encoding') |
| 177 | VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111100 ....... @vldr_vstr \ |
| 178 | size=0 p=0 w=1 |
| 179 | VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111101 ....... @vldr_vstr \ |
| 180 | size=1 p=0 w=1 |
| 181 | VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111110 ....... @vldr_vstr \ |
| 182 | size=2 p=0 w=1 |
| 183 | VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111100 ....... @vldr_vstr \ |
| 184 | size=0 p=1 |
| 185 | VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101 ....... @vldr_vstr \ |
| 186 | size=1 p=1 |
| 187 | VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \ |
| 188 | size=2 p=1 |
| 189 | |
| 190 | # gather loads/scatter stores |
| 191 | VLDR_S_sg 111 0 1100 1 . 01 .... ... 0 111 . .... .... @vldst_sg |
| 192 | VLDR_U_sg 111 1 1100 1 . 01 .... ... 0 111 . .... .... @vldst_sg |
| 193 | VSTR_sg 111 0 1100 1 . 00 .... ... 0 111 . .... .... @vldst_sg |
| 194 | |
| 195 | VLDRW_sg_imm 111 1 1101 ... 1 ... 0 ... 1 1110 .... .... @vldst_sg_imm |
| 196 | VLDRD_sg_imm 111 1 1101 ... 1 ... 0 ... 1 1111 .... .... @vldst_sg_imm |
| 197 | VSTRW_sg_imm 111 1 1101 ... 0 ... 0 ... 1 1110 .... .... @vldst_sg_imm |
| 198 | VSTRD_sg_imm 111 1 1101 ... 0 ... 0 ... 1 1111 .... .... @vldst_sg_imm |
| 199 | |
| 200 | # deinterleaving loads/interleaving stores |
| 201 | VLD2 1111 1100 1 .. 1 .... ... 1 111 .. .. 00000 @vldst_il |
| 202 | VLD4 1111 1100 1 .. 1 .... ... 1 111 .. .. 00001 @vldst_il |
| 203 | VST2 1111 1100 1 .. 0 .... ... 1 111 .. .. 00000 @vldst_il |
| 204 | VST4 1111 1100 1 .. 0 .... ... 1 111 .. .. 00001 @vldst_il |
| 205 | |
| 206 | # Moves between 2 32-bit vector lanes and 2 general purpose registers |
| 207 | VMOV_to_2gp 1110 1100 0 . 00 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=%qd |
| 208 | VMOV_from_2gp 1110 1100 0 . 01 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=%qd |
| 209 | |
| 210 | # Vector 2-op |
| 211 | VAND 1110 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz |
| 212 | VBIC 1110 1111 0 . 01 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz |
| 213 | VORR 1110 1111 0 . 10 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz |
| 214 | VORN 1110 1111 0 . 11 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz |
| 215 | VEOR 1111 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz |
| 216 | |
| 217 | VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op |
| 218 | VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op |
| 219 | VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op |
| 220 | |
| 221 | # The VSHLL T2 encoding is not a @2op pattern, but is here because it |
| 222 | # overlaps what would be size=0b11 VMULH/VRMULH |
| 223 | { |
| 224 | VCVTB_SH 111 0 1110 0 . 11 1111 ... 0 1110 0 0 . 0 ... 1 @1op_nosz |
| 225 | |
| 226 | VMAXNMA 111 0 1110 0 . 11 1111 ... 0 1110 1 0 . 0 ... 1 @vmaxnma size=2 |
| 227 | |
| 228 | VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b |
| 229 | VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h |
| 230 | |
| 231 | VQMOVUNB 111 0 1110 0 . 11 .. 01 ... 0 1110 1 0 . 0 ... 1 @1op |
| 232 | VQMOVN_BS 111 0 1110 0 . 11 .. 11 ... 0 1110 0 0 . 0 ... 1 @1op |
| 233 | |
| 234 | VMAXA 111 0 1110 0 . 11 .. 11 ... 0 1110 1 0 . 0 ... 1 @1op |
| 235 | |
| 236 | VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op |
| 237 | } |
| 238 | |
| 239 | { |
| 240 | VCVTB_HS 111 1 1110 0 . 11 1111 ... 0 1110 0 0 . 0 ... 1 @1op_nosz |
| 241 | |
| 242 | VMAXNMA 111 1 1110 0 . 11 1111 ... 0 1110 1 0 . 0 ... 1 @vmaxnma size=1 |
| 243 | |
| 244 | VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b |
| 245 | VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h |
| 246 | |
| 247 | VMOVNB 111 1 1110 0 . 11 .. 01 ... 0 1110 1 0 . 0 ... 1 @1op |
| 248 | VQMOVN_BU 111 1 1110 0 . 11 .. 11 ... 0 1110 0 0 . 0 ... 1 @1op |
| 249 | |
| 250 | VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op |
| 251 | } |
| 252 | |
| 253 | { |
| 254 | VCVTT_SH 111 0 1110 0 . 11 1111 ... 1 1110 0 0 . 0 ... 1 @1op_nosz |
| 255 | |
| 256 | VMINNMA 111 0 1110 0 . 11 1111 ... 1 1110 1 0 . 0 ... 1 @vmaxnma size=2 |
| 257 | VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b |
| 258 | VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h |
| 259 | |
| 260 | VQMOVUNT 111 0 1110 0 . 11 .. 01 ... 1 1110 1 0 . 0 ... 1 @1op |
| 261 | VQMOVN_TS 111 0 1110 0 . 11 .. 11 ... 1 1110 0 0 . 0 ... 1 @1op |
| 262 | |
| 263 | VMINA 111 0 1110 0 . 11 .. 11 ... 1 1110 1 0 . 0 ... 1 @1op |
| 264 | |
| 265 | VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op |
| 266 | } |
| 267 | |
| 268 | { |
| 269 | VCVTT_HS 111 1 1110 0 . 11 1111 ... 1 1110 0 0 . 0 ... 1 @1op_nosz |
| 270 | |
| 271 | VMINNMA 111 1 1110 0 . 11 1111 ... 1 1110 1 0 . 0 ... 1 @vmaxnma size=1 |
| 272 | VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b |
| 273 | VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h |
| 274 | |
| 275 | VMOVNT 111 1 1110 0 . 11 .. 01 ... 1 1110 1 0 . 0 ... 1 @1op |
| 276 | VQMOVN_TU 111 1 1110 0 . 11 .. 11 ... 1 1110 0 0 . 0 ... 1 @1op |
| 277 | |
| 278 | VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op |
| 279 | } |
| 280 | |
| 281 | VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op |
| 282 | VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op |
| 283 | VMIN_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op |
| 284 | VMIN_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op |
| 285 | |
| 286 | VABD_S 111 0 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op |
| 287 | VABD_U 111 1 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op |
| 288 | |
| 289 | VHADD_S 111 0 1111 0 . .. ... 0 ... 0 0000 . 1 . 0 ... 0 @2op |
| 290 | VHADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 0 ... 0 @2op |
| 291 | VHSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op |
| 292 | VHSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op |
| 293 | |
| 294 | { |
| 295 | VMULLP_B 111 . 1110 0 . 11 ... 1 ... 0 1110 . 0 . 0 ... 0 @2op_sz28 |
| 296 | VMULL_BS 111 0 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op |
| 297 | VMULL_BU 111 1 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op |
| 298 | } |
| 299 | { |
| 300 | VMULLP_T 111 . 1110 0 . 11 ... 1 ... 1 1110 . 0 . 0 ... 0 @2op_sz28 |
| 301 | VMULL_TS 111 0 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op |
| 302 | VMULL_TU 111 1 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op |
| 303 | } |
| 304 | |
| 305 | VQDMULH 1110 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op |
| 306 | VQRDMULH 1111 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op |
| 307 | |
| 308 | VQADD_S 111 0 1111 0 . .. ... 0 ... 0 0000 . 1 . 1 ... 0 @2op |
| 309 | VQADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 1 ... 0 @2op |
| 310 | VQSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op |
| 311 | VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op |
| 312 | |
| 313 | VSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev |
| 314 | VSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev |
| 315 | |
| 316 | VRSHL_S 111 0 1111 0 . .. ... 0 ... 0 0101 . 1 . 0 ... 0 @2op_rev |
| 317 | VRSHL_U 111 1 1111 0 . .. ... 0 ... 0 0101 . 1 . 0 ... 0 @2op_rev |
| 318 | |
| 319 | VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev |
| 320 | VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev |
| 321 | |
| 322 | VQRSHL_S 111 0 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev |
| 323 | VQRSHL_U 111 1 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev |
| 324 | |
| 325 | { |
| 326 | VCMUL0 111 . 1110 0 . 11 ... 0 ... 0 1110 . 0 . 0 ... 0 @2op_sz28 |
| 327 | VQDMLADH 1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op |
| 328 | VQDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op |
| 329 | } |
| 330 | |
| 331 | { |
| 332 | VCMUL180 111 . 1110 0 . 11 ... 0 ... 1 1110 . 0 . 0 ... 0 @2op_sz28 |
| 333 | VQDMLADHX 111 0 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op |
| 334 | VQDMLSDHX 111 1 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op |
| 335 | } |
| 336 | |
| 337 | { |
| 338 | VCMUL90 111 . 1110 0 . 11 ... 0 ... 0 1110 . 0 . 0 ... 1 @2op_sz28 |
| 339 | VQRDMLADH 111 0 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op |
| 340 | VQRDMLSDH 111 1 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op |
| 341 | } |
| 342 | |
| 343 | { |
| 344 | VCMUL270 111 . 1110 0 . 11 ... 0 ... 1 1110 . 0 . 0 ... 1 @2op_sz28 |
| 345 | VQRDMLADHX 111 0 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op |
| 346 | VQRDMLSDHX 111 1 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op |
| 347 | } |
| 348 | |
| 349 | VQDMULLB 111 . 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 1 @2op_sz28 |
| 350 | VQDMULLT 111 . 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 1 @2op_sz28 |
| 351 | |
| 352 | VRHADD_S 111 0 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op |
| 353 | VRHADD_U 111 1 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op |
| 354 | |
| 355 | { |
| 356 | VADC 1110 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 0 @2op_nosz |
| 357 | VADCI 1110 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 0 @2op_nosz |
| 358 | VHCADD90 1110 1110 0 . .. ... 0 ... 0 1111 . 0 . 0 ... 0 @2op |
| 359 | VHCADD270 1110 1110 0 . .. ... 0 ... 1 1111 . 0 . 0 ... 0 @2op |
| 360 | } |
| 361 | |
| 362 | { |
| 363 | VSBC 1111 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 0 @2op_nosz |
| 364 | VSBCI 1111 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 0 @2op_nosz |
| 365 | VCADD90 1111 1110 0 . .. ... 0 ... 0 1111 . 0 . 0 ... 0 @2op |
| 366 | VCADD270 1111 1110 0 . .. ... 0 ... 1 1111 . 0 . 0 ... 0 @2op |
| 367 | } |
| 368 | |
| 369 | # Vector miscellaneous |
| 370 | |
| 371 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op |
| 372 | VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op |
| 373 | |
| 374 | VREV16 1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op |
| 375 | VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op |
| 376 | VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op |
| 377 | |
| 378 | VMVN 1111 1111 1 . 11 00 00 ... 0 0101 11 . 0 ... 0 @1op_nosz |
| 379 | |
| 380 | VABS 1111 1111 1 . 11 .. 01 ... 0 0011 01 . 0 ... 0 @1op |
| 381 | VABS_fp 1111 1111 1 . 11 .. 01 ... 0 0111 01 . 0 ... 0 @1op |
| 382 | VNEG 1111 1111 1 . 11 .. 01 ... 0 0011 11 . 0 ... 0 @1op |
| 383 | VNEG_fp 1111 1111 1 . 11 .. 01 ... 0 0111 11 . 0 ... 0 @1op |
| 384 | |
| 385 | VQABS 1111 1111 1 . 11 .. 00 ... 0 0111 01 . 0 ... 0 @1op |
| 386 | VQNEG 1111 1111 1 . 11 .. 00 ... 0 0111 11 . 0 ... 0 @1op |
| 387 | |
| 388 | &vdup qd rt size |
| 389 | # Qd is in the fields usually named Qn |
| 390 | @vdup .... .... . . .. ... . rt:4 .... . . . . .... qd=%qn &vdup |
| 391 | |
| 392 | # B and E bits encode size, which we decode here to the usual size values |
| 393 | VDUP 1110 1110 1 1 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=0 |
| 394 | VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 1 1 0000 @vdup size=1 |
| 395 | VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=2 |
| 396 | |
| 397 | # Incrementing and decrementing dup |
| 398 | |
| 399 | # VIDUP, VDDUP format immediate: 1 << (immh:imml) |
| 400 | %imm_vidup 7:1 0:1 !function=vidup_imm |
| 401 | |
| 402 | # VIDUP, VDDUP registers: Rm bits [3:1] from insn, bit 0 is 1; |
| 403 | # Rn bits [3:1] from insn, bit 0 is 0 |
| 404 | %vidup_rm 1:3 !function=times_2_plus_1 |
| 405 | %vidup_rn 17:3 !function=times_2 |
| 406 | |
| 407 | @vidup .... .... . . size:2 .... .... .... .... .... \ |
| 408 | qd=%qd imm=%imm_vidup rn=%vidup_rn &vidup |
| 409 | @viwdup .... .... . . size:2 .... .... .... .... .... \ |
| 410 | qd=%qd imm=%imm_vidup rm=%vidup_rm rn=%vidup_rn &viwdup |
| 411 | { |
| 412 | VIDUP 1110 1110 0 . .. ... 1 ... 0 1111 . 110 111 . @vidup |
| 413 | VIWDUP 1110 1110 0 . .. ... 1 ... 0 1111 . 110 ... . @viwdup |
| 414 | } |
| 415 | { |
| 416 | VCMPGT_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 0110 .... @vcmp_fp_scalar size=2 |
| 417 | VCMPLE_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 1110 .... @vcmp_fp_scalar size=2 |
| 418 | VDDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 111 . @vidup |
| 419 | VDWDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 ... . @viwdup |
| 420 | } |
| 421 | |
| 422 | # multiply-add long dual accumulate |
| 423 | # rdahi: bits [3:1] from insn, bit 0 is 1 |
| 424 | # rdalo: bits [3:1] from insn, bit 0 is 0 |
| 425 | %rdahi 20:3 !function=times_2_plus_1 |
| 426 | %rdalo 13:3 !function=times_2 |
| 427 | # size bit is 0 for 16 bit, 1 for 32 bit |
| 428 | %size_16 16:1 !function=plus_1 |
| 429 | |
| 430 | &vmlaldav rdahi rdalo size qn qm x a |
| 431 | &vmladav rda size qn qm x a |
| 432 | |
| 433 | @vmlaldav .... .... . ... ... . ... x:1 .... .. a:1 . qm:3 . \ |
| 434 | qn=%qn rdahi=%rdahi rdalo=%rdalo size=%size_16 &vmlaldav |
| 435 | @vmlaldav_nosz .... .... . ... ... . ... x:1 .... .. a:1 . qm:3 . \ |
| 436 | qn=%qn rdahi=%rdahi rdalo=%rdalo size=0 &vmlaldav |
| 437 | @vmladav .... .... .... ... . ... x:1 .... . . a:1 . qm:3 . \ |
| 438 | qn=%qn rda=%rdalo size=%size_16 &vmladav |
| 439 | @vmladav_nosz .... .... .... ... . ... x:1 .... . . a:1 . qm:3 . \ |
| 440 | qn=%qn rda=%rdalo size=0 &vmladav |
| 441 | |
| 442 | { |
| 443 | VMLADAV_S 1110 1110 1111 ... . ... . 1110 . 0 . 0 ... 0 @vmladav |
| 444 | VMLALDAV_S 1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav |
| 445 | } |
| 446 | { |
| 447 | VMLADAV_U 1111 1110 1111 ... . ... . 1110 . 0 . 0 ... 0 @vmladav |
| 448 | VMLALDAV_U 1111 1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav |
| 449 | } |
| 450 | |
| 451 | { |
| 452 | VMLSDAV 1110 1110 1111 ... . ... . 1110 . 0 . 0 ... 1 @vmladav |
| 453 | VMLSLDAV 1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 1 @vmlaldav |
| 454 | } |
| 455 | |
| 456 | { |
| 457 | VMLSDAV 1111 1110 1111 ... 0 ... . 1110 . 0 . 0 ... 1 @vmladav_nosz |
| 458 | VRMLSLDAVH 1111 1110 1 ... ... 0 ... . 1110 . 0 . 0 ... 1 @vmlaldav_nosz |
| 459 | } |
| 460 | |
| 461 | VMLADAV_S 1110 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 1 @vmladav_nosz |
| 462 | VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 1 @vmladav_nosz |
| 463 | |
| 464 | { |
| 465 | [ |
| 466 | VMAXNMAV 1110 1110 1110 11 00 .... 1111 0 0 . 0 ... 0 @vmaxnmv size=2 |
| 467 | VMINNMAV 1110 1110 1110 11 00 .... 1111 1 0 . 0 ... 0 @vmaxnmv size=2 |
| 468 | VMAXNMV 1110 1110 1110 11 10 .... 1111 0 0 . 0 ... 0 @vmaxnmv size=2 |
| 469 | VMINNMV 1110 1110 1110 11 10 .... 1111 1 0 . 0 ... 0 @vmaxnmv size=2 |
| 470 | ] |
| 471 | [ |
| 472 | VMAXV_S 1110 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv |
| 473 | VMINV_S 1110 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv |
| 474 | VMAXAV 1110 1110 1110 .. 00 .... 1111 0 0 . 0 ... 0 @vmaxv |
| 475 | VMINAV 1110 1110 1110 .. 00 .... 1111 1 0 . 0 ... 0 @vmaxv |
| 476 | ] |
| 477 | VMLADAV_S 1110 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 0 @vmladav_nosz |
| 478 | VRMLALDAVH_S 1110 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_nosz |
| 479 | } |
| 480 | |
| 481 | { |
| 482 | [ |
| 483 | VMAXNMAV 1111 1110 1110 11 00 .... 1111 0 0 . 0 ... 0 @vmaxnmv size=1 |
| 484 | VMINNMAV 1111 1110 1110 11 00 .... 1111 1 0 . 0 ... 0 @vmaxnmv size=1 |
| 485 | VMAXNMV 1111 1110 1110 11 10 .... 1111 0 0 . 0 ... 0 @vmaxnmv size=1 |
| 486 | VMINNMV 1111 1110 1110 11 10 .... 1111 1 0 . 0 ... 0 @vmaxnmv size=1 |
| 487 | ] |
| 488 | [ |
| 489 | VMAXV_U 1111 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv |
| 490 | VMINV_U 1111 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv |
| 491 | ] |
| 492 | VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 0 @vmladav_nosz |
| 493 | VRMLALDAVH_U 1111 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_nosz |
| 494 | } |
| 495 | |
| 496 | # Scalar operations |
| 497 | |
| 498 | { |
| 499 | VCMPEQ_fp_scalar 1110 1110 0 . 11 ... 1 ... 0 1111 0100 .... @vcmp_fp_scalar size=2 |
| 500 | VCMPNE_fp_scalar 1110 1110 0 . 11 ... 1 ... 0 1111 1100 .... @vcmp_fp_scalar size=2 |
| 501 | VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar |
| 502 | } |
| 503 | |
| 504 | { |
| 505 | VCMPLT_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 1100 .... @vcmp_fp_scalar size=2 |
| 506 | VCMPGE_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 0100 .... @vcmp_fp_scalar size=2 |
| 507 | VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar |
| 508 | } |
| 509 | |
| 510 | { |
| 511 | VSHL_S_scalar 1110 1110 0 . 11 .. 01 ... 1 1110 0110 .... @shl_scalar |
| 512 | VRSHL_S_scalar 1110 1110 0 . 11 .. 11 ... 1 1110 0110 .... @shl_scalar |
| 513 | VQSHL_S_scalar 1110 1110 0 . 11 .. 01 ... 1 1110 1110 .... @shl_scalar |
| 514 | VQRSHL_S_scalar 1110 1110 0 . 11 .. 11 ... 1 1110 1110 .... @shl_scalar |
| 515 | VMUL_scalar 1110 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar |
| 516 | } |
| 517 | |
| 518 | { |
| 519 | VSHL_U_scalar 1111 1110 0 . 11 .. 01 ... 1 1110 0110 .... @shl_scalar |
| 520 | VRSHL_U_scalar 1111 1110 0 . 11 .. 11 ... 1 1110 0110 .... @shl_scalar |
| 521 | VQSHL_U_scalar 1111 1110 0 . 11 .. 01 ... 1 1110 1110 .... @shl_scalar |
| 522 | VQRSHL_U_scalar 1111 1110 0 . 11 .. 11 ... 1 1110 1110 .... @shl_scalar |
| 523 | VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar |
| 524 | } |
| 525 | |
| 526 | { |
| 527 | VADD_fp_scalar 111 . 1110 0 . 11 ... 0 ... 0 1111 . 100 .... @2op_fp_scalar |
| 528 | VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar |
| 529 | VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar |
| 530 | } |
| 531 | |
| 532 | { |
| 533 | VSUB_fp_scalar 111 . 1110 0 . 11 ... 0 ... 1 1111 . 100 .... @2op_fp_scalar |
| 534 | VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar |
| 535 | VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar |
| 536 | } |
| 537 | |
| 538 | { |
| 539 | VQADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar |
| 540 | VQADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar |
| 541 | VQDMULLB_scalar 111 . 1110 0 . 11 ... 0 ... 0 1111 . 110 .... @2scalar_nosz \ |
| 542 | size=%size_28 |
| 543 | } |
| 544 | |
| 545 | { |
| 546 | VQSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar |
| 547 | VQSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar |
| 548 | VQDMULLT_scalar 111 . 1110 0 . 11 ... 0 ... 1 1111 . 110 .... @2scalar_nosz \ |
| 549 | size=%size_28 |
| 550 | } |
| 551 | |
| 552 | { |
| 553 | VMUL_fp_scalar 111 . 1110 0 . 11 ... 1 ... 0 1110 . 110 .... @2op_fp_scalar |
| 554 | VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar |
| 555 | VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar |
| 556 | } |
| 557 | |
| 558 | { |
| 559 | VFMA_scalar 111 . 1110 0 . 11 ... 1 ... 0 1110 . 100 .... @2op_fp_scalar |
| 560 | # The U bit (28) is don't-care because it does not affect the result |
| 561 | VMLA 111 - 1110 0 . .. ... 1 ... 0 1110 . 100 .... @2scalar |
| 562 | } |
| 563 | |
| 564 | { |
| 565 | VFMAS_scalar 111 . 1110 0 . 11 ... 1 ... 1 1110 . 100 .... @2op_fp_scalar |
| 566 | # The U bit (28) is don't-care because it does not affect the result |
| 567 | VMLAS 111 - 1110 0 . .. ... 1 ... 1 1110 . 100 .... @2scalar |
| 568 | } |
| 569 | |
| 570 | VQRDMLAH 1110 1110 0 . .. ... 0 ... 0 1110 . 100 .... @2scalar |
| 571 | VQRDMLASH 1110 1110 0 . .. ... 0 ... 1 1110 . 100 .... @2scalar |
| 572 | VQDMLAH 1110 1110 0 . .. ... 0 ... 0 1110 . 110 .... @2scalar |
| 573 | VQDMLASH 1110 1110 0 . .. ... 0 ... 1 1110 . 110 .... @2scalar |
| 574 | |
| 575 | # Vector add across vector |
| 576 | { |
| 577 | VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo |
| 578 | VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \ |
| 579 | rdahi=%rdahi rdalo=%rdalo |
| 580 | } |
| 581 | |
| 582 | @vabav .... .... .. size:2 .... rda:4 .... .... .... &vabav qn=%qn qm=%qm |
| 583 | |
| 584 | VABAV_S 111 0 1110 10 .. ... 0 .... 1111 . 0 . 0 ... 1 @vabav |
| 585 | VABAV_U 111 1 1110 10 .. ... 0 .... 1111 . 0 . 0 ... 1 @vabav |
| 586 | |
| 587 | # Logical immediate operations (1 reg and modified-immediate) |
| 588 | |
| 589 | # The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but |
| 590 | # not in a way we can conveniently represent in decodetree without |
| 591 | # a lot of repetition: |
| 592 | # VORR: op=0, (cmode & 1) && cmode < 12 |
| 593 | # VBIC: op=1, (cmode & 1) && cmode < 12 |
| 594 | # VMOV: everything else |
| 595 | # So we have a single decode line and check the cmode/op in the |
| 596 | # trans function. |
| 597 | Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm |
| 598 | |
| 599 | # Shifts by immediate |
| 600 | |
| 601 | VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b |
| 602 | VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h |
| 603 | VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w |
| 604 | |
| 605 | VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b |
| 606 | VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h |
| 607 | VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w |
| 608 | |
| 609 | VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b |
| 610 | VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h |
| 611 | VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w |
| 612 | |
| 613 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b |
| 614 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h |
| 615 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w |
| 616 | |
| 617 | VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b |
| 618 | VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h |
| 619 | VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w |
| 620 | |
| 621 | VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b |
| 622 | VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h |
| 623 | VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w |
| 624 | |
| 625 | VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b |
| 626 | VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h |
| 627 | VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w |
| 628 | |
| 629 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b |
| 630 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h |
| 631 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w |
| 632 | |
| 633 | # VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file |
| 634 | # Note that VMOVL is encoded as "VSHLL with a zero shift count"; we |
| 635 | # implement it that way rather than special-casing it in the decode. |
| 636 | VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b |
| 637 | VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h |
| 638 | |
| 639 | VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b |
| 640 | VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h |
| 641 | |
| 642 | VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b |
| 643 | VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h |
| 644 | |
| 645 | VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b |
| 646 | VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h |
| 647 | |
| 648 | # Shift-and-insert |
| 649 | VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b |
| 650 | VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h |
| 651 | VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w |
| 652 | |
| 653 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b |
| 654 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h |
| 655 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w |
| 656 | |
| 657 | # Narrowing shifts (which only support b and h sizes) |
| 658 | VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b |
| 659 | VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h |
| 660 | VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b |
| 661 | VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h |
| 662 | |
| 663 | VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b |
| 664 | VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h |
| 665 | VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b |
| 666 | VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h |
| 667 | |
| 668 | VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b |
| 669 | VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h |
| 670 | VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b |
| 671 | VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h |
| 672 | VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b |
| 673 | VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h |
| 674 | VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b |
| 675 | VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h |
| 676 | |
| 677 | VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b |
| 678 | VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h |
| 679 | VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b |
| 680 | VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h |
| 681 | |
| 682 | VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b |
| 683 | VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h |
| 684 | VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b |
| 685 | VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h |
| 686 | VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b |
| 687 | VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h |
| 688 | VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b |
| 689 | VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h |
| 690 | |
| 691 | VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b |
| 692 | VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h |
| 693 | VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b |
| 694 | VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h |
| 695 | |
| 696 | VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd |
| 697 | |
| 698 | # Comparisons. We expand out the conditions which are split across |
| 699 | # encodings T1, T2, T3 and the fc bits. These include VPT, which is |
| 700 | # effectively "VCMP then VPST". A plain "VCMP" has a mask field of zero. |
| 701 | { |
| 702 | VCMPEQ_fp 111 . 1110 0 . 11 ... 1 ... 0 1111 0 0 . 0 ... 0 @vcmp_fp |
| 703 | VCMPEQ 111 1 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 0 @vcmp |
| 704 | } |
| 705 | |
| 706 | { |
| 707 | VCMPNE_fp 111 . 1110 0 . 11 ... 1 ... 0 1111 1 0 . 0 ... 0 @vcmp_fp |
| 708 | VCMPNE 111 1 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 0 @vcmp |
| 709 | } |
| 710 | |
| 711 | { |
| 712 | VCMPGE_fp 111 . 1110 0 . 11 ... 1 ... 1 1111 0 0 . 0 ... 0 @vcmp_fp |
| 713 | VCMPGE 111 1 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 0 @vcmp |
| 714 | } |
| 715 | |
| 716 | { |
| 717 | VCMPLT_fp 111 . 1110 0 . 11 ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp_fp |
| 718 | VCMPLT 111 1 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp |
| 719 | } |
| 720 | |
| 721 | { |
| 722 | VCMPGT_fp 111 . 1110 0 . 11 ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp_fp |
| 723 | VCMPGT 111 1 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp |
| 724 | } |
| 725 | |
| 726 | { |
| 727 | VCMPLE_fp 111 . 1110 0 . 11 ... 1 ... 1 1111 1 0 . 0 ... 1 @vcmp_fp |
| 728 | VCMPLE 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 1 @vcmp |
| 729 | } |
| 730 | |
| 731 | { |
| 732 | VPSEL 1111 1110 0 . 11 ... 1 ... 0 1111 . 0 . 0 ... 1 @2op_nosz |
| 733 | VCMPCS 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 1 @vcmp |
| 734 | VCMPHI 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 1 @vcmp |
| 735 | } |
| 736 | |
| 737 | { |
| 738 | VPNOT 1111 1110 0 0 11 000 1 000 0 1111 0100 1101 |
| 739 | VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 |
| 740 | VCMPEQ_fp_scalar 1111 1110 0 . 11 ... 1 ... 0 1111 0100 .... @vcmp_fp_scalar size=1 |
| 741 | VCMPEQ_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0100 .... @vcmp_scalar |
| 742 | } |
| 743 | |
| 744 | { |
| 745 | VCMPNE_fp_scalar 1111 1110 0 . 11 ... 1 ... 0 1111 1100 .... @vcmp_fp_scalar size=1 |
| 746 | VCMPNE_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1100 .... @vcmp_scalar |
| 747 | } |
| 748 | |
| 749 | { |
| 750 | VCMPGT_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 0110 .... @vcmp_fp_scalar size=1 |
| 751 | VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0110 .... @vcmp_scalar |
| 752 | } |
| 753 | |
| 754 | { |
| 755 | VCMPLE_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 1110 .... @vcmp_fp_scalar size=1 |
| 756 | VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1110 .... @vcmp_scalar |
| 757 | } |
| 758 | |
| 759 | { |
| 760 | VCMPGE_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 0100 .... @vcmp_fp_scalar size=1 |
| 761 | VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0100 .... @vcmp_scalar |
| 762 | } |
| 763 | { |
| 764 | VCMPLT_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 1100 .... @vcmp_fp_scalar size=1 |
| 765 | VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1100 .... @vcmp_scalar |
| 766 | } |
| 767 | |
| 768 | VCMPCS_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 1 0 .... @vcmp_scalar |
| 769 | VCMPHI_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 1 0 .... @vcmp_scalar |
| 770 | |
| 771 | # 2-operand FP |
| 772 | VADD_fp 1110 1111 0 . 0 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp |
| 773 | VSUB_fp 1110 1111 0 . 1 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp |
| 774 | VMUL_fp 1111 1111 0 . 0 . ... 0 ... 0 1101 . 1 . 1 ... 0 @2op_fp |
| 775 | VABD_fp 1111 1111 0 . 1 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp |
| 776 | |
| 777 | VMAXNM 1111 1111 0 . 0 . ... 0 ... 0 1111 . 1 . 1 ... 0 @2op_fp |
| 778 | VMINNM 1111 1111 0 . 1 . ... 0 ... 0 1111 . 1 . 1 ... 0 @2op_fp |
| 779 | |
| 780 | VCADD90_fp 1111 1100 1 . 0 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp_size_rev |
| 781 | VCADD270_fp 1111 1101 1 . 0 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp_size_rev |
| 782 | |
| 783 | VFMA 1110 1111 0 . 0 . ... 0 ... 0 1100 . 1 . 1 ... 0 @2op_fp |
| 784 | VFMS 1110 1111 0 . 1 . ... 0 ... 0 1100 . 1 . 1 ... 0 @2op_fp |
| 785 | |
| 786 | VCMLA0 1111 110 00 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp_size_rev |
| 787 | VCMLA90 1111 110 01 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp_size_rev |
| 788 | VCMLA180 1111 110 10 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp_size_rev |
| 789 | VCMLA270 1111 110 11 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp_size_rev |
| 790 | |
| 791 | # floating-point <-> fixed-point conversions. Naming convention: |
| 792 | # VCVT_<from><to>, S = signed int, U = unsigned int, H = halfprec, F = singleprec |
| 793 | @vcvt .... .... .. 1 ..... .... .. 1 . .... .... &2shift \ |
| 794 | qd=%qd qm=%qm shift=%rshift_i5 size=2 |
| 795 | @vcvt_f16 .... .... .. 11 .... .... .. 0 . .... .... &2shift \ |
| 796 | qd=%qd qm=%qm shift=%rshift_i4 size=1 |
| 797 | |
| 798 | VCVT_SH_fixed 1110 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt_f16 |
| 799 | VCVT_UH_fixed 1111 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt_f16 |
| 800 | |
| 801 | VCVT_HS_fixed 1110 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt_f16 |
| 802 | VCVT_HU_fixed 1111 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt_f16 |
| 803 | |
| 804 | VCVT_SF_fixed 1110 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt |
| 805 | VCVT_UF_fixed 1111 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt |
| 806 | |
| 807 | VCVT_FS_fixed 1110 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt |
| 808 | VCVT_FU_fixed 1111 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt |
| 809 | |
| 810 | # VCVT between floating point and integer (halfprec and single); |
| 811 | # VCVT_<from><to>, S = signed int, U = unsigned int, F = float |
| 812 | VCVT_SF 1111 1111 1 . 11 .. 11 ... 0 011 00 1 . 0 ... 0 @1op |
| 813 | VCVT_UF 1111 1111 1 . 11 .. 11 ... 0 011 01 1 . 0 ... 0 @1op |
| 814 | VCVT_FS 1111 1111 1 . 11 .. 11 ... 0 011 10 1 . 0 ... 0 @1op |
| 815 | VCVT_FU 1111 1111 1 . 11 .. 11 ... 0 011 11 1 . 0 ... 0 @1op |
| 816 | |
| 817 | # VCVT from floating point to integer with specified rounding mode |
| 818 | VCVTAS 1111 1111 1 . 11 .. 11 ... 000 00 0 1 . 0 ... 0 @1op |
| 819 | VCVTAU 1111 1111 1 . 11 .. 11 ... 000 00 1 1 . 0 ... 0 @1op |
| 820 | VCVTNS 1111 1111 1 . 11 .. 11 ... 000 01 0 1 . 0 ... 0 @1op |
| 821 | VCVTNU 1111 1111 1 . 11 .. 11 ... 000 01 1 1 . 0 ... 0 @1op |
| 822 | VCVTPS 1111 1111 1 . 11 .. 11 ... 000 10 0 1 . 0 ... 0 @1op |
| 823 | VCVTPU 1111 1111 1 . 11 .. 11 ... 000 10 1 1 . 0 ... 0 @1op |
| 824 | VCVTMS 1111 1111 1 . 11 .. 11 ... 000 11 0 1 . 0 ... 0 @1op |
| 825 | VCVTMU 1111 1111 1 . 11 .. 11 ... 000 11 1 1 . 0 ... 0 @1op |
| 826 | |
| 827 | VRINTN 1111 1111 1 . 11 .. 10 ... 001 000 1 . 0 ... 0 @1op |
| 828 | VRINTX 1111 1111 1 . 11 .. 10 ... 001 001 1 . 0 ... 0 @1op |
| 829 | VRINTA 1111 1111 1 . 11 .. 10 ... 001 010 1 . 0 ... 0 @1op |
| 830 | VRINTZ 1111 1111 1 . 11 .. 10 ... 001 011 1 . 0 ... 0 @1op |
| 831 | VRINTM 1111 1111 1 . 11 .. 10 ... 001 101 1 . 0 ... 0 @1op |
| 832 | VRINTP 1111 1111 1 . 11 .. 10 ... 001 111 1 . 0 ... 0 @1op |