| 1 | /* |
| 2 | * ARM helper routines |
| 3 | * |
| 4 | * Copyright (c) 2005-2007 CodeSourcery, LLC |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | #include "qemu/osdep.h" |
| 20 | #include "qemu/main-loop.h" |
| 21 | #include "cpu.h" |
| 22 | #include "exec/target_page.h" |
| 23 | #include "helper.h" |
| 24 | #include "internals.h" |
| 25 | #include "cpu-features.h" |
| 26 | #include "accel/tcg/cpu-loop.h" |
| 27 | #include "accel/tcg/probe.h" |
| 28 | #include "cpregs.h" |
| 29 | |
| 30 | #define SIGNBIT (uint32_t)0x80000000 |
| 31 | #define SIGNBIT64 ((uint64_t)1 << 63) |
| 32 | |
| 33 | int exception_target_el(CPUARMState *env) |
| 34 | { |
| 35 | int target_el = MAX(1, arm_current_el(env)); |
| 36 | |
| 37 | /* |
| 38 | * No such thing as secure EL1 if EL3 is aarch32, |
| 39 | * so update the target EL to EL3 in this case. |
| 40 | */ |
| 41 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { |
| 42 | target_el = 3; |
| 43 | } |
| 44 | |
| 45 | return target_el; |
| 46 | } |
| 47 | |
| 48 | void raise_exception(CPUARMState *env, uint32_t excp, |
| 49 | uint64_t syndrome, uint32_t target_el) |
| 50 | { |
| 51 | CPUState *cs = env_cpu(env); |
| 52 | |
| 53 | if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { |
| 54 | /* |
| 55 | * Redirect NS EL1 exceptions to NS EL2. These are reported with |
| 56 | * their original syndrome register value, with the exception of |
| 57 | * SIMD/FP access traps, which are reported as uncategorized |
| 58 | * (see DDI0478C.a D1.10.4) |
| 59 | */ |
| 60 | target_el = 2; |
| 61 | if (syn_get_ec(syndrome) == EC_ADVSIMDFPACCESSTRAP) { |
| 62 | syndrome = syn_uncategorized(); |
| 63 | } |
| 64 | } |
| 65 | |
| 66 | assert(!excp_is_internal(excp)); |
| 67 | cs->exception_index = excp; |
| 68 | env->exception.syndrome = syndrome; |
| 69 | env->exception.target_el = target_el; |
| 70 | cpu_loop_exit(cs); |
| 71 | } |
| 72 | |
| 73 | void raise_exception_ra(CPUARMState *env, uint32_t excp, uint64_t syndrome, |
| 74 | uint32_t target_el, uintptr_t ra) |
| 75 | { |
| 76 | CPUState *cs = env_cpu(env); |
| 77 | |
| 78 | /* |
| 79 | * restore_state_to_opc() will set env->exception.syndrome, so |
| 80 | * we must restore CPU state here before setting the syndrome |
| 81 | * the caller passed us, and cannot use cpu_loop_exit_restore(). |
| 82 | */ |
| 83 | cpu_restore_state(cs, ra); |
| 84 | raise_exception(env, excp, syndrome, target_el); |
| 85 | } |
| 86 | |
| 87 | uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, |
| 88 | uint64_t ireg, uint64_t def) |
| 89 | { |
| 90 | uint64_t tmp, val = 0; |
| 91 | uint32_t maxindex = ((desc & 3) + 1) * 8; |
| 92 | uint32_t base_reg = desc >> 2; |
| 93 | uint32_t shift, index, reg; |
| 94 | |
| 95 | for (shift = 0; shift < 64; shift += 8) { |
| 96 | index = (ireg >> shift) & 0xff; |
| 97 | if (index < maxindex) { |
| 98 | reg = base_reg + (index >> 3); |
| 99 | tmp = *aa32_vfp_dreg(env, reg); |
| 100 | tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift; |
| 101 | } else { |
| 102 | tmp = def & (0xffull << shift); |
| 103 | } |
| 104 | val |= tmp; |
| 105 | } |
| 106 | return val; |
| 107 | } |
| 108 | |
| 109 | void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) |
| 110 | { |
| 111 | /* |
| 112 | * Perform the v8M stack limit check for SP updates from translated code, |
| 113 | * raising an exception if the limit is breached. |
| 114 | */ |
| 115 | if (newvalue < v7m_sp_limit(env)) { |
| 116 | /* |
| 117 | * Stack limit exceptions are a rare case, so rather than syncing |
| 118 | * PC/condbits before the call, we use raise_exception_ra() so |
| 119 | * that cpu_restore_state() will sort them out. |
| 120 | */ |
| 121 | raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC()); |
| 122 | } |
| 123 | } |
| 124 | |
| 125 | /* Sign/zero extend */ |
| 126 | uint32_t HELPER(sxtb16)(uint32_t x) |
| 127 | { |
| 128 | uint32_t res; |
| 129 | res = (uint16_t)(int8_t)x; |
| 130 | res |= (uint32_t)(int8_t)(x >> 16) << 16; |
| 131 | return res; |
| 132 | } |
| 133 | |
| 134 | static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) |
| 135 | { |
| 136 | /* |
| 137 | * Take a division-by-zero exception if necessary; otherwise return |
| 138 | * to get the usual non-trapping division behaviour (result of 0) |
| 139 | */ |
| 140 | if (arm_feature(env, ARM_FEATURE_M) |
| 141 | && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { |
| 142 | raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); |
| 143 | } |
| 144 | } |
| 145 | |
| 146 | uint32_t HELPER(uxtb16)(uint32_t x) |
| 147 | { |
| 148 | uint32_t res; |
| 149 | res = (uint16_t)(uint8_t)x; |
| 150 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; |
| 151 | return res; |
| 152 | } |
| 153 | |
| 154 | int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) |
| 155 | { |
| 156 | if (den == 0) { |
| 157 | handle_possible_div0_trap(env, GETPC()); |
| 158 | return 0; |
| 159 | } |
| 160 | if (num == INT_MIN && den == -1) { |
| 161 | return INT_MIN; |
| 162 | } |
| 163 | return num / den; |
| 164 | } |
| 165 | |
| 166 | uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) |
| 167 | { |
| 168 | if (den == 0) { |
| 169 | handle_possible_div0_trap(env, GETPC()); |
| 170 | return 0; |
| 171 | } |
| 172 | return num / den; |
| 173 | } |
| 174 | |
| 175 | uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) |
| 176 | { |
| 177 | uint32_t res = a + b; |
| 178 | if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) |
| 179 | env->QF = 1; |
| 180 | return res; |
| 181 | } |
| 182 | |
| 183 | uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b) |
| 184 | { |
| 185 | uint32_t res = a + b; |
| 186 | if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) { |
| 187 | env->QF = 1; |
| 188 | res = ~(((int32_t)a >> 31) ^ SIGNBIT); |
| 189 | } |
| 190 | return res; |
| 191 | } |
| 192 | |
| 193 | uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b) |
| 194 | { |
| 195 | uint32_t res = a - b; |
| 196 | if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) { |
| 197 | env->QF = 1; |
| 198 | res = ~(((int32_t)a >> 31) ^ SIGNBIT); |
| 199 | } |
| 200 | return res; |
| 201 | } |
| 202 | |
| 203 | uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b) |
| 204 | { |
| 205 | uint32_t res = a + b; |
| 206 | if (res < a) { |
| 207 | env->QF = 1; |
| 208 | res = ~0; |
| 209 | } |
| 210 | return res; |
| 211 | } |
| 212 | |
| 213 | uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b) |
| 214 | { |
| 215 | uint32_t res = a - b; |
| 216 | if (res > a) { |
| 217 | env->QF = 1; |
| 218 | res = 0; |
| 219 | } |
| 220 | return res; |
| 221 | } |
| 222 | |
| 223 | /* Signed saturation. */ |
| 224 | static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift) |
| 225 | { |
| 226 | int32_t top; |
| 227 | uint32_t mask; |
| 228 | |
| 229 | top = val >> shift; |
| 230 | mask = (1u << shift) - 1; |
| 231 | if (top > 0) { |
| 232 | env->QF = 1; |
| 233 | return mask; |
| 234 | } else if (top < -1) { |
| 235 | env->QF = 1; |
| 236 | return ~mask; |
| 237 | } |
| 238 | return val; |
| 239 | } |
| 240 | |
| 241 | /* Unsigned saturation. */ |
| 242 | static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift) |
| 243 | { |
| 244 | uint32_t max; |
| 245 | |
| 246 | max = (1u << shift) - 1; |
| 247 | if (val < 0) { |
| 248 | env->QF = 1; |
| 249 | return 0; |
| 250 | } else if (val > max) { |
| 251 | env->QF = 1; |
| 252 | return max; |
| 253 | } |
| 254 | return val; |
| 255 | } |
| 256 | |
| 257 | /* Signed saturate. */ |
| 258 | uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift) |
| 259 | { |
| 260 | return do_ssat(env, x, shift); |
| 261 | } |
| 262 | |
| 263 | /* Dual halfword signed saturate. */ |
| 264 | uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift) |
| 265 | { |
| 266 | uint32_t res; |
| 267 | |
| 268 | res = (uint16_t)do_ssat(env, (int16_t)x, shift); |
| 269 | res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16; |
| 270 | return res; |
| 271 | } |
| 272 | |
| 273 | /* Unsigned saturate. */ |
| 274 | uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift) |
| 275 | { |
| 276 | return do_usat(env, x, shift); |
| 277 | } |
| 278 | |
| 279 | /* Dual halfword unsigned saturate. */ |
| 280 | uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift) |
| 281 | { |
| 282 | uint32_t res; |
| 283 | |
| 284 | res = (uint16_t)do_usat(env, (int16_t)x, shift); |
| 285 | res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16; |
| 286 | return res; |
| 287 | } |
| 288 | |
| 289 | void HELPER(setend)(CPUARMState *env) |
| 290 | { |
| 291 | env->uncached_cpsr ^= CPSR_E; |
| 292 | arm_rebuild_hflags(env); |
| 293 | } |
| 294 | |
| 295 | void HELPER(check_bxj_trap)(CPUARMState *env, uint32_t rm) |
| 296 | { |
| 297 | /* |
| 298 | * Only called if in NS EL0 or EL1 for a BXJ for a v7A CPU; |
| 299 | * check if HSTR.TJDBX means we need to trap to EL2. |
| 300 | */ |
| 301 | if (env->cp15.hstr_el2 & HSTR_TJDBX) { |
| 302 | /* |
| 303 | * We know the condition code check passed, so take the IMPDEF |
| 304 | * choice to always report CV=1 COND 0xe |
| 305 | */ |
| 306 | uint32_t syn = syn_bxjtrap(1, 0xe, rm); |
| 307 | raise_exception_ra(env, EXCP_HYP_TRAP, syn, 2, GETPC()); |
| 308 | } |
| 309 | } |
| 310 | |
| 311 | #ifndef CONFIG_USER_ONLY |
| 312 | /* |
| 313 | * Function checks whether WFx (WFI/WFE) instructions are set up to be trapped. |
| 314 | * The function returns the target EL (1-3) if the instruction is to be trapped; |
| 315 | * otherwise it returns 0 indicating it is not trapped. |
| 316 | * For a trap, *excp is updated with the EXCP_* trap type to use. |
| 317 | */ |
| 318 | static inline int check_wfx_trap(CPUARMState *env, bool is_wfe, uint32_t *excp) |
| 319 | { |
| 320 | int cur_el = arm_current_el(env); |
| 321 | uint64_t mask; |
| 322 | |
| 323 | *excp = EXCP_UDEF; |
| 324 | |
| 325 | if (arm_feature(env, ARM_FEATURE_M)) { |
| 326 | /* M profile cores can never trap WFI/WFE. */ |
| 327 | return 0; |
| 328 | } |
| 329 | |
| 330 | /* If we are currently in EL0 then we need to check if SCTLR is set up for |
| 331 | * WFx instructions being trapped to EL1. These trap bits don't exist in v7. |
| 332 | */ |
| 333 | if (cur_el < 1 && arm_feature(env, ARM_FEATURE_V8)) { |
| 334 | mask = is_wfe ? SCTLR_nTWE : SCTLR_nTWI; |
| 335 | if (!(arm_sctlr(env, cur_el) & mask)) { |
| 336 | return exception_target_el(env); |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it |
| 341 | * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the |
| 342 | * bits will be zero indicating no trap. |
| 343 | */ |
| 344 | if (cur_el < 2) { |
| 345 | mask = is_wfe ? HCR_TWE : HCR_TWI; |
| 346 | if (arm_hcr_el2_eff(env) & mask) { |
| 347 | return 2; |
| 348 | } |
| 349 | } |
| 350 | |
| 351 | /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */ |
| 352 | if (arm_feature(env, ARM_FEATURE_V8) && !arm_is_el3_or_mon(env)) { |
| 353 | mask = (is_wfe) ? SCR_TWE : SCR_TWI; |
| 354 | if (env->cp15.scr_el3 & mask) { |
| 355 | if (!arm_el_is_aa64(env, 3)) { |
| 356 | *excp = EXCP_MON_TRAP; |
| 357 | } |
| 358 | return 3; |
| 359 | } |
| 360 | } |
| 361 | |
| 362 | return 0; |
| 363 | } |
| 364 | #endif |
| 365 | |
| 366 | void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) |
| 367 | { |
| 368 | #ifdef CONFIG_USER_ONLY |
| 369 | /* |
| 370 | * WFI in the user-mode emulator is technically permitted but not |
| 371 | * something any real-world code would do. AArch64 Linux kernels |
| 372 | * trap it via SCTRL_EL1.nTWI and make it an (expensive) NOP; |
| 373 | * AArch32 kernels don't trap it so it will delay a bit. |
| 374 | * For QEMU, make it NOP here, because trying to raise EXCP_HLT |
| 375 | * would trigger an abort. |
| 376 | */ |
| 377 | return; |
| 378 | #else |
| 379 | CPUState *cs = env_cpu(env); |
| 380 | uint32_t excp; |
| 381 | int target_el = check_wfx_trap(env, false, &excp); |
| 382 | |
| 383 | if (cpu_has_work(cs)) { |
| 384 | /* Don't bother to go into our "low power state" if |
| 385 | * we would just wake up immediately. |
| 386 | */ |
| 387 | return; |
| 388 | } |
| 389 | |
| 390 | if (target_el) { |
| 391 | if (env->aarch64) { |
| 392 | env->pc -= insn_len; |
| 393 | } else { |
| 394 | env->regs[15] -= insn_len; |
| 395 | } |
| 396 | |
| 397 | raise_exception(env, excp, syn_wfx(1, 0xe, 0, false, WFI, insn_len == 2), |
| 398 | target_el); |
| 399 | } |
| 400 | |
| 401 | env->halt_reason = HALT_WFI; |
| 402 | cs->exception_index = EXCP_HLT; |
| 403 | cs->halted = 1; |
| 404 | cpu_loop_exit(cs); |
| 405 | #endif |
| 406 | } |
| 407 | |
| 408 | void HELPER(wfit)(CPUARMState *env, uint32_t rd) |
| 409 | { |
| 410 | #ifdef CONFIG_USER_ONLY |
| 411 | /* |
| 412 | * WFI in the user-mode emulator is technically permitted but not |
| 413 | * something any real-world code would do. AArch64 Linux kernels |
| 414 | * trap it via SCTRL_EL1.nTWI and make it an (expensive) NOP; |
| 415 | * AArch32 kernels don't trap it so it will delay a bit. |
| 416 | * For QEMU, make it NOP here, because trying to raise EXCP_HLT |
| 417 | * would trigger an abort. |
| 418 | */ |
| 419 | return; |
| 420 | #else |
| 421 | ARMCPU *cpu = env_archcpu(env); |
| 422 | CPUState *cs = env_cpu(env); |
| 423 | uint32_t excp; |
| 424 | int target_el = check_wfx_trap(env, false, &excp); |
| 425 | /* The WFIT should time out when CNTVCT_EL0 >= the specified value. */ |
| 426 | uint64_t cntval = gt_get_countervalue(env); |
| 427 | uint64_t timeout = env->xregs[rd]; |
| 428 | /* |
| 429 | * We want the value that we would get if we read CNTVCT_EL0 from |
| 430 | * the current exception level, so the direct_access offset, not |
| 431 | * the indirect_access one. Compare the pseudocode LocalTimeoutEvent(), |
| 432 | * which calls VirtualCounterTimer(). |
| 433 | */ |
| 434 | uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT); |
| 435 | uint64_t cntvct = cntval - offset; |
| 436 | uint64_t nexttick; |
| 437 | |
| 438 | if (cpu_has_work(cs) || cntvct >= timeout) { |
| 439 | /* |
| 440 | * Don't bother to go into our "low power state" if |
| 441 | * we would just wake up immediately. |
| 442 | */ |
| 443 | return; |
| 444 | } |
| 445 | |
| 446 | if (target_el) { |
| 447 | env->pc -= 4; |
| 448 | raise_exception(env, excp, syn_wfx(1, 0xe, rd, true, WFIT, false), target_el); |
| 449 | } |
| 450 | |
| 451 | if (uadd64_overflow(timeout, offset, &nexttick)) { |
| 452 | nexttick = UINT64_MAX; |
| 453 | } |
| 454 | if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { |
| 455 | /* |
| 456 | * If the timeout is too long for the signed 64-bit range |
| 457 | * of a QEMUTimer, let it expire early. |
| 458 | */ |
| 459 | timer_mod_ns(cpu->wfxt_timer, INT64_MAX); |
| 460 | } else { |
| 461 | timer_mod(cpu->wfxt_timer, nexttick); |
| 462 | } |
| 463 | env->halt_reason = HALT_WFI; |
| 464 | cs->exception_index = EXCP_HLT; |
| 465 | cs->halted = 1; |
| 466 | cpu_loop_exit(cs); |
| 467 | #endif |
| 468 | } |
| 469 | |
| 470 | void HELPER(sev)(CPUARMState *env) |
| 471 | { |
| 472 | CPUState *cs = env_cpu(env); |
| 473 | CPU_FOREACH(cs) { |
| 474 | ARMCPU *target_cpu = ARM_CPU(cs); |
| 475 | target_cpu->env.event_register = true; |
| 476 | if (!qemu_cpu_is_self(cs)) { |
| 477 | qemu_cpu_kick(cs); |
| 478 | } |
| 479 | } |
| 480 | } |
| 481 | |
| 482 | #ifndef CONFIG_USER_ONLY |
| 483 | /* |
| 484 | * Event Stream events don't do anything apart from wake up sleeping |
| 485 | * cores. These helpers calculate the next event stream event time so |
| 486 | * the WFE helper can decide when its next wake up tick will be. |
| 487 | */ |
| 488 | static int64_t gt_recalc_one_evt(CPUARMState *env, uint32_t control, uint64_t offset) |
| 489 | { |
| 490 | ARMCPU *cpu = env_archcpu(env); |
| 491 | bool evnten = FIELD_EX32(control, CNTxCTL, EVNTEN); |
| 492 | |
| 493 | if (evnten) { |
| 494 | int evnti = FIELD_EX32(control, CNTxCTL, EVNTI); |
| 495 | bool evntis = FIELD_EX32(control, CNTxCTL, EVNTIS); |
| 496 | bool evntdir = FIELD_EX32(control, CNTxCTL, EVNTDIR); |
| 497 | /* |
| 498 | * To figure out when the next event timer should fire we need |
| 499 | * to calculate which bit of the counter we want to flip and |
| 500 | * which transition counts. |
| 501 | * |
| 502 | * So we calculate 1 << bit - current lower bits and then add |
| 503 | * 1 << bit if the bit needs to flip twice to meet evntdir |
| 504 | */ |
| 505 | int bit = evntis ? evnti + 8 : evnti; |
| 506 | uint64_t count = gt_get_countervalue(env) - offset; |
| 507 | uint64_t target_bit = BIT_ULL(bit); |
| 508 | uint64_t lower_bits = MAKE_64BIT_MASK(0, bit - 1); |
| 509 | uint64_t next_tick = target_bit - (count & lower_bits); |
| 510 | uint64_t abstick; |
| 511 | |
| 512 | /* do we need to bit flip twice? */ |
| 513 | if (((count & target_bit) != 0) ^ evntdir) { |
| 514 | next_tick += target_bit; |
| 515 | } |
| 516 | |
| 517 | /* |
| 518 | * Note that the desired next expiry time might be beyond the |
| 519 | * signed-64-bit range of a QEMUTimer -- in this case we just |
| 520 | * set the timer for as far in the future as possible. When the |
| 521 | * timer expires we will reset the timer for any remaining period. |
| 522 | */ |
| 523 | if (uadd64_overflow(next_tick, offset, &abstick)) { |
| 524 | abstick = UINT64_MAX; |
| 525 | } |
| 526 | if (abstick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { |
| 527 | return INT64_MAX; |
| 528 | } else { |
| 529 | return abstick; |
| 530 | } |
| 531 | } |
| 532 | |
| 533 | return -1; |
| 534 | } |
| 535 | |
| 536 | /* |
| 537 | * Calculate the next event stream time and return it. Returns -1 if |
| 538 | * no event streams are enabled. It is up to the WFE helpers to decide |
| 539 | * on the next time. |
| 540 | */ |
| 541 | static int64_t gt_calc_next_event_stream(CPUARMState *env) |
| 542 | { |
| 543 | ARMCPU *cpu = env_archcpu(env); |
| 544 | uint64_t hcr = arm_hcr_el2_eff(env); |
| 545 | int64_t next_time = -1; |
| 546 | uint64_t offset; |
| 547 | |
| 548 | /* Unless we are missing EL2 this can generate events */ |
| 549 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
| 550 | offset = gt_direct_access_timer_offset(env, GTIMER_PHYS); |
| 551 | next_time = gt_recalc_one_evt(env, env->cp15.cnthctl_el2, offset); |
| 552 | } |
| 553 | |
| 554 | /* Event stream events from virtual counter enabled? */ |
| 555 | if (!cpu_isar_feature(aa64_vh, cpu) || |
| 556 | !((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE))) { |
| 557 | int64_t next_virt_time; |
| 558 | offset = gt_direct_access_timer_offset(env, GTIMER_VIRT); |
| 559 | next_virt_time = gt_recalc_one_evt(env, env->cp15.c14_cntkctl, offset); |
| 560 | |
| 561 | /* is this earlier than the next physical event? */ |
| 562 | if (next_virt_time > 0) { |
| 563 | if (next_time < 0 || next_virt_time < next_time) { |
| 564 | next_time = next_virt_time; |
| 565 | } |
| 566 | } |
| 567 | } |
| 568 | |
| 569 | return next_time; |
| 570 | } |
| 571 | #endif |
| 572 | |
| 573 | void HELPER(wfe)(CPUARMState *env, uint32_t insn_len) |
| 574 | { |
| 575 | #ifdef CONFIG_USER_ONLY |
| 576 | /* |
| 577 | * WFE in the user-mode emulator is a NOP. Real-world user-mode code |
| 578 | * shouldn't execute WFE, but if it does, we make it a NOP rather than |
| 579 | * aborting when we try to raise EXCP_HLT. |
| 580 | */ |
| 581 | return; |
| 582 | #else |
| 583 | /* |
| 584 | * WFE (Wait For Event) is a hint instruction. |
| 585 | * |
| 586 | * 1. Check the Event Register (set by SEV or SEVONPEND). |
| 587 | * 2. If set, clear it and continue (consume the event). |
| 588 | */ |
| 589 | CPUState *cs = env_cpu(env); |
| 590 | ARMCPU *cpu = env_archcpu(env); |
| 591 | uint32_t excp; |
| 592 | int target_el; |
| 593 | |
| 594 | if (qatomic_xchg(&env->event_register, false)) { |
| 595 | return; |
| 596 | } |
| 597 | |
| 598 | /* We might sleep, so now we check to see if we should trap */ |
| 599 | target_el = check_wfx_trap(env, true, &excp); |
| 600 | if (target_el) { |
| 601 | if (env->aarch64) { |
| 602 | env->pc -= insn_len; |
| 603 | } else { |
| 604 | env->regs[15] -= insn_len; |
| 605 | } |
| 606 | raise_exception(env, excp, syn_wfx(1, 0xe, 0, false, WFE, insn_len == 2), |
| 607 | target_el); |
| 608 | } |
| 609 | |
| 610 | /* |
| 611 | * If the CPU has entered the exclusive region we could sleep |
| 612 | * until the global monitor moves from Exclusive to Open Access. |
| 613 | * However it would be expensive for QEMU to fully model the |
| 614 | * global monitor and not doing so would potentially trigger |
| 615 | * deadlocks in WFE enabled locking code. However as WFE is a hint |
| 616 | * instruction the architecture allows for the PE to leave |
| 617 | * low-power state for any reason. QEMU chooses to treat being in |
| 618 | * an exclusive region as such and return directly. |
| 619 | */ |
| 620 | if (env->exclusive_addr != -1) { |
| 621 | return; |
| 622 | } |
| 623 | |
| 624 | /* For A-profile we also can be woken by the event stream */ |
| 625 | if (cpu->wfxt_timer) { |
| 626 | int64_t next_event = gt_calc_next_event_stream(env); |
| 627 | if (next_event > 0) { |
| 628 | timer_mod(cpu->wfxt_timer, next_event); |
| 629 | } |
| 630 | } |
| 631 | |
| 632 | env->halt_reason = HALT_WFE; |
| 633 | cs->exception_index = EXCP_HLT; |
| 634 | cs->halted = 1; |
| 635 | cpu_loop_exit(cs); |
| 636 | #endif |
| 637 | } |
| 638 | |
| 639 | void HELPER(wfet)(CPUARMState *env, uint32_t rd) |
| 640 | { |
| 641 | #ifdef CONFIG_USER_ONLY |
| 642 | /* |
| 643 | * As for WFIT make it NOP here, because trying to raise EXCP_HLT |
| 644 | * would trigger an abort. |
| 645 | */ |
| 646 | return; |
| 647 | #else |
| 648 | CPUState *cs = env_cpu(env); |
| 649 | uint32_t excp; |
| 650 | int target_el; |
| 651 | ARMCPU *cpu; |
| 652 | uint64_t cntval, timeout, offset, cntvct, nexttick; |
| 653 | int64_t next_event; |
| 654 | |
| 655 | /* |
| 656 | * As for WFE if the event register is already set we can consume |
| 657 | * the event and return immediately. |
| 658 | */ |
| 659 | if (qatomic_xchg(&env->event_register, false)) { |
| 660 | return; |
| 661 | } |
| 662 | |
| 663 | /* |
| 664 | * Don't bother to go into our "low power state" if |
| 665 | * we would just wake up immediately. |
| 666 | * |
| 667 | * We want the value that we would get if we read CNTVCT_EL0 from |
| 668 | * the current exception level, so the direct_access offset, not |
| 669 | * the indirect_access one. Compare the pseudocode LocalTimeoutEvent(), |
| 670 | * which calls VirtualCounterTimer(). |
| 671 | */ |
| 672 | cntval = gt_get_countervalue(env); |
| 673 | offset = gt_direct_access_timer_offset(env, GTIMER_VIRT); |
| 674 | cntvct = cntval - offset; |
| 675 | timeout = env->xregs[rd]; |
| 676 | if (cpu_has_work(cs) || cntvct >= timeout) { |
| 677 | return; |
| 678 | } |
| 679 | |
| 680 | /* We might sleep, so now we check to see if we should trap */ |
| 681 | target_el = check_wfx_trap(env, true, &excp); |
| 682 | if (target_el) { |
| 683 | env->pc -= 4; |
| 684 | raise_exception(env, excp, syn_wfx(1, 0xe, rd, true, WFET, false), target_el); |
| 685 | } |
| 686 | |
| 687 | /* |
| 688 | * If the CPU has entered the exclusive region we could sleep |
| 689 | * until the global monitor moves from Exclusive to Open Access. |
| 690 | * However it would be expensive for QEMU to fully model the |
| 691 | * global monitor and not doing so would potentially trigger |
| 692 | * deadlocks in WFE enabled locking code. However as WFE is a hint |
| 693 | * instruction the architecture allows for the PE to leave |
| 694 | * low-power state for any reason. QEMU chooses to treat being in |
| 695 | * an exclusive region as such and return directly. |
| 696 | */ |
| 697 | if (env->exclusive_addr != -1) { |
| 698 | return; |
| 699 | } |
| 700 | |
| 701 | /* |
| 702 | * Finally work out if the timeout or event stream will kick in |
| 703 | * earlier. |
| 704 | * |
| 705 | * The WFET should time out when CNTVCT_EL0 >= the specified value. |
| 706 | */ |
| 707 | cpu = env_archcpu(env); |
| 708 | if (uadd64_overflow(timeout, offset, &nexttick)) { |
| 709 | nexttick = UINT64_MAX; |
| 710 | } |
| 711 | if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { |
| 712 | nexttick = INT64_MAX; |
| 713 | } |
| 714 | |
| 715 | next_event = gt_calc_next_event_stream(env); |
| 716 | if (next_event > 0 && next_event < nexttick) { |
| 717 | timer_mod(cpu->wfxt_timer, next_event); |
| 718 | } else { |
| 719 | if (nexttick == INT64_MAX) { |
| 720 | timer_mod_ns(cpu->wfxt_timer, INT64_MAX); |
| 721 | } else { |
| 722 | timer_mod(cpu->wfxt_timer, nexttick); |
| 723 | } |
| 724 | } |
| 725 | |
| 726 | env->halt_reason = HALT_WFE; |
| 727 | cs->exception_index = EXCP_HLT; |
| 728 | cs->halted = 1; |
| 729 | cpu_loop_exit(cs); |
| 730 | #endif |
| 731 | } |
| 732 | |
| 733 | void HELPER(yield)(CPUARMState *env) |
| 734 | { |
| 735 | CPUState *cs = env_cpu(env); |
| 736 | |
| 737 | /* This is a non-trappable hint instruction that generally indicates |
| 738 | * that the guest is currently busy-looping. Yield control back to the |
| 739 | * top level loop so that a more deserving VCPU has a chance to run. |
| 740 | */ |
| 741 | cs->exception_index = EXCP_YIELD; |
| 742 | cpu_loop_exit(cs); |
| 743 | } |
| 744 | |
| 745 | /* Raise an internal-to-QEMU exception. This is limited to only |
| 746 | * those EXCP values which are special cases for QEMU to interrupt |
| 747 | * execution and not to be used for exceptions which are passed to |
| 748 | * the guest (those must all have syndrome information and thus should |
| 749 | * use exception_with_syndrome*). |
| 750 | */ |
| 751 | void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) |
| 752 | { |
| 753 | CPUState *cs = env_cpu(env); |
| 754 | |
| 755 | assert(excp_is_internal(excp)); |
| 756 | cs->exception_index = excp; |
| 757 | cpu_loop_exit(cs); |
| 758 | } |
| 759 | |
| 760 | /* Raise an exception with the specified syndrome register value */ |
| 761 | void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp, |
| 762 | uint32_t syndrome, uint32_t target_el) |
| 763 | { |
| 764 | raise_exception(env, excp, syndrome, target_el); |
| 765 | } |
| 766 | |
| 767 | /* |
| 768 | * Raise an exception with the specified syndrome register value |
| 769 | * to the default target el. |
| 770 | */ |
| 771 | void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, |
| 772 | uint32_t syndrome) |
| 773 | { |
| 774 | raise_exception(env, excp, syndrome, exception_target_el(env)); |
| 775 | } |
| 776 | |
| 777 | uint32_t HELPER(cpsr_read)(CPUARMState *env) |
| 778 | { |
| 779 | return cpsr_read(env) & ~CPSR_EXEC; |
| 780 | } |
| 781 | |
| 782 | void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) |
| 783 | { |
| 784 | cpsr_write(env, val, mask, CPSRWriteByInstr); |
| 785 | /* TODO: Not all cpsr bits are relevant to hflags. */ |
| 786 | arm_rebuild_hflags(env); |
| 787 | } |
| 788 | |
| 789 | /* Write the CPSR for a 32-bit exception return */ |
| 790 | void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) |
| 791 | { |
| 792 | uint32_t mask; |
| 793 | |
| 794 | bql_lock(); |
| 795 | arm_call_pre_el_change_hook(env_archcpu(env)); |
| 796 | bql_unlock(); |
| 797 | |
| 798 | mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar); |
| 799 | cpsr_write(env, val, mask, CPSRWriteExceptionReturn); |
| 800 | |
| 801 | /* Generated code has already stored the new PC value, but |
| 802 | * without masking out its low bits, because which bits need |
| 803 | * masking depends on whether we're returning to Thumb or ARM |
| 804 | * state. Do the masking now. |
| 805 | */ |
| 806 | env->regs[15] &= (env->thumb ? ~1 : ~3); |
| 807 | arm_rebuild_hflags(env); |
| 808 | |
| 809 | bql_lock(); |
| 810 | arm_call_el_change_hook(env_archcpu(env)); |
| 811 | bql_unlock(); |
| 812 | } |
| 813 | |
| 814 | /* Access to user mode registers from privileged modes. */ |
| 815 | uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno) |
| 816 | { |
| 817 | uint32_t val; |
| 818 | |
| 819 | if (regno == 13) { |
| 820 | val = env->banked_r13[BANK_USRSYS]; |
| 821 | } else if (regno == 14) { |
| 822 | val = env->banked_r14[BANK_USRSYS]; |
| 823 | } else if (regno >= 8 |
| 824 | && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { |
| 825 | val = env->usr_regs[regno - 8]; |
| 826 | } else { |
| 827 | val = env->regs[regno]; |
| 828 | } |
| 829 | return val; |
| 830 | } |
| 831 | |
| 832 | void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val) |
| 833 | { |
| 834 | if (regno == 13) { |
| 835 | env->banked_r13[BANK_USRSYS] = val; |
| 836 | } else if (regno == 14) { |
| 837 | env->banked_r14[BANK_USRSYS] = val; |
| 838 | } else if (regno >= 8 |
| 839 | && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { |
| 840 | env->usr_regs[regno - 8] = val; |
| 841 | } else { |
| 842 | env->regs[regno] = val; |
| 843 | } |
| 844 | } |
| 845 | |
| 846 | void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) |
| 847 | { |
| 848 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
| 849 | env->regs[13] = val; |
| 850 | } else { |
| 851 | env->banked_r13[bank_number(mode)] = val; |
| 852 | } |
| 853 | } |
| 854 | |
| 855 | uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
| 856 | { |
| 857 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { |
| 858 | /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF. |
| 859 | * Other UNPREDICTABLE and UNDEF cases were caught at translate time. |
| 860 | */ |
| 861 | raise_exception(env, EXCP_UDEF, syn_uncategorized(), |
| 862 | exception_target_el(env)); |
| 863 | } |
| 864 | |
| 865 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
| 866 | return env->regs[13]; |
| 867 | } else { |
| 868 | return env->banked_r13[bank_number(mode)]; |
| 869 | } |
| 870 | } |
| 871 | |
| 872 | static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode, |
| 873 | uint32_t regno) |
| 874 | { |
| 875 | /* Raise an exception if the requested access is one of the UNPREDICTABLE |
| 876 | * cases; otherwise return. This broadly corresponds to the pseudocode |
| 877 | * BankedRegisterAccessValid() and SPSRAccessValid(), |
| 878 | * except that we have already handled some cases at translate time. |
| 879 | */ |
| 880 | int curmode = env->uncached_cpsr & CPSR_M; |
| 881 | |
| 882 | if (tgtmode == ARM_CPU_MODE_HYP) { |
| 883 | /* |
| 884 | * Handle Hyp target regs first because some are special cases |
| 885 | * which don't want the usual "not accessible from tgtmode" check. |
| 886 | */ |
| 887 | switch (regno) { |
| 888 | case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */ |
| 889 | if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) { |
| 890 | goto undef; |
| 891 | } |
| 892 | break; |
| 893 | case 13: |
| 894 | if (curmode != ARM_CPU_MODE_MON) { |
| 895 | goto undef; |
| 896 | } |
| 897 | break; |
| 898 | default: |
| 899 | g_assert_not_reached(); |
| 900 | } |
| 901 | return; |
| 902 | } |
| 903 | |
| 904 | if (curmode == tgtmode) { |
| 905 | goto undef; |
| 906 | } |
| 907 | |
| 908 | if (tgtmode == ARM_CPU_MODE_USR) { |
| 909 | switch (regno) { |
| 910 | case 8 ... 12: |
| 911 | if (curmode != ARM_CPU_MODE_FIQ) { |
| 912 | goto undef; |
| 913 | } |
| 914 | break; |
| 915 | case 13: |
| 916 | if (curmode == ARM_CPU_MODE_SYS) { |
| 917 | goto undef; |
| 918 | } |
| 919 | break; |
| 920 | case 14: |
| 921 | if (curmode == ARM_CPU_MODE_HYP || curmode == ARM_CPU_MODE_SYS) { |
| 922 | goto undef; |
| 923 | } |
| 924 | break; |
| 925 | default: |
| 926 | break; |
| 927 | } |
| 928 | } |
| 929 | |
| 930 | return; |
| 931 | |
| 932 | undef: |
| 933 | raise_exception(env, EXCP_UDEF, syn_uncategorized(), |
| 934 | exception_target_el(env)); |
| 935 | } |
| 936 | |
| 937 | void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode, |
| 938 | uint32_t regno) |
| 939 | { |
| 940 | msr_mrs_banked_exc_checks(env, tgtmode, regno); |
| 941 | |
| 942 | switch (regno) { |
| 943 | case 16: /* SPSRs */ |
| 944 | if (tgtmode == (env->uncached_cpsr & CPSR_M)) { |
| 945 | /* Only happens for SPSR_Hyp access in Hyp mode */ |
| 946 | env->spsr = value; |
| 947 | } else { |
| 948 | env->banked_spsr[bank_number(tgtmode)] = value; |
| 949 | } |
| 950 | break; |
| 951 | case 17: /* ELR_Hyp */ |
| 952 | env->elr_el[2] = value; |
| 953 | break; |
| 954 | case 13: |
| 955 | env->banked_r13[bank_number(tgtmode)] = value; |
| 956 | break; |
| 957 | case 14: |
| 958 | env->banked_r14[r14_bank_number(tgtmode)] = value; |
| 959 | break; |
| 960 | case 8 ... 12: |
| 961 | switch (tgtmode) { |
| 962 | case ARM_CPU_MODE_USR: |
| 963 | env->usr_regs[regno - 8] = value; |
| 964 | break; |
| 965 | case ARM_CPU_MODE_FIQ: |
| 966 | env->fiq_regs[regno - 8] = value; |
| 967 | break; |
| 968 | default: |
| 969 | g_assert_not_reached(); |
| 970 | } |
| 971 | break; |
| 972 | default: |
| 973 | g_assert_not_reached(); |
| 974 | } |
| 975 | } |
| 976 | |
| 977 | uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno) |
| 978 | { |
| 979 | msr_mrs_banked_exc_checks(env, tgtmode, regno); |
| 980 | |
| 981 | switch (regno) { |
| 982 | case 16: /* SPSRs */ |
| 983 | if (tgtmode == (env->uncached_cpsr & CPSR_M)) { |
| 984 | /* Only happens for SPSR_Hyp access in Hyp mode */ |
| 985 | return env->spsr; |
| 986 | } else { |
| 987 | return env->banked_spsr[bank_number(tgtmode)]; |
| 988 | } |
| 989 | case 17: /* ELR_Hyp */ |
| 990 | return env->elr_el[2]; |
| 991 | case 13: |
| 992 | return env->banked_r13[bank_number(tgtmode)]; |
| 993 | case 14: |
| 994 | return env->banked_r14[r14_bank_number(tgtmode)]; |
| 995 | case 8 ... 12: |
| 996 | switch (tgtmode) { |
| 997 | case ARM_CPU_MODE_USR: |
| 998 | return env->usr_regs[regno - 8]; |
| 999 | case ARM_CPU_MODE_FIQ: |
| 1000 | return env->fiq_regs[regno - 8]; |
| 1001 | default: |
| 1002 | g_assert_not_reached(); |
| 1003 | } |
| 1004 | default: |
| 1005 | g_assert_not_reached(); |
| 1006 | } |
| 1007 | } |
| 1008 | |
| 1009 | const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, |
| 1010 | uint32_t syndrome, uint32_t isread) |
| 1011 | { |
| 1012 | ARMCPU *cpu = env_archcpu(env); |
| 1013 | const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, key); |
| 1014 | CPAccessResult res = CP_ACCESS_OK; |
| 1015 | int target_el; |
| 1016 | uint32_t excp; |
| 1017 | |
| 1018 | assert(ri != NULL); |
| 1019 | |
| 1020 | if (ri->accessfn) { |
| 1021 | res = ri->accessfn(env, ri, isread); |
| 1022 | } |
| 1023 | |
| 1024 | /* |
| 1025 | * If the access function indicates a trap from EL0 to EL1 then |
| 1026 | * that always takes priority over the HSTR_EL2 trap. (If it indicates |
| 1027 | * a trap to EL3, then the HSTR_EL2 trap takes priority; if it indicates |
| 1028 | * a trap to EL2, then the syndrome is the same either way so we don't |
| 1029 | * care whether technically the architecture says that HSTR_EL2 trap or |
| 1030 | * the other trap takes priority. So we take the "check HSTR_EL2" path |
| 1031 | * for all of those cases.) |
| 1032 | */ |
| 1033 | if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) < 2) && |
| 1034 | arm_current_el(env) == 0) { |
| 1035 | goto fail; |
| 1036 | } |
| 1037 | |
| 1038 | /* |
| 1039 | * HSTR_EL2 traps from EL1 are checked earlier, in generated code; |
| 1040 | * we only need to check here for traps from EL0. |
| 1041 | */ |
| 1042 | if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 && |
| 1043 | arm_is_el2_enabled(env) && |
| 1044 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
| 1045 | uint32_t mask = 1 << ri->crn; |
| 1046 | |
| 1047 | if (ri->type & ARM_CP_64BIT) { |
| 1048 | mask = 1 << ri->crm; |
| 1049 | } |
| 1050 | |
| 1051 | /* T4 and T14 are RES0 */ |
| 1052 | mask &= ~((1 << 4) | (1 << 14)); |
| 1053 | |
| 1054 | if (env->cp15.hstr_el2 & mask) { |
| 1055 | res = CP_ACCESS_TRAP_EL2; |
| 1056 | goto fail; |
| 1057 | } |
| 1058 | } |
| 1059 | |
| 1060 | /* |
| 1061 | * Fine-grained traps also are lower priority than undef-to-EL1, |
| 1062 | * higher priority than trap-to-EL3, and we don't care about priority |
| 1063 | * order with other EL2 traps because the syndrome value is the same. |
| 1064 | * |
| 1065 | * FGWTE3 traps are exclusively traps to EL3 on registers that are |
| 1066 | * only accessible to EL3, so there's no possibility of a trap to EL2. |
| 1067 | * So we can handle these checks here too. |
| 1068 | */ |
| 1069 | if (ri->fgt) { |
| 1070 | uint64_t trapword = 0; |
| 1071 | unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX); |
| 1072 | unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS); |
| 1073 | bool trapbit; |
| 1074 | |
| 1075 | if (ri->fgt & FGT_EXEC) { |
| 1076 | assert(idx < ARRAY_SIZE(env->cp15.fgt_exec)); |
| 1077 | trapword = env->cp15.fgt_exec[idx]; |
| 1078 | } else if (isread && (ri->fgt & FGT_R)) { |
| 1079 | assert(idx < ARRAY_SIZE(env->cp15.fgt_read)); |
| 1080 | trapword = env->cp15.fgt_read[idx]; |
| 1081 | } else if (!isread && (ri->fgt & FGT_W)) { |
| 1082 | assert(idx < ARRAY_SIZE(env->cp15.fgt_write)); |
| 1083 | trapword = env->cp15.fgt_write[idx]; |
| 1084 | } |
| 1085 | trapbit = extract64(trapword, bitpos, 1); |
| 1086 | |
| 1087 | if ((ri->access & ~PL3_RW) == 0) { |
| 1088 | /* |
| 1089 | * EL3 cpreg -- must be FGWTE3, and FGWTE3_EL3 can only be |
| 1090 | * set from AArch64, and if the feature is enabled. |
| 1091 | */ |
| 1092 | if (trapbit) { |
| 1093 | res = CP_ACCESS_TRAP_EL3; |
| 1094 | goto fail; |
| 1095 | } |
| 1096 | } else if (arm_fgt_active(env, arm_current_el(env))) { |
| 1097 | bool nxs = FIELD_EX32(ri->fgt, FGT, NXS); |
| 1098 | bool rev = FIELD_EX32(ri->fgt, FGT, REV); |
| 1099 | if (nxs && (arm_hcrx_el2_eff(env) & HCRX_FGTNXS)) { |
| 1100 | /* |
| 1101 | * If HCRX_EL2.FGTnXS is 1 then the fine-grained trap for |
| 1102 | * TLBI maintenance insns does *not* apply to the nXS variant. |
| 1103 | */ |
| 1104 | trapbit = 0; |
| 1105 | } |
| 1106 | if (trapbit != rev) { |
| 1107 | res = CP_ACCESS_TRAP_EL2; |
| 1108 | goto fail; |
| 1109 | } |
| 1110 | } |
| 1111 | } |
| 1112 | |
| 1113 | if (likely(res == CP_ACCESS_OK)) { |
| 1114 | return ri; |
| 1115 | } |
| 1116 | |
| 1117 | fail: |
| 1118 | excp = EXCP_UDEF; |
| 1119 | switch (res) { |
| 1120 | /* CP_ACCESS_TRAP* traps are always direct to a specified EL */ |
| 1121 | case CP_ACCESS_TRAP_EL3: |
| 1122 | /* |
| 1123 | * If EL3 is AArch32 then there's no syndrome register; the cases |
| 1124 | * where we would raise a SystemAccessTrap to AArch64 EL3 all become |
| 1125 | * raising a Monitor trap exception. (Because there's no visible |
| 1126 | * syndrome it doesn't matter what we pass to raise_exception().) |
| 1127 | */ |
| 1128 | if (!arm_el_is_aa64(env, 3)) { |
| 1129 | excp = EXCP_MON_TRAP; |
| 1130 | } |
| 1131 | break; |
| 1132 | case CP_ACCESS_TRAP_EL2: |
| 1133 | case CP_ACCESS_TRAP_EL1: |
| 1134 | break; |
| 1135 | case CP_ACCESS_UNDEFINED: |
| 1136 | /* CP_ACCESS_UNDEFINED is never direct to a specified EL */ |
| 1137 | if (cpu_isar_feature(aa64_ids, cpu) && isread && |
| 1138 | arm_cpreg_in_idspace(ri)) { |
| 1139 | /* |
| 1140 | * FEAT_IDST says this should be reported as EC_SYSTEMREGISTERTRAP, |
| 1141 | * not EC_UNCATEGORIZED |
| 1142 | */ |
| 1143 | break; |
| 1144 | } |
| 1145 | syndrome = syn_uncategorized(); |
| 1146 | break; |
| 1147 | case CP_ACCESS_EXLOCK: |
| 1148 | /* |
| 1149 | * CP_ACCESS_EXLOCK is always directed to the current EL, |
| 1150 | * which is going to be the same as the usual target EL. |
| 1151 | */ |
| 1152 | syndrome = syn_gcs_exlock(); |
| 1153 | break; |
| 1154 | default: |
| 1155 | g_assert_not_reached(); |
| 1156 | } |
| 1157 | |
| 1158 | target_el = res & CP_ACCESS_EL_MASK; |
| 1159 | switch (target_el) { |
| 1160 | case 0: |
| 1161 | target_el = exception_target_el(env); |
| 1162 | break; |
| 1163 | case 1: |
| 1164 | assert(arm_current_el(env) < 2); |
| 1165 | break; |
| 1166 | case 2: |
| 1167 | assert(arm_current_el(env) != 3); |
| 1168 | assert(arm_is_el2_enabled(env)); |
| 1169 | break; |
| 1170 | case 3: |
| 1171 | assert(arm_feature(env, ARM_FEATURE_EL3)); |
| 1172 | break; |
| 1173 | default: |
| 1174 | g_assert_not_reached(); |
| 1175 | } |
| 1176 | |
| 1177 | raise_exception(env, excp, syndrome, target_el); |
| 1178 | } |
| 1179 | |
| 1180 | const void *HELPER(lookup_cp_reg)(CPUARMState *env, uint32_t key) |
| 1181 | { |
| 1182 | ARMCPU *cpu = env_archcpu(env); |
| 1183 | const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, key); |
| 1184 | |
| 1185 | assert(ri != NULL); |
| 1186 | return ri; |
| 1187 | } |
| 1188 | |
| 1189 | /* |
| 1190 | * Test for HCR_EL2.TIDCP at EL1. |
| 1191 | * Since implementation defined registers are rare, and within QEMU |
| 1192 | * most of them are no-op, do not waste HFLAGS space for this and |
| 1193 | * always use a helper. |
| 1194 | */ |
| 1195 | void HELPER(tidcp_el1)(CPUARMState *env, uint32_t syndrome) |
| 1196 | { |
| 1197 | if (arm_hcr_el2_eff(env) & HCR_TIDCP) { |
| 1198 | raise_exception_ra(env, EXCP_UDEF, syndrome, 2, GETPC()); |
| 1199 | } |
| 1200 | } |
| 1201 | |
| 1202 | /* |
| 1203 | * Similarly, for FEAT_TIDCP1 at EL0. |
| 1204 | * We have already checked for the presence of the feature. |
| 1205 | */ |
| 1206 | void HELPER(tidcp_el0)(CPUARMState *env, uint32_t syndrome) |
| 1207 | { |
| 1208 | /* See arm_sctlr(), but we also need the sctlr el. */ |
| 1209 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); |
| 1210 | int target_el; |
| 1211 | |
| 1212 | switch (mmu_idx) { |
| 1213 | case ARMMMUIdx_E20_0: |
| 1214 | target_el = 2; |
| 1215 | break; |
| 1216 | case ARMMMUIdx_E30_0: |
| 1217 | target_el = 3; |
| 1218 | break; |
| 1219 | default: |
| 1220 | target_el = 1; |
| 1221 | break; |
| 1222 | } |
| 1223 | |
| 1224 | /* |
| 1225 | * The bit is not valid unless the target el is aa64, but since the |
| 1226 | * bit test is simpler perform that first and check validity after. |
| 1227 | */ |
| 1228 | if ((env->cp15.sctlr_el[target_el] & SCTLR_TIDCP) |
| 1229 | && arm_el_is_aa64(env, target_el)) { |
| 1230 | raise_exception_ra(env, EXCP_UDEF, syndrome, target_el, GETPC()); |
| 1231 | } |
| 1232 | } |
| 1233 | |
| 1234 | void HELPER(set_cp_reg)(CPUARMState *env, const void *rip, uint32_t value) |
| 1235 | { |
| 1236 | const ARMCPRegInfo *ri = rip; |
| 1237 | |
| 1238 | if (ri->type & ARM_CP_IO) { |
| 1239 | bql_lock(); |
| 1240 | ri->writefn(env, ri, value); |
| 1241 | bql_unlock(); |
| 1242 | } else { |
| 1243 | ri->writefn(env, ri, value); |
| 1244 | } |
| 1245 | } |
| 1246 | |
| 1247 | uint32_t HELPER(get_cp_reg)(CPUARMState *env, const void *rip) |
| 1248 | { |
| 1249 | const ARMCPRegInfo *ri = rip; |
| 1250 | uint32_t res; |
| 1251 | |
| 1252 | if (ri->type & ARM_CP_IO) { |
| 1253 | bql_lock(); |
| 1254 | res = ri->readfn(env, ri); |
| 1255 | bql_unlock(); |
| 1256 | } else { |
| 1257 | res = ri->readfn(env, ri); |
| 1258 | } |
| 1259 | |
| 1260 | return res; |
| 1261 | } |
| 1262 | |
| 1263 | void HELPER(set_cp_reg64)(CPUARMState *env, const void *rip, uint64_t value) |
| 1264 | { |
| 1265 | const ARMCPRegInfo *ri = rip; |
| 1266 | |
| 1267 | if (ri->type & ARM_CP_IO) { |
| 1268 | bql_lock(); |
| 1269 | ri->writefn(env, ri, value); |
| 1270 | bql_unlock(); |
| 1271 | } else { |
| 1272 | ri->writefn(env, ri, value); |
| 1273 | } |
| 1274 | } |
| 1275 | |
| 1276 | uint64_t HELPER(get_cp_reg64)(CPUARMState *env, const void *rip) |
| 1277 | { |
| 1278 | const ARMCPRegInfo *ri = rip; |
| 1279 | uint64_t res; |
| 1280 | |
| 1281 | if (ri->type & ARM_CP_IO) { |
| 1282 | bql_lock(); |
| 1283 | res = ri->readfn(env, ri); |
| 1284 | bql_unlock(); |
| 1285 | } else { |
| 1286 | res = ri->readfn(env, ri); |
| 1287 | } |
| 1288 | |
| 1289 | return res; |
| 1290 | } |
| 1291 | |
| 1292 | void HELPER(pre_hvc)(CPUARMState *env) |
| 1293 | { |
| 1294 | ARMCPU *cpu = env_archcpu(env); |
| 1295 | int cur_el = arm_current_el(env); |
| 1296 | /* FIXME: Use actual secure state. */ |
| 1297 | bool secure = false; |
| 1298 | bool undef; |
| 1299 | |
| 1300 | if (arm_is_psci_call(cpu, EXCP_HVC)) { |
| 1301 | /* If PSCI is enabled and this looks like a valid PSCI call then |
| 1302 | * that overrides the architecturally mandated HVC behaviour. |
| 1303 | */ |
| 1304 | return; |
| 1305 | } |
| 1306 | |
| 1307 | if (!arm_feature(env, ARM_FEATURE_EL2)) { |
| 1308 | /* If EL2 doesn't exist, HVC always UNDEFs */ |
| 1309 | undef = true; |
| 1310 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { |
| 1311 | /* EL3.HCE has priority over EL2.HCD. */ |
| 1312 | undef = !(env->cp15.scr_el3 & SCR_HCE); |
| 1313 | } else { |
| 1314 | undef = env->cp15.hcr_el2 & HCR_HCD; |
| 1315 | } |
| 1316 | |
| 1317 | /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state. |
| 1318 | * For ARMv8/AArch64, HVC is allowed in EL3. |
| 1319 | * Note that we've already trapped HVC from EL0 at translation |
| 1320 | * time. |
| 1321 | */ |
| 1322 | if (secure && (!is_a64(env) || cur_el == 1)) { |
| 1323 | undef = true; |
| 1324 | } |
| 1325 | |
| 1326 | if (undef) { |
| 1327 | raise_exception(env, EXCP_UDEF, syn_uncategorized(), |
| 1328 | exception_target_el(env)); |
| 1329 | } |
| 1330 | } |
| 1331 | |
| 1332 | void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) |
| 1333 | { |
| 1334 | ARMCPU *cpu = env_archcpu(env); |
| 1335 | int cur_el = arm_current_el(env); |
| 1336 | bool secure = arm_is_secure(env); |
| 1337 | bool smd_flag = env->cp15.scr_el3 & SCR_SMD; |
| 1338 | |
| 1339 | /* |
| 1340 | * SMC behaviour is summarized in the following table. |
| 1341 | * This helper handles the "Trap to EL2" and "Undef insn" cases. |
| 1342 | * The "Trap to EL3" and "PSCI call" cases are handled in the exception |
| 1343 | * helper. |
| 1344 | * |
| 1345 | * -> ARM_FEATURE_EL3 and !SMD |
| 1346 | * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 |
| 1347 | * |
| 1348 | * Conduit SMC, valid call Trap to EL2 PSCI Call |
| 1349 | * Conduit SMC, inval call Trap to EL2 Trap to EL3 |
| 1350 | * Conduit not SMC Trap to EL2 Trap to EL3 |
| 1351 | * |
| 1352 | * |
| 1353 | * -> ARM_FEATURE_EL3 and SMD |
| 1354 | * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 |
| 1355 | * |
| 1356 | * Conduit SMC, valid call Trap to EL2 PSCI Call |
| 1357 | * Conduit SMC, inval call Trap to EL2 Undef insn |
| 1358 | * Conduit not SMC Trap to EL2 Undef insn |
| 1359 | * |
| 1360 | * |
| 1361 | * -> !ARM_FEATURE_EL3 |
| 1362 | * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 |
| 1363 | * |
| 1364 | * Conduit SMC, valid call Trap to EL2 PSCI Call |
| 1365 | * Conduit SMC, inval call Trap to EL2 Undef insn |
| 1366 | * Conduit not SMC Undef or trap[1] Undef insn |
| 1367 | * |
| 1368 | * [1] In this case: |
| 1369 | * - if HCR_EL2.NV == 1 we must trap to EL2 |
| 1370 | * - if HCR_EL2.NV == 0 then newer architecture revisions permit |
| 1371 | * AArch64 (but not AArch32) to trap to EL2 as an IMPDEF choice |
| 1372 | * - otherwise we must UNDEF |
| 1373 | * We take the IMPDEF choice to always UNDEF if HCR_EL2.NV == 0. |
| 1374 | */ |
| 1375 | |
| 1376 | /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state. |
| 1377 | * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization |
| 1378 | * extensions, SMD only applies to NS state. |
| 1379 | * On ARMv7 without the Virtualization extensions, the SMD bit |
| 1380 | * doesn't exist, but we forbid the guest to set it to 1 in scr_write(), |
| 1381 | * so we need not special case this here. |
| 1382 | */ |
| 1383 | bool smd = arm_feature(env, ARM_FEATURE_AARCH64) ? smd_flag |
| 1384 | : smd_flag && !secure; |
| 1385 | |
| 1386 | if (!arm_feature(env, ARM_FEATURE_EL3) && |
| 1387 | !(arm_hcr_el2_eff(env) & HCR_NV) && |
| 1388 | cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { |
| 1389 | /* |
| 1390 | * If we have no EL3 then traditionally SMC always UNDEFs and can't be |
| 1391 | * trapped to EL2. For nested virtualization, SMC can be trapped to |
| 1392 | * the outer hypervisor. PSCI-via-SMC is a sort of ersatz EL3 |
| 1393 | * firmware within QEMU, and we want an EL2 guest to be able |
| 1394 | * to forbid its EL1 from making PSCI calls into QEMU's |
| 1395 | * "firmware" via HCR.TSC, so for these purposes treat |
| 1396 | * PSCI-via-SMC as implying an EL3. |
| 1397 | * This handles the very last line of the previous table. |
| 1398 | */ |
| 1399 | raise_exception(env, EXCP_UDEF, syn_uncategorized(), |
| 1400 | exception_target_el(env)); |
| 1401 | } |
| 1402 | |
| 1403 | if (cur_el == 1 && (arm_hcr_el2_eff(env) & HCR_TSC)) { |
| 1404 | /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. |
| 1405 | * We also want an EL2 guest to be able to forbid its EL1 from |
| 1406 | * making PSCI calls into QEMU's "firmware" via HCR.TSC. |
| 1407 | * This handles all the "Trap to EL2" cases of the previous table. |
| 1408 | */ |
| 1409 | raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); |
| 1410 | } |
| 1411 | |
| 1412 | /* Catch the two remaining "Undef insn" cases of the previous table: |
| 1413 | * - PSCI conduit is SMC but we don't have a valid PCSI call, |
| 1414 | * - We don't have EL3 or SMD is set. |
| 1415 | */ |
| 1416 | if (!arm_is_psci_call(cpu, EXCP_SMC) && |
| 1417 | (smd || !arm_feature(env, ARM_FEATURE_EL3))) { |
| 1418 | raise_exception(env, EXCP_UDEF, syn_uncategorized(), |
| 1419 | exception_target_el(env)); |
| 1420 | } |
| 1421 | } |
| 1422 | |
| 1423 | /* ??? Flag setting arithmetic is awkward because we need to do comparisons. |
| 1424 | The only way to do that in TCG is a conditional branch, which clobbers |
| 1425 | all our temporaries. For now implement these as helper functions. */ |
| 1426 | |
| 1427 | /* Similarly for variable shift instructions. */ |
| 1428 | |
| 1429 | uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i) |
| 1430 | { |
| 1431 | int shift = i & 0xff; |
| 1432 | if (shift >= 32) { |
| 1433 | if (shift == 32) |
| 1434 | env->CF = x & 1; |
| 1435 | else |
| 1436 | env->CF = 0; |
| 1437 | return 0; |
| 1438 | } else if (shift != 0) { |
| 1439 | env->CF = (x >> (32 - shift)) & 1; |
| 1440 | return x << shift; |
| 1441 | } |
| 1442 | return x; |
| 1443 | } |
| 1444 | |
| 1445 | uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i) |
| 1446 | { |
| 1447 | int shift = i & 0xff; |
| 1448 | if (shift >= 32) { |
| 1449 | if (shift == 32) |
| 1450 | env->CF = (x >> 31) & 1; |
| 1451 | else |
| 1452 | env->CF = 0; |
| 1453 | return 0; |
| 1454 | } else if (shift != 0) { |
| 1455 | env->CF = (x >> (shift - 1)) & 1; |
| 1456 | return x >> shift; |
| 1457 | } |
| 1458 | return x; |
| 1459 | } |
| 1460 | |
| 1461 | uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i) |
| 1462 | { |
| 1463 | int shift = i & 0xff; |
| 1464 | if (shift >= 32) { |
| 1465 | env->CF = (x >> 31) & 1; |
| 1466 | return (int32_t)x >> 31; |
| 1467 | } else if (shift != 0) { |
| 1468 | env->CF = (x >> (shift - 1)) & 1; |
| 1469 | return (int32_t)x >> shift; |
| 1470 | } |
| 1471 | return x; |
| 1472 | } |
| 1473 | |
| 1474 | uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i) |
| 1475 | { |
| 1476 | int shift1, shift; |
| 1477 | shift1 = i & 0xff; |
| 1478 | shift = shift1 & 0x1f; |
| 1479 | if (shift == 0) { |
| 1480 | if (shift1 != 0) |
| 1481 | env->CF = (x >> 31) & 1; |
| 1482 | return x; |
| 1483 | } else { |
| 1484 | env->CF = (x >> (shift - 1)) & 1; |
| 1485 | return ((uint32_t)x >> shift) | (x << (32 - shift)); |
| 1486 | } |
| 1487 | } |
| 1488 | |
| 1489 | void HELPER(probe_access)(CPUARMState *env, vaddr ptr, |
| 1490 | uint32_t access_type, uint32_t mmu_idx, |
| 1491 | uint32_t size) |
| 1492 | { |
| 1493 | uint32_t in_page = -((uint32_t)ptr | TARGET_PAGE_SIZE); |
| 1494 | uintptr_t ra = GETPC(); |
| 1495 | |
| 1496 | if (likely(size <= in_page)) { |
| 1497 | probe_access(env, ptr, size, access_type, mmu_idx, ra); |
| 1498 | } else { |
| 1499 | probe_access(env, ptr, in_page, access_type, mmu_idx, ra); |
| 1500 | probe_access(env, ptr + in_page, size - in_page, |
| 1501 | access_type, mmu_idx, ra); |
| 1502 | } |
| 1503 | } |
| 1504 | |
| 1505 | /* |
| 1506 | * This function corresponds to AArch64.vESBOperation(). |
| 1507 | * Note that the AArch32 version is not functionally different. |
| 1508 | */ |
| 1509 | void HELPER(vesb)(CPUARMState *env) |
| 1510 | { |
| 1511 | /* |
| 1512 | * The EL2Enabled() check is done inside arm_hcr_el2_eff, |
| 1513 | * and will return HCR_EL2.VSE == 0, so nothing happens. |
| 1514 | */ |
| 1515 | uint64_t hcr = arm_hcr_el2_eff(env); |
| 1516 | bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO); |
| 1517 | bool pending = enabled && (hcr & HCR_VSE); |
| 1518 | bool masked = (env->daif & PSTATE_A); |
| 1519 | |
| 1520 | /* If VSE pending and masked, defer the exception. */ |
| 1521 | if (pending && masked) { |
| 1522 | uint32_t syndrome; |
| 1523 | |
| 1524 | if (arm_el_is_aa64(env, 1)) { |
| 1525 | /* Copy across IDS and ISS from VSESR. */ |
| 1526 | syndrome = env->cp15.vsesr_el2 & 0x1ffffff; |
| 1527 | } else { |
| 1528 | ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal }; |
| 1529 | |
| 1530 | if (extended_addresses_enabled(env)) { |
| 1531 | syndrome = arm_fi_to_lfsc(&fi); |
| 1532 | } else { |
| 1533 | syndrome = arm_fi_to_sfsc(&fi); |
| 1534 | } |
| 1535 | /* Copy across AET and ExT from VSESR. */ |
| 1536 | syndrome |= env->cp15.vsesr_el2 & 0xd000; |
| 1537 | } |
| 1538 | |
| 1539 | /* Set VDISR_EL2.A along with the syndrome. */ |
| 1540 | env->cp15.vdisr_el2 = syndrome | (1u << 31); |
| 1541 | |
| 1542 | /* Clear pending virtual SError */ |
| 1543 | env->cp15.hcr_el2 &= ~HCR_VSE; |
| 1544 | cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); |
| 1545 | } |
| 1546 | } |