@samitouri / QOSamiQemu
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1 /*
2 * Copyright (C) 2014 - Linaro
3 * Author: Rob Herring <rob.herring@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "helper.h"
22 #include "kvm-consts.h"
23 #include "qemu/main-loop.h"
24 #include "system/runstate.h"
25 #include "internals.h"
26 #include "arm-powerctl.h"
27 #include "target/arm/multiprocessing.h"
28 #include "target/arm/trace.h"
29
30 bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
31 {
32 /*
33 * Return true if the exception type matches the configured PSCI conduit.
34 * This is called before the SMC/HVC instruction is executed, to decide
35 * whether we should treat it as a PSCI call or with the architecturally
36 * defined behaviour for an SMC or HVC (which might be UNDEF or trap
37 * to EL2 or to EL3).
38 */
39
40 switch (excp_type) {
41 case EXCP_HVC:
42 if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_HVC) {
43 return false;
44 }
45 break;
46 case EXCP_SMC:
47 if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
48 return false;
49 }
50 break;
51 default:
52 return false;
53 }
54
55 return true;
56 }
57
58 void arm_handle_psci_call(ARMCPU *cpu)
59 {
60 /*
61 * This function partially implements the logic for dispatching Power State
62 * Coordination Interface (PSCI) calls (as described in ARM DEN 0022D.b),
63 * to the extent required for bringing up and taking down secondary cores,
64 * and for handling reset and poweroff requests.
65 * Additional information about the calling convention used is available in
66 * the document 'SMC Calling Convention' (ARM DEN 0028)
67 */
68 CPUARMState *env = &cpu->env;
69 uint64_t param[4];
70 uint64_t context_id, mpidr;
71 uint64_t entry;
72 int32_t ret = 0;
73 int i;
74
75 for (i = 0; i < 4; i++) {
76 /*
77 * All PSCI functions take explicit 32-bit or native int sized
78 * arguments so we can simply zero-extend all arguments regardless
79 * of which exact function we are about to call.
80 */
81 param[i] = is_a64(env) ? env->xregs[i] : env->regs[i];
82 }
83 trace_arm_psci_call(param[0], param[1], param[2], param[3],
84 arm_cpu_mp_affinity(cpu));
85
86 if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) {
87 ret = QEMU_PSCI_RET_NOT_SUPPORTED;
88 goto err;
89 }
90
91 switch (param[0]) {
92 CPUState *target_cpu_state;
93 ARMCPU *target_cpu;
94
95 case QEMU_PSCI_0_2_FN_PSCI_VERSION:
96 ret = QEMU_PSCI_VERSION_1_1;
97 break;
98 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
99 ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
100 break;
101 case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
102 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
103 mpidr = param[1];
104
105 switch (param[2]) {
106 case 0:
107 target_cpu_state = arm_get_cpu_by_id(mpidr);
108 if (!target_cpu_state) {
109 ret = QEMU_PSCI_RET_INVALID_PARAMS;
110 break;
111 }
112 target_cpu = ARM_CPU(target_cpu_state);
113
114 g_assert(bql_locked());
115 ret = target_cpu->power_state;
116 break;
117 default:
118 /* Everything above affinity level 0 is always on. */
119 ret = 0;
120 }
121 break;
122 case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
123 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
124 /* QEMU reset and shutdown are async requests, but PSCI
125 * mandates that we never return from the reset/shutdown
126 * call, so power the CPU off now so it doesn't execute
127 * anything further.
128 */
129 goto cpu_off;
130 case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
131 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
132 goto cpu_off;
133 case QEMU_PSCI_0_1_FN_CPU_ON:
134 case QEMU_PSCI_0_2_FN_CPU_ON:
135 case QEMU_PSCI_0_2_FN64_CPU_ON:
136 {
137 /* The PSCI spec mandates that newly brought up CPUs start
138 * in the highest exception level which exists and is enabled
139 * on the calling CPU. Since the QEMU PSCI implementation is
140 * acting as a "fake EL3" or "fake EL2" firmware, this for us
141 * means that we want to start at the highest NS exception level
142 * that we are providing to the guest.
143 * The execution mode should be that which is currently in use
144 * by the same exception level on the calling CPU.
145 * The CPU should be started with the context_id value
146 * in x0 (if AArch64) or r0 (if AArch32).
147 */
148 int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1;
149 bool target_aarch64 = arm_el_is_aa64(env, target_el);
150
151 mpidr = param[1];
152 entry = param[2];
153 context_id = param[3];
154 ret = arm_set_cpu_on(mpidr, entry, context_id,
155 target_el, target_aarch64);
156 break;
157 }
158 case QEMU_PSCI_0_1_FN_CPU_OFF:
159 case QEMU_PSCI_0_2_FN_CPU_OFF:
160 goto cpu_off;
161 case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
162 case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
163 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
164 /* Affinity levels are not supported in QEMU */
165 if (param[1] & 0xfffe0000) {
166 ret = QEMU_PSCI_RET_INVALID_PARAMS;
167 break;
168 }
169 /* Powerdown is not supported, we always go into WFI */
170 if (is_a64(env)) {
171 env->xregs[0] = 0;
172 } else {
173 env->regs[0] = 0;
174 }
175 helper_wfi(env, 4);
176 break;
177 case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
178 switch (param[1]) {
179 case QEMU_PSCI_0_2_FN_PSCI_VERSION:
180 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
181 case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
182 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
183 case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
184 case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
185 case QEMU_PSCI_0_1_FN_CPU_ON:
186 case QEMU_PSCI_0_2_FN_CPU_ON:
187 case QEMU_PSCI_0_2_FN64_CPU_ON:
188 case QEMU_PSCI_0_1_FN_CPU_OFF:
189 case QEMU_PSCI_0_2_FN_CPU_OFF:
190 case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
191 case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
192 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
193 case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
194 if (!(param[1] & QEMU_PSCI_0_2_64BIT) || is_a64(env)) {
195 ret = 0;
196 break;
197 }
198 /* fallthrough */
199 case QEMU_PSCI_0_1_FN_MIGRATE:
200 case QEMU_PSCI_0_2_FN_MIGRATE:
201 default:
202 ret = QEMU_PSCI_RET_NOT_SUPPORTED;
203 break;
204 }
205 break;
206 case QEMU_PSCI_0_1_FN_MIGRATE:
207 case QEMU_PSCI_0_2_FN_MIGRATE:
208 default:
209 ret = QEMU_PSCI_RET_NOT_SUPPORTED;
210 break;
211 }
212
213 err:
214 if (is_a64(env)) {
215 env->xregs[0] = ret;
216 } else {
217 env->regs[0] = ret;
218 }
219 return;
220
221 cpu_off:
222 ret = arm_set_cpu_off(arm_cpu_mp_affinity(cpu));
223 /* notreached */
224 /* sanity check in case something failed */
225 assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
226 }