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1 # AArch64 SVE instruction descriptions
2 #
3 # Copyright (c) 2017 Linaro, Ltd
4 #
5 # This library is free software; you can redistribute it and/or
6 # modify it under the terms of the GNU Lesser General Public
7 # License as published by the Free Software Foundation; either
8 # version 2.1 of the License, or (at your option) any later version.
9 #
10 # This library is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 # Lesser General Public License for more details.
14 #
15 # You should have received a copy of the GNU Lesser General Public
16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
17
18 #
19 # This file is processed by scripts/decodetree.py
20 #
21
22 ###########################################################################
23 # Named fields. These are primarily for disjoint fields.
24
25 %imm4_16_p1 16:4 !function=plus_1
26 %imm6_22_5 22:1 5:5
27 %imm7_22_16 22:2 16:5
28 %imm8_16_10 16:5 10:3
29 %imm9_16_10 16:s6 10:3
30 %size_23 23:2
31 %dtype_23_13 23:2 13:2
32 %index4_19_10 19:2 10:2
33 %index3_22_19 22:1 19:2
34 %index3_22_17 22:1 17:2
35 %index3_22_12 22:2 12:1
36 %index3_19_11 19:2 11:1
37 %index2_20_11 20:1 11:1
38
39 # A combination of tsz:imm3 -- extract esize.
40 %tszimm_esz 22:2 5:5 !function=tszimm_esz
41 # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
42 %tszimm_shr 22:2 5:5 !function=tszimm_shr
43 # A combination of tsz:imm3 -- extract (tsz:imm3) - esize
44 %tszimm_shl 22:2 5:5 !function=tszimm_shl
45
46 # Similarly for the tszh/tszl pair at 22/16 for zzi
47 %tszimm16_esz 22:2 16:5 !function=tszimm_esz
48 %tszimm16_shr 22:2 16:5 !function=tszimm_shr
49 %tszimm16_shl 22:2 16:5 !function=tszimm_shl
50
51 # Signed 8-bit immediate, optionally shifted left by 8.
52 %sh8_i8s 5:9 !function=expand_imm_sh8s
53 # Unsigned 8-bit immediate, optionally shifted left by 8.
54 %sh8_i8u 5:9 !function=expand_imm_sh8u
55
56 # Unsigned load of msz into esz=2, represented as a dtype.
57 %msz_dtype 23:2 !function=msz_dtype
58
59 # Either a copy of rd (at bit 0), or a different source
60 # as propagated via the MOVPRFX instruction.
61 %reg_movprfx 0:5
62
63 %zd_ax2 1:4 !function=times_2
64 %zd_ax4 2:3 !function=times_4
65 %rn_ax2 6:4 !function=times_2
66
67 %pnd 0:3 !function=plus_8
68 %pnn 5:3 !function=plus_8
69
70 ###########################################################################
71 # Named attribute sets. These are used to make nice(er) names
72 # when creating helpers common to those for the individual
73 # instruction patterns.
74
75 &rx_n rdn rm index n
76 &rr_esz rd rn esz
77 &rri rd rn imm
78 &rr_dbm rd rn dbm
79 &rrri rd rn rm imm
80 &rxx rd rn rm idxn idxm
81 &rri_esz rd rn imm esz
82 &rrri_esz rd rn rm imm esz
83 &rrr_esz rd rn rm esz
84 &rrx_esz rd rn rm index esz
85 &rpr_esz rd pg rn esz
86 &rpr_s rd pg rn s
87 &rprr_s rd pg rn rm s
88 &rprr_esz rd pg rn rm esz
89 &rrrr_esz rd ra rn rm esz
90 &rrxr_esz rd rn rm ra index esz
91 &rprrr_esz rd pg rn rm ra esz
92 &rpri_esz rd pg rn imm esz
93 &ptrue rd esz pat s
94 &incdec_cnt rd pat esz imm d u
95 &incdec2_cnt rd rn pat esz imm d u
96 &incdec_pred rd pg esz d u
97 &incdec2_pred rd rn pg esz d u
98 &rprr_load rd pg rn rm dtype nreg
99 &rpri_load rd pg rn imm dtype nreg
100 &rprr_store rd pg rn rm msz esz nreg
101 &rpri_store rd pg rn imm msz esz nreg
102 &rprr_gather_load rd pg rn rm esz msz u ff xs scale
103 &rpri_gather_load rd pg rn imm esz msz u ff
104 &rprr_scatter_store rd pg rn rm esz msz xs scale
105 &rpri_scatter_store rd pg rn imm esz msz
106
107 ###########################################################################
108 # Named instruction formats. These are generally used to
109 # reduce the amount of duplication between instruction patterns.
110
111 # Two operand with unused vector element size
112 @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
113
114 # Two operand
115 @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
116 @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
117 @rd_rn_e0 ........ .. ...... ...... rn:5 rd:5 &rr_esz esz=0
118 @rd_rnx2 ........ ... ..... ...... ..... rd:5 &rr_esz rn=%rn_ax2
119
120 # Two operand with governing predicate, flags setting
121 @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s
122 @pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0
123
124 # Three operand with unused vector element size
125 @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
126
127 # Three predicate operand, with governing predicate, flag setting
128 @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
129
130 # Three operand, vector element size
131 @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
132 @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz
133 @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \
134 &rrr_esz rn=%reg_movprfx
135 @rdn_rm_e0 ........ .. ...... ...... rm:5 rd:5 \
136 &rrr_esz rn=%reg_movprfx esz=0
137 @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \
138 &rri_esz rn=%reg_movprfx imm=%sh8_i8u
139 @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \
140 &rri_esz rn=%reg_movprfx
141 @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \
142 &rri_esz rn=%reg_movprfx
143
144 # Four operand, vector element size
145 @rda_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 \
146 &rrrr_esz ra=%reg_movprfx
147
148 # Four operand with explicit vector element size
149 @rda_rn_rm_ex ........ ... rm:5 ... ... rn:5 rd:5 \
150 &rrrr_esz ra=%reg_movprfx
151 @rdn_ra_rm_ex ........ ... rm:5 ... ... ra:5 rd:5 \
152 &rrrr_esz rn=%reg_movprfx
153
154 # Three operand with "memory" size, aka immediate left shift
155 @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
156
157 # Two register operand, with governing predicate, vector element size
158 @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
159 &rprr_esz rn=%reg_movprfx
160 @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
161 &rprr_esz rm=%reg_movprfx
162 @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz
163 @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz
164
165 @rdn_pg_rm_e0 ........ .. ... ... ... pg:3 rm:5 rd:5 \
166 &rprr_esz esz=0 rn=%reg_movprfx
167
168 # Three register operand, with governing predicate, vector element size
169 @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
170 &rprrr_esz ra=%reg_movprfx
171 @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \
172 &rprrr_esz rn=%reg_movprfx
173 @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \
174 &rprrr_esz rn=%reg_movprfx
175 @rd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 &rprr_esz
176
177 # One register operand, with governing predicate, vector element size
178 @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
179 @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz
180 @pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz
181
182 # One register operand, with governing predicate, no vector element size
183 @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0
184
185 # Two register operands with a 6-bit signed immediate.
186 @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
187
188 # Two register operand, one immediate operand, with predicate,
189 # element size encoded as TSZHL.
190 @rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \
191 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl
192 @rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \
193 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr
194
195 # Similarly without predicate.
196 @rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \
197 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl
198 @rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \
199 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr
200
201 # Two register operand, one immediate operand, with 4-bit predicate.
202 # User must fill in imm.
203 @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \
204 &rpri_esz rn=%reg_movprfx
205
206 # Two register operand, one one-bit floating-point operand.
207 @rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \
208 &rpri_esz rn=%reg_movprfx
209
210 # Two register operand, one encoded bitmask.
211 @rdn_dbm ........ .. .... dbm:13 rd:5 \
212 &rr_dbm rn=%reg_movprfx
213
214 # Predicate output, vector and immediate input,
215 # controlling predicate, element size.
216 @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz
217 @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz
218
219 # Basic Load/Store with 9-bit immediate offset
220 @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
221 &rri imm=%imm9_16_10
222 @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
223 &rri imm=%imm9_16_10
224
225 # One register, pattern, and uint4+1.
226 # User must fill in U and D.
227 @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
228 &incdec_cnt imm=%imm4_16_p1
229 @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
230 &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx
231
232 # One register, predicate.
233 # User must fill in U and D.
234 @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred
235 @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \
236 &incdec2_pred rn=%reg_movprfx
237
238 # Loads; user must fill in NREG.
239 @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load
240 @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load
241
242 @rprr_load ....... .... rm:5 ... pg:3 rn:5 rd:5 &rprr_load
243 @rpri_load ....... .... . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load
244
245 @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \
246 &rprr_load dtype=%msz_dtype
247 @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \
248 &rpri_load dtype=%msz_dtype
249
250 # Gather Loads.
251 @rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
252 &rprr_gather_load xs=2
253 @rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
254 &rprr_gather_load
255 @rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
256 &rprr_gather_load
257 @rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
258 &rprr_gather_load
259 @rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
260 &rprr_gather_load xs=2
261 @rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
262 &rprr_gather_load xs=2
263 @rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
264 &rpri_gather_load
265
266 # Stores; user must fill in ESZ, MSZ, NREG as needed.
267 @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store
268 @rpri_store ....... .. .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store
269 @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \
270 &rprr_store nreg=0
271 @rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \
272 &rprr_scatter_store
273 @rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \
274 &rpri_scatter_store
275
276 # Two registers and a scalar by N-bit index
277 @rrx_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \
278 &rrx_esz index=%index3_22_19
279 @rrx_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 &rrx_esz
280 @rrx_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 &rrx_esz
281
282 # Two registers and a scalar by N-bit index, alternate
283 @rrx_3a ........ .. . .. rm:3 ...... rn:5 rd:5 \
284 &rrx_esz index=%index3_19_11
285 @rrx_2a ........ .. . . rm:4 ...... rn:5 rd:5 \
286 &rrx_esz index=%index2_20_11
287
288 # Three registers and a scalar by N-bit index
289 @rrxr_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \
290 &rrxr_esz ra=%reg_movprfx index=%index3_22_19
291 @rrxr_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 \
292 &rrxr_esz ra=%reg_movprfx
293 @rrxr_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 \
294 &rrxr_esz ra=%reg_movprfx
295
296 # Three registers and a scalar by N-bit index, alternate
297 @rrxr_3a ........ .. ... rm:3 ...... rn:5 rd:5 \
298 &rrxr_esz ra=%reg_movprfx index=%index3_19_11
299 @rrxr_2a ........ .. .. rm:4 ...... rn:5 rd:5 \
300 &rrxr_esz ra=%reg_movprfx index=%index2_20_11
301
302 ###########################################################################
303 # Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
304
305 ### SVE Integer Arithmetic - Binary Predicated Group
306
307 # SVE bitwise logical vector operations (predicated)
308 ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
309 EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
310 AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
311 BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
312
313 # SVE integer add/subtract vectors (predicated)
314 ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
315 SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
316 SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
317
318 # SVE integer min/max/difference (predicated)
319 SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
320 UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
321 SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
322 UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
323 SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
324 UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
325
326 # SVE integer multiply/divide (predicated)
327 MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
328 SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
329 UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
330 # Note that divide requires size >= 2; below 2 is unallocated.
331 SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
332 UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
333 SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
334 UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
335
336 ### SVE Integer Reduction Group
337
338 # SVE bitwise logical reduction (predicated)
339 ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
340 EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
341 ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
342
343 # SVE2.1 bitwise logical reduction (quadwords)
344 ORQV 00000100 .. 011 100 001 ... ..... ..... @rd_pg_rn
345 EORQV 00000100 .. 011 101 001 ... ..... ..... @rd_pg_rn
346 ANDQV 00000100 .. 011 110 001 ... ..... ..... @rd_pg_rn
347
348 # SVE constructive prefix (predicated)
349 MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn
350 MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn
351
352 # SVE integer add reduction (predicated)
353 # Note that saddv requires size != 3.
354 UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
355 SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
356
357 # SVE integer min/max reduction (predicated)
358 SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
359 UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
360 SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
361 UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
362
363 # SVE2.1 segment reduction
364 ADDQV 00000100 .. 000 101 001 ... ..... ..... @rd_pg_rn
365 SMAXQV 00000100 .. 001 100 001 ... ..... ..... @rd_pg_rn
366 SMINQV 00000100 .. 001 110 001 ... ..... ..... @rd_pg_rn
367 UMAXQV 00000100 .. 001 101 001 ... ..... ..... @rd_pg_rn
368 UMINQV 00000100 .. 001 111 001 ... ..... ..... @rd_pg_rn
369
370 ### SVE Shift by Immediate - Predicated Group
371
372 # SVE bitwise shift by immediate (predicated)
373 ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr
374 LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr
375 LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl
376 ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr
377 SQSHL_zpzi 00000100 .. 000 110 100 ... .. ... ..... @rdn_pg_tszimm_shl
378 UQSHL_zpzi 00000100 .. 000 111 100 ... .. ... ..... @rdn_pg_tszimm_shl
379 SRSHR 00000100 .. 001 100 100 ... .. ... ..... @rdn_pg_tszimm_shr
380 URSHR 00000100 .. 001 101 100 ... .. ... ..... @rdn_pg_tszimm_shr
381 SQSHLU 00000100 .. 001 111 100 ... .. ... ..... @rdn_pg_tszimm_shl
382
383 # SVE bitwise shift by vector (predicated)
384 ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
385 LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
386 LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
387 ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
388 LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
389 LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
390
391 # SVE bitwise shift by wide elements (predicated)
392 # Note these require size != 3.
393 ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
394 LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
395 LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
396
397 ### SVE Integer Arithmetic - Unary Predicated Group
398
399 # SVE unary bit operations (predicated)
400 # Note esz != 0 for FABS and FNEG.
401 CLS_m 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
402 CLZ_m 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
403 CNT_zpz_m 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
404 CNOT_m 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
405 NOT_zpz_m 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
406 FABS_m 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
407 FNEG_m 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
408
409 CLS_z 00000100 .. 001 000 101 ... ..... ..... @rd_pg_rn
410 CLZ_z 00000100 .. 001 001 101 ... ..... ..... @rd_pg_rn
411 CNT_zpz_z 00000100 .. 001 010 101 ... ..... ..... @rd_pg_rn
412 CNOT_z 00000100 .. 001 011 101 ... ..... ..... @rd_pg_rn
413 NOT_zpz_z 00000100 .. 001 110 101 ... ..... ..... @rd_pg_rn
414 FABS_z 00000100 .. 001 100 101 ... ..... ..... @rd_pg_rn
415 FNEG_z 00000100 .. 001 101 101 ... ..... ..... @rd_pg_rn
416
417 # SVE integer unary operations (predicated)
418 # Note esz > original size for extensions.
419 ABS_m 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
420 NEG_m 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
421 SXTB_m 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
422 UXTB_m 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
423 SXTH_m 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
424 UXTH_m 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
425 SXTW_m 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
426 UXTW_m 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
427
428 ABS_z 00000100 .. 000 110 101 ... ..... ..... @rd_pg_rn
429 NEG_z 00000100 .. 000 111 101 ... ..... ..... @rd_pg_rn
430 SXTB_z 00000100 .. 000 000 101 ... ..... ..... @rd_pg_rn
431 UXTB_z 00000100 .. 000 001 101 ... ..... ..... @rd_pg_rn
432 SXTH_z 00000100 .. 000 010 101 ... ..... ..... @rd_pg_rn
433 UXTH_z 00000100 .. 000 011 101 ... ..... ..... @rd_pg_rn
434 SXTW_z 00000100 .. 000 100 101 ... ..... ..... @rd_pg_rn
435 UXTW_z 00000100 .. 000 101 101 ... ..... ..... @rd_pg_rn
436
437 ### SVE Floating Point Compare - Vectors Group
438
439 # SVE floating-point compare vectors
440 FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
441 FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
442 FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
443 FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
444 FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
445 FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
446 FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
447
448 ### SVE Integer Multiply-Add Group
449
450 # SVE integer multiply-add writing addend (predicated)
451 MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm
452 MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
453
454 # SVE integer multiply-add writing multiplicand (predicated)
455 MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
456 MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
457
458 ### SVE Integer Arithmetic - Unpredicated Group
459
460 # SVE integer add/subtract vectors (unpredicated)
461 ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
462 SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
463 SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
464 UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
465 SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
466 UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
467
468 ### SVE Logical - Unpredicated Group
469
470 # SVE bitwise logical operations (unpredicated)
471 AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
472 ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
473 EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
474 BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
475
476 XAR 00000100 .. 1 ..... 001 101 rm:5 rd:5 &rrri_esz \
477 rn=%reg_movprfx esz=%tszimm16_esz imm=%tszimm16_shr
478
479 # SVE2 bitwise ternary operations
480 EOR3 00000100 00 1 ..... 001 110 ..... ..... @rdn_ra_rm_ex esz=0
481 BSL 00000100 00 1 ..... 001 111 ..... ..... @rdn_ra_rm_ex esz=0
482 BCAX 00000100 01 1 ..... 001 110 ..... ..... @rdn_ra_rm_ex esz=0
483 BSL1N 00000100 01 1 ..... 001 111 ..... ..... @rdn_ra_rm_ex esz=0
484 BSL2N 00000100 10 1 ..... 001 111 ..... ..... @rdn_ra_rm_ex esz=0
485 NBSL 00000100 11 1 ..... 001 111 ..... ..... @rdn_ra_rm_ex esz=0
486
487 ### SVE Index Generation Group
488
489 # SVE index generation (immediate start, immediate increment)
490 INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
491
492 # SVE index generation (immediate start, register increment)
493 INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
494
495 # SVE index generation (register start, immediate increment)
496 INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
497
498 # SVE index generation (register start, register increment)
499 INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
500
501 ### SVE / Streaming SVE Stack Allocation Group
502
503 # SVE stack frame adjustment
504 ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
505 ADDSVL 00000100 001 ..... 01011 ...... ..... @rd_rn_i6
506 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
507 ADDSPL 00000100 011 ..... 01011 ...... ..... @rd_rn_i6
508
509 # SVE stack frame size
510 RDVL 00000100 101 11111 01010 imm:s6 rd:5
511 RDSVL 00000100 101 11111 01011 imm:s6 rd:5
512
513 ### SVE Bitwise Shift - Unpredicated Group
514
515 # SVE bitwise shift by immediate (unpredicated)
516 ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr
517 LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr
518 LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl
519
520 # SVE bitwise shift by wide elements (unpredicated)
521 # Note esz != 3
522 ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
523 LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
524 LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
525
526 ### SVE Compute Vector Address Group
527
528 # SVE vector address generation
529 ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
530 ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
531 ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
532 ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
533
534 ### SVE Integer Misc - Unpredicated Group
535
536 # SVE constructive prefix (unpredicated)
537 MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5
538
539 # SVE floating-point exponential accelerator
540 # Note esz != 0
541 FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
542
543 # SVE floating-point trig select coefficient
544 # Note esz != 0
545 FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
546
547 ### SVE Element Count Group
548
549 # SVE element count
550 CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1
551
552 # SVE inc/dec register by element count
553 INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1
554
555 # SVE saturating inc/dec register by element count
556 SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
557 SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
558
559 # SVE inc/dec vector by element count
560 # Note this requires esz != 0.
561 INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1
562
563 # SVE saturating inc/dec vector by element count
564 # Note these require esz != 0.
565 SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
566
567 ### SVE Bitwise Immediate Group
568
569 # SVE bitwise logical with immediate (unpredicated)
570 ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm
571 EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm
572 AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
573
574 # SVE broadcast bitmask immediate
575 DUPM 00000101 11 0000 dbm:13 rd:5
576
577 ### SVE Integer Wide Immediate - Predicated Group
578
579 # SVE copy floating-point immediate (predicated)
580 FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
581
582 # SVE copy integer immediate (predicated)
583 {
584 INVALID 00000101 00 01 ---- 01 1 -------- -----
585 CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
586 }
587 {
588 INVALID 00000101 00 01 ---- 00 1 -------- -----
589 CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
590 }
591
592 ### SVE Permute - Extract Group
593
594 # SVE extract vector (destructive)
595 EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
596 &rrri rn=%reg_movprfx imm=%imm8_16_10
597
598 # SVE2 extract vector (constructive)
599 EXT_sve2 00000101 011 ..... 000 ... rn:5 rd:5 \
600 &rri imm=%imm8_16_10
601
602 ### SVE Permute - Unpredicated Group
603
604 # SVE broadcast general register
605 DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn
606
607 # SVE broadcast indexed element
608 DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \
609 &rri imm=%imm7_22_16
610
611 # SVE Permute Vector - one source quadwords
612 DUPQ 00000101 001 imm:4 1 001001 rn:5 rd:5 &rri_esz esz=0
613 DUPQ 00000101 001 imm:3 10 001001 rn:5 rd:5 &rri_esz esz=1
614 DUPQ 00000101 001 imm:2 100 001001 rn:5 rd:5 &rri_esz esz=2
615 DUPQ 00000101 001 imm:1 1000 001001 rn:5 rd:5 &rri_esz esz=3
616
617 EXTQ 00000101 0110 imm:4 001001 rn:5 rd:5 &rri
618
619 # SVE insert SIMD&FP scalar register
620 INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm
621
622 # SVE insert general register
623 INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm
624
625 # SVE reverse vector elements
626 REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn
627
628 # SVE move predicate to/from vector
629
630 PMOV_pv 00000101 00 101 01 0001110 rn:5 0 rd:4 \
631 &rri_esz esz=0 imm=0
632 PMOV_pv 00000101 00 101 1 imm:1 0001110 rn:5 0 rd:4 &rri_esz esz=1
633 PMOV_pv 00000101 01 101 imm:2 0001110 rn:5 0 rd:4 &rri_esz esz=2
634 PMOV_pv 00000101 1. 101 .. 0001110 rn:5 0 rd:4 \
635 &rri_esz esz=3 imm=%index3_22_17
636
637 PMOV_vp 00000101 00 101 01 1001110 0 rn:4 rd:5 \
638 &rri_esz esz=0 imm=0
639 PMOV_vp 00000101 00 101 1 imm:1 1001110 0 rn:4 rd:5 &rri_esz esz=1
640 PMOV_vp 00000101 01 101 imm:2 1001110 0 rn:4 rd:5 &rri_esz esz=2
641 PMOV_vp 00000101 1. 101 .. 1001110 0 rn:4 rd:5 \
642 &rri_esz esz=3 imm=%index3_22_17
643
644 # SVE vector table lookup
645 TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm
646
647 # SVE unpack vector elements
648 UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5
649
650 # SVE2 Table Lookup (three sources)
651
652 TBL_sve2 00000101 .. 1 ..... 001010 ..... ..... @rd_rn_rm
653 TBX 00000101 .. 1 ..... 001011 ..... ..... @rd_rn_rm
654
655 ### SVE Permute - Predicates Group
656
657 # SVE permute predicate elements
658 ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm
659 ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm
660 UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm
661 UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm
662 TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm
663 TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm
664
665 # SVE reverse predicate elements
666 REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn
667
668 # SVE unpack predicate elements
669 PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0
670 PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0
671
672 ### SVE Permute - Interleaving Group
673
674 # SVE permute vector elements
675 ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm
676 ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
677 UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
678 UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
679 TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
680 TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
681
682 # SVE2 permute vector segments
683 ZIP1_q 00000101 10 1 ..... 000 000 ..... ..... @rd_rn_rm_e0
684 ZIP2_q 00000101 10 1 ..... 000 001 ..... ..... @rd_rn_rm_e0
685 UZP1_q 00000101 10 1 ..... 000 010 ..... ..... @rd_rn_rm_e0
686 UZP2_q 00000101 10 1 ..... 000 011 ..... ..... @rd_rn_rm_e0
687 TRN1_q 00000101 10 1 ..... 000 110 ..... ..... @rd_rn_rm_e0
688 TRN2_q 00000101 10 1 ..... 000 111 ..... ..... @rd_rn_rm_e0
689
690 # SVE2.1 permute vector elements (quadwords)
691 ZIPQ1 01000100 .. 0 ..... 111 000 ..... ..... @rd_rn_rm
692 ZIPQ2 01000100 .. 0 ..... 111 001 ..... ..... @rd_rn_rm
693 UZPQ1 01000100 .. 0 ..... 111 010 ..... ..... @rd_rn_rm
694 UZPQ2 01000100 .. 0 ..... 111 011 ..... ..... @rd_rn_rm
695
696 TBLQ 01000100 .. 0 ..... 111 110 ..... ..... @rd_rn_rm
697 TBXQ 00000101 .. 1 ..... 001 101 ..... ..... @rd_rn_rm
698
699 ### SVE Permute - Predicated Group
700
701 # SVE compress active elements
702 COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn
703
704 # SVE conditionally broadcast element to vector
705 CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm
706 CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm
707
708 # SVE conditionally copy element to SIMD&FP scalar
709 CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn
710 CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn
711
712 # SVE conditionally copy element to general register
713 CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn
714 CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn
715
716 # SVE copy element to SIMD&FP scalar register
717 LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn
718 LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn
719
720 # SVE copy element to general register
721 LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn
722 LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn
723
724 # SVE copy element from SIMD&FP scalar register
725 CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn
726
727 # SVE copy element from general register to vector (predicated)
728 CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn
729
730 # SVE reverse within elements
731 # Note esz >= operation size
732 REVB_m 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn
733 REVH_m 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn
734 REVW_m 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
735 RBIT_m 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
736 REVD_m 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_e0
737
738 REVB_z 00000101 .. 1001 00 101 ... ..... ..... @rd_pg_rn
739 REVH_z 00000101 .. 1001 01 101 ... ..... ..... @rd_pg_rn
740 REVW_z 00000101 .. 1001 10 101 ... ..... ..... @rd_pg_rn
741 RBIT_z 00000101 .. 1001 11 101 ... ..... ..... @rd_pg_rn
742 REVD_z 00000101 00 1011 10 101 ... ..... ..... @rd_pg_rn_e0
743
744 # SVE vector splice (predicated, destructive)
745 SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
746
747 # SVE2 vector splice (predicated, constructive)
748 SPLICE_sve2 00000101 .. 101 101 100 ... ..... ..... @rd_pg_rn
749
750 EXPAND 00000101 .. 110 001 100 ... ..... ..... @rd_pg_rn
751
752 ### SVE Select Vectors Group
753
754 # SVE select vector elements (predicated)
755 SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm
756
757 ### SVE Integer Compare - Vectors Group
758
759 # SVE integer compare_vectors
760 CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm
761 CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm
762 CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm
763 CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm
764 CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm
765 CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm
766
767 # SVE integer compare with wide elements
768 # Note these require esz != 3.
769 CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm
770 CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm
771 CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
772 CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
773 CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
774 CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
775 CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
776 CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
777 CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm
778 CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
779
780 ### SVE Integer Compare - Unsigned Immediate Group
781
782 # SVE integer compare with unsigned immediate
783 CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7
784 CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7
785 CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7
786 CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7
787
788 ### SVE Integer Compare - Signed Immediate Group
789
790 # SVE integer compare with signed immediate
791 CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5
792 CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5
793 CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5
794 CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5
795 CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5
796 CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5
797
798 ### SVE Predicate Logical Operations Group
799
800 # SVE predicate logical operations
801 AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
802 BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
803 EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
804 SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
805 ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
806 ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
807 NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
808 NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
809
810 ### SVE Predicate Misc Group
811
812 # SVE predicate test
813 PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
814
815 # SVE predicate initialize
816 PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
817 PTRUE_cnt 00100101 esz:2 1000000111100000010 ... rd=%pnd
818
819 # SVE initialize FFR
820 SETFFR 00100101 0010 1100 1001 0000 0000 0000
821
822 # SVE zero predicate register
823 PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
824
825 # SVE predicate read from FFR (predicated)
826 RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
827
828 # SVE predicate read from FFR (unpredicated)
829 RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
830
831 # SVE FFR write from predicate (WRFFR)
832 WRFFR 00100101 0010 1000 1001 000 rn:4 00000
833
834 # SVE predicate first active
835 PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
836
837 # SVE predicate next active
838 PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
839
840 ### SVE Partition Break Group
841
842 # SVE propagate break from previous partition
843 BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s
844 BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s
845
846 # SVE partition break condition
847 BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
848 BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
849 BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0
850 BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0
851
852 # SVE propagate break to next partition
853 BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s
854
855 ### SVE Predicate Count Group
856
857 # SVE predicate count
858 CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn
859 CNTP_c 00100101 esz:2 100 000 10 000 vl:1 1 rn:4 rd:5
860
861 FIRSTP 00100101 .. 100 001 10 .... 0 .... ..... @rd_pg4_pn
862 LASTP 00100101 .. 100 010 10 .... 0 .... ..... @rd_pg4_pn
863
864 # SVE inc/dec register by predicate count
865 INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1
866
867 # SVE inc/dec vector by predicate count
868 INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1
869
870 # SVE saturating inc/dec register by predicate count
871 SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred
872 SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred
873
874 # SVE saturating inc/dec vector by predicate count
875 SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred
876
877 ### SVE Integer Compare - Scalars Group
878
879 # SVE conditionally terminate scalars
880 CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000
881
882 # SVE integer compare scalar count and limit
883 &while esz rd rn rm sf u eq
884 WHILE_lt 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4 &while
885 WHILE_gt 00100101 esz:2 1 rm:5 000 sf:1 u:1 0 rn:5 eq:1 rd:4 &while
886
887 # SVE2 pointer conflict compare
888 WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4
889
890 # SVE2.1 predicate pair
891 %pd_pair 1:3 !function=times_2
892 @while_pair ........ esz:2 . rm:5 .... u:1 . rn:5 . ... eq:1 \
893 &while rd=%pd_pair sf=1
894
895 WHILE_lt_pair 00100101 .. 1 ..... 0101 . 1 ..... 1 ... . @while_pair
896 WHILE_gt_pair 00100101 .. 1 ..... 0101 . 0 ..... 1 ... . @while_pair
897
898 # SVE2.1 predicate as count
899 @while_cnt ........ esz:2 . rm:5 .... u:1 . rn:5 . eq:1 ... \
900 &while rd=%pnd sf=1
901
902 WHILE_lt_cnt2 00100101 .. 1 ..... 0100 . 1 ..... 1 . ... @while_cnt
903 WHILE_lt_cnt4 00100101 .. 1 ..... 0110 . 1 ..... 1 . ... @while_cnt
904 WHILE_gt_cnt2 00100101 .. 1 ..... 0100 . 0 ..... 1 . ... @while_cnt
905 WHILE_gt_cnt4 00100101 .. 1 ..... 0110 . 0 ..... 1 . ... @while_cnt
906
907 # SVE2.1 extract mask predicate from predicate-as-counter
908 &pext rd rn esz imm
909 PEXT_1 00100101 esz:2 1 00000 0111 00 imm:2 ... 1 rd:4 &pext rn=%pnn
910 PEXT_2 00100101 esz:2 1 00000 0111 010 imm:1 ... 1 rd:4 &pext rn=%pnn
911
912 ### SVE Integer Wide Immediate - Unpredicated Group
913
914 # SVE broadcast floating-point immediate (unpredicated)
915 FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
916
917 # SVE broadcast integer immediate (unpredicated)
918 {
919 INVALID 00100101 00 111 00 011 1 -------- -----
920 DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
921 }
922
923 # SVE integer add/subtract immediate (unpredicated)
924 {
925 INVALID 00100101 00 100 000 11 1 -------- -----
926 ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
927 }
928 {
929 INVALID 00100101 00 100 001 11 1 -------- -----
930 SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
931 }
932 {
933 INVALID 00100101 00 100 011 11 1 -------- -----
934 SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
935 }
936 {
937 INVALID 00100101 00 100 100 11 1 -------- -----
938 SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
939 }
940 {
941 INVALID 00100101 00 100 101 11 1 -------- -----
942 UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
943 }
944 {
945 INVALID 00100101 00 100 110 11 1 -------- -----
946 SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
947 }
948 {
949 INVALID 00100101 00 100 111 11 1 -------- -----
950 UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
951 }
952
953 # SVE integer min/max immediate (unpredicated)
954 SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s
955 UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u
956 SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s
957 UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u
958
959 # SVE integer multiply immediate (unpredicated)
960 MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s
961
962 # SVE integer dot product (unpredicated)
963 DOT_zzzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 \
964 ra=%reg_movprfx
965
966 # SVE2 complex dot product (vectors)
967 CDOT_zzzz 01000100 esz:2 0 rm:5 0001 rot:2 rn:5 rd:5 ra=%reg_movprfx
968
969 #### SVE Multiply - Indexed
970
971 # SVE integer dot product (indexed)
972 SDOT_zzxw_4s 01000100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2
973 SDOT_zzxw_4d 01000100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3
974 UDOT_zzxw_4s 01000100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2
975 UDOT_zzxw_4d 01000100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3
976
977 SDOT_zzxw_2s 01000100 10 0 ..... 110010 ..... ..... @rrxr_2 esz=2
978 UDOT_zzxw_2s 01000100 10 0 ..... 110011 ..... ..... @rrxr_2 esz=2
979
980 # SVE2 integer multiply-add (indexed)
981 MLA_zzxz_h 01000100 0. 1 ..... 000010 ..... ..... @rrxr_3 esz=1
982 MLA_zzxz_s 01000100 10 1 ..... 000010 ..... ..... @rrxr_2 esz=2
983 MLA_zzxz_d 01000100 11 1 ..... 000010 ..... ..... @rrxr_1 esz=3
984 MLS_zzxz_h 01000100 0. 1 ..... 000011 ..... ..... @rrxr_3 esz=1
985 MLS_zzxz_s 01000100 10 1 ..... 000011 ..... ..... @rrxr_2 esz=2
986 MLS_zzxz_d 01000100 11 1 ..... 000011 ..... ..... @rrxr_1 esz=3
987
988 # SVE2 saturating multiply-add high (indexed)
989 SQRDMLAH_zzxz_h 01000100 0. 1 ..... 000100 ..... ..... @rrxr_3 esz=1
990 SQRDMLAH_zzxz_s 01000100 10 1 ..... 000100 ..... ..... @rrxr_2 esz=2
991 SQRDMLAH_zzxz_d 01000100 11 1 ..... 000100 ..... ..... @rrxr_1 esz=3
992 SQRDMLSH_zzxz_h 01000100 0. 1 ..... 000101 ..... ..... @rrxr_3 esz=1
993 SQRDMLSH_zzxz_s 01000100 10 1 ..... 000101 ..... ..... @rrxr_2 esz=2
994 SQRDMLSH_zzxz_d 01000100 11 1 ..... 000101 ..... ..... @rrxr_1 esz=3
995
996 # SVE mixed sign dot product (indexed)
997 USDOT_zzxw_4s 01000100 10 1 ..... 000110 ..... ..... @rrxr_2 esz=2
998 SUDOT_zzxw_4s 01000100 10 1 ..... 000111 ..... ..... @rrxr_2 esz=2
999
1000 # SVE2 saturating multiply-add (indexed)
1001 SQDMLALB_zzxw_s 01000100 10 1 ..... 0010.0 ..... ..... @rrxr_3a esz=2
1002 SQDMLALB_zzxw_d 01000100 11 1 ..... 0010.0 ..... ..... @rrxr_2a esz=3
1003 SQDMLALT_zzxw_s 01000100 10 1 ..... 0010.1 ..... ..... @rrxr_3a esz=2
1004 SQDMLALT_zzxw_d 01000100 11 1 ..... 0010.1 ..... ..... @rrxr_2a esz=3
1005 SQDMLSLB_zzxw_s 01000100 10 1 ..... 0011.0 ..... ..... @rrxr_3a esz=2
1006 SQDMLSLB_zzxw_d 01000100 11 1 ..... 0011.0 ..... ..... @rrxr_2a esz=3
1007 SQDMLSLT_zzxw_s 01000100 10 1 ..... 0011.1 ..... ..... @rrxr_3a esz=2
1008 SQDMLSLT_zzxw_d 01000100 11 1 ..... 0011.1 ..... ..... @rrxr_2a esz=3
1009
1010 # SVE2 complex integer dot product (indexed)
1011 CDOT_zzxw_s 01000100 10 1 index:2 rm:3 0100 rot:2 rn:5 rd:5 \
1012 ra=%reg_movprfx
1013 CDOT_zzxw_d 01000100 11 1 index:1 rm:4 0100 rot:2 rn:5 rd:5 \
1014 ra=%reg_movprfx
1015
1016 # SVE2 complex integer multiply-add (indexed)
1017 CMLA_zzxz_h 01000100 10 1 index:2 rm:3 0110 rot:2 rn:5 rd:5 \
1018 ra=%reg_movprfx
1019 CMLA_zzxz_s 01000100 11 1 index:1 rm:4 0110 rot:2 rn:5 rd:5 \
1020 ra=%reg_movprfx
1021
1022 # SVE2 complex saturating integer multiply-add (indexed)
1023 SQRDCMLAH_zzxz_h 01000100 10 1 index:2 rm:3 0111 rot:2 rn:5 rd:5 \
1024 ra=%reg_movprfx
1025 SQRDCMLAH_zzxz_s 01000100 11 1 index:1 rm:4 0111 rot:2 rn:5 rd:5 \
1026 ra=%reg_movprfx
1027
1028 # SVE2 multiply-add long (indexed)
1029 SMLALB_zzxw_s 01000100 10 1 ..... 1000.0 ..... ..... @rrxr_3a esz=2
1030 SMLALB_zzxw_d 01000100 11 1 ..... 1000.0 ..... ..... @rrxr_2a esz=3
1031 SMLALT_zzxw_s 01000100 10 1 ..... 1000.1 ..... ..... @rrxr_3a esz=2
1032 SMLALT_zzxw_d 01000100 11 1 ..... 1000.1 ..... ..... @rrxr_2a esz=3
1033 UMLALB_zzxw_s 01000100 10 1 ..... 1001.0 ..... ..... @rrxr_3a esz=2
1034 UMLALB_zzxw_d 01000100 11 1 ..... 1001.0 ..... ..... @rrxr_2a esz=3
1035 UMLALT_zzxw_s 01000100 10 1 ..... 1001.1 ..... ..... @rrxr_3a esz=2
1036 UMLALT_zzxw_d 01000100 11 1 ..... 1001.1 ..... ..... @rrxr_2a esz=3
1037 SMLSLB_zzxw_s 01000100 10 1 ..... 1010.0 ..... ..... @rrxr_3a esz=2
1038 SMLSLB_zzxw_d 01000100 11 1 ..... 1010.0 ..... ..... @rrxr_2a esz=3
1039 SMLSLT_zzxw_s 01000100 10 1 ..... 1010.1 ..... ..... @rrxr_3a esz=2
1040 SMLSLT_zzxw_d 01000100 11 1 ..... 1010.1 ..... ..... @rrxr_2a esz=3
1041 UMLSLB_zzxw_s 01000100 10 1 ..... 1011.0 ..... ..... @rrxr_3a esz=2
1042 UMLSLB_zzxw_d 01000100 11 1 ..... 1011.0 ..... ..... @rrxr_2a esz=3
1043 UMLSLT_zzxw_s 01000100 10 1 ..... 1011.1 ..... ..... @rrxr_3a esz=2
1044 UMLSLT_zzxw_d 01000100 11 1 ..... 1011.1 ..... ..... @rrxr_2a esz=3
1045
1046 # SVE2 integer multiply long (indexed)
1047 SMULLB_zzx_s 01000100 10 1 ..... 1100.0 ..... ..... @rrx_3a esz=2
1048 SMULLB_zzx_d 01000100 11 1 ..... 1100.0 ..... ..... @rrx_2a esz=3
1049 SMULLT_zzx_s 01000100 10 1 ..... 1100.1 ..... ..... @rrx_3a esz=2
1050 SMULLT_zzx_d 01000100 11 1 ..... 1100.1 ..... ..... @rrx_2a esz=3
1051 UMULLB_zzx_s 01000100 10 1 ..... 1101.0 ..... ..... @rrx_3a esz=2
1052 UMULLB_zzx_d 01000100 11 1 ..... 1101.0 ..... ..... @rrx_2a esz=3
1053 UMULLT_zzx_s 01000100 10 1 ..... 1101.1 ..... ..... @rrx_3a esz=2
1054 UMULLT_zzx_d 01000100 11 1 ..... 1101.1 ..... ..... @rrx_2a esz=3
1055
1056 # SVE2 saturating multiply (indexed)
1057 SQDMULLB_zzx_s 01000100 10 1 ..... 1110.0 ..... ..... @rrx_3a esz=2
1058 SQDMULLB_zzx_d 01000100 11 1 ..... 1110.0 ..... ..... @rrx_2a esz=3
1059 SQDMULLT_zzx_s 01000100 10 1 ..... 1110.1 ..... ..... @rrx_3a esz=2
1060 SQDMULLT_zzx_d 01000100 11 1 ..... 1110.1 ..... ..... @rrx_2a esz=3
1061
1062 # SVE2 saturating multiply high (indexed)
1063 SQDMULH_zzx_h 01000100 0. 1 ..... 111100 ..... ..... @rrx_3 esz=1
1064 SQDMULH_zzx_s 01000100 10 1 ..... 111100 ..... ..... @rrx_2 esz=2
1065 SQDMULH_zzx_d 01000100 11 1 ..... 111100 ..... ..... @rrx_1 esz=3
1066 SQRDMULH_zzx_h 01000100 0. 1 ..... 111101 ..... ..... @rrx_3 esz=1
1067 SQRDMULH_zzx_s 01000100 10 1 ..... 111101 ..... ..... @rrx_2 esz=2
1068 SQRDMULH_zzx_d 01000100 11 1 ..... 111101 ..... ..... @rrx_1 esz=3
1069
1070 # SVE2 integer multiply (indexed)
1071 MUL_zzx_h 01000100 0. 1 ..... 111110 ..... ..... @rrx_3 esz=1
1072 MUL_zzx_s 01000100 10 1 ..... 111110 ..... ..... @rrx_2 esz=2
1073 MUL_zzx_d 01000100 11 1 ..... 111110 ..... ..... @rrx_1 esz=3
1074
1075 # SVE floating-point complex add (predicated)
1076 FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \
1077 rn=%reg_movprfx
1078
1079 # SVE floating-point complex multiply-add (predicated)
1080 FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \
1081 ra=%reg_movprfx
1082
1083 # SVE floating-point complex multiply-add (indexed)
1084 FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \
1085 ra=%reg_movprfx esz=1
1086 FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \
1087 ra=%reg_movprfx esz=2
1088
1089 ### SVE FP Multiply-Add Indexed Group
1090
1091 # SVE floating-point multiply-add (indexed)
1092 FMLA_zzxz 01100100 0. 1 ..... 000010 ..... ..... @rrxr_3 esz=0
1093 FMLA_zzxz 01100100 0. 1 ..... 000000 ..... ..... @rrxr_3 esz=1
1094 FMLA_zzxz 01100100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2
1095 FMLA_zzxz 01100100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3
1096 FMLS_zzxz 01100100 0. 1 ..... 000011 ..... ..... @rrxr_3 esz=0
1097 FMLS_zzxz 01100100 0. 1 ..... 000001 ..... ..... @rrxr_3 esz=1
1098 FMLS_zzxz 01100100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2
1099 FMLS_zzxz 01100100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3
1100
1101 ### SVE FP Multiply Indexed Group
1102
1103 # SVE floating-point multiply (indexed)
1104 FMUL_zzx 01100100 0. 1 ..... 001010 ..... ..... @rrx_3 esz=0
1105 FMUL_zzx 01100100 0. 1 ..... 001000 ..... ..... @rrx_3 esz=1
1106 FMUL_zzx 01100100 10 1 ..... 001000 ..... ..... @rrx_2 esz=2
1107 FMUL_zzx 01100100 11 1 ..... 001000 ..... ..... @rrx_1 esz=3
1108
1109 ### SVE FP Fast Reduction Group
1110
1111 FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn
1112 FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn
1113 FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn
1114 FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn
1115 FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn
1116
1117 ### SVE FP recursive reduction (quadwords)
1118
1119 FADDQV 01100100 .. 010 000 101 ... ..... ..... @rd_pg_rn
1120 FMAXNMQV 01100100 .. 010 100 101 ... ..... ..... @rd_pg_rn
1121 FMINNMQV 01100100 .. 010 101 101 ... ..... ..... @rd_pg_rn
1122 FMAXQV 01100100 .. 010 110 101 ... ..... ..... @rd_pg_rn
1123 FMINQV 01100100 .. 010 111 101 ... ..... ..... @rd_pg_rn
1124
1125 ## SVE Floating Point Unary Operations - Unpredicated Group
1126
1127 FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn
1128 FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn
1129
1130 F1CVT 01100101 00 001 000 001100 ..... ..... @rd_rn_e0
1131 F2CVT 01100101 00 001 000 001101 ..... ..... @rd_rn_e0
1132 F1CVTLT 01100101 00 001 001 001100 ..... ..... @rd_rn_e0
1133 F2CVTLT 01100101 00 001 001 001101 ..... ..... @rd_rn_e0
1134
1135 BF1CVT 01100101 00 001 000 001110 ..... ..... @rd_rn_e0
1136 BF2CVT 01100101 00 001 000 001111 ..... ..... @rd_rn_e0
1137 BF1CVTLT 01100101 00 001 001 001110 ..... ..... @rd_rn_e0
1138 BF2CVTLT 01100101 00 001 001 001111 ..... ..... @rd_rn_e0
1139
1140 FCVTN 01100101 00 001 010 001100 ....0 ..... @rd_rnx2 esz=1
1141 BFCVTN 01100101 00 001 010 001110 ....0 ..... @rd_rnx2 esz=1
1142 FCVTNB 01100101 00 001 010 001101 ....0 ..... @rd_rnx2 esz=2
1143 FCVTNT 01100101 00 001 010 001111 ....0 ..... @rd_rnx2 esz=2
1144
1145 ### SVE FP Compare with Zero Group
1146
1147 FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn
1148 FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn
1149 FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn
1150 FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn
1151 FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn
1152 FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn
1153
1154 ### SVE FP Accumulating Reduction Group
1155
1156 # SVE floating-point serial reduction (predicated)
1157 FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm
1158
1159 ### SVE Floating Point Arithmetic - Unpredicated Group
1160
1161 # SVE floating-point arithmetic (unpredicated)
1162 FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm
1163 FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm
1164 FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm
1165 FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm
1166 FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm
1167 FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm
1168
1169 ### SVE FP Arithmetic Predicated Group
1170
1171 # SVE floating-point arithmetic (predicated)
1172 {
1173 BFADD_zpzz 01100101 00 00 0000 100 ... ..... ..... @rdn_pg_rm_e0
1174 FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm
1175 }
1176 {
1177 BFSUB_zpzz 01100101 00 00 0001 100 ... ..... ..... @rdn_pg_rm_e0
1178 FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm
1179 }
1180 {
1181 BFMUL_zpzz 01100101 00 00 0010 100 ... ..... ..... @rdn_pg_rm_e0
1182 FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm
1183 }
1184 FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR
1185 {
1186 BFMAXNM_zpzz 01100101 00 00 0100 100 ... ..... ..... @rdn_pg_rm_e0
1187 FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm
1188 }
1189 {
1190 BFMINNM_zpzz 01100101 00 00 0101 100 ... ..... ..... @rdn_pg_rm_e0
1191 FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm
1192 }
1193 {
1194 BFMAX_zpzz 01100101 00 00 0110 100 ... ..... ..... @rdn_pg_rm_e0
1195 FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm
1196 }
1197 {
1198 BFMIN_zpzz 01100101 00 00 0111 100 ... ..... ..... @rdn_pg_rm_e0
1199 FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm
1200 }
1201 FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm
1202 {
1203 BFSCALE 01100101 00 00 1001 100 ... ..... ..... @rdn_pg_rm_e0
1204 FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm
1205 }
1206 FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm
1207 FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR
1208 FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm
1209 FAMAX 01100101 .. 00 1110 100 ... ..... ..... @rdn_pg_rm
1210 FAMIN 01100101 .. 00 1111 100 ... ..... ..... @rdn_pg_rm
1211
1212 # SVE floating-point arithmetic with immediate (predicated)
1213 FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1
1214 FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1
1215 FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1
1216 FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1
1217 FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1
1218 FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1
1219 FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1
1220 FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1
1221
1222 # SVE floating-point trig multiply-add coefficient
1223 FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx
1224
1225 ### SVE FP Multiply-Add Group
1226
1227 # SVE floating-point multiply-accumulate writing addend
1228 FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm
1229 FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm
1230 FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm
1231 FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm
1232
1233 # SVE floating-point multiply-accumulate writing multiplicand
1234 # Alter the operand extraction order and reuse the helpers from above.
1235 # FMAD, FMSB, FNMAD, FNMS
1236 FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra
1237 FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra
1238 FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra
1239 FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra
1240
1241 ### SVE FP Unary Operations Predicated Group
1242
1243 # SVE floating-point convert precision
1244 FCVT_sh_m 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
1245 FCVT_hs_m 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
1246 BFCVT_m 01100101 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1247 FCVT_dh_m 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0
1248 FCVT_hd_m 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0
1249 FCVT_ds_m 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1250 FCVT_sd_m 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
1251
1252 FCVTX_ds_z 01100100 00 0110 101 10 ... ..... ..... @rd_pg_rn_e0
1253
1254 FCVT_sh_z 01100100 10 0110 101 00 ... ..... ..... @rd_pg_rn_e0
1255 FCVT_hs_z 01100100 10 0110 101 01 ... ..... ..... @rd_pg_rn_e0
1256 BFCVT_z 01100100 10 0110 101 10 ... ..... ..... @rd_pg_rn_e0
1257
1258 FCVT_dh_z 01100100 11 0110 101 00 ... ..... ..... @rd_pg_rn_e0
1259 FCVT_hd_z 01100100 11 0110 101 01 ... ..... ..... @rd_pg_rn_e0
1260 FCVT_ds_z 01100100 11 0110 101 10 ... ..... ..... @rd_pg_rn_e0
1261 FCVT_sd_z 01100100 11 0110 101 11 ... ..... ..... @rd_pg_rn_e0
1262
1263 # SVE floating-point convert to integer
1264 FCVTZS_hh_m 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0
1265 FCVTZU_hh_m 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0
1266 FCVTZS_hs_m 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
1267 FCVTZU_hs_m 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1268 FCVTZS_hd_m 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
1269 FCVTZU_hd_m 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
1270 FCVTZS_ss_m 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
1271 FCVTZU_ss_m 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1272 FCVTZS_ds_m 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0
1273 FCVTZU_ds_m 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0
1274 FCVTZS_sd_m 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
1275 FCVTZU_sd_m 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1276 FCVTZS_dd_m 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
1277 FCVTZU_dd_m 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
1278
1279 FCVTZS_hh_z 01100100 01 011 11 0 110 ... ..... ..... @rd_pg_rn_e0
1280 FCVTZU_hh_z 01100100 01 011 11 0 111 ... ..... ..... @rd_pg_rn_e0
1281 FCVTZS_hs_z 01100100 01 011 11 1 100 ... ..... ..... @rd_pg_rn_e0
1282 FCVTZU_hs_z 01100100 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
1283 FCVTZS_hd_z 01100100 01 011 11 1 110 ... ..... ..... @rd_pg_rn_e0
1284 FCVTZU_hd_z 01100100 01 011 11 1 111 ... ..... ..... @rd_pg_rn_e0
1285 FCVTZS_ss_z 01100100 10 011 11 1 100 ... ..... ..... @rd_pg_rn_e0
1286 FCVTZU_ss_z 01100100 10 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
1287 FCVTZS_sd_z 01100100 11 011 11 1 100 ... ..... ..... @rd_pg_rn_e0
1288 FCVTZU_sd_z 01100100 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
1289 FCVTZS_ds_z 01100100 11 011 11 0 100 ... ..... ..... @rd_pg_rn_e0
1290 FCVTZU_ds_z 01100100 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
1291 FCVTZS_dd_z 01100100 11 011 11 1 110 ... ..... ..... @rd_pg_rn_e0
1292 FCVTZU_dd_z 01100100 11 011 11 1 111 ... ..... ..... @rd_pg_rn_e0
1293
1294 # SVE floating-point round to integral value
1295 FRINTN_m 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn
1296 FRINTP_m 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn
1297 FRINTM_m 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn
1298 FRINTZ_m 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn
1299 FRINTA_m 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn
1300 FRINTX_m 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn
1301 FRINTI_m 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn
1302
1303 FRINTN_z 01100100 .. 011 000 100 ... ..... ..... @rd_pg_rn
1304 FRINTP_z 01100100 .. 011 000 101 ... ..... ..... @rd_pg_rn
1305 FRINTM_z 01100100 .. 011 000 110 ... ..... ..... @rd_pg_rn
1306 FRINTZ_z 01100100 .. 011 000 111 ... ..... ..... @rd_pg_rn
1307 FRINTA_z 01100100 .. 011 001 100 ... ..... ..... @rd_pg_rn
1308 FRINTX_z 01100100 .. 011 001 110 ... ..... ..... @rd_pg_rn
1309 FRINTI_z 01100100 .. 011 001 111 ... ..... ..... @rd_pg_rn
1310
1311 FRINT32X_s_m 01100101 00 010 001 101 ... ..... ..... @rd_pg_rn_e0
1312 FRINT32X_d_m 01100101 00 010 011 101 ... ..... ..... @rd_pg_rn_e0
1313 FRINT64X_s_m 01100101 00 010 101 101 ... ..... ..... @rd_pg_rn_e0
1314 FRINT64X_d_m 01100101 00 010 111 101 ... ..... ..... @rd_pg_rn_e0
1315
1316 FRINT32X_s_z 01100100 00 011 100 101 ... ..... ..... @rd_pg_rn_e0
1317 FRINT32X_d_z 01100100 00 011 100 111 ... ..... ..... @rd_pg_rn_e0
1318 FRINT64X_s_z 01100100 00 011 101 101 ... ..... ..... @rd_pg_rn_e0
1319 FRINT64X_d_z 01100100 00 011 101 111 ... ..... ..... @rd_pg_rn_e0
1320
1321 FRINT32Z_s_m 01100101 00 010 000 101 ... ..... ..... @rd_pg_rn_e0
1322 FRINT32Z_d_m 01100101 00 010 010 101 ... ..... ..... @rd_pg_rn_e0
1323 FRINT64Z_s_m 01100101 00 010 100 101 ... ..... ..... @rd_pg_rn_e0
1324 FRINT64Z_d_m 01100101 00 010 110 101 ... ..... ..... @rd_pg_rn_e0
1325
1326 FRINT32Z_s_z 01100100 00 011 100 100 ... ..... ..... @rd_pg_rn_e0
1327 FRINT32Z_d_z 01100100 00 011 100 110 ... ..... ..... @rd_pg_rn_e0
1328 FRINT64Z_s_z 01100100 00 011 101 100 ... ..... ..... @rd_pg_rn_e0
1329 FRINT64Z_d_z 01100100 00 011 101 110 ... ..... ..... @rd_pg_rn_e0
1330
1331 # SVE floating-point unary operations
1332 FRECPX_m 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn
1333 FSQRT_m 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn
1334
1335 FRECPX_z 01100100 .. 011 011 100 ... ..... ..... @rd_pg_rn
1336 FSQRT_z 01100100 .. 011 011 101 ... ..... ..... @rd_pg_rn
1337
1338 # SVE integer convert to floating-point
1339 SCVTF_hh_m 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0
1340 SCVTF_sh_m 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
1341 SCVTF_dh_m 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
1342 SCVTF_ss_m 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
1343 SCVTF_sd_m 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0
1344 SCVTF_ds_m 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
1345 SCVTF_dd_m 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
1346
1347 UCVTF_hh_m 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0
1348 UCVTF_sh_m 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1349 UCVTF_dh_m 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
1350 UCVTF_ss_m 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1351 UCVTF_sd_m 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0
1352 UCVTF_ds_m 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1353 UCVTF_dd_m 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
1354
1355 SCVTF_hh_z 01100100 01 011 10 0 110 ... ..... ..... @rd_pg_rn_e0
1356 SCVTF_sh_z 01100100 01 011 10 1 100 ... ..... ..... @rd_pg_rn_e0
1357 SCVTF_ss_z 01100100 10 011 10 1 100 ... ..... ..... @rd_pg_rn_e0
1358 SCVTF_sd_z 01100100 11 011 10 0 100 ... ..... ..... @rd_pg_rn_e0
1359 SCVTF_dh_z 01100100 01 011 10 1 110 ... ..... ..... @rd_pg_rn_e0
1360 SCVTF_ds_z 01100100 11 011 10 1 100 ... ..... ..... @rd_pg_rn_e0
1361 SCVTF_dd_z 01100100 11 011 10 1 110 ... ..... ..... @rd_pg_rn_e0
1362
1363 UCVTF_hh_z 01100100 01 011 10 0 111 ... ..... ..... @rd_pg_rn_e0
1364 UCVTF_sh_z 01100100 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1365 UCVTF_ss_z 01100100 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1366 UCVTF_sd_z 01100100 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
1367 UCVTF_dh_z 01100100 01 011 10 1 111 ... ..... ..... @rd_pg_rn_e0
1368 UCVTF_ds_z 01100100 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1369 UCVTF_dd_z 01100100 11 011 10 1 111 ... ..... ..... @rd_pg_rn_e0
1370
1371 ### SVE Memory - 32-bit Gather and Unsized Contiguous Group
1372
1373 # SVE load predicate register
1374 LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
1375
1376 # SVE load vector register
1377 LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9
1378
1379 # SVE load and broadcast element
1380 LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \
1381 &rpri_load dtype=%dtype_23_13 nreg=0
1382
1383 # SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
1384 # SVE 32-bit gather load (scalar plus 32-bit scaled offsets)
1385 LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \
1386 @rprr_g_load_xs_u esz=2 msz=0 scale=0
1387 LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \
1388 @rprr_g_load_xs_u_sc esz=2 msz=1
1389 LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \
1390 @rprr_g_load_xs_sc esz=2 msz=2 u=1
1391
1392 # SVE 32-bit gather load (vector plus immediate)
1393 LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \
1394 @rpri_g_load esz=2
1395
1396 ### SVE Memory Contiguous Load Group
1397
1398 # SVE contiguous load (scalar plus scalar)
1399 LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0
1400 # LD1W (128-bit element)
1401 LD_zprr 1010010 1000 rm:5 100 pg:3 rn:5 rd:5 \
1402 &rprr_load dtype=16 nreg=0
1403 # LD1D (128-bit element)
1404 LD_zprr 1010010 1100 rm:5 100 pg:3 rn:5 rd:5 \
1405 &rprr_load dtype=17 nreg=0
1406
1407 # SVE contiguous first-fault load (scalar plus scalar)
1408 LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0
1409
1410 # SVE contiguous load (scalar plus immediate)
1411 LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0
1412 # LD1W (128-bit element)
1413 LD_zpri 1010010 1000 1 imm:s4 001 pg:3 rn:5 rd:5 \
1414 &rpri_load dtype=16 nreg=0
1415 # LD1D (128-bit element)
1416 LD_zpri 1010010 1100 1 imm:s4 001 pg:3 rn:5 rd:5 \
1417 &rpri_load dtype=17 nreg=0
1418
1419 # SVE contiguous non-fault load (scalar plus immediate)
1420 LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0
1421
1422 # SVE contiguous non-temporal load (scalar plus scalar)
1423 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
1424 # SVE load multiple structures (scalar plus scalar)
1425 # LD2B, LD2H, LD2W, LD2D; etc.
1426 LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz
1427 # LD[234]Q
1428 LD_zprr 1010010 01 01 ..... 100 ... ..... ..... \
1429 @rprr_load dtype=18 nreg=1
1430 LD_zprr 1010010 10 01 ..... 100 ... ..... ..... \
1431 @rprr_load dtype=18 nreg=2
1432 LD_zprr 1010010 11 01 ..... 100 ... ..... ..... \
1433 @rprr_load dtype=18 nreg=3
1434
1435 # SVE contiguous non-temporal load (scalar plus immediate)
1436 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
1437 # SVE load multiple structures (scalar plus immediate)
1438 # LD2B, LD2H, LD2W, LD2D; etc.
1439 LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz
1440 # LD[234]Q
1441 LD_zpri 1010010 01 001 .... 111 ... ..... ..... \
1442 @rpri_load dtype=18 nreg=1
1443 LD_zpri 1010010 10 001 .... 111 ... ..... ..... \
1444 @rpri_load dtype=18 nreg=2
1445 LD_zpri 1010010 11 001 .... 111 ... ..... ..... \
1446 @rpri_load dtype=18 nreg=3
1447
1448 # SVE load and broadcast quadword (scalar plus scalar)
1449 LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \
1450 @rprr_load_msz nreg=0
1451 LD1RO_zprr 1010010 .. 01 ..... 000 ... ..... ..... \
1452 @rprr_load_msz nreg=0
1453
1454 # SVE load and broadcast quadword (scalar plus immediate)
1455 # LD1RQB, LD1RQH, LD1RQS, LD1RQD
1456 LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \
1457 @rpri_load_msz nreg=0
1458 LD1RO_zpri 1010010 .. 01 0.... 001 ... ..... ..... \
1459 @rpri_load_msz nreg=0
1460
1461 # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
1462 PRF_ns 1000010 00 -1 ----- 0-- --- ----- 0 ----
1463
1464 # SVE 32-bit gather prefetch (vector plus immediate)
1465 PRF_ns 1000010 -- 00 ----- 111 --- ----- 0 ----
1466
1467 # SVE contiguous prefetch (scalar plus immediate)
1468 PRF 1000010 11 1- ----- 0-- --- ----- 0 ----
1469
1470 # SVE contiguous prefetch (scalar plus scalar)
1471 PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ----
1472
1473 ### SVE Memory 64-bit Gather Group
1474
1475 # SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets)
1476 # SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)
1477 LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \
1478 @rprr_g_load_xs_u esz=3 msz=0 scale=0
1479 LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \
1480 @rprr_g_load_xs_u_sc esz=3 msz=1
1481 LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \
1482 @rprr_g_load_xs_u_sc esz=3 msz=2
1483 LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \
1484 @rprr_g_load_xs_sc esz=3 msz=3 u=1
1485
1486 # SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)
1487 # SVE 64-bit gather load (scalar plus 64-bit scaled offsets)
1488 LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \
1489 @rprr_g_load_u esz=3 msz=0 scale=0
1490 LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \
1491 @rprr_g_load_u_sc esz=3 msz=1
1492 LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \
1493 @rprr_g_load_u_sc esz=3 msz=2
1494 LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \
1495 @rprr_g_load_sc esz=3 msz=3 u=1
1496
1497 # LD1Q. Note that this is subtly different from LD1_zprz because
1498 # it is vector + scalar, not scalar + vector.
1499 LD1Q 1100 0100 000 rm:5 101 pg:3 rn:5 rd:5
1500
1501 # SVE 64-bit gather load (vector plus immediate)
1502 LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \
1503 @rpri_g_load esz=3
1504
1505 # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
1506 PRF_ns 1100010 00 11 ----- 1-- --- ----- 0 ----
1507
1508 # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
1509 PRF_ns 1100010 00 -1 ----- 0-- --- ----- 0 ----
1510
1511 # SVE 64-bit gather prefetch (vector plus immediate)
1512 PRF_ns 1100010 -- 00 ----- 111 --- ----- 0 ----
1513
1514 ### SVE Memory Store Group
1515
1516 # SVE store predicate register
1517 STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9
1518
1519 # SVE store vector register
1520 STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9
1521
1522 # SVE contiguous store (scalar plus immediate)
1523 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
1524 ST_zpri 1110010 00 esz:2 0.... 111 ... ..... ..... \
1525 @rpri_store msz=0 nreg=0
1526 ST_zpri 1110010 01 esz:2 0.... 111 ... ..... ..... \
1527 @rpri_store msz=1 nreg=0
1528 ST_zpri 1110010 10 10 0.... 111 ... ..... ..... \
1529 @rpri_store msz=2 esz=2 nreg=0
1530 ST_zpri 1110010 10 11 0.... 111 ... ..... ..... \
1531 @rpri_store msz=2 esz=3 nreg=0
1532 ST_zpri 1110010 11 11 0.... 111 ... ..... ..... \
1533 @rpri_store msz=3 esz=3 nreg=0
1534 ST_zpri 1110010 10 00 0.... 111 ... ..... ..... \
1535 @rpri_store msz=2 esz=4 nreg=0
1536 ST_zpri 1110010 11 10 0.... 111 ... ..... ..... \
1537 @rpri_store msz=3 esz=4 nreg=0
1538
1539 # SVE contiguous store (scalar plus scalar)
1540 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
1541 # Enumerate msz lest we conflict with STR_zri.
1542 ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \
1543 @rprr_store_esz_n0 msz=0
1544 ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \
1545 @rprr_store_esz_n0 msz=1
1546 ST_zprr 1110010 10 10 ..... 010 ... ..... ..... \
1547 @rprr_store msz=2 esz=2 nreg=0
1548 ST_zprr 1110010 10 11 ..... 010 ... ..... ..... \
1549 @rprr_store msz=2 esz=3 nreg=0
1550 ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \
1551 @rprr_store msz=3 esz=3 nreg=0
1552 ST_zprr 1110010 10 00 ..... 010 ... ..... ..... \
1553 @rprr_store msz=2 esz=4 nreg=0
1554 ST_zprr 1110010 11 10 ..... 010 ... ..... ..... \
1555 @rprr_store msz=3 esz=4 nreg=0
1556
1557 # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0)
1558 # SVE store multiple structures (scalar plus immediate) (nreg != 0)
1559 ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \
1560 @rpri_store msz=%size_23 esz=%size_23
1561 # ST[234]Q
1562 ST_zpri 11100100 01 00 .... 000 ... ..... ..... \
1563 @rpri_store msz=4 esz=4 nreg=1
1564 ST_zpri 11100100 10 00 .... 000 ... ..... ..... \
1565 @rpri_store msz=4 esz=4 nreg=2
1566 ST_zpri 11100100 11 00 .... 000 ... ..... ..... \
1567 @rpri_store msz=4 esz=4 nreg=3
1568
1569 # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0)
1570 # SVE store multiple structures (scalar plus scalar) (nreg != 0)
1571 ST_zprr 1110010 .. nreg:2 ..... 011 ... ..... ..... \
1572 @rprr_store msz=%size_23 esz=%size_23
1573 # ST[234]Q
1574 ST_zprr 11100100 01 1 ..... 000 ... ..... ..... \
1575 @rprr_store msz=4 esz=4 nreg=1
1576 ST_zprr 11100100 10 1 ..... 000 ... ..... ..... \
1577 @rprr_store msz=4 esz=4 nreg=2
1578 ST_zprr 11100100 11 1 ..... 000 ... ..... ..... \
1579 @rprr_store msz=4 esz=4 nreg=3
1580
1581 # SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)
1582 # Require msz > 0 && msz <= esz.
1583 ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \
1584 @rprr_scatter_store xs=0 esz=2 scale=1
1585 ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \
1586 @rprr_scatter_store xs=1 esz=2 scale=1
1587
1588 # SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
1589 # Require msz <= esz.
1590 ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \
1591 @rprr_scatter_store xs=0 esz=2 scale=0
1592 ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \
1593 @rprr_scatter_store xs=1 esz=2 scale=0
1594
1595 # SVE 64-bit scatter store (scalar plus 64-bit scaled offset)
1596 # Require msz > 0
1597 ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \
1598 @rprr_scatter_store xs=2 esz=3 scale=1
1599
1600 # SVE 64-bit scatter store (scalar plus 64-bit unscaled offset)
1601 ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \
1602 @rprr_scatter_store xs=2 esz=3 scale=0
1603
1604 # ST1Q. Note that this is subtly different from ST1_zprz because
1605 # it is vector + scalar, not scalar + vector.
1606 ST1Q 1110 0100 001 rm:5 001 pg:3 rn:5 rd:5
1607
1608 # SVE 64-bit scatter store (vector plus immediate)
1609 ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \
1610 @rpri_scatter_store esz=3
1611
1612 # SVE 32-bit scatter store (vector plus immediate)
1613 ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \
1614 @rpri_scatter_store esz=2
1615
1616 # SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset)
1617 # Require msz > 0
1618 ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \
1619 @rprr_scatter_store xs=0 esz=3 scale=1
1620 ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \
1621 @rprr_scatter_store xs=1 esz=3 scale=1
1622
1623 # SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset)
1624 ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \
1625 @rprr_scatter_store xs=0 esz=3 scale=0
1626 ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \
1627 @rprr_scatter_store xs=1 esz=3 scale=0
1628
1629 #### SVE2 Support
1630
1631 ### SVE2 Integer Multiply - Unpredicated
1632
1633 # SVE2 integer multiply vectors (unpredicated)
1634 MUL_zzz 00000100 .. 1 ..... 0110 00 ..... ..... @rd_rn_rm
1635 SMULH_zzz 00000100 .. 1 ..... 0110 10 ..... ..... @rd_rn_rm
1636 UMULH_zzz 00000100 .. 1 ..... 0110 11 ..... ..... @rd_rn_rm
1637 PMUL_zzz 00000100 00 1 ..... 0110 01 ..... ..... @rd_rn_rm_e0
1638
1639 # SVE2 signed saturating doubling multiply high (unpredicated)
1640 SQDMULH_zzz 00000100 .. 1 ..... 0111 00 ..... ..... @rd_rn_rm
1641 SQRDMULH_zzz 00000100 .. 1 ..... 0111 01 ..... ..... @rd_rn_rm
1642
1643 ### SVE2 Integer - Predicated
1644
1645 SADALP_zpzz 01000100 .. 000 100 101 ... ..... ..... @rdm_pg_rn
1646 UADALP_zpzz 01000100 .. 000 101 101 ... ..... ..... @rdm_pg_rn
1647
1648 ### SVE2 integer unary operations (predicated)
1649
1650 URECPE_m 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn
1651 URSQRTE_m 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn
1652 SQABS_m 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn
1653 SQNEG_m 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn
1654
1655 URECPE_z 01000100 .. 000 010 101 ... ..... ..... @rd_pg_rn
1656 URSQRTE_z 01000100 .. 000 011 101 ... ..... ..... @rd_pg_rn
1657 SQABS_z 01000100 .. 001 010 101 ... ..... ..... @rd_pg_rn
1658 SQNEG_z 01000100 .. 001 011 101 ... ..... ..... @rd_pg_rn
1659
1660 ### SVE2 saturating/rounding bitwise shift left (predicated)
1661
1662 SRSHL 01000100 .. 000 010 100 ... ..... ..... @rdn_pg_rm
1663 URSHL 01000100 .. 000 011 100 ... ..... ..... @rdn_pg_rm
1664 SRSHL 01000100 .. 000 110 100 ... ..... ..... @rdm_pg_rn # SRSHLR
1665 URSHL 01000100 .. 000 111 100 ... ..... ..... @rdm_pg_rn # URSHLR
1666
1667 SQSHL 01000100 .. 001 000 100 ... ..... ..... @rdn_pg_rm
1668 UQSHL 01000100 .. 001 001 100 ... ..... ..... @rdn_pg_rm
1669 SQSHL 01000100 .. 001 100 100 ... ..... ..... @rdm_pg_rn # SQSHLR
1670 UQSHL 01000100 .. 001 101 100 ... ..... ..... @rdm_pg_rn # UQSHLR
1671
1672 SQRSHL 01000100 .. 001 010 100 ... ..... ..... @rdn_pg_rm
1673 UQRSHL 01000100 .. 001 011 100 ... ..... ..... @rdn_pg_rm
1674 SQRSHL 01000100 .. 001 110 100 ... ..... ..... @rdm_pg_rn # SQRSHLR
1675 UQRSHL 01000100 .. 001 111 100 ... ..... ..... @rdm_pg_rn # UQRSHLR
1676
1677 ### SVE2 integer halving add/subtract (predicated)
1678
1679 SHADD 01000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
1680 UHADD 01000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
1681 SHSUB 01000100 .. 010 010 100 ... ..... ..... @rdn_pg_rm
1682 UHSUB 01000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
1683 SRHADD 01000100 .. 010 100 100 ... ..... ..... @rdn_pg_rm
1684 URHADD 01000100 .. 010 101 100 ... ..... ..... @rdn_pg_rm
1685 SHSUB 01000100 .. 010 110 100 ... ..... ..... @rdm_pg_rn # SHSUBR
1686 UHSUB 01000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # UHSUBR
1687
1688 ### SVE2 integer pairwise arithmetic
1689
1690 ADDP 01000100 .. 010 001 101 ... ..... ..... @rdn_pg_rm
1691 SMAXP 01000100 .. 010 100 101 ... ..... ..... @rdn_pg_rm
1692 UMAXP 01000100 .. 010 101 101 ... ..... ..... @rdn_pg_rm
1693 SMINP 01000100 .. 010 110 101 ... ..... ..... @rdn_pg_rm
1694 UMINP 01000100 .. 010 111 101 ... ..... ..... @rdn_pg_rm
1695
1696 ### SVE2 saturating add/subtract (predicated)
1697
1698 SQADD_zpzz 01000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
1699 UQADD_zpzz 01000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
1700 SQSUB_zpzz 01000100 .. 011 010 100 ... ..... ..... @rdn_pg_rm
1701 UQSUB_zpzz 01000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
1702 SUQADD 01000100 .. 011 100 100 ... ..... ..... @rdn_pg_rm
1703 USQADD 01000100 .. 011 101 100 ... ..... ..... @rdn_pg_rm
1704 SQSUB_zpzz 01000100 .. 011 110 100 ... ..... ..... @rdm_pg_rn # SQSUBR
1705 UQSUB_zpzz 01000100 .. 011 111 100 ... ..... ..... @rdm_pg_rn # UQSUBR
1706
1707 #### SVE2 Widening Integer Arithmetic
1708
1709 ## SVE2 integer add/subtract long
1710
1711 SADDLB 01000101 .. 0 ..... 00 0000 ..... ..... @rd_rn_rm
1712 SADDLT 01000101 .. 0 ..... 00 0001 ..... ..... @rd_rn_rm
1713 UADDLB 01000101 .. 0 ..... 00 0010 ..... ..... @rd_rn_rm
1714 UADDLT 01000101 .. 0 ..... 00 0011 ..... ..... @rd_rn_rm
1715
1716 SSUBLB 01000101 .. 0 ..... 00 0100 ..... ..... @rd_rn_rm
1717 SSUBLT 01000101 .. 0 ..... 00 0101 ..... ..... @rd_rn_rm
1718 USUBLB 01000101 .. 0 ..... 00 0110 ..... ..... @rd_rn_rm
1719 USUBLT 01000101 .. 0 ..... 00 0111 ..... ..... @rd_rn_rm
1720
1721 SABDLB 01000101 .. 0 ..... 00 1100 ..... ..... @rd_rn_rm
1722 SABDLT 01000101 .. 0 ..... 00 1101 ..... ..... @rd_rn_rm
1723 UABDLB 01000101 .. 0 ..... 00 1110 ..... ..... @rd_rn_rm
1724 UABDLT 01000101 .. 0 ..... 00 1111 ..... ..... @rd_rn_rm
1725
1726 ## SVE2 integer add/subtract interleaved long
1727
1728 SADDLBT 01000101 .. 0 ..... 1000 00 ..... ..... @rd_rn_rm
1729 SSUBLBT 01000101 .. 0 ..... 1000 10 ..... ..... @rd_rn_rm
1730 SSUBLTB 01000101 .. 0 ..... 1000 11 ..... ..... @rd_rn_rm
1731
1732 ## SVE2 integer add/subtract wide
1733
1734 SADDWB 01000101 .. 0 ..... 010 000 ..... ..... @rd_rn_rm
1735 SADDWT 01000101 .. 0 ..... 010 001 ..... ..... @rd_rn_rm
1736 UADDWB 01000101 .. 0 ..... 010 010 ..... ..... @rd_rn_rm
1737 UADDWT 01000101 .. 0 ..... 010 011 ..... ..... @rd_rn_rm
1738
1739 SSUBWB 01000101 .. 0 ..... 010 100 ..... ..... @rd_rn_rm
1740 SSUBWT 01000101 .. 0 ..... 010 101 ..... ..... @rd_rn_rm
1741 USUBWB 01000101 .. 0 ..... 010 110 ..... ..... @rd_rn_rm
1742 USUBWT 01000101 .. 0 ..... 010 111 ..... ..... @rd_rn_rm
1743
1744 ## SVE2 integer multiply long
1745
1746 SQDMULLB_zzz 01000101 .. 0 ..... 011 000 ..... ..... @rd_rn_rm
1747 SQDMULLT_zzz 01000101 .. 0 ..... 011 001 ..... ..... @rd_rn_rm
1748 PMULLB 01000101 .. 0 ..... 011 010 ..... ..... @rd_rn_rm
1749 PMULLT 01000101 .. 0 ..... 011 011 ..... ..... @rd_rn_rm
1750 SMULLB_zzz 01000101 .. 0 ..... 011 100 ..... ..... @rd_rn_rm
1751 SMULLT_zzz 01000101 .. 0 ..... 011 101 ..... ..... @rd_rn_rm
1752 UMULLB_zzz 01000101 .. 0 ..... 011 110 ..... ..... @rd_rn_rm
1753 UMULLT_zzz 01000101 .. 0 ..... 011 111 ..... ..... @rd_rn_rm
1754
1755 ## SVE2 bitwise shift left long
1756
1757 # Note bit23 == 0 is handled by esz > 0 in do_sve2_shll_tb.
1758 SSHLLB 01000101 .. 0 ..... 1010 00 ..... ..... @rd_rn_tszimm_shl
1759 SSHLLT 01000101 .. 0 ..... 1010 01 ..... ..... @rd_rn_tszimm_shl
1760 USHLLB 01000101 .. 0 ..... 1010 10 ..... ..... @rd_rn_tszimm_shl
1761 USHLLT 01000101 .. 0 ..... 1010 11 ..... ..... @rd_rn_tszimm_shl
1762
1763 ## SVE2 bitwise exclusive-or interleaved
1764
1765 EORBT 01000101 .. 0 ..... 10010 0 ..... ..... @rd_rn_rm
1766 EORTB 01000101 .. 0 ..... 10010 1 ..... ..... @rd_rn_rm
1767
1768 ## SVE integer matrix multiply accumulate
1769
1770 SMMLA 01000101 00 0 ..... 10011 0 ..... ..... @rda_rn_rm_ex esz=2
1771 USMMLA 01000101 10 0 ..... 10011 0 ..... ..... @rda_rn_rm_ex esz=2
1772 UMMLA 01000101 11 0 ..... 10011 0 ..... ..... @rda_rn_rm_ex esz=2
1773
1774 ## SVE2 bitwise permute
1775
1776 BEXT 01000101 .. 0 ..... 1011 00 ..... ..... @rd_rn_rm
1777 BDEP 01000101 .. 0 ..... 1011 01 ..... ..... @rd_rn_rm
1778 BGRP 01000101 .. 0 ..... 1011 10 ..... ..... @rd_rn_rm
1779
1780 #### SVE2 Accumulate
1781
1782 ## SVE2 complex integer add
1783
1784 CADD_rot90 01000101 .. 00000 0 11011 0 ..... ..... @rdn_rm
1785 CADD_rot270 01000101 .. 00000 0 11011 1 ..... ..... @rdn_rm
1786 SQCADD_rot90 01000101 .. 00000 1 11011 0 ..... ..... @rdn_rm
1787 SQCADD_rot270 01000101 .. 00000 1 11011 1 ..... ..... @rdn_rm
1788
1789 ## SVE2 integer absolute difference and accumulate long
1790
1791 SABALB 01000101 .. 0 ..... 1100 00 ..... ..... @rda_rn_rm
1792 SABALT 01000101 .. 0 ..... 1100 01 ..... ..... @rda_rn_rm
1793 UABALB 01000101 .. 0 ..... 1100 10 ..... ..... @rda_rn_rm
1794 UABALT 01000101 .. 0 ..... 1100 11 ..... ..... @rda_rn_rm
1795
1796 ## SVE2 integer add/subtract long with carry
1797
1798 # ADC and SBC decoded via size in helper dispatch.
1799 ADCLB 01000101 .. 0 ..... 11010 0 ..... ..... @rda_rn_rm
1800 ADCLT 01000101 .. 0 ..... 11010 1 ..... ..... @rda_rn_rm
1801
1802 ## SVE2 bitwise shift right and accumulate
1803
1804 # TODO: Use @rda and %reg_movprfx here.
1805 SSRA 01000101 .. 0 ..... 1110 00 ..... ..... @rd_rn_tszimm_shr
1806 USRA 01000101 .. 0 ..... 1110 01 ..... ..... @rd_rn_tszimm_shr
1807 SRSRA 01000101 .. 0 ..... 1110 10 ..... ..... @rd_rn_tszimm_shr
1808 URSRA 01000101 .. 0 ..... 1110 11 ..... ..... @rd_rn_tszimm_shr
1809
1810 ## SVE2 bitwise shift and insert
1811
1812 SRI 01000101 .. 0 ..... 11110 0 ..... ..... @rd_rn_tszimm_shr
1813 SLI 01000101 .. 0 ..... 11110 1 ..... ..... @rd_rn_tszimm_shl
1814
1815 ## SVE2 integer absolute difference and accumulate
1816
1817 # TODO: Use @rda and %reg_movprfx here.
1818 SABA 01000101 .. 0 ..... 11111 0 ..... ..... @rd_rn_rm
1819 UABA 01000101 .. 0 ..... 11111 1 ..... ..... @rd_rn_rm
1820
1821 #### SVE2 Narrowing
1822
1823 ## SVE2 saturating extract narrow
1824 # Bits 23, 18-16 are zero, limited in the translator via esz < 3 & imm == 0.
1825
1826 {
1827 SQCVTN_sh 01000101 00 1 10001 010 000 ....0 ..... @rd_rnx2 esz=1
1828 SQXTNB 01000101 .. 1 ..... 010 000 ..... ..... @rd_rn_tszimm_shl
1829 }
1830 SQXTNT 01000101 .. 1 ..... 010 001 ..... ..... @rd_rn_tszimm_shl
1831 {
1832 UQCVTN_sh 01000101 00 1 10001 010 010 ....0 ..... @rd_rnx2 esz=1
1833 UQXTNB 01000101 .. 1 ..... 010 010 ..... ..... @rd_rn_tszimm_shl
1834 }
1835 UQXTNT 01000101 .. 1 ..... 010 011 ..... ..... @rd_rn_tszimm_shl
1836 {
1837 SQCVTUN_sh 01000101 00 1 10001 010 100 ....0 ..... @rd_rnx2 esz=1
1838 SQXTUNB 01000101 .. 1 ..... 010 100 ..... ..... @rd_rn_tszimm_shl
1839 }
1840 SQXTUNT 01000101 .. 1 ..... 010 101 ..... ..... @rd_rn_tszimm_shl
1841
1842 ## SVE2 bitwise shift right narrow
1843
1844 # Bit 23 == 0 is handled by esz > 0 in the translator.
1845 SQSHRUNB 01000101 .. 1 ..... 00 0000 ..... ..... @rd_rn_tszimm_shr
1846 SQSHRUNT 01000101 .. 1 ..... 00 0001 ..... ..... @rd_rn_tszimm_shr
1847 SQRSHRUNB 01000101 .. 1 ..... 00 0010 ..... ..... @rd_rn_tszimm_shr
1848 SQRSHRUNT 01000101 .. 1 ..... 00 0011 ..... ..... @rd_rn_tszimm_shr
1849 SHRNB 01000101 .. 1 ..... 00 0100 ..... ..... @rd_rn_tszimm_shr
1850 SHRNT 01000101 .. 1 ..... 00 0101 ..... ..... @rd_rn_tszimm_shr
1851 RSHRNB 01000101 .. 1 ..... 00 0110 ..... ..... @rd_rn_tszimm_shr
1852 RSHRNT 01000101 .. 1 ..... 00 0111 ..... ..... @rd_rn_tszimm_shr
1853 SQSHRNB 01000101 .. 1 ..... 00 1000 ..... ..... @rd_rn_tszimm_shr
1854 SQSHRNT 01000101 .. 1 ..... 00 1001 ..... ..... @rd_rn_tszimm_shr
1855 SQRSHRNB 01000101 .. 1 ..... 00 1010 ..... ..... @rd_rn_tszimm_shr
1856 SQRSHRNT 01000101 .. 1 ..... 00 1011 ..... ..... @rd_rn_tszimm_shr
1857 UQSHRNB 01000101 .. 1 ..... 00 1100 ..... ..... @rd_rn_tszimm_shr
1858 UQSHRNT 01000101 .. 1 ..... 00 1101 ..... ..... @rd_rn_tszimm_shr
1859 UQRSHRNB 01000101 .. 1 ..... 00 1110 ..... ..... @rd_rn_tszimm_shr
1860 UQRSHRNT 01000101 .. 1 ..... 00 1111 ..... ..... @rd_rn_tszimm_shr
1861
1862 ## SVE2 integer add/subtract narrow high part
1863
1864 ADDHNB 01000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm
1865 ADDHNT 01000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
1866 RADDHNB 01000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
1867 RADDHNT 01000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
1868 SUBHNB 01000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
1869 SUBHNT 01000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
1870 RSUBHNB 01000101 .. 1 ..... 011 110 ..... ..... @rd_rn_rm
1871 RSUBHNT 01000101 .. 1 ..... 011 111 ..... ..... @rd_rn_rm
1872
1873 ### SVE2 Character Match
1874
1875 MATCH 01000101 .. 1 ..... 100 ... ..... 0 .... @pd_pg_rn_rm
1876 NMATCH 01000101 .. 1 ..... 100 ... ..... 1 .... @pd_pg_rn_rm
1877
1878 ### SVE2 Histogram Computation and Lookup Table
1879
1880 HISTCNT 01000101 .. 1 ..... 110 ... ..... ..... @rd_pg_rn_rm
1881 HISTSEG 01000101 .. 1 ..... 101 000 ..... ..... @rd_rn_rm
1882
1883 LUTI2_1b 01000101 index:2 1 rm:5 101100 rn:5 rd:5 &rrx_esz esz=0
1884 LUTI2_1h 01000101 .. 1 rm:5 101.10 rn:5 rd:5 \
1885 &rrx_esz esz=1 index=%index3_22_12
1886
1887 LUTI4_1b 01000101 index:1 11 rm:5 101001 rn:5 rd:5 &rrx_esz esz=0
1888 LUTI4_1h 01000101 index:2 1 rm:5 101111 rn:5 rd:5 &rrx_esz esz=1
1889 LUTI4_2h 01000101 index:2 1 rm:5 101101 rn:5 rd:5 &rrx_esz esz=1
1890
1891 ## SVE2 floating-point pairwise operations
1892
1893 FADDP 01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm
1894 FMAXNMP 01100100 .. 010 10 0 100 ... ..... ..... @rdn_pg_rm
1895 FMINNMP 01100100 .. 010 10 1 100 ... ..... ..... @rdn_pg_rm
1896 FMAXP 01100100 .. 010 11 0 100 ... ..... ..... @rdn_pg_rm
1897 FMINP 01100100 .. 010 11 1 100 ... ..... ..... @rdn_pg_rm
1898
1899 #### SVE Integer Multiply-Add (unpredicated)
1900
1901 ## SVE2 saturating multiply-add long
1902
1903 SQDMLALB_zzzw 01000100 .. 0 ..... 0110 00 ..... ..... @rda_rn_rm
1904 SQDMLALT_zzzw 01000100 .. 0 ..... 0110 01 ..... ..... @rda_rn_rm
1905 SQDMLSLB_zzzw 01000100 .. 0 ..... 0110 10 ..... ..... @rda_rn_rm
1906 SQDMLSLT_zzzw 01000100 .. 0 ..... 0110 11 ..... ..... @rda_rn_rm
1907
1908 ## SVE2 saturating multiply-add interleaved long
1909
1910 SQDMLALBT 01000100 .. 0 ..... 00001 0 ..... ..... @rda_rn_rm
1911 SQDMLSLBT 01000100 .. 0 ..... 00001 1 ..... ..... @rda_rn_rm
1912
1913 ## SVE2 saturating multiply-add high
1914
1915 SQRDMLAH_zzzz 01000100 .. 0 ..... 01110 0 ..... ..... @rda_rn_rm
1916 SQRDMLSH_zzzz 01000100 .. 0 ..... 01110 1 ..... ..... @rda_rn_rm
1917
1918 ## SVE2 integer multiply-add long
1919
1920 SMLALB_zzzw 01000100 .. 0 ..... 010 000 ..... ..... @rda_rn_rm
1921 SMLALT_zzzw 01000100 .. 0 ..... 010 001 ..... ..... @rda_rn_rm
1922 UMLALB_zzzw 01000100 .. 0 ..... 010 010 ..... ..... @rda_rn_rm
1923 UMLALT_zzzw 01000100 .. 0 ..... 010 011 ..... ..... @rda_rn_rm
1924 SMLSLB_zzzw 01000100 .. 0 ..... 010 100 ..... ..... @rda_rn_rm
1925 SMLSLT_zzzw 01000100 .. 0 ..... 010 101 ..... ..... @rda_rn_rm
1926 UMLSLB_zzzw 01000100 .. 0 ..... 010 110 ..... ..... @rda_rn_rm
1927 UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm
1928
1929 ## SVE2 complex integer multiply-add
1930
1931 CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx
1932 SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
1933
1934 ## SVE dot product
1935
1936 SDOT_zzzz_2s 01000100 00 0 ..... 110 010 ..... ..... @rda_rn_rm_ex esz=2
1937 UDOT_zzzz_2s 01000100 00 0 ..... 110 011 ..... ..... @rda_rn_rm_ex esz=2
1938
1939 USDOT_zzzz_4s 01000100 10 0 ..... 011 110 ..... ..... @rda_rn_rm_ex esz=2
1940
1941 ### SVE2 floating point matrix multiply accumulate
1942 BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=1
1943 FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=2
1944 FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=3
1945
1946 FMMLA_sb 01100100 00 1 ..... 111 000 ..... ..... @rda_rn_rm_ex esz=2
1947 FMMLA_hb 01100100 01 1 ..... 111 000 ..... ..... @rda_rn_rm_ex esz=1
1948
1949 ### SVE2 Memory Gather Load Group
1950
1951 # SVE2 64-bit gather non-temporal load (scalar plus 64-bit unscaled offsets)
1952 LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \
1953 &rprr_gather_load xs=2 esz=3 scale=0 ff=0
1954
1955 # SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets)
1956 LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \
1957 &rprr_gather_load xs=0 esz=2 scale=0 ff=0
1958
1959 ### SVE2 Memory Store Group
1960
1961 # SVE2 64-bit scatter non-temporal store (vector plus scalar)
1962 STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \
1963 @rprr_scatter_store xs=2 esz=3 scale=0
1964
1965 # SVE2 32-bit scatter non-temporal store (vector plus scalar)
1966 STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
1967 @rprr_scatter_store xs=0 esz=2 scale=0
1968
1969 ### SVE2 Crypto Extensions
1970
1971 # SVE2 crypto unary operations
1972 AESMC 01000101 00 10000011100 0 00000 rd:5
1973 AESIMC 01000101 00 10000011100 1 00000 rd:5
1974
1975 # SVE2 crypto destructive binary operations
1976 AESE 01000101 00 10001 0 11100 0 ..... ..... @rdn_rm_e0
1977 AESD 01000101 00 10001 0 11100 1 ..... ..... @rdn_rm_e0
1978 SM4E 01000101 00 10001 1 11100 0 ..... ..... @rdn_rm_e0
1979
1980 @aes2_2 ........ .. . index:2 0........ rm:5 ..... \
1981 &rx_n n=2 rdn=%zd_ax2
1982 @aes2_4 ........ .. . index:2 1........ rm:5 ..... \
1983 &rx_n n=4 rdn=%zd_ax4
1984
1985 AESE_idx 01000101 00 1 .. .10111010 ..... ....0 @aes2_2
1986 AESE_idx 01000101 00 1 .. .10111010 ..... ...00 @aes2_4
1987
1988 AESD_idx 01000101 00 1 .. .10111011 ..... ....0 @aes2_2
1989 AESD_idx 01000101 00 1 .. .10111011 ..... ...00 @aes2_4
1990
1991 AESEMC 01000101 00 1 .. .11111010 ..... ....0 @aes2_2
1992 AESEMC 01000101 00 1 .. .11111010 ..... ...00 @aes2_4
1993
1994 AESDIMC 01000101 00 1 .. .11111011 ..... ....0 @aes2_2
1995 AESDIMC 01000101 00 1 .. .11111011 ..... ...00 @aes2_4
1996
1997 PMULL 01000101 00 1 rm:5 111110 rn:5 ....0 \
1998 &rrr_esz esz=0 rd=%zd_ax2
1999 PMLAL 01000101 00 1 rm:5 111111 rn:5 ....0 \
2000 &rrr_esz esz=0 rd=%zd_ax2
2001
2002 # SVE2 crypto constructive binary operations
2003 SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0
2004 RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0
2005
2006 ### SVE2 floating-point convert precision odd elements
2007 FCVTXNT_ds_m 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0
2008 FCVTX_ds_m 01100101 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0
2009 FCVTNT_sh_m 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
2010 BFCVTNT_m 01100100 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0
2011 FCVTLT_hs_m 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
2012 FCVTNT_ds_m 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
2013 FCVTLT_sd_m 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
2014
2015 FCVTXNT_ds_z 01100100 00 0000 10 101 ... ..... ..... @rd_pg_rn_e0
2016 FCVTNT_sh_z 01100100 10 0000 00 101 ... ..... ..... @rd_pg_rn_e0
2017 FCVTNT_ds_z 01100100 11 0000 10 101 ... ..... ..... @rd_pg_rn_e0
2018 BFCVTNT_z 01100100 10 0000 10 101 ... ..... ..... @rd_pg_rn_e0
2019 FCVTLT_hs_z 01100100 10 0000 01 101 ... ..... ..... @rd_pg_rn_e0
2020 FCVTLT_sd_z 01100100 11 0000 11 101 ... ..... ..... @rd_pg_rn_e0
2021
2022 ### SVE2 floating-point convert to integer
2023 FLOGB_m 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz
2024 FLOGB_z 01100100 00 011 1101 esz:2 pg:3 rn:5 rd:5 &rpr_esz
2025
2026 ### SVE2 floating-point multiply-add long (vectors)
2027 FMLALB_zzzw 01100100 10 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
2028 FMLALT_zzzw 01100100 10 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2
2029 FMLSLB_zzzw 01100100 10 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_ex esz=2
2030 FMLSLT_zzzw 01100100 10 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_ex esz=2
2031
2032 BFMLALB_zzzw 01100100 11 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
2033 BFMLALT_zzzw 01100100 11 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2
2034 BFMLSLB_zzzw 01100100 11 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_ex esz=2
2035 BFMLSLT_zzzw 01100100 11 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_ex esz=2
2036
2037 FMLAL_hb 01100100 10 1 rm:5 100 idxn:1 10 rn:5 rd:5 &rxx idxm=0
2038
2039 FMLALL_sb 01100100 00 1 rm:5 10 idxn:2 10 rn:5 rd:5 &rxx idxm=0
2040
2041 ### SVE2 floating-point dot-product
2042 FDOT_zzzz 01100100 00 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
2043 BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
2044
2045 FDOT_sb 01100100 01 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2
2046 FDOT_hb 01100100 00 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=1
2047
2048 ### SVE2 floating-point multiply-add long (indexed)
2049
2050 FMLALB_zzxw 01100100 10 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2
2051 FMLALT_zzxw 01100100 10 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2
2052 FMLSLB_zzxw 01100100 10 1 ..... 0110.0 ..... ..... @rrxr_3a esz=2
2053 FMLSLT_zzxw 01100100 10 1 ..... 0110.1 ..... ..... @rrxr_3a esz=2
2054
2055 BFMLALB_zzxw 01100100 11 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2
2056 BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2
2057 BFMLSLB_zzxw 01100100 11 1 ..... 0110.0 ..... ..... @rrxr_3a esz=2
2058 BFMLSLT_zzxw 01100100 11 1 ..... 0110.1 ..... ..... @rrxr_3a esz=2
2059
2060 FMLAL_idx_hb 01100100 idxn:1 01 .. rm:3 0101 .. rn:5 rd:5 \
2061 &rxx idxm=%index4_19_10
2062
2063 FMLALL_idx_sb 01100100 idxn:2 1 .. rm:3 1100 .. rn:5 rd:5 \
2064 &rxx idxm=%index4_19_10
2065
2066 ### SVE2 floating-point dot-product (indexed)
2067
2068 FDOT_zzxz 01100100 00 1 ..... 010000 ..... ..... @rrxr_2 esz=2
2069 BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2
2070
2071 FDOT_idx_sb 01100100 01 1 ..... 010001 ..... ..... @rrxr_2 esz=2
2072 FDOT_idx_hb 01100100 00 1 ..... 0100.1 ..... ..... @rrx_3a esz=1
2073
2074 ### SVE broadcast predicate element
2075
2076 &psel esz pd pn pm rv imm
2077 %psel_rv 16:2 !function=plus_12
2078 %psel_imm_b 22:2 19:2
2079 %psel_imm_h 22:2 20:1
2080 %psel_imm_s 22:2
2081 %psel_imm_d 23:1
2082 @psel ........ .. . ... .. .. pn:4 . pm:4 . pd:4 \
2083 &psel rv=%psel_rv
2084
2085 PSEL 00100101 .. 1 ..1 .. 01 .... 0 .... 0 .... \
2086 @psel esz=0 imm=%psel_imm_b
2087 PSEL 00100101 .. 1 .10 .. 01 .... 0 .... 0 .... \
2088 @psel esz=1 imm=%psel_imm_h
2089 PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \
2090 @psel esz=2 imm=%psel_imm_s
2091 PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \
2092 @psel esz=3 imm=%psel_imm_d
2093
2094 ### SVE clamp
2095
2096 SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm
2097 UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm
2098
2099 FCLAMP 01100100 .. 1 ..... 001001 ..... ..... @rda_rn_rm
2100
2101 ### SVE2p1 multi-vec contiguous load
2102
2103 &zcrr_ldst rd png rn rm esz nreg
2104 &zcri_ldst rd png rn imm esz nreg
2105 %png 10:3 !function=plus_8
2106
2107 LD1_zcrr 10100000000 rm:5 0 esz:2 ... rn:5 .... - \
2108 &zcrr_ldst %png rd=%zd_ax2 nreg=2
2109 LD1_zcrr 10100000000 rm:5 1 esz:2 ... rn:5 ... 0- \
2110 &zcrr_ldst %png rd=%zd_ax4 nreg=4
2111
2112 ST1_zcrr 10100000001 rm:5 0 esz:2 ... rn:5 .... - \
2113 &zcrr_ldst %png rd=%zd_ax2 nreg=2
2114 ST1_zcrr 10100000001 rm:5 1 esz:2 ... rn:5 ... 0- \
2115 &zcrr_ldst %png rd=%zd_ax4 nreg=4
2116
2117 LD1_zcri 101000000100 imm:s4 0 esz:2 ... rn:5 .... - \
2118 &zcri_ldst %png rd=%zd_ax2 nreg=2
2119 LD1_zcri 101000000100 imm:s4 1 esz:2 ... rn:5 ... 0- \
2120 &zcri_ldst %png rd=%zd_ax4 nreg=4
2121
2122 ST1_zcri 101000000110 imm:s4 0 esz:2 ... rn:5 .... - \
2123 &zcri_ldst %png rd=%zd_ax2 nreg=2
2124 ST1_zcri 101000000110 imm:s4 1 esz:2 ... rn:5 ... 0- \
2125 &zcri_ldst %png rd=%zd_ax4 nreg=4
2126
2127 # Note: N bit and 0 bit (for nreg4) still mashed in rd.
2128 # This is handled within gen_ldst_c().
2129 LD1_zcrr_stride 10100001000 rm:5 0 esz:2 ... rn:5 rd:5 \
2130 &zcrr_ldst %png nreg=2
2131 LD1_zcrr_stride 10100001000 rm:5 1 esz:2 ... rn:5 rd:5 \
2132 &zcrr_ldst %png nreg=4
2133
2134 ST1_zcrr_stride 10100001001 rm:5 0 esz:2 ... rn:5 rd:5 \
2135 &zcrr_ldst %png nreg=2
2136 ST1_zcrr_stride 10100001001 rm:5 1 esz:2 ... rn:5 rd:5 \
2137 &zcrr_ldst %png nreg=4
2138
2139 LD1_zcri_stride 101000010100 imm:s4 0 esz:2 ... rn:5 rd:5 \
2140 &zcri_ldst %png nreg=2
2141 LD1_zcri_stride 101000010100 imm:s4 1 esz:2 ... rn:5 rd:5 \
2142 &zcri_ldst %png nreg=4
2143
2144 ST1_zcri_stride 101000010110 imm:s4 0 esz:2 ... rn:5 rd:5 \
2145 &zcri_ldst %png nreg=2
2146 ST1_zcri_stride 101000010110 imm:s4 1 esz:2 ... rn:5 rd:5 \
2147 &zcri_ldst %png nreg=4