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1 /*
2 * AArch32 translation, common definitions.
3 *
4 * Copyright (c) 2021 Linaro, Ltd.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef TARGET_ARM_TRANSLATE_A32_H
21 #define TARGET_ARM_TRANSLATE_A32_H
22
23 /* Prototypes for autogenerated disassembler functions */
24 bool disas_m_nocp(DisasContext *dc, uint32_t insn);
25 bool disas_mve(DisasContext *dc, uint32_t insn);
26 bool disas_vfp(DisasContext *s, uint32_t insn);
27 bool disas_vfp_uncond(DisasContext *s, uint32_t insn);
28 bool disas_neon_dp(DisasContext *s, uint32_t insn);
29 bool disas_neon_ls(DisasContext *s, uint32_t insn);
30 bool disas_neon_shared(DisasContext *s, uint32_t insn);
31
32 void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
33 void arm_gen_condlabel(DisasContext *s);
34 bool vfp_access_check(DisasContext *s);
35 bool vfp_access_check_m(DisasContext *s, bool skip_context_update);
36 bool neon_access_check(DisasContext *s);
37 void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop);
38 void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop);
39 void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop);
40 void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
41 TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
42 void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
43 void gen_set_condexec(DisasContext *s);
44 void gen_update_pc(DisasContext *s, int64_t diff);
45 void gen_lookup_tb(DisasContext *s);
46 long vfp_reg_offset(bool dp, unsigned reg);
47 long neon_full_reg_offset(unsigned reg);
48 long neon_element_offset(int reg, int element, MemOp memop);
49 void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
50 void clear_eci_state(DisasContext *s);
51 bool mve_eci_check(DisasContext *s);
52 void mve_update_eci(DisasContext *s);
53 void mve_update_and_store_eci(DisasContext *s);
54 bool mve_skip_vmov(DisasContext *s, int vn, int index, int size);
55
56 static inline TCGv_i32 load_cpu_offset(int offset)
57 {
58 TCGv_i32 tmp = tcg_temp_new_i32();
59 tcg_gen_ld_i32(tmp, tcg_env, offset);
60 return tmp;
61 }
62
63 /* Load from a 32-bit field to a TCGv_i32 */
64 #define load_cpu_field(name) \
65 ({ \
66 QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 4); \
67 load_cpu_offset(offsetof(CPUARMState, name)); \
68 })
69
70 /* Load from the low half of a 64-bit field to a TCGv_i32 */
71 #define load_cpu_field_low32(name) \
72 ({ \
73 QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 8); \
74 load_cpu_offset(offsetoflow32(CPUARMState, name)); \
75 })
76
77 void store_cpu_offset(TCGv_i32 var, int offset, int size);
78
79 #define store_cpu_field(val, name) \
80 ({ \
81 QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 4 \
82 && sizeof_field(CPUARMState, name) != 1); \
83 store_cpu_offset(val, offsetof(CPUARMState, name), \
84 sizeof_field(CPUARMState, name)); \
85 })
86
87 /* Store to the low half of a 64-bit field from a TCGv_i32 */
88 #define store_cpu_field_low32(val, name) \
89 ({ \
90 QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 8); \
91 store_cpu_offset(val, offsetoflow32(CPUARMState, name), 4); \
92 })
93
94 #define store_cpu_field_constant(val, name) \
95 store_cpu_field(tcg_constant_i32(val), name)
96
97 /* Create a new temporary and set it to the value of a CPU register. */
98 static inline TCGv_i32 load_reg(DisasContext *s, int reg)
99 {
100 TCGv_i32 tmp = tcg_temp_new_i32();
101 load_reg_var(s, tmp, reg);
102 return tmp;
103 }
104
105 void store_reg(DisasContext *s, int reg, TCGv_i32 var);
106
107 void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
108 TCGv_i32 a32, int index, MemOp opc);
109 void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
110 TCGv_i32 a32, int index, MemOp opc);
111 void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
112 TCGv_i32 a32, int index, MemOp opc);
113 void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
114 TCGv_i32 a32, int index, MemOp opc);
115 void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
116 int index, MemOp opc);
117 void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
118 int index, MemOp opc);
119 void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
120 int index, MemOp opc);
121 void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
122 int index, MemOp opc);
123
124 #define DO_GEN_LD(SUFF, OPC) \
125 static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
126 TCGv_i32 a32, int index) \
127 { \
128 gen_aa32_ld_i32(s, val, a32, index, OPC); \
129 }
130
131 #define DO_GEN_ST(SUFF, OPC) \
132 static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
133 TCGv_i32 a32, int index) \
134 { \
135 gen_aa32_st_i32(s, val, a32, index, OPC); \
136 }
137
138 static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
139 TCGv_i32 a32, int index)
140 {
141 gen_aa32_ld_i64(s, val, a32, index, MO_UQ);
142 }
143
144 static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
145 TCGv_i32 a32, int index)
146 {
147 gen_aa32_st_i64(s, val, a32, index, MO_UQ);
148 }
149
150 DO_GEN_LD(8u, MO_UB)
151 DO_GEN_LD(16u, MO_UW)
152 DO_GEN_LD(32u, MO_UL)
153 DO_GEN_ST(8, MO_UB)
154 DO_GEN_ST(16, MO_UW)
155 DO_GEN_ST(32, MO_UL)
156
157 #undef DO_GEN_LD
158 #undef DO_GEN_ST
159
160 #if defined(CONFIG_USER_ONLY)
161 #define IS_USER(s) 1
162 #else
163 #define IS_USER(s) (s->user)
164 #endif
165
166 /* Set NZCV flags from the high 4 bits of var. */
167 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
168
169 /* Swap low and high halfwords. */
170 static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
171 {
172 tcg_gen_rotri_i32(dest, var, 16);
173 }
174
175 #endif