| 1 | |
| 2 | /* |
| 3 | * ARM translation |
| 4 | * |
| 5 | * Copyright (c) 2003 Fabrice Bellard |
| 6 | * Copyright (c) 2005-2007 CodeSourcery |
| 7 | * Copyright (c) 2007 OpenedHand, Ltd. |
| 8 | * |
| 9 | * This library is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU Lesser General Public |
| 11 | * License as published by the Free Software Foundation; either |
| 12 | * version 2.1 of the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This library is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 17 | * Lesser General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU Lesser General Public |
| 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 21 | */ |
| 22 | #include "qemu/osdep.h" |
| 23 | |
| 24 | #include "translate.h" |
| 25 | #include "translate-a32.h" |
| 26 | #define TCG_ADDRESS_BITS 32 |
| 27 | #include "tcg/tcg-op-mem.h" |
| 28 | #include "qemu/log.h" |
| 29 | #include "semihosting/semihost.h" |
| 30 | #include "cpregs.h" |
| 31 | #include "exec/target_page.h" |
| 32 | #include "exec/translator.h" |
| 33 | #include "helper.h" |
| 34 | #include "helper-mve.h" |
| 35 | |
| 36 | #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T) |
| 37 | #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) |
| 38 | /* currently all emulated v5 cores are also v5TE, so don't bother */ |
| 39 | #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) |
| 40 | #define ENABLE_ARCH_5J dc_isar_feature(aa32_jazelle, s) |
| 41 | #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) |
| 42 | #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) |
| 43 | #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) |
| 44 | #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7) |
| 45 | #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) |
| 46 | |
| 47 | #define HELPER_H "tcg/helper-defs.h" |
| 48 | #include "exec/helper-info.c.inc" |
| 49 | |
| 50 | /* These are TCG globals which alias CPUARMState fields */ |
| 51 | static TCGv_i32 cpu_R[16]; |
| 52 | TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; |
| 53 | TCGv_i64 cpu_exclusive_addr; |
| 54 | TCGv_i64 cpu_exclusive_val; |
| 55 | |
| 56 | static const char * const regnames[] = |
| 57 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 58 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; |
| 59 | |
| 60 | |
| 61 | /* initialize TCG globals. */ |
| 62 | void arm_translate_init(void) |
| 63 | { |
| 64 | int i; |
| 65 | |
| 66 | for (i = 0; i < 16; i++) { |
| 67 | cpu_R[i] = tcg_global_mem_new_i32(tcg_env, |
| 68 | offsetof(CPUARMState, regs[i]), |
| 69 | regnames[i]); |
| 70 | } |
| 71 | cpu_CF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, CF), "CF"); |
| 72 | cpu_NF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, NF), "NF"); |
| 73 | cpu_VF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, VF), "VF"); |
| 74 | cpu_ZF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, ZF), "ZF"); |
| 75 | |
| 76 | cpu_exclusive_addr = tcg_global_mem_new_i64(tcg_env, |
| 77 | offsetof(CPUARMState, exclusive_addr), "exclusive_addr"); |
| 78 | cpu_exclusive_val = tcg_global_mem_new_i64(tcg_env, |
| 79 | offsetof(CPUARMState, exclusive_val), "exclusive_val"); |
| 80 | |
| 81 | a64_translate_init(); |
| 82 | } |
| 83 | |
| 84 | uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) |
| 85 | { |
| 86 | /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */ |
| 87 | switch (cmode) { |
| 88 | case 0: case 1: |
| 89 | /* no-op */ |
| 90 | break; |
| 91 | case 2: case 3: |
| 92 | imm <<= 8; |
| 93 | break; |
| 94 | case 4: case 5: |
| 95 | imm <<= 16; |
| 96 | break; |
| 97 | case 6: case 7: |
| 98 | imm <<= 24; |
| 99 | break; |
| 100 | case 8: case 9: |
| 101 | imm |= imm << 16; |
| 102 | break; |
| 103 | case 10: case 11: |
| 104 | imm = (imm << 8) | (imm << 24); |
| 105 | break; |
| 106 | case 12: |
| 107 | imm = (imm << 8) | 0xff; |
| 108 | break; |
| 109 | case 13: |
| 110 | imm = (imm << 16) | 0xffff; |
| 111 | break; |
| 112 | case 14: |
| 113 | if (op) { |
| 114 | /* |
| 115 | * This and cmode == 15 op == 1 are the only cases where |
| 116 | * the top and bottom 32 bits of the encoded constant differ. |
| 117 | */ |
| 118 | uint64_t imm64 = 0; |
| 119 | int n; |
| 120 | |
| 121 | for (n = 0; n < 8; n++) { |
| 122 | if (imm & (1 << n)) { |
| 123 | imm64 |= (0xffULL << (n * 8)); |
| 124 | } |
| 125 | } |
| 126 | return imm64; |
| 127 | } |
| 128 | imm |= (imm << 8) | (imm << 16) | (imm << 24); |
| 129 | break; |
| 130 | case 15: |
| 131 | if (op) { |
| 132 | /* Reserved encoding for AArch32; valid for AArch64 */ |
| 133 | uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48; |
| 134 | if (imm & 0x80) { |
| 135 | imm64 |= 0x8000000000000000ULL; |
| 136 | } |
| 137 | if (imm & 0x40) { |
| 138 | imm64 |= 0x3fc0000000000000ULL; |
| 139 | } else { |
| 140 | imm64 |= 0x4000000000000000ULL; |
| 141 | } |
| 142 | return imm64; |
| 143 | } |
| 144 | imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) |
| 145 | | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); |
| 146 | break; |
| 147 | } |
| 148 | if (op) { |
| 149 | imm = ~imm; |
| 150 | } |
| 151 | return dup_const(MO_32, imm); |
| 152 | } |
| 153 | |
| 154 | /* Generate a label used for skipping this instruction */ |
| 155 | void arm_gen_condlabel(DisasContext *s) |
| 156 | { |
| 157 | if (!s->condjmp) { |
| 158 | s->condlabel = gen_disas_label(s); |
| 159 | s->condjmp = 1; |
| 160 | } |
| 161 | } |
| 162 | |
| 163 | /* Flags for the disas_set_da_iss info argument: |
| 164 | * lower bits hold the Rt register number, higher bits are flags. |
| 165 | */ |
| 166 | typedef enum ISSInfo { |
| 167 | ISSNone = 0, |
| 168 | ISSRegMask = 0x1f, |
| 169 | ISSInvalid = (1 << 5), |
| 170 | ISSIsAcqRel = (1 << 6), |
| 171 | ISSIsWrite = (1 << 7), |
| 172 | ISSIs16Bit = (1 << 8), |
| 173 | } ISSInfo; |
| 174 | |
| 175 | /* |
| 176 | * Store var into env + offset to a member with size bytes. |
| 177 | * Free var after use. |
| 178 | */ |
| 179 | void store_cpu_offset(TCGv_i32 var, int offset, int size) |
| 180 | { |
| 181 | switch (size) { |
| 182 | case 1: |
| 183 | tcg_gen_st8_i32(var, tcg_env, offset); |
| 184 | break; |
| 185 | case 4: |
| 186 | tcg_gen_st_i32(var, tcg_env, offset); |
| 187 | break; |
| 188 | default: |
| 189 | g_assert_not_reached(); |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | /* Save the syndrome information for a Data Abort */ |
| 194 | static void disas_set_da_iss(DisasContext *s, MemOp memop, ISSInfo issinfo) |
| 195 | { |
| 196 | uint32_t syn; |
| 197 | int sas = memop & MO_SIZE; |
| 198 | bool sse = memop & MO_SIGN; |
| 199 | bool is_acqrel = issinfo & ISSIsAcqRel; |
| 200 | bool is_write = issinfo & ISSIsWrite; |
| 201 | bool is_16bit = issinfo & ISSIs16Bit; |
| 202 | int srt = issinfo & ISSRegMask; |
| 203 | |
| 204 | if (issinfo & ISSInvalid) { |
| 205 | /* Some callsites want to conditionally provide ISS info, |
| 206 | * eg "only if this was not a writeback" |
| 207 | */ |
| 208 | return; |
| 209 | } |
| 210 | |
| 211 | if (srt == 15) { |
| 212 | /* For AArch32, insns where the src/dest is R15 never generate |
| 213 | * ISS information. Catching that here saves checking at all |
| 214 | * the call sites. |
| 215 | */ |
| 216 | return; |
| 217 | } |
| 218 | |
| 219 | syn = syn_data_abort_with_iss(0, sas, sse, srt, 0, is_acqrel, |
| 220 | 0, 0, 0, is_write, 0, is_16bit); |
| 221 | disas_set_insn_syndrome(s, syn); |
| 222 | } |
| 223 | |
| 224 | static inline int get_a32_user_mem_index(DisasContext *s) |
| 225 | { |
| 226 | /* Return the core mmu_idx to use for A32/T32 "unprivileged load/store" |
| 227 | * insns: |
| 228 | * if PL2, UNPREDICTABLE (we choose to implement as if PL0) |
| 229 | * otherwise, access as if at PL0. |
| 230 | */ |
| 231 | switch (s->mmu_idx) { |
| 232 | case ARMMMUIdx_E3: |
| 233 | case ARMMMUIdx_E30_0: |
| 234 | case ARMMMUIdx_E30_3_PAN: |
| 235 | return arm_to_core_mmu_idx(ARMMMUIdx_E30_0); |
| 236 | case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ |
| 237 | case ARMMMUIdx_E10_0: |
| 238 | case ARMMMUIdx_E10_1: |
| 239 | case ARMMMUIdx_E10_1_PAN: |
| 240 | return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); |
| 241 | case ARMMMUIdx_MUser: |
| 242 | case ARMMMUIdx_MPriv: |
| 243 | return arm_to_core_mmu_idx(ARMMMUIdx_MUser); |
| 244 | case ARMMMUIdx_MUserNegPri: |
| 245 | case ARMMMUIdx_MPrivNegPri: |
| 246 | return arm_to_core_mmu_idx(ARMMMUIdx_MUserNegPri); |
| 247 | case ARMMMUIdx_MSUser: |
| 248 | case ARMMMUIdx_MSPriv: |
| 249 | return arm_to_core_mmu_idx(ARMMMUIdx_MSUser); |
| 250 | case ARMMMUIdx_MSUserNegPri: |
| 251 | case ARMMMUIdx_MSPrivNegPri: |
| 252 | return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri); |
| 253 | default: |
| 254 | g_assert_not_reached(); |
| 255 | } |
| 256 | } |
| 257 | |
| 258 | /* The pc_curr difference for an architectural jump. */ |
| 259 | static int64_t jmp_diff(DisasContext *s, int64_t diff) |
| 260 | { |
| 261 | return diff + (s->thumb ? 4 : 8); |
| 262 | } |
| 263 | |
| 264 | static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, int64_t diff) |
| 265 | { |
| 266 | assert(s->pc_save != -1); |
| 267 | if (tb_cflags(s->base.tb) & CF_PCREL) { |
| 268 | tcg_gen_addi_i32(var, cpu_R[15], (s->pc_curr - s->pc_save) + diff); |
| 269 | } else { |
| 270 | tcg_gen_movi_i32(var, s->pc_curr + diff); |
| 271 | } |
| 272 | } |
| 273 | |
| 274 | /* Set a variable to the value of a CPU register. */ |
| 275 | void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) |
| 276 | { |
| 277 | if (reg == 15) { |
| 278 | gen_pc_plus_diff(s, var, jmp_diff(s, 0)); |
| 279 | } else { |
| 280 | tcg_gen_mov_i32(var, cpu_R[reg]); |
| 281 | } |
| 282 | } |
| 283 | |
| 284 | /* |
| 285 | * Create a new temp, REG + OFS, except PC is ALIGN(PC, 4). |
| 286 | * This is used for load/store for which use of PC implies (literal), |
| 287 | * or ADD that implies ADR. |
| 288 | */ |
| 289 | TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) |
| 290 | { |
| 291 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 292 | |
| 293 | if (reg == 15) { |
| 294 | /* |
| 295 | * This address is computed from an aligned PC: |
| 296 | * subtract off the low bits. |
| 297 | */ |
| 298 | gen_pc_plus_diff(s, tmp, jmp_diff(s, ofs - (s->pc_curr & 3))); |
| 299 | } else { |
| 300 | tcg_gen_addi_i32(tmp, cpu_R[reg], ofs); |
| 301 | } |
| 302 | return tmp; |
| 303 | } |
| 304 | |
| 305 | /* Set a CPU register. The source must be a temporary and will be |
| 306 | marked as dead. */ |
| 307 | void store_reg(DisasContext *s, int reg, TCGv_i32 var) |
| 308 | { |
| 309 | uint32_t mask = 0; |
| 310 | |
| 311 | if (reg == 15) { |
| 312 | /* |
| 313 | * In Thumb mode, we must ignore bit 0. |
| 314 | * In ARM mode, for ARMv4 and ARMv5, it is UNPREDICTABLE if bits [1:0] |
| 315 | * are not 0b00, but for ARMv6 and above, we must ignore bits [1:0]. |
| 316 | * We choose to ignore [1:0] in ARM mode for all architecture versions. |
| 317 | */ |
| 318 | mask = s->thumb ? 1 : 3; |
| 319 | s->base.is_jmp = DISAS_JUMP; |
| 320 | s->pc_save = -1; |
| 321 | } else if (reg == 13 && arm_dc_feature(s, ARM_FEATURE_M)) { |
| 322 | /* For M-profile SP bits [1:0] are always zero */ |
| 323 | mask = 3; |
| 324 | } |
| 325 | tcg_gen_andi_i32(cpu_R[reg], var, ~mask); |
| 326 | } |
| 327 | |
| 328 | /* |
| 329 | * Variant of store_reg which applies v8M stack-limit checks before updating |
| 330 | * SP. If the check fails this will result in an exception being taken. |
| 331 | * We disable the stack checks for CONFIG_USER_ONLY because we have |
| 332 | * no idea what the stack limits should be in that case. |
| 333 | * If stack checking is not being done this just acts like store_reg(). |
| 334 | */ |
| 335 | static void store_sp_checked(DisasContext *s, TCGv_i32 var) |
| 336 | { |
| 337 | #ifndef CONFIG_USER_ONLY |
| 338 | if (s->v8m_stackcheck) { |
| 339 | gen_helper_v8m_stackcheck(tcg_env, var); |
| 340 | } |
| 341 | #endif |
| 342 | store_reg(s, 13, var); |
| 343 | } |
| 344 | |
| 345 | /* Value extensions. */ |
| 346 | #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var) |
| 347 | #define gen_uxth(var) tcg_gen_ext16u_i32(var, var) |
| 348 | #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var) |
| 349 | #define gen_sxth(var) tcg_gen_ext16s_i32(var, var) |
| 350 | |
| 351 | #define gen_sxtb16(var) gen_helper_sxtb16(var, var) |
| 352 | #define gen_uxtb16(var) gen_helper_uxtb16(var, var) |
| 353 | |
| 354 | void gen_set_cpsr(TCGv_i32 var, uint32_t mask) |
| 355 | { |
| 356 | gen_helper_cpsr_write(tcg_env, var, tcg_constant_i32(mask)); |
| 357 | } |
| 358 | |
| 359 | static void gen_rebuild_hflags(DisasContext *s, bool new_el) |
| 360 | { |
| 361 | bool m_profile = arm_dc_feature(s, ARM_FEATURE_M); |
| 362 | |
| 363 | if (new_el) { |
| 364 | if (m_profile) { |
| 365 | gen_helper_rebuild_hflags_m32_newel(tcg_env); |
| 366 | } else { |
| 367 | gen_helper_rebuild_hflags_a32_newel(tcg_env); |
| 368 | } |
| 369 | } else { |
| 370 | TCGv_i32 tcg_el = tcg_constant_i32(s->current_el); |
| 371 | if (m_profile) { |
| 372 | gen_helper_rebuild_hflags_m32(tcg_env, tcg_el); |
| 373 | } else { |
| 374 | gen_helper_rebuild_hflags_a32(tcg_env, tcg_el); |
| 375 | } |
| 376 | } |
| 377 | } |
| 378 | |
| 379 | void gen_exception_internal(int excp) |
| 380 | { |
| 381 | assert(excp_is_internal(excp)); |
| 382 | gen_helper_exception_internal(tcg_env, tcg_constant_i32(excp)); |
| 383 | } |
| 384 | |
| 385 | static void gen_singlestep_exception(DisasContext *s) |
| 386 | { |
| 387 | /* We just completed step of an insn. Move from Active-not-pending |
| 388 | * to Active-pending, and then also take the swstep exception. |
| 389 | * This corresponds to making the (IMPDEF) choice to prioritize |
| 390 | * swstep exceptions over asynchronous exceptions taken to an exception |
| 391 | * level where debug is disabled. This choice has the advantage that |
| 392 | * we do not need to maintain internal state corresponding to the |
| 393 | * ISV/EX syndrome bits between completion of the step and generation |
| 394 | * of the exception, and our syndrome information is always correct. |
| 395 | */ |
| 396 | gen_ss_advance(s); |
| 397 | gen_swstep_exception(s, 1, s->is_ldex); |
| 398 | s->base.is_jmp = DISAS_NORETURN; |
| 399 | } |
| 400 | |
| 401 | void clear_eci_state(DisasContext *s) |
| 402 | { |
| 403 | /* |
| 404 | * Clear any ECI/ICI state: used when a load multiple/store |
| 405 | * multiple insn executes. |
| 406 | */ |
| 407 | if (s->eci) { |
| 408 | store_cpu_field_constant(0, condexec_bits); |
| 409 | s->eci = 0; |
| 410 | } |
| 411 | } |
| 412 | |
| 413 | static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) |
| 414 | { |
| 415 | TCGv_i32 tmp1 = tcg_temp_new_i32(); |
| 416 | TCGv_i32 tmp2 = tcg_temp_new_i32(); |
| 417 | tcg_gen_ext16s_i32(tmp1, a); |
| 418 | tcg_gen_ext16s_i32(tmp2, b); |
| 419 | tcg_gen_mul_i32(tmp1, tmp1, tmp2); |
| 420 | tcg_gen_sari_i32(a, a, 16); |
| 421 | tcg_gen_sari_i32(b, b, 16); |
| 422 | tcg_gen_mul_i32(b, b, a); |
| 423 | tcg_gen_mov_i32(a, tmp1); |
| 424 | } |
| 425 | |
| 426 | /* Byteswap each halfword. */ |
| 427 | void gen_rev16(TCGv_i32 dest, TCGv_i32 var) |
| 428 | { |
| 429 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 430 | TCGv_i32 mask = tcg_constant_i32(0x00ff00ff); |
| 431 | tcg_gen_shri_i32(tmp, var, 8); |
| 432 | tcg_gen_and_i32(tmp, tmp, mask); |
| 433 | tcg_gen_and_i32(var, var, mask); |
| 434 | tcg_gen_shli_i32(var, var, 8); |
| 435 | tcg_gen_or_i32(dest, var, tmp); |
| 436 | } |
| 437 | |
| 438 | /* Byteswap low halfword and sign extend. */ |
| 439 | static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) |
| 440 | { |
| 441 | tcg_gen_bswap16_i32(var, var, TCG_BSWAP_OS); |
| 442 | } |
| 443 | |
| 444 | /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. |
| 445 | tmp = (t0 ^ t1) & 0x8000; |
| 446 | t0 &= ~0x8000; |
| 447 | t1 &= ~0x8000; |
| 448 | t0 = (t0 + t1) ^ tmp; |
| 449 | */ |
| 450 | |
| 451 | static void gen_add16(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) |
| 452 | { |
| 453 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 454 | tcg_gen_xor_i32(tmp, t0, t1); |
| 455 | tcg_gen_andi_i32(tmp, tmp, 0x8000); |
| 456 | tcg_gen_andi_i32(t0, t0, ~0x8000); |
| 457 | tcg_gen_andi_i32(t1, t1, ~0x8000); |
| 458 | tcg_gen_add_i32(t0, t0, t1); |
| 459 | tcg_gen_xor_i32(dest, t0, tmp); |
| 460 | } |
| 461 | |
| 462 | /* Set N and Z flags from var. */ |
| 463 | static inline void gen_logic_CC(TCGv_i32 var) |
| 464 | { |
| 465 | tcg_gen_mov_i32(cpu_NF, var); |
| 466 | tcg_gen_mov_i32(cpu_ZF, var); |
| 467 | } |
| 468 | |
| 469 | /* dest = T0 + T1 + CF. */ |
| 470 | static void gen_add_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) |
| 471 | { |
| 472 | tcg_gen_add_i32(dest, t0, t1); |
| 473 | tcg_gen_add_i32(dest, dest, cpu_CF); |
| 474 | } |
| 475 | |
| 476 | /* dest = T0 - T1 + CF - 1. */ |
| 477 | static void gen_sub_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) |
| 478 | { |
| 479 | tcg_gen_sub_i32(dest, t0, t1); |
| 480 | tcg_gen_add_i32(dest, dest, cpu_CF); |
| 481 | tcg_gen_subi_i32(dest, dest, 1); |
| 482 | } |
| 483 | |
| 484 | /* dest = T0 + T1. Compute C, N, V and Z flags */ |
| 485 | static void gen_add_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) |
| 486 | { |
| 487 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 488 | tcg_gen_movi_i32(tmp, 0); |
| 489 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, t1, tmp); |
| 490 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); |
| 491 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0); |
| 492 | tcg_gen_xor_i32(tmp, t0, t1); |
| 493 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); |
| 494 | tcg_gen_mov_i32(dest, cpu_NF); |
| 495 | } |
| 496 | |
| 497 | /* dest = T0 + T1 + CF. Compute C, N, V and Z flags */ |
| 498 | static void gen_adc_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) |
| 499 | { |
| 500 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 501 | |
| 502 | tcg_gen_addcio_i32(cpu_NF, cpu_CF, t0, t1, cpu_CF); |
| 503 | |
| 504 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); |
| 505 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0); |
| 506 | tcg_gen_xor_i32(tmp, t0, t1); |
| 507 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); |
| 508 | tcg_gen_mov_i32(dest, cpu_NF); |
| 509 | } |
| 510 | |
| 511 | /* dest = T0 - T1. Compute C, N, V and Z flags */ |
| 512 | static void gen_sub_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) |
| 513 | { |
| 514 | TCGv_i32 tmp; |
| 515 | tcg_gen_sub_i32(cpu_NF, t0, t1); |
| 516 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); |
| 517 | tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0, t1); |
| 518 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0); |
| 519 | tmp = tcg_temp_new_i32(); |
| 520 | tcg_gen_xor_i32(tmp, t0, t1); |
| 521 | tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); |
| 522 | tcg_gen_mov_i32(dest, cpu_NF); |
| 523 | } |
| 524 | |
| 525 | /* dest = T0 + ~T1 + CF. Compute C, N, V and Z flags */ |
| 526 | static void gen_sbc_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) |
| 527 | { |
| 528 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 529 | tcg_gen_not_i32(tmp, t1); |
| 530 | gen_adc_CC(dest, t0, tmp); |
| 531 | } |
| 532 | |
| 533 | #define GEN_SHIFT(name) \ |
| 534 | static void gen_##name(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) \ |
| 535 | { \ |
| 536 | TCGv_i32 tmpd = tcg_temp_new_i32(); \ |
| 537 | TCGv_i32 tmp1 = tcg_temp_new_i32(); \ |
| 538 | TCGv_i32 zero = tcg_constant_i32(0); \ |
| 539 | tcg_gen_andi_i32(tmp1, t1, 0x1f); \ |
| 540 | tcg_gen_##name##_i32(tmpd, t0, tmp1); \ |
| 541 | tcg_gen_andi_i32(tmp1, t1, 0xe0); \ |
| 542 | tcg_gen_movcond_i32(TCG_COND_NE, dest, tmp1, zero, zero, tmpd); \ |
| 543 | } |
| 544 | GEN_SHIFT(shl) |
| 545 | GEN_SHIFT(shr) |
| 546 | #undef GEN_SHIFT |
| 547 | |
| 548 | static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) |
| 549 | { |
| 550 | TCGv_i32 tmp1 = tcg_temp_new_i32(); |
| 551 | |
| 552 | tcg_gen_andi_i32(tmp1, t1, 0xff); |
| 553 | tcg_gen_umin_i32(tmp1, tmp1, tcg_constant_i32(31)); |
| 554 | tcg_gen_sar_i32(dest, t0, tmp1); |
| 555 | } |
| 556 | |
| 557 | static void shifter_out_im(TCGv_i32 var, int shift) |
| 558 | { |
| 559 | tcg_gen_extract_i32(cpu_CF, var, shift, 1); |
| 560 | } |
| 561 | |
| 562 | /* Shift by immediate. Includes special handling for shift == 0. */ |
| 563 | static inline void gen_arm_shift_im(TCGv_i32 var, int shiftop, |
| 564 | int shift, int flags) |
| 565 | { |
| 566 | switch (shiftop) { |
| 567 | case 0: /* LSL */ |
| 568 | if (shift != 0) { |
| 569 | if (flags) |
| 570 | shifter_out_im(var, 32 - shift); |
| 571 | tcg_gen_shli_i32(var, var, shift); |
| 572 | } |
| 573 | break; |
| 574 | case 1: /* LSR */ |
| 575 | if (shift == 0) { |
| 576 | if (flags) { |
| 577 | tcg_gen_shri_i32(cpu_CF, var, 31); |
| 578 | } |
| 579 | tcg_gen_movi_i32(var, 0); |
| 580 | } else { |
| 581 | if (flags) |
| 582 | shifter_out_im(var, shift - 1); |
| 583 | tcg_gen_shri_i32(var, var, shift); |
| 584 | } |
| 585 | break; |
| 586 | case 2: /* ASR */ |
| 587 | if (shift == 0) |
| 588 | shift = 32; |
| 589 | if (flags) |
| 590 | shifter_out_im(var, shift - 1); |
| 591 | if (shift == 32) |
| 592 | shift = 31; |
| 593 | tcg_gen_sari_i32(var, var, shift); |
| 594 | break; |
| 595 | case 3: /* ROR/RRX */ |
| 596 | if (shift != 0) { |
| 597 | if (flags) |
| 598 | shifter_out_im(var, shift - 1); |
| 599 | tcg_gen_rotri_i32(var, var, shift); break; |
| 600 | } else { |
| 601 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 602 | tcg_gen_shli_i32(tmp, cpu_CF, 31); |
| 603 | if (flags) |
| 604 | shifter_out_im(var, 0); |
| 605 | tcg_gen_shri_i32(var, var, 1); |
| 606 | tcg_gen_or_i32(var, var, tmp); |
| 607 | } |
| 608 | } |
| 609 | }; |
| 610 | |
| 611 | static inline void gen_arm_shift_reg(TCGv_i32 var, int shiftop, |
| 612 | TCGv_i32 shift, int flags) |
| 613 | { |
| 614 | if (flags) { |
| 615 | switch (shiftop) { |
| 616 | case 0: gen_helper_shl_cc(var, tcg_env, var, shift); break; |
| 617 | case 1: gen_helper_shr_cc(var, tcg_env, var, shift); break; |
| 618 | case 2: gen_helper_sar_cc(var, tcg_env, var, shift); break; |
| 619 | case 3: gen_helper_ror_cc(var, tcg_env, var, shift); break; |
| 620 | } |
| 621 | } else { |
| 622 | switch (shiftop) { |
| 623 | case 0: |
| 624 | gen_shl(var, var, shift); |
| 625 | break; |
| 626 | case 1: |
| 627 | gen_shr(var, var, shift); |
| 628 | break; |
| 629 | case 2: |
| 630 | gen_sar(var, var, shift); |
| 631 | break; |
| 632 | case 3: tcg_gen_andi_i32(shift, shift, 0x1f); |
| 633 | tcg_gen_rotr_i32(var, var, shift); break; |
| 634 | } |
| 635 | } |
| 636 | } |
| 637 | |
| 638 | /* |
| 639 | * Generate a conditional based on ARM condition code cc. |
| 640 | * This is common between ARM and Aarch64 targets. |
| 641 | */ |
| 642 | void arm_test_cc(DisasCompare *cmp, int cc) |
| 643 | { |
| 644 | TCGv_i32 value; |
| 645 | TCGCond cond; |
| 646 | |
| 647 | switch (cc) { |
| 648 | case 0: /* eq: Z */ |
| 649 | case 1: /* ne: !Z */ |
| 650 | cond = TCG_COND_EQ; |
| 651 | value = cpu_ZF; |
| 652 | break; |
| 653 | |
| 654 | case 2: /* cs: C */ |
| 655 | case 3: /* cc: !C */ |
| 656 | cond = TCG_COND_NE; |
| 657 | value = cpu_CF; |
| 658 | break; |
| 659 | |
| 660 | case 4: /* mi: N */ |
| 661 | case 5: /* pl: !N */ |
| 662 | cond = TCG_COND_LT; |
| 663 | value = cpu_NF; |
| 664 | break; |
| 665 | |
| 666 | case 6: /* vs: V */ |
| 667 | case 7: /* vc: !V */ |
| 668 | cond = TCG_COND_LT; |
| 669 | value = cpu_VF; |
| 670 | break; |
| 671 | |
| 672 | case 8: /* hi: C && !Z */ |
| 673 | case 9: /* ls: !C || Z -> !(C && !Z) */ |
| 674 | cond = TCG_COND_NE; |
| 675 | value = tcg_temp_new_i32(); |
| 676 | /* CF is 1 for C, so -CF is an all-bits-set mask for C; |
| 677 | ZF is non-zero for !Z; so AND the two subexpressions. */ |
| 678 | tcg_gen_neg_i32(value, cpu_CF); |
| 679 | tcg_gen_and_i32(value, value, cpu_ZF); |
| 680 | break; |
| 681 | |
| 682 | case 10: /* ge: N == V -> N ^ V == 0 */ |
| 683 | case 11: /* lt: N != V -> N ^ V != 0 */ |
| 684 | /* Since we're only interested in the sign bit, == 0 is >= 0. */ |
| 685 | cond = TCG_COND_GE; |
| 686 | value = tcg_temp_new_i32(); |
| 687 | tcg_gen_xor_i32(value, cpu_VF, cpu_NF); |
| 688 | break; |
| 689 | |
| 690 | case 12: /* gt: !Z && N == V */ |
| 691 | case 13: /* le: Z || N != V */ |
| 692 | cond = TCG_COND_NE; |
| 693 | value = tcg_temp_new_i32(); |
| 694 | /* (N == V) is equal to the sign bit of ~(NF ^ VF). Propagate |
| 695 | * the sign bit then AND with ZF to yield the result. */ |
| 696 | tcg_gen_xor_i32(value, cpu_VF, cpu_NF); |
| 697 | tcg_gen_sari_i32(value, value, 31); |
| 698 | tcg_gen_andc_i32(value, cpu_ZF, value); |
| 699 | break; |
| 700 | |
| 701 | case 14: /* always */ |
| 702 | case 15: /* always */ |
| 703 | /* Use the ALWAYS condition, which will fold early. |
| 704 | * It doesn't matter what we use for the value. */ |
| 705 | cond = TCG_COND_ALWAYS; |
| 706 | value = cpu_ZF; |
| 707 | goto no_invert; |
| 708 | |
| 709 | default: |
| 710 | fprintf(stderr, "Bad condition code 0x%x\n", cc); |
| 711 | abort(); |
| 712 | } |
| 713 | |
| 714 | if (cc & 1) { |
| 715 | cond = tcg_invert_cond(cond); |
| 716 | } |
| 717 | |
| 718 | no_invert: |
| 719 | cmp->cond = cond; |
| 720 | cmp->value = value; |
| 721 | } |
| 722 | |
| 723 | void arm_jump_cc(DisasCompare *cmp, TCGLabel *label) |
| 724 | { |
| 725 | tcg_gen_brcondi_i32(cmp->cond, cmp->value, 0, label); |
| 726 | } |
| 727 | |
| 728 | void arm_gen_test_cc(int cc, TCGLabel *label) |
| 729 | { |
| 730 | DisasCompare cmp; |
| 731 | arm_test_cc(&cmp, cc); |
| 732 | arm_jump_cc(&cmp, label); |
| 733 | } |
| 734 | |
| 735 | void gen_set_condexec(DisasContext *s) |
| 736 | { |
| 737 | if (s->condexec_mask) { |
| 738 | uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1); |
| 739 | |
| 740 | store_cpu_field_constant(val, condexec_bits); |
| 741 | } |
| 742 | } |
| 743 | |
| 744 | void gen_update_pc(DisasContext *s, int64_t diff) |
| 745 | { |
| 746 | gen_pc_plus_diff(s, cpu_R[15], diff); |
| 747 | s->pc_save = s->pc_curr + diff; |
| 748 | } |
| 749 | |
| 750 | /* Set PC and Thumb state from var. var is marked as dead. */ |
| 751 | static inline void gen_bx(DisasContext *s, TCGv_i32 var) |
| 752 | { |
| 753 | s->base.is_jmp = DISAS_JUMP; |
| 754 | tcg_gen_andi_i32(cpu_R[15], var, ~1); |
| 755 | tcg_gen_andi_i32(var, var, 1); |
| 756 | store_cpu_field(var, thumb); |
| 757 | s->pc_save = -1; |
| 758 | } |
| 759 | |
| 760 | /* |
| 761 | * Set PC and Thumb state from var. var is marked as dead. |
| 762 | * For M-profile CPUs, include logic to detect exception-return |
| 763 | * branches and handle them. This is needed for Thumb POP/LDM to PC, LDR to PC, |
| 764 | * and BX reg, and no others, and happens only for code in Handler mode. |
| 765 | * The Security Extension also requires us to check for the FNC_RETURN |
| 766 | * which signals a function return from non-secure state; this can happen |
| 767 | * in both Handler and Thread mode. |
| 768 | * To avoid having to do multiple comparisons in inline generated code, |
| 769 | * we make the check we do here loose, so it will match for EXC_RETURN |
| 770 | * in Thread mode. For system emulation do_v7m_exception_exit() checks |
| 771 | * for these spurious cases and returns without doing anything (giving |
| 772 | * the same behaviour as for a branch to a non-magic address). |
| 773 | * |
| 774 | * In linux-user mode it is unclear what the right behaviour for an |
| 775 | * attempted FNC_RETURN should be, because in real hardware this will go |
| 776 | * directly to Secure code (ie not the Linux kernel) which will then treat |
| 777 | * the error in any way it chooses. For QEMU we opt to make the FNC_RETURN |
| 778 | * attempt behave the way it would on a CPU without the security extension, |
| 779 | * which is to say "like a normal branch". That means we can simply treat |
| 780 | * all branches as normal with no magic address behaviour. |
| 781 | */ |
| 782 | static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var) |
| 783 | { |
| 784 | /* Generate the same code here as for a simple bx, but flag via |
| 785 | * s->base.is_jmp that we need to do the rest of the work later. |
| 786 | */ |
| 787 | gen_bx(s, var); |
| 788 | #ifndef CONFIG_USER_ONLY |
| 789 | if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY) || |
| 790 | (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M))) { |
| 791 | s->base.is_jmp = DISAS_BX_EXCRET; |
| 792 | } |
| 793 | #endif |
| 794 | } |
| 795 | |
| 796 | static inline void gen_bx_excret_final_code(DisasContext *s) |
| 797 | { |
| 798 | /* Generate the code to finish possible exception return and end the TB */ |
| 799 | DisasLabel excret_label = gen_disas_label(s); |
| 800 | uint32_t min_magic; |
| 801 | |
| 802 | if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY)) { |
| 803 | /* Covers FNC_RETURN and EXC_RETURN magic */ |
| 804 | min_magic = FNC_RETURN_MIN_MAGIC; |
| 805 | } else { |
| 806 | /* EXC_RETURN magic only */ |
| 807 | min_magic = EXC_RETURN_MIN_MAGIC; |
| 808 | } |
| 809 | |
| 810 | /* Is the new PC value in the magic range indicating exception return? */ |
| 811 | tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label.label); |
| 812 | /* No: end the TB as we would for a DISAS_JMP */ |
| 813 | if (s->ss_active) { |
| 814 | gen_singlestep_exception(s); |
| 815 | } else { |
| 816 | tcg_gen_exit_tb(NULL, 0); |
| 817 | } |
| 818 | set_disas_label(s, excret_label); |
| 819 | /* Yes: this is an exception return. |
| 820 | * At this point in runtime env->regs[15] and env->thumb will hold |
| 821 | * the exception-return magic number, which do_v7m_exception_exit() |
| 822 | * will read. Nothing else will be able to see those values because |
| 823 | * the cpu-exec main loop guarantees that we will always go straight |
| 824 | * from raising the exception to the exception-handling code. |
| 825 | * |
| 826 | * gen_ss_advance(s) does nothing on M profile currently but |
| 827 | * calling it is conceptually the right thing as we have executed |
| 828 | * this instruction (compare SWI, HVC, SMC handling). |
| 829 | */ |
| 830 | gen_ss_advance(s); |
| 831 | gen_exception_internal(EXCP_EXCEPTION_EXIT); |
| 832 | } |
| 833 | |
| 834 | static inline void gen_bxns(DisasContext *s, int rm) |
| 835 | { |
| 836 | TCGv_i32 var = load_reg(s, rm); |
| 837 | |
| 838 | /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory |
| 839 | * we need to sync state before calling it, but: |
| 840 | * - we don't need to do gen_update_pc() because the bxns helper will |
| 841 | * always set the PC itself |
| 842 | * - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE |
| 843 | * unless it's outside an IT block or the last insn in an IT block, |
| 844 | * so we know that condexec == 0 (already set at the top of the TB) |
| 845 | * is correct in the non-UNPREDICTABLE cases, and we can choose |
| 846 | * "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise. |
| 847 | */ |
| 848 | gen_helper_v7m_bxns(tcg_env, var); |
| 849 | s->base.is_jmp = DISAS_EXIT; |
| 850 | } |
| 851 | |
| 852 | static inline void gen_blxns(DisasContext *s, int rm) |
| 853 | { |
| 854 | TCGv_i32 var = load_reg(s, rm); |
| 855 | |
| 856 | /* We don't need to sync condexec state, for the same reason as bxns. |
| 857 | * We do however need to set the PC, because the blxns helper reads it. |
| 858 | * The blxns helper may throw an exception. |
| 859 | */ |
| 860 | gen_update_pc(s, curr_insn_len(s)); |
| 861 | gen_helper_v7m_blxns(tcg_env, var); |
| 862 | s->base.is_jmp = DISAS_EXIT; |
| 863 | } |
| 864 | |
| 865 | /* Variant of store_reg which uses branch&exchange logic when storing |
| 866 | to r15 in ARM architecture v7 and above. The source must be a temporary |
| 867 | and will be marked as dead. */ |
| 868 | static inline void store_reg_bx(DisasContext *s, int reg, TCGv_i32 var) |
| 869 | { |
| 870 | if (reg == 15 && ENABLE_ARCH_7) { |
| 871 | gen_bx(s, var); |
| 872 | } else { |
| 873 | store_reg(s, reg, var); |
| 874 | } |
| 875 | } |
| 876 | |
| 877 | /* Variant of store_reg which uses branch&exchange logic when storing |
| 878 | * to r15 in ARM architecture v5T and above. This is used for storing |
| 879 | * the results of a LDR/LDM/POP into r15, and corresponds to the cases |
| 880 | * in the ARM ARM which use the LoadWritePC() pseudocode function. */ |
| 881 | static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var) |
| 882 | { |
| 883 | if (reg == 15 && ENABLE_ARCH_5) { |
| 884 | gen_bx_excret(s, var); |
| 885 | } else { |
| 886 | store_reg(s, reg, var); |
| 887 | } |
| 888 | } |
| 889 | |
| 890 | #ifdef CONFIG_USER_ONLY |
| 891 | #define IS_USER_ONLY 1 |
| 892 | #else |
| 893 | #define IS_USER_ONLY 0 |
| 894 | #endif |
| 895 | |
| 896 | MemOp pow2_align(unsigned i) |
| 897 | { |
| 898 | static const MemOp mop_align[] = { |
| 899 | 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, MO_ALIGN_32 |
| 900 | }; |
| 901 | g_assert(i < ARRAY_SIZE(mop_align)); |
| 902 | return mop_align[i]; |
| 903 | } |
| 904 | |
| 905 | /* |
| 906 | * Abstractions of "generate code to do a guest load/store for |
| 907 | * AArch32", where a vaddr is always 32 bits (and is zero |
| 908 | * extended if we're a 64 bit core) and data is also |
| 909 | * 32 bits unless specifically doing a 64 bit access. |
| 910 | * These functions work like tcg_gen_qemu_{ld,st}* except |
| 911 | * that the address argument is TCGv_i32 rather than TCGv. |
| 912 | */ |
| 913 | |
| 914 | static TCGv_va gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) |
| 915 | { |
| 916 | TCGv_va addr = tcgv_va_temp_new(); |
| 917 | tcg_gen_mov_i32(addr, a32); |
| 918 | |
| 919 | /* Not needed for user-mode BE32, where we use MO_BE instead. */ |
| 920 | if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_32) { |
| 921 | tcg_gen_xori_i32(addr, addr, 4 - (1 << (op & MO_SIZE))); |
| 922 | } |
| 923 | return addr; |
| 924 | } |
| 925 | |
| 926 | /* |
| 927 | * Internal routines are used for NEON cases where the endianness |
| 928 | * and/or alignment has already been taken into account and manipulated. |
| 929 | */ |
| 930 | void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, |
| 931 | TCGv_i32 a32, int index, MemOp opc) |
| 932 | { |
| 933 | TCGv_va addr = gen_aa32_addr(s, a32, opc); |
| 934 | tcg_gen_qemu_ld_i32(val, addr, index, opc); |
| 935 | } |
| 936 | |
| 937 | void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, |
| 938 | TCGv_i32 a32, int index, MemOp opc) |
| 939 | { |
| 940 | TCGv_va addr = gen_aa32_addr(s, a32, opc); |
| 941 | tcg_gen_qemu_st_i32(val, addr, index, opc); |
| 942 | } |
| 943 | |
| 944 | void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, |
| 945 | TCGv_i32 a32, int index, MemOp opc) |
| 946 | { |
| 947 | TCGv_va addr = gen_aa32_addr(s, a32, opc); |
| 948 | |
| 949 | tcg_gen_qemu_ld_i64(val, addr, index, opc); |
| 950 | |
| 951 | /* Not needed for user-mode BE32, where we use MO_BE instead. */ |
| 952 | if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { |
| 953 | tcg_gen_rotri_i64(val, val, 32); |
| 954 | } |
| 955 | } |
| 956 | |
| 957 | void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, |
| 958 | TCGv_i32 a32, int index, MemOp opc) |
| 959 | { |
| 960 | TCGv_va addr = gen_aa32_addr(s, a32, opc); |
| 961 | |
| 962 | /* Not needed for user-mode BE32, where we use MO_BE instead. */ |
| 963 | if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { |
| 964 | TCGv_i64 tmp = tcg_temp_new_i64(); |
| 965 | tcg_gen_rotri_i64(tmp, val, 32); |
| 966 | tcg_gen_qemu_st_i64(tmp, addr, index, opc); |
| 967 | } else { |
| 968 | tcg_gen_qemu_st_i64(val, addr, index, opc); |
| 969 | } |
| 970 | } |
| 971 | |
| 972 | void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, |
| 973 | int index, MemOp opc) |
| 974 | { |
| 975 | gen_aa32_ld_internal_i32(s, val, a32, index, finalize_memop(s, opc)); |
| 976 | } |
| 977 | |
| 978 | void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, |
| 979 | int index, MemOp opc) |
| 980 | { |
| 981 | gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); |
| 982 | } |
| 983 | |
| 984 | void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, |
| 985 | int index, MemOp opc) |
| 986 | { |
| 987 | gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc)); |
| 988 | } |
| 989 | |
| 990 | void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, |
| 991 | int index, MemOp opc) |
| 992 | { |
| 993 | gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc)); |
| 994 | } |
| 995 | |
| 996 | #define DO_GEN_LD(SUFF, OPC) \ |
| 997 | static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ |
| 998 | TCGv_i32 a32, int index) \ |
| 999 | { \ |
| 1000 | gen_aa32_ld_i32(s, val, a32, index, OPC); \ |
| 1001 | } |
| 1002 | |
| 1003 | #define DO_GEN_ST(SUFF, OPC) \ |
| 1004 | static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ |
| 1005 | TCGv_i32 a32, int index) \ |
| 1006 | { \ |
| 1007 | gen_aa32_st_i32(s, val, a32, index, OPC); \ |
| 1008 | } |
| 1009 | |
| 1010 | static inline void gen_hvc(DisasContext *s, int imm16) |
| 1011 | { |
| 1012 | /* The pre HVC helper handles cases when HVC gets trapped |
| 1013 | * as an undefined insn by runtime configuration (ie before |
| 1014 | * the insn really executes). |
| 1015 | */ |
| 1016 | gen_update_pc(s, 0); |
| 1017 | gen_helper_pre_hvc(tcg_env); |
| 1018 | /* Otherwise we will treat this as a real exception which |
| 1019 | * happens after execution of the insn. (The distinction matters |
| 1020 | * for the PC value reported to the exception handler and also |
| 1021 | * for single stepping.) |
| 1022 | */ |
| 1023 | s->svc_imm = imm16; |
| 1024 | gen_update_pc(s, curr_insn_len(s)); |
| 1025 | s->base.is_jmp = DISAS_HVC; |
| 1026 | } |
| 1027 | |
| 1028 | static inline void gen_smc(DisasContext *s) |
| 1029 | { |
| 1030 | /* As with HVC, we may take an exception either before or after |
| 1031 | * the insn executes. |
| 1032 | */ |
| 1033 | gen_update_pc(s, 0); |
| 1034 | gen_helper_pre_smc(tcg_env, tcg_constant_i32(syn_aa32_smc())); |
| 1035 | gen_update_pc(s, curr_insn_len(s)); |
| 1036 | s->base.is_jmp = DISAS_SMC; |
| 1037 | } |
| 1038 | |
| 1039 | static void gen_exception_internal_insn(DisasContext *s, int excp) |
| 1040 | { |
| 1041 | gen_set_condexec(s); |
| 1042 | gen_update_pc(s, 0); |
| 1043 | gen_exception_internal(excp); |
| 1044 | s->base.is_jmp = DISAS_NORETURN; |
| 1045 | } |
| 1046 | |
| 1047 | static void gen_exception_el_v(int excp, uint32_t syndrome, TCGv_i32 tcg_el) |
| 1048 | { |
| 1049 | gen_helper_exception_with_syndrome_el(tcg_env, tcg_constant_i32(excp), |
| 1050 | tcg_constant_i32(syndrome), tcg_el); |
| 1051 | } |
| 1052 | |
| 1053 | static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) |
| 1054 | { |
| 1055 | gen_exception_el_v(excp, syndrome, tcg_constant_i32(target_el)); |
| 1056 | } |
| 1057 | |
| 1058 | static void gen_exception(int excp, uint32_t syndrome) |
| 1059 | { |
| 1060 | gen_helper_exception_with_syndrome(tcg_env, tcg_constant_i32(excp), |
| 1061 | tcg_constant_i32(syndrome)); |
| 1062 | } |
| 1063 | |
| 1064 | static void gen_exception_insn_el_v(DisasContext *s, int64_t pc_diff, |
| 1065 | int excp, uint32_t syn, TCGv_i32 tcg_el) |
| 1066 | { |
| 1067 | if (s->aarch64) { |
| 1068 | gen_a64_update_pc(s, pc_diff); |
| 1069 | } else { |
| 1070 | gen_set_condexec(s); |
| 1071 | gen_update_pc(s, pc_diff); |
| 1072 | } |
| 1073 | gen_exception_el_v(excp, syn, tcg_el); |
| 1074 | s->base.is_jmp = DISAS_NORETURN; |
| 1075 | } |
| 1076 | |
| 1077 | void gen_exception_insn_el(DisasContext *s, int64_t pc_diff, int excp, |
| 1078 | uint32_t syn, uint32_t target_el) |
| 1079 | { |
| 1080 | gen_exception_insn_el_v(s, pc_diff, excp, syn, |
| 1081 | tcg_constant_i32(target_el)); |
| 1082 | } |
| 1083 | |
| 1084 | void gen_exception_insn(DisasContext *s, int64_t pc_diff, |
| 1085 | int excp, uint32_t syn) |
| 1086 | { |
| 1087 | if (s->aarch64) { |
| 1088 | gen_a64_update_pc(s, pc_diff); |
| 1089 | } else { |
| 1090 | gen_set_condexec(s); |
| 1091 | gen_update_pc(s, pc_diff); |
| 1092 | } |
| 1093 | gen_exception(excp, syn); |
| 1094 | s->base.is_jmp = DISAS_NORETURN; |
| 1095 | } |
| 1096 | |
| 1097 | TCGLabel *delay_exception_el(DisasContext *s, int excp, |
| 1098 | uint32_t syn, uint32_t target_el) |
| 1099 | { |
| 1100 | /* Use tcg_malloc for automatic release on longjmp out of translation. */ |
| 1101 | DisasDelayException *e = tcg_malloc(sizeof(DisasDelayException)); |
| 1102 | |
| 1103 | memset(e, 0, sizeof(*e)); |
| 1104 | |
| 1105 | /* Save enough of the current state to satisfy gen_exception_insn. */ |
| 1106 | e->pc_curr = s->pc_curr; |
| 1107 | e->pc_save = s->pc_save; |
| 1108 | if (!s->aarch64) { |
| 1109 | e->condexec_cond = s->condexec_cond; |
| 1110 | e->condexec_mask = s->condexec_mask; |
| 1111 | } |
| 1112 | |
| 1113 | e->excp = excp; |
| 1114 | e->syn = syn; |
| 1115 | e->target_el = target_el; |
| 1116 | |
| 1117 | e->next = s->delay_excp_list; |
| 1118 | s->delay_excp_list = e; |
| 1119 | |
| 1120 | e->lab = gen_new_label(); |
| 1121 | return e->lab; |
| 1122 | } |
| 1123 | |
| 1124 | TCGLabel *delay_exception(DisasContext *s, int excp, uint32_t syn) |
| 1125 | { |
| 1126 | return delay_exception_el(s, excp, syn, 0); |
| 1127 | } |
| 1128 | |
| 1129 | void emit_delayed_exceptions(DisasContext *s) |
| 1130 | { |
| 1131 | for (DisasDelayException *e = s->delay_excp_list; e ; e = e->next) { |
| 1132 | gen_set_label(e->lab); |
| 1133 | |
| 1134 | /* Restore the insn state to satisfy gen_exception_insn. */ |
| 1135 | s->pc_curr = e->pc_curr; |
| 1136 | s->pc_save = e->pc_save; |
| 1137 | s->condexec_cond = e->condexec_cond; |
| 1138 | s->condexec_mask = e->condexec_mask; |
| 1139 | |
| 1140 | if (e->target_el) { |
| 1141 | gen_exception_insn_el(s, 0, e->excp, e->syn, e->target_el); |
| 1142 | } else { |
| 1143 | gen_exception_insn(s, 0, e->excp, e->syn); |
| 1144 | } |
| 1145 | } |
| 1146 | } |
| 1147 | |
| 1148 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) |
| 1149 | { |
| 1150 | gen_set_condexec(s); |
| 1151 | gen_update_pc(s, 0); |
| 1152 | gen_helper_exception_bkpt_insn(tcg_env, tcg_constant_i32(syn)); |
| 1153 | s->base.is_jmp = DISAS_NORETURN; |
| 1154 | } |
| 1155 | |
| 1156 | void unallocated_encoding(DisasContext *s) |
| 1157 | { |
| 1158 | /* Unallocated and reserved encodings are uncategorized */ |
| 1159 | gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized()); |
| 1160 | } |
| 1161 | |
| 1162 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
| 1163 | void gen_lookup_tb(DisasContext *s) |
| 1164 | { |
| 1165 | gen_pc_plus_diff(s, cpu_R[15], curr_insn_len(s)); |
| 1166 | s->base.is_jmp = DISAS_EXIT; |
| 1167 | } |
| 1168 | |
| 1169 | static inline void gen_hlt(DisasContext *s, int imm) |
| 1170 | { |
| 1171 | /* HLT. This has two purposes. |
| 1172 | * Architecturally, it is an external halting debug instruction. |
| 1173 | * Since QEMU doesn't implement external debug, we treat this as |
| 1174 | * it is required for halting debug disabled: it will UNDEF. |
| 1175 | * Secondly, "HLT 0x3C" is a T32 semihosting trap instruction, |
| 1176 | * and "HLT 0xF000" is an A32 semihosting syscall. These traps |
| 1177 | * must trigger semihosting even for ARMv7 and earlier, where |
| 1178 | * HLT was an undefined encoding. |
| 1179 | * In system mode, we don't allow userspace access to |
| 1180 | * semihosting, to provide some semblance of security |
| 1181 | * (and for consistency with our 32-bit semihosting). |
| 1182 | */ |
| 1183 | if (semihosting_enabled(s->current_el == 0) && |
| 1184 | (imm == (s->thumb ? 0x3c : 0xf000))) { |
| 1185 | gen_exception_internal_insn(s, EXCP_SEMIHOST); |
| 1186 | return; |
| 1187 | } |
| 1188 | |
| 1189 | unallocated_encoding(s); |
| 1190 | } |
| 1191 | |
| 1192 | /* |
| 1193 | * Return the offset of a "full" NEON Dreg. |
| 1194 | */ |
| 1195 | long neon_full_reg_offset(unsigned reg) |
| 1196 | { |
| 1197 | return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); |
| 1198 | } |
| 1199 | |
| 1200 | /* |
| 1201 | * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, |
| 1202 | * where 0 is the least significant end of the register. |
| 1203 | */ |
| 1204 | long neon_element_offset(int reg, int element, MemOp memop) |
| 1205 | { |
| 1206 | int element_size = 1 << (memop & MO_SIZE); |
| 1207 | int ofs = element * element_size; |
| 1208 | #if HOST_BIG_ENDIAN |
| 1209 | /* |
| 1210 | * Calculate the offset assuming fully little-endian, |
| 1211 | * then XOR to account for the order of the 8-byte units. |
| 1212 | */ |
| 1213 | if (element_size < 8) { |
| 1214 | ofs ^= 8 - element_size; |
| 1215 | } |
| 1216 | #endif |
| 1217 | return neon_full_reg_offset(reg) + ofs; |
| 1218 | } |
| 1219 | |
| 1220 | /* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */ |
| 1221 | long vfp_reg_offset(bool dp, unsigned reg) |
| 1222 | { |
| 1223 | if (dp) { |
| 1224 | return neon_element_offset(reg, 0, MO_64); |
| 1225 | } else { |
| 1226 | return neon_element_offset(reg >> 1, reg & 1, MO_32); |
| 1227 | } |
| 1228 | } |
| 1229 | |
| 1230 | void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) |
| 1231 | { |
| 1232 | long off = neon_element_offset(reg, ele, memop); |
| 1233 | |
| 1234 | switch (memop) { |
| 1235 | case MO_SB: |
| 1236 | tcg_gen_ld8s_i32(dest, tcg_env, off); |
| 1237 | break; |
| 1238 | case MO_UB: |
| 1239 | tcg_gen_ld8u_i32(dest, tcg_env, off); |
| 1240 | break; |
| 1241 | case MO_SW: |
| 1242 | tcg_gen_ld16s_i32(dest, tcg_env, off); |
| 1243 | break; |
| 1244 | case MO_UW: |
| 1245 | tcg_gen_ld16u_i32(dest, tcg_env, off); |
| 1246 | break; |
| 1247 | case MO_UL: |
| 1248 | case MO_SL: |
| 1249 | tcg_gen_ld_i32(dest, tcg_env, off); |
| 1250 | break; |
| 1251 | default: |
| 1252 | g_assert_not_reached(); |
| 1253 | } |
| 1254 | } |
| 1255 | |
| 1256 | void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) |
| 1257 | { |
| 1258 | long off = neon_element_offset(reg, ele, memop); |
| 1259 | |
| 1260 | switch (memop) { |
| 1261 | case MO_SL: |
| 1262 | tcg_gen_ld32s_i64(dest, tcg_env, off); |
| 1263 | break; |
| 1264 | case MO_UL: |
| 1265 | tcg_gen_ld32u_i64(dest, tcg_env, off); |
| 1266 | break; |
| 1267 | case MO_UQ: |
| 1268 | tcg_gen_ld_i64(dest, tcg_env, off); |
| 1269 | break; |
| 1270 | default: |
| 1271 | g_assert_not_reached(); |
| 1272 | } |
| 1273 | } |
| 1274 | |
| 1275 | void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) |
| 1276 | { |
| 1277 | long off = neon_element_offset(reg, ele, memop); |
| 1278 | |
| 1279 | switch (memop) { |
| 1280 | case MO_8: |
| 1281 | tcg_gen_st8_i32(src, tcg_env, off); |
| 1282 | break; |
| 1283 | case MO_16: |
| 1284 | tcg_gen_st16_i32(src, tcg_env, off); |
| 1285 | break; |
| 1286 | case MO_32: |
| 1287 | tcg_gen_st_i32(src, tcg_env, off); |
| 1288 | break; |
| 1289 | default: |
| 1290 | g_assert_not_reached(); |
| 1291 | } |
| 1292 | } |
| 1293 | |
| 1294 | void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) |
| 1295 | { |
| 1296 | long off = neon_element_offset(reg, ele, memop); |
| 1297 | |
| 1298 | switch (memop) { |
| 1299 | case MO_32: |
| 1300 | tcg_gen_st32_i64(src, tcg_env, off); |
| 1301 | break; |
| 1302 | case MO_64: |
| 1303 | tcg_gen_st_i64(src, tcg_env, off); |
| 1304 | break; |
| 1305 | default: |
| 1306 | g_assert_not_reached(); |
| 1307 | } |
| 1308 | } |
| 1309 | |
| 1310 | static void gen_goto_ptr(void) |
| 1311 | { |
| 1312 | tcg_gen_lookup_and_goto_ptr(); |
| 1313 | } |
| 1314 | |
| 1315 | /* This will end the TB but doesn't guarantee we'll return to |
| 1316 | * cpu_loop_exec. Any live exit_requests will be processed as we |
| 1317 | * enter the next TB. |
| 1318 | */ |
| 1319 | static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, int64_t diff) |
| 1320 | { |
| 1321 | if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) { |
| 1322 | /* |
| 1323 | * For pcrel, the pc must always be up-to-date on entry to |
| 1324 | * the linked TB, so that it can use simple additions for all |
| 1325 | * further adjustments. For !pcrel, the linked TB is compiled |
| 1326 | * to know its full virtual address, so we can delay the |
| 1327 | * update to pc to the unlinked path. A long chain of links |
| 1328 | * can thus avoid many updates to the PC. |
| 1329 | */ |
| 1330 | if (tb_cflags(s->base.tb) & CF_PCREL) { |
| 1331 | gen_update_pc(s, diff); |
| 1332 | tcg_gen_goto_tb(tb_slot_idx); |
| 1333 | } else { |
| 1334 | tcg_gen_goto_tb(tb_slot_idx); |
| 1335 | gen_update_pc(s, diff); |
| 1336 | } |
| 1337 | tcg_gen_exit_tb(s->base.tb, tb_slot_idx); |
| 1338 | } else { |
| 1339 | gen_update_pc(s, diff); |
| 1340 | gen_goto_ptr(); |
| 1341 | } |
| 1342 | s->base.is_jmp = DISAS_NORETURN; |
| 1343 | } |
| 1344 | |
| 1345 | /* Jump, specifying which TB number to use if we gen_goto_tb() */ |
| 1346 | static void gen_jmp_tb(DisasContext *s, int64_t diff, int tbno) |
| 1347 | { |
| 1348 | if (unlikely(s->ss_active)) { |
| 1349 | /* An indirect jump so that we still trigger the debug exception. */ |
| 1350 | gen_update_pc(s, diff); |
| 1351 | s->base.is_jmp = DISAS_JUMP; |
| 1352 | return; |
| 1353 | } |
| 1354 | switch (s->base.is_jmp) { |
| 1355 | case DISAS_NEXT: |
| 1356 | case DISAS_TOO_MANY: |
| 1357 | case DISAS_NORETURN: |
| 1358 | /* |
| 1359 | * The normal case: just go to the destination TB. |
| 1360 | * NB: NORETURN happens if we generate code like |
| 1361 | * gen_brcondi(l); |
| 1362 | * gen_jmp(); |
| 1363 | * gen_set_label(l); |
| 1364 | * gen_jmp(); |
| 1365 | * on the second call to gen_jmp(). |
| 1366 | */ |
| 1367 | gen_goto_tb(s, tbno, diff); |
| 1368 | break; |
| 1369 | case DISAS_UPDATE_NOCHAIN: |
| 1370 | case DISAS_UPDATE_EXIT: |
| 1371 | /* |
| 1372 | * We already decided we're leaving the TB for some other reason. |
| 1373 | * Avoid using goto_tb so we really do exit back to the main loop |
| 1374 | * and don't chain to another TB. |
| 1375 | */ |
| 1376 | gen_update_pc(s, diff); |
| 1377 | gen_goto_ptr(); |
| 1378 | s->base.is_jmp = DISAS_NORETURN; |
| 1379 | break; |
| 1380 | default: |
| 1381 | /* |
| 1382 | * We shouldn't be emitting code for a jump and also have |
| 1383 | * is_jmp set to one of the special cases like DISAS_SWI. |
| 1384 | */ |
| 1385 | g_assert_not_reached(); |
| 1386 | } |
| 1387 | } |
| 1388 | |
| 1389 | static inline void gen_jmp(DisasContext *s, int64_t diff) |
| 1390 | { |
| 1391 | gen_jmp_tb(s, diff, 0); |
| 1392 | } |
| 1393 | |
| 1394 | static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y) |
| 1395 | { |
| 1396 | if (x) |
| 1397 | tcg_gen_sari_i32(t0, t0, 16); |
| 1398 | else |
| 1399 | gen_sxth(t0); |
| 1400 | if (y) |
| 1401 | tcg_gen_sari_i32(t1, t1, 16); |
| 1402 | else |
| 1403 | gen_sxth(t1); |
| 1404 | tcg_gen_mul_i32(t0, t0, t1); |
| 1405 | } |
| 1406 | |
| 1407 | /* Return the mask of PSR bits set by a MSR instruction. */ |
| 1408 | static uint32_t msr_mask(DisasContext *s, int flags, int spsr) |
| 1409 | { |
| 1410 | uint32_t mask = 0; |
| 1411 | |
| 1412 | if (flags & (1 << 0)) { |
| 1413 | mask |= 0xff; |
| 1414 | } |
| 1415 | if (flags & (1 << 1)) { |
| 1416 | mask |= 0xff00; |
| 1417 | } |
| 1418 | if (flags & (1 << 2)) { |
| 1419 | mask |= 0xff0000; |
| 1420 | } |
| 1421 | if (flags & (1 << 3)) { |
| 1422 | mask |= 0xff000000; |
| 1423 | } |
| 1424 | |
| 1425 | /* Mask out undefined and reserved bits. */ |
| 1426 | mask &= aarch32_cpsr_valid_mask(s->features, s->isar); |
| 1427 | |
| 1428 | /* Mask out execution state. */ |
| 1429 | if (!spsr) { |
| 1430 | mask &= ~CPSR_EXEC; |
| 1431 | } |
| 1432 | |
| 1433 | /* Mask out privileged bits. */ |
| 1434 | if (IS_USER(s)) { |
| 1435 | mask &= CPSR_USER; |
| 1436 | } |
| 1437 | return mask; |
| 1438 | } |
| 1439 | |
| 1440 | /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */ |
| 1441 | static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv_i32 t0) |
| 1442 | { |
| 1443 | TCGv_i32 tmp; |
| 1444 | if (spsr) { |
| 1445 | /* ??? This is also undefined in system mode. */ |
| 1446 | if (IS_USER(s)) |
| 1447 | return 1; |
| 1448 | |
| 1449 | tmp = load_cpu_field(spsr); |
| 1450 | tcg_gen_andi_i32(tmp, tmp, ~mask); |
| 1451 | tcg_gen_andi_i32(t0, t0, mask); |
| 1452 | tcg_gen_or_i32(tmp, tmp, t0); |
| 1453 | store_cpu_field(tmp, spsr); |
| 1454 | } else { |
| 1455 | gen_set_cpsr(t0, mask); |
| 1456 | } |
| 1457 | gen_lookup_tb(s); |
| 1458 | return 0; |
| 1459 | } |
| 1460 | |
| 1461 | /* Returns nonzero if access to the PSR is not permitted. */ |
| 1462 | static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val) |
| 1463 | { |
| 1464 | TCGv_i32 tmp; |
| 1465 | tmp = tcg_temp_new_i32(); |
| 1466 | tcg_gen_movi_i32(tmp, val); |
| 1467 | return gen_set_psr(s, mask, spsr, tmp); |
| 1468 | } |
| 1469 | |
| 1470 | static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, |
| 1471 | int *tgtmode, int *regno) |
| 1472 | { |
| 1473 | /* Decode the r and sysm fields of MSR/MRS banked accesses into |
| 1474 | * the target mode and register number, and identify the various |
| 1475 | * unpredictable cases. |
| 1476 | * MSR (banked) and MRS (banked) are CONSTRAINED UNPREDICTABLE if: |
| 1477 | * + executed in user mode |
| 1478 | * + using R15 as the src/dest register |
| 1479 | * + accessing an unimplemented register |
| 1480 | * + accessing a register that's inaccessible at current PL/security state* |
| 1481 | * + accessing a register that you could access with a different insn |
| 1482 | * We choose to UNDEF in all these cases. |
| 1483 | * Since we don't know which of the various AArch32 modes we are in |
| 1484 | * we have to defer some checks to runtime. |
| 1485 | * Accesses to Monitor mode registers from Secure EL1 (which implies |
| 1486 | * that EL3 is AArch64) must trap to EL3. |
| 1487 | * |
| 1488 | * If the access checks fail this function will emit code to take |
| 1489 | * an exception and return false. Otherwise it will return true, |
| 1490 | * and set *tgtmode and *regno appropriately. |
| 1491 | */ |
| 1492 | /* These instructions are present only in ARMv8, or in ARMv7 with the |
| 1493 | * Virtualization Extensions. |
| 1494 | */ |
| 1495 | if (!arm_dc_feature(s, ARM_FEATURE_V8) && |
| 1496 | !arm_dc_feature(s, ARM_FEATURE_EL2)) { |
| 1497 | goto undef; |
| 1498 | } |
| 1499 | |
| 1500 | if (IS_USER(s) || rn == 15) { |
| 1501 | goto undef; |
| 1502 | } |
| 1503 | |
| 1504 | /* The table in the v8 ARM ARM section F5.2.3 describes the encoding |
| 1505 | * of registers into (r, sysm). |
| 1506 | */ |
| 1507 | if (r) { |
| 1508 | /* SPSRs for other modes */ |
| 1509 | switch (sysm) { |
| 1510 | case 0xe: /* SPSR_fiq */ |
| 1511 | *tgtmode = ARM_CPU_MODE_FIQ; |
| 1512 | break; |
| 1513 | case 0x10: /* SPSR_irq */ |
| 1514 | *tgtmode = ARM_CPU_MODE_IRQ; |
| 1515 | break; |
| 1516 | case 0x12: /* SPSR_svc */ |
| 1517 | *tgtmode = ARM_CPU_MODE_SVC; |
| 1518 | break; |
| 1519 | case 0x14: /* SPSR_abt */ |
| 1520 | *tgtmode = ARM_CPU_MODE_ABT; |
| 1521 | break; |
| 1522 | case 0x16: /* SPSR_und */ |
| 1523 | *tgtmode = ARM_CPU_MODE_UND; |
| 1524 | break; |
| 1525 | case 0x1c: /* SPSR_mon */ |
| 1526 | *tgtmode = ARM_CPU_MODE_MON; |
| 1527 | break; |
| 1528 | case 0x1e: /* SPSR_hyp */ |
| 1529 | *tgtmode = ARM_CPU_MODE_HYP; |
| 1530 | break; |
| 1531 | default: /* unallocated */ |
| 1532 | goto undef; |
| 1533 | } |
| 1534 | /* We arbitrarily assign SPSR a register number of 16. */ |
| 1535 | *regno = 16; |
| 1536 | } else { |
| 1537 | /* general purpose registers for other modes */ |
| 1538 | switch (sysm) { |
| 1539 | case 0x0 ... 0x6: /* 0b00xxx : r8_usr ... r14_usr */ |
| 1540 | *tgtmode = ARM_CPU_MODE_USR; |
| 1541 | *regno = sysm + 8; |
| 1542 | break; |
| 1543 | case 0x8 ... 0xe: /* 0b01xxx : r8_fiq ... r14_fiq */ |
| 1544 | *tgtmode = ARM_CPU_MODE_FIQ; |
| 1545 | *regno = sysm; |
| 1546 | break; |
| 1547 | case 0x10 ... 0x11: /* 0b1000x : r14_irq, r13_irq */ |
| 1548 | *tgtmode = ARM_CPU_MODE_IRQ; |
| 1549 | *regno = sysm & 1 ? 13 : 14; |
| 1550 | break; |
| 1551 | case 0x12 ... 0x13: /* 0b1001x : r14_svc, r13_svc */ |
| 1552 | *tgtmode = ARM_CPU_MODE_SVC; |
| 1553 | *regno = sysm & 1 ? 13 : 14; |
| 1554 | break; |
| 1555 | case 0x14 ... 0x15: /* 0b1010x : r14_abt, r13_abt */ |
| 1556 | *tgtmode = ARM_CPU_MODE_ABT; |
| 1557 | *regno = sysm & 1 ? 13 : 14; |
| 1558 | break; |
| 1559 | case 0x16 ... 0x17: /* 0b1011x : r14_und, r13_und */ |
| 1560 | *tgtmode = ARM_CPU_MODE_UND; |
| 1561 | *regno = sysm & 1 ? 13 : 14; |
| 1562 | break; |
| 1563 | case 0x1c ... 0x1d: /* 0b1110x : r14_mon, r13_mon */ |
| 1564 | *tgtmode = ARM_CPU_MODE_MON; |
| 1565 | *regno = sysm & 1 ? 13 : 14; |
| 1566 | break; |
| 1567 | case 0x1e ... 0x1f: /* 0b1111x : elr_hyp, r13_hyp */ |
| 1568 | *tgtmode = ARM_CPU_MODE_HYP; |
| 1569 | /* Arbitrarily pick 17 for ELR_Hyp (which is not a banked LR!) */ |
| 1570 | *regno = sysm & 1 ? 13 : 17; |
| 1571 | break; |
| 1572 | default: /* unallocated */ |
| 1573 | goto undef; |
| 1574 | } |
| 1575 | } |
| 1576 | |
| 1577 | /* Catch the 'accessing inaccessible register' cases we can detect |
| 1578 | * at translate time. |
| 1579 | */ |
| 1580 | switch (*tgtmode) { |
| 1581 | case ARM_CPU_MODE_MON: |
| 1582 | if (!arm_dc_feature(s, ARM_FEATURE_EL3) || s->ns) { |
| 1583 | goto undef; |
| 1584 | } |
| 1585 | if (s->current_el == 1) { |
| 1586 | /* If we're in Secure EL1 (which implies that EL3 is AArch64) |
| 1587 | * then accesses to Mon registers trap to Secure EL2, if it exists, |
| 1588 | * otherwise EL3. |
| 1589 | */ |
| 1590 | TCGv_i32 tcg_el; |
| 1591 | |
| 1592 | if (arm_dc_feature(s, ARM_FEATURE_AARCH64) && |
| 1593 | dc_isar_feature(aa64_sel2, s)) { |
| 1594 | /* Target EL is EL<3 minus SCR_EL3.EEL2> */ |
| 1595 | tcg_el = load_cpu_field_low32(cp15.scr_el3); |
| 1596 | tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1); |
| 1597 | tcg_gen_addi_i32(tcg_el, tcg_el, 3); |
| 1598 | } else { |
| 1599 | tcg_el = tcg_constant_i32(3); |
| 1600 | } |
| 1601 | |
| 1602 | gen_exception_insn_el_v(s, 0, EXCP_UDEF, |
| 1603 | syn_uncategorized(), tcg_el); |
| 1604 | return false; |
| 1605 | } |
| 1606 | break; |
| 1607 | case ARM_CPU_MODE_HYP: |
| 1608 | /* |
| 1609 | * r13_hyp can only be accessed from Monitor mode, and so we |
| 1610 | * can forbid accesses from EL2 or below. |
| 1611 | * elr_hyp can be accessed also from Hyp mode, so forbid |
| 1612 | * accesses from EL0 or EL1. |
| 1613 | * SPSR_hyp is supposed to be in the same category as r13_hyp |
| 1614 | * and UNPREDICTABLE if accessed from anything except Monitor |
| 1615 | * mode. However there is some real-world code that will do |
| 1616 | * it because at least some hardware happens to permit the |
| 1617 | * access. (Notably a standard Cortex-R52 startup code fragment |
| 1618 | * does this.) So we permit SPSR_hyp from Hyp mode also, to allow |
| 1619 | * this (incorrect) guest code to run. |
| 1620 | */ |
| 1621 | if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 |
| 1622 | || (s->current_el < 3 && *regno != 16 && *regno != 17)) { |
| 1623 | goto undef; |
| 1624 | } |
| 1625 | break; |
| 1626 | default: |
| 1627 | break; |
| 1628 | } |
| 1629 | |
| 1630 | return true; |
| 1631 | |
| 1632 | undef: |
| 1633 | /* If we get here then some access check did not pass */ |
| 1634 | gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized()); |
| 1635 | return false; |
| 1636 | } |
| 1637 | |
| 1638 | static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) |
| 1639 | { |
| 1640 | TCGv_i32 tcg_reg; |
| 1641 | int tgtmode = 0, regno = 0; |
| 1642 | |
| 1643 | if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, ®no)) { |
| 1644 | return; |
| 1645 | } |
| 1646 | |
| 1647 | /* Sync state because msr_banked() can raise exceptions */ |
| 1648 | gen_set_condexec(s); |
| 1649 | gen_update_pc(s, 0); |
| 1650 | tcg_reg = load_reg(s, rn); |
| 1651 | gen_helper_msr_banked(tcg_env, tcg_reg, |
| 1652 | tcg_constant_i32(tgtmode), |
| 1653 | tcg_constant_i32(regno)); |
| 1654 | s->base.is_jmp = DISAS_UPDATE_EXIT; |
| 1655 | } |
| 1656 | |
| 1657 | static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) |
| 1658 | { |
| 1659 | TCGv_i32 tcg_reg; |
| 1660 | int tgtmode = 0, regno = 0; |
| 1661 | |
| 1662 | if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, ®no)) { |
| 1663 | return; |
| 1664 | } |
| 1665 | |
| 1666 | /* Sync state because mrs_banked() can raise exceptions */ |
| 1667 | gen_set_condexec(s); |
| 1668 | gen_update_pc(s, 0); |
| 1669 | tcg_reg = tcg_temp_new_i32(); |
| 1670 | gen_helper_mrs_banked(tcg_reg, tcg_env, |
| 1671 | tcg_constant_i32(tgtmode), |
| 1672 | tcg_constant_i32(regno)); |
| 1673 | store_reg(s, rn, tcg_reg); |
| 1674 | s->base.is_jmp = DISAS_UPDATE_EXIT; |
| 1675 | } |
| 1676 | |
| 1677 | /* Store value to PC as for an exception return (ie don't |
| 1678 | * mask bits). The subsequent call to gen_helper_cpsr_write_eret() |
| 1679 | * will do the masking based on the new value of the Thumb bit. |
| 1680 | */ |
| 1681 | static void store_pc_exc_ret(DisasContext *s, TCGv_i32 pc) |
| 1682 | { |
| 1683 | tcg_gen_mov_i32(cpu_R[15], pc); |
| 1684 | } |
| 1685 | |
| 1686 | /* Generate a v6 exception return. Marks both values as dead. */ |
| 1687 | static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr) |
| 1688 | { |
| 1689 | store_pc_exc_ret(s, pc); |
| 1690 | /* The cpsr_write_eret helper will mask the low bits of PC |
| 1691 | * appropriately depending on the new Thumb bit, so it must |
| 1692 | * be called after storing the new PC. |
| 1693 | */ |
| 1694 | translator_io_start(&s->base); |
| 1695 | gen_helper_cpsr_write_eret(tcg_env, cpsr); |
| 1696 | /* Must exit loop to check un-masked IRQs */ |
| 1697 | s->base.is_jmp = DISAS_EXIT; |
| 1698 | } |
| 1699 | |
| 1700 | /* Generate an old-style exception return. Marks pc as dead. */ |
| 1701 | static void gen_exception_return(DisasContext *s, TCGv_i32 pc) |
| 1702 | { |
| 1703 | gen_rfe(s, pc, load_cpu_field(spsr)); |
| 1704 | } |
| 1705 | |
| 1706 | static bool aa32_cpreg_encoding_in_impdef_space(uint8_t crn, uint8_t crm) |
| 1707 | { |
| 1708 | static const uint16_t mask[3] = { |
| 1709 | 0b0000000111100111, /* crn == 9, crm == {c0-c2, c5-c8} */ |
| 1710 | 0b0000000100010011, /* crn == 10, crm == {c0, c1, c4, c8} */ |
| 1711 | 0b1000000111111111, /* crn == 11, crm == {c0-c8, c15} */ |
| 1712 | }; |
| 1713 | |
| 1714 | if (crn >= 9 && crn <= 11) { |
| 1715 | return (mask[crn - 9] >> crm) & 1; |
| 1716 | } |
| 1717 | return false; |
| 1718 | } |
| 1719 | |
| 1720 | static void do_coproc_insn(DisasContext *s, int cpnum, int is64, |
| 1721 | int opc1, int crn, int crm, int opc2, |
| 1722 | bool isread, int rt, int rt2) |
| 1723 | { |
| 1724 | uint32_t key = ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2); |
| 1725 | const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key); |
| 1726 | TCGv_ptr tcg_ri = NULL; |
| 1727 | bool need_exit_tb = false; |
| 1728 | uint32_t syndrome; |
| 1729 | |
| 1730 | /* |
| 1731 | * Note that since we are an implementation which takes an |
| 1732 | * exception on a trapped conditional instruction only if the |
| 1733 | * instruction passes its condition code check, we can take |
| 1734 | * advantage of the clause in the ARM ARM that allows us to set |
| 1735 | * the COND field in the instruction to 0xE in all cases. |
| 1736 | * We could fish the actual condition out of the insn (ARM) |
| 1737 | * or the condexec bits (Thumb) but it isn't necessary. |
| 1738 | */ |
| 1739 | switch (cpnum) { |
| 1740 | case 14: |
| 1741 | if (is64) { |
| 1742 | syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, |
| 1743 | isread, false); |
| 1744 | } else { |
| 1745 | syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, |
| 1746 | rt, isread, false); |
| 1747 | } |
| 1748 | break; |
| 1749 | case 15: |
| 1750 | if (is64) { |
| 1751 | syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, |
| 1752 | isread, false); |
| 1753 | } else { |
| 1754 | syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, |
| 1755 | rt, isread, false); |
| 1756 | } |
| 1757 | break; |
| 1758 | default: |
| 1759 | /* |
| 1760 | * ARMv8 defines that only coprocessors 14 and 15 exist, |
| 1761 | * so this can only happen if this is an ARMv7 or earlier CPU, |
| 1762 | * in which case the syndrome information won't actually be |
| 1763 | * guest visible. |
| 1764 | */ |
| 1765 | assert(!arm_dc_feature(s, ARM_FEATURE_V8)); |
| 1766 | syndrome = syn_uncategorized(); |
| 1767 | break; |
| 1768 | } |
| 1769 | |
| 1770 | if (s->hstr_active && cpnum == 15 && s->current_el == 1) { |
| 1771 | /* |
| 1772 | * At EL1, check for a HSTR_EL2 trap, which must take precedence |
| 1773 | * over the UNDEF for "no such register" or the UNDEF for "access |
| 1774 | * permissions forbid this EL1 access". HSTR_EL2 traps from EL0 |
| 1775 | * only happen if the cpreg doesn't UNDEF at EL0, so we do those in |
| 1776 | * access_check_cp_reg(), after the checks for whether the access |
| 1777 | * configurably trapped to EL1. |
| 1778 | */ |
| 1779 | uint32_t maskbit = is64 ? crm : crn; |
| 1780 | |
| 1781 | if (maskbit != 4 && maskbit != 14) { |
| 1782 | /* T4 and T14 are RES0 so never cause traps */ |
| 1783 | TCGLabel *fail = delay_exception_el(s, EXCP_UDEF, syndrome, 2); |
| 1784 | TCGv_i32 t = |
| 1785 | load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2)); |
| 1786 | |
| 1787 | tcg_gen_brcondi_i32(TCG_COND_TSTNE, t, 1u << maskbit, fail); |
| 1788 | } |
| 1789 | } |
| 1790 | |
| 1791 | if (cpnum == 15 && aa32_cpreg_encoding_in_impdef_space(crn, crm)) { |
| 1792 | /* |
| 1793 | * Check for TIDCP trap, which must take precedence over the UNDEF |
| 1794 | * for "no such register" etc. It shares precedence with HSTR, |
| 1795 | * but raises the same exception, so order doesn't matter. |
| 1796 | */ |
| 1797 | switch (s->current_el) { |
| 1798 | case 0: |
| 1799 | if (arm_dc_feature(s, ARM_FEATURE_AARCH64) |
| 1800 | && dc_isar_feature(aa64_tidcp1, s)) { |
| 1801 | gen_helper_tidcp_el0(tcg_env, tcg_constant_i32(syndrome)); |
| 1802 | } |
| 1803 | break; |
| 1804 | case 1: |
| 1805 | gen_helper_tidcp_el1(tcg_env, tcg_constant_i32(syndrome)); |
| 1806 | break; |
| 1807 | } |
| 1808 | } |
| 1809 | |
| 1810 | if (!ri) { |
| 1811 | /* |
| 1812 | * Unknown register; this might be a guest error or a QEMU |
| 1813 | * unimplemented feature. |
| 1814 | */ |
| 1815 | if (is64) { |
| 1816 | qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 " |
| 1817 | "64 bit system register cp:%d opc1: %d crm:%d " |
| 1818 | "(%s)\n", |
| 1819 | isread ? "read" : "write", cpnum, opc1, crm, |
| 1820 | s->ns ? "non-secure" : "secure"); |
| 1821 | } else { |
| 1822 | qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 " |
| 1823 | "system register cp:%d opc1:%d crn:%d crm:%d " |
| 1824 | "opc2:%d (%s)\n", |
| 1825 | isread ? "read" : "write", cpnum, opc1, crn, |
| 1826 | crm, opc2, s->ns ? "non-secure" : "secure"); |
| 1827 | } |
| 1828 | unallocated_encoding(s); |
| 1829 | return; |
| 1830 | } |
| 1831 | |
| 1832 | /* Check access permissions */ |
| 1833 | if (!cp_access_ok(s->current_el, ri, isread)) { |
| 1834 | unallocated_encoding(s); |
| 1835 | return; |
| 1836 | } |
| 1837 | |
| 1838 | if ((s->hstr_active && s->current_el == 0) || ri->accessfn || |
| 1839 | (ri->fgt && s->fgt_active)) { |
| 1840 | /* |
| 1841 | * Emit code to perform further access permissions checks at |
| 1842 | * runtime; this may result in an exception. |
| 1843 | */ |
| 1844 | gen_set_condexec(s); |
| 1845 | gen_update_pc(s, 0); |
| 1846 | tcg_ri = tcg_temp_new_ptr(); |
| 1847 | gen_helper_access_check_cp_reg(tcg_ri, tcg_env, |
| 1848 | tcg_constant_i32(key), |
| 1849 | tcg_constant_i32(syndrome), |
| 1850 | tcg_constant_i32(isread)); |
| 1851 | } else if (ri->type & ARM_CP_RAISES_EXC) { |
| 1852 | /* |
| 1853 | * The readfn or writefn might raise an exception; |
| 1854 | * synchronize the CPU state in case it does. |
| 1855 | */ |
| 1856 | gen_set_condexec(s); |
| 1857 | gen_update_pc(s, 0); |
| 1858 | } |
| 1859 | |
| 1860 | /* Handle special cases first */ |
| 1861 | switch (ri->type & ARM_CP_SPECIAL_MASK) { |
| 1862 | case 0: |
| 1863 | break; |
| 1864 | case ARM_CP_NOP: |
| 1865 | return; |
| 1866 | case ARM_CP_WFI: |
| 1867 | if (isread) { |
| 1868 | unallocated_encoding(s); |
| 1869 | } else { |
| 1870 | gen_update_pc(s, curr_insn_len(s)); |
| 1871 | s->base.is_jmp = DISAS_WFI; |
| 1872 | } |
| 1873 | return; |
| 1874 | default: |
| 1875 | g_assert_not_reached(); |
| 1876 | } |
| 1877 | |
| 1878 | if (ri->type & ARM_CP_IO) { |
| 1879 | /* I/O operations must end the TB here (whether read or write) */ |
| 1880 | need_exit_tb = translator_io_start(&s->base); |
| 1881 | } |
| 1882 | |
| 1883 | if (isread) { |
| 1884 | /* Read */ |
| 1885 | if (is64) { |
| 1886 | TCGv_i64 tmp64; |
| 1887 | TCGv_i32 tmp; |
| 1888 | if (ri->type & ARM_CP_CONST) { |
| 1889 | tmp64 = tcg_constant_i64(ri->resetvalue); |
| 1890 | } else if (ri->readfn) { |
| 1891 | if (!tcg_ri) { |
| 1892 | tcg_ri = gen_lookup_cp_reg(key); |
| 1893 | } |
| 1894 | tmp64 = tcg_temp_new_i64(); |
| 1895 | gen_helper_get_cp_reg64(tmp64, tcg_env, tcg_ri); |
| 1896 | } else { |
| 1897 | tmp64 = tcg_temp_new_i64(); |
| 1898 | tcg_gen_ld_i64(tmp64, tcg_env, ri->fieldoffset); |
| 1899 | } |
| 1900 | tmp = tcg_temp_new_i32(); |
| 1901 | tcg_gen_extrl_i64_i32(tmp, tmp64); |
| 1902 | store_reg(s, rt, tmp); |
| 1903 | tmp = tcg_temp_new_i32(); |
| 1904 | tcg_gen_extrh_i64_i32(tmp, tmp64); |
| 1905 | store_reg(s, rt2, tmp); |
| 1906 | } else { |
| 1907 | TCGv_i32 tmp; |
| 1908 | if (ri->type & ARM_CP_CONST) { |
| 1909 | tmp = tcg_constant_i32(ri->resetvalue); |
| 1910 | } else if (ri->readfn) { |
| 1911 | if (!tcg_ri) { |
| 1912 | tcg_ri = gen_lookup_cp_reg(key); |
| 1913 | } |
| 1914 | tmp = tcg_temp_new_i32(); |
| 1915 | gen_helper_get_cp_reg(tmp, tcg_env, tcg_ri); |
| 1916 | } else { |
| 1917 | tmp = load_cpu_offset(ri->fieldoffset); |
| 1918 | } |
| 1919 | if (rt == 15) { |
| 1920 | /* Destination register of r15 for 32 bit loads sets |
| 1921 | * the condition codes from the high 4 bits of the value |
| 1922 | */ |
| 1923 | gen_set_nzcv(tmp); |
| 1924 | } else { |
| 1925 | store_reg(s, rt, tmp); |
| 1926 | } |
| 1927 | } |
| 1928 | } else { |
| 1929 | /* Write */ |
| 1930 | if (ri->type & ARM_CP_CONST) { |
| 1931 | /* If not forbidden by access permissions, treat as WI */ |
| 1932 | return; |
| 1933 | } |
| 1934 | |
| 1935 | if (is64) { |
| 1936 | TCGv_i32 tmplo, tmphi; |
| 1937 | TCGv_i64 tmp64 = tcg_temp_new_i64(); |
| 1938 | tmplo = load_reg(s, rt); |
| 1939 | tmphi = load_reg(s, rt2); |
| 1940 | tcg_gen_concat_i32_i64(tmp64, tmplo, tmphi); |
| 1941 | if (ri->writefn) { |
| 1942 | if (!tcg_ri) { |
| 1943 | tcg_ri = gen_lookup_cp_reg(key); |
| 1944 | } |
| 1945 | gen_helper_set_cp_reg64(tcg_env, tcg_ri, tmp64); |
| 1946 | } else { |
| 1947 | tcg_gen_st_i64(tmp64, tcg_env, ri->fieldoffset); |
| 1948 | } |
| 1949 | } else { |
| 1950 | TCGv_i32 tmp = load_reg(s, rt); |
| 1951 | if (ri->writefn) { |
| 1952 | if (!tcg_ri) { |
| 1953 | tcg_ri = gen_lookup_cp_reg(key); |
| 1954 | } |
| 1955 | gen_helper_set_cp_reg(tcg_env, tcg_ri, tmp); |
| 1956 | } else { |
| 1957 | store_cpu_offset(tmp, ri->fieldoffset, 4); |
| 1958 | } |
| 1959 | } |
| 1960 | } |
| 1961 | |
| 1962 | if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { |
| 1963 | /* |
| 1964 | * A write to any coprocessor register that ends a TB |
| 1965 | * must rebuild the hflags for the next TB. |
| 1966 | */ |
| 1967 | gen_rebuild_hflags(s, ri->type & ARM_CP_NEWEL); |
| 1968 | /* |
| 1969 | * We default to ending the TB on a coprocessor register write, |
| 1970 | * but allow this to be suppressed by the register definition |
| 1971 | * (usually only necessary to work around guest bugs). |
| 1972 | */ |
| 1973 | need_exit_tb = true; |
| 1974 | } |
| 1975 | if (need_exit_tb) { |
| 1976 | gen_lookup_tb(s); |
| 1977 | } |
| 1978 | } |
| 1979 | |
| 1980 | /* Store a 64-bit value to a register pair. Clobbers val. */ |
| 1981 | static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val) |
| 1982 | { |
| 1983 | TCGv_i32 tmp; |
| 1984 | tmp = tcg_temp_new_i32(); |
| 1985 | tcg_gen_extrl_i64_i32(tmp, val); |
| 1986 | store_reg(s, rlow, tmp); |
| 1987 | tmp = tcg_temp_new_i32(); |
| 1988 | tcg_gen_extrh_i64_i32(tmp, val); |
| 1989 | store_reg(s, rhigh, tmp); |
| 1990 | } |
| 1991 | |
| 1992 | /* load and add a 64-bit value from a register pair. */ |
| 1993 | static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) |
| 1994 | { |
| 1995 | TCGv_i64 tmp; |
| 1996 | TCGv_i32 tmpl; |
| 1997 | TCGv_i32 tmph; |
| 1998 | |
| 1999 | /* Load 64-bit value rd:rn. */ |
| 2000 | tmpl = load_reg(s, rlow); |
| 2001 | tmph = load_reg(s, rhigh); |
| 2002 | tmp = tcg_temp_new_i64(); |
| 2003 | tcg_gen_concat_i32_i64(tmp, tmpl, tmph); |
| 2004 | tcg_gen_add_i64(val, val, tmp); |
| 2005 | } |
| 2006 | |
| 2007 | /* Set N and Z flags from hi|lo. */ |
| 2008 | static void gen_logicq_cc(TCGv_i32 lo, TCGv_i32 hi) |
| 2009 | { |
| 2010 | tcg_gen_mov_i32(cpu_NF, hi); |
| 2011 | tcg_gen_or_i32(cpu_ZF, lo, hi); |
| 2012 | } |
| 2013 | |
| 2014 | /* Load/Store exclusive instructions are implemented by remembering |
| 2015 | the value/address loaded, and seeing if these are the same |
| 2016 | when the store is performed. This should be sufficient to implement |
| 2017 | the architecturally mandated semantics, and avoids having to monitor |
| 2018 | regular stores. The compare vs the remembered value is done during |
| 2019 | the cmpxchg operation, but we must compare the addresses manually. */ |
| 2020 | static void gen_load_exclusive(DisasContext *s, int rt, int rt2, |
| 2021 | TCGv_i32 addr, int size) |
| 2022 | { |
| 2023 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 2024 | MemOp opc = size | MO_ALIGN | s->be_data; |
| 2025 | |
| 2026 | s->is_ldex = true; |
| 2027 | |
| 2028 | if (size == 3) { |
| 2029 | TCGv_i32 tmp2 = tcg_temp_new_i32(); |
| 2030 | TCGv_i64 t64 = tcg_temp_new_i64(); |
| 2031 | |
| 2032 | /* |
| 2033 | * For AArch32, architecturally the 32-bit word at the lowest |
| 2034 | * address is always Rt and the one at addr+4 is Rt2, even if |
| 2035 | * the CPU is big-endian. That means we don't want to do a |
| 2036 | * gen_aa32_ld_i64(), which checks SCTLR_B as if for an |
| 2037 | * architecturally 64-bit access, but instead do a 64-bit access |
| 2038 | * using MO_BE if appropriate and then split the two halves. |
| 2039 | */ |
| 2040 | TCGv_va taddr = gen_aa32_addr(s, addr, opc); |
| 2041 | |
| 2042 | tcg_gen_qemu_ld_i64(t64, taddr, get_mem_index(s), opc); |
| 2043 | tcg_gen_mov_i64(cpu_exclusive_val, t64); |
| 2044 | if (s->be_data == MO_BE) { |
| 2045 | tcg_gen_extr_i64_i32(tmp2, tmp, t64); |
| 2046 | } else { |
| 2047 | tcg_gen_extr_i64_i32(tmp, tmp2, t64); |
| 2048 | } |
| 2049 | store_reg(s, rt2, tmp2); |
| 2050 | } else { |
| 2051 | gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), opc); |
| 2052 | tcg_gen_extu_i32_i64(cpu_exclusive_val, tmp); |
| 2053 | } |
| 2054 | |
| 2055 | store_reg(s, rt, tmp); |
| 2056 | tcg_gen_extu_i32_i64(cpu_exclusive_addr, addr); |
| 2057 | } |
| 2058 | |
| 2059 | static void gen_clrex(DisasContext *s) |
| 2060 | { |
| 2061 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); |
| 2062 | } |
| 2063 | |
| 2064 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, |
| 2065 | TCGv_i32 addr, int size) |
| 2066 | { |
| 2067 | TCGv_i32 t0, t1, t2; |
| 2068 | TCGv_i64 extaddr; |
| 2069 | TCGv_va taddr; |
| 2070 | TCGLabel *done_label; |
| 2071 | TCGLabel *fail_label; |
| 2072 | MemOp opc = size | MO_ALIGN | s->be_data; |
| 2073 | |
| 2074 | /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) { |
| 2075 | [addr] = {Rt}; |
| 2076 | {Rd} = 0; |
| 2077 | } else { |
| 2078 | {Rd} = 1; |
| 2079 | } */ |
| 2080 | fail_label = gen_new_label(); |
| 2081 | done_label = gen_new_label(); |
| 2082 | extaddr = tcg_temp_new_i64(); |
| 2083 | tcg_gen_extu_i32_i64(extaddr, addr); |
| 2084 | tcg_gen_brcond_i64(TCG_COND_NE, extaddr, cpu_exclusive_addr, fail_label); |
| 2085 | |
| 2086 | taddr = gen_aa32_addr(s, addr, opc); |
| 2087 | t0 = tcg_temp_new_i32(); |
| 2088 | t1 = load_reg(s, rt); |
| 2089 | if (size == 3) { |
| 2090 | TCGv_i64 o64 = tcg_temp_new_i64(); |
| 2091 | TCGv_i64 n64 = tcg_temp_new_i64(); |
| 2092 | |
| 2093 | t2 = load_reg(s, rt2); |
| 2094 | |
| 2095 | /* |
| 2096 | * For AArch32, architecturally the 32-bit word at the lowest |
| 2097 | * address is always Rt and the one at addr+4 is Rt2, even if |
| 2098 | * the CPU is big-endian. Since we're going to treat this as a |
| 2099 | * single 64-bit BE store, we need to put the two halves in the |
| 2100 | * opposite order for BE to LE, so that they end up in the right |
| 2101 | * places. We don't want gen_aa32_st_i64, because that checks |
| 2102 | * SCTLR_B as if for an architectural 64-bit access. |
| 2103 | */ |
| 2104 | if (s->be_data == MO_BE) { |
| 2105 | tcg_gen_concat_i32_i64(n64, t2, t1); |
| 2106 | } else { |
| 2107 | tcg_gen_concat_i32_i64(n64, t1, t2); |
| 2108 | } |
| 2109 | |
| 2110 | tcg_gen_atomic_cmpxchg_i64(o64, taddr, cpu_exclusive_val, n64, |
| 2111 | get_mem_index(s), opc); |
| 2112 | |
| 2113 | tcg_gen_setcond_i64(TCG_COND_NE, o64, o64, cpu_exclusive_val); |
| 2114 | tcg_gen_extrl_i64_i32(t0, o64); |
| 2115 | } else { |
| 2116 | t2 = tcg_temp_new_i32(); |
| 2117 | tcg_gen_extrl_i64_i32(t2, cpu_exclusive_val); |
| 2118 | tcg_gen_atomic_cmpxchg_i32(t0, taddr, t2, t1, get_mem_index(s), opc); |
| 2119 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t2); |
| 2120 | } |
| 2121 | tcg_gen_mov_i32(cpu_R[rd], t0); |
| 2122 | tcg_gen_br(done_label); |
| 2123 | |
| 2124 | gen_set_label(fail_label); |
| 2125 | tcg_gen_movi_i32(cpu_R[rd], 1); |
| 2126 | gen_set_label(done_label); |
| 2127 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); |
| 2128 | } |
| 2129 | |
| 2130 | /* gen_srs: |
| 2131 | * @env: CPUARMState |
| 2132 | * @s: DisasContext |
| 2133 | * @mode: mode field from insn (which stack to store to) |
| 2134 | * @amode: addressing mode (DA/IA/DB/IB), encoded as per P,U bits in ARM insn |
| 2135 | * @writeback: true if writeback bit set |
| 2136 | * |
| 2137 | * Generate code for the SRS (Store Return State) insn. |
| 2138 | */ |
| 2139 | static void gen_srs(DisasContext *s, |
| 2140 | uint32_t mode, uint32_t amode, bool writeback) |
| 2141 | { |
| 2142 | int32_t offset; |
| 2143 | TCGv_i32 addr, tmp; |
| 2144 | bool undef = false; |
| 2145 | |
| 2146 | /* SRS is: |
| 2147 | * - trapped to EL3 if EL3 is AArch64 and we are at Secure EL1 |
| 2148 | * and specified mode is monitor mode |
| 2149 | * - UNDEFINED in Hyp mode |
| 2150 | * - UNPREDICTABLE in User or System mode |
| 2151 | * - UNPREDICTABLE if the specified mode is: |
| 2152 | * -- not implemented |
| 2153 | * -- not a valid mode number |
| 2154 | * -- a mode that's at a higher exception level |
| 2155 | * -- Monitor, if we are Non-secure |
| 2156 | * For the UNPREDICTABLE cases we choose to UNDEF. |
| 2157 | */ |
| 2158 | if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) { |
| 2159 | gen_exception_insn_el(s, 0, EXCP_UDEF, syn_uncategorized(), 3); |
| 2160 | return; |
| 2161 | } |
| 2162 | |
| 2163 | if (s->current_el == 0 || s->current_el == 2) { |
| 2164 | undef = true; |
| 2165 | } |
| 2166 | |
| 2167 | switch (mode) { |
| 2168 | case ARM_CPU_MODE_USR: |
| 2169 | case ARM_CPU_MODE_FIQ: |
| 2170 | case ARM_CPU_MODE_IRQ: |
| 2171 | case ARM_CPU_MODE_SVC: |
| 2172 | case ARM_CPU_MODE_ABT: |
| 2173 | case ARM_CPU_MODE_UND: |
| 2174 | case ARM_CPU_MODE_SYS: |
| 2175 | break; |
| 2176 | case ARM_CPU_MODE_HYP: |
| 2177 | if (s->current_el == 1 || !arm_dc_feature(s, ARM_FEATURE_EL2)) { |
| 2178 | undef = true; |
| 2179 | } |
| 2180 | break; |
| 2181 | case ARM_CPU_MODE_MON: |
| 2182 | /* No need to check specifically for "are we non-secure" because |
| 2183 | * we've already made EL0 UNDEF and handled the trap for S-EL1; |
| 2184 | * so if this isn't EL3 then we must be non-secure. |
| 2185 | */ |
| 2186 | if (s->current_el != 3) { |
| 2187 | undef = true; |
| 2188 | } |
| 2189 | break; |
| 2190 | default: |
| 2191 | undef = true; |
| 2192 | } |
| 2193 | |
| 2194 | if (undef) { |
| 2195 | unallocated_encoding(s); |
| 2196 | return; |
| 2197 | } |
| 2198 | |
| 2199 | addr = tcg_temp_new_i32(); |
| 2200 | /* get_r13_banked() will raise an exception if called from System mode */ |
| 2201 | gen_set_condexec(s); |
| 2202 | gen_update_pc(s, 0); |
| 2203 | gen_helper_get_r13_banked(addr, tcg_env, tcg_constant_i32(mode)); |
| 2204 | switch (amode) { |
| 2205 | case 0: /* DA */ |
| 2206 | offset = -4; |
| 2207 | break; |
| 2208 | case 1: /* IA */ |
| 2209 | offset = 0; |
| 2210 | break; |
| 2211 | case 2: /* DB */ |
| 2212 | offset = -8; |
| 2213 | break; |
| 2214 | case 3: /* IB */ |
| 2215 | offset = 4; |
| 2216 | break; |
| 2217 | default: |
| 2218 | g_assert_not_reached(); |
| 2219 | } |
| 2220 | tcg_gen_addi_i32(addr, addr, offset); |
| 2221 | tmp = load_reg(s, 14); |
| 2222 | gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); |
| 2223 | tmp = load_cpu_field(spsr); |
| 2224 | tcg_gen_addi_i32(addr, addr, 4); |
| 2225 | gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); |
| 2226 | if (writeback) { |
| 2227 | switch (amode) { |
| 2228 | case 0: |
| 2229 | offset = -8; |
| 2230 | break; |
| 2231 | case 1: |
| 2232 | offset = 4; |
| 2233 | break; |
| 2234 | case 2: |
| 2235 | offset = -4; |
| 2236 | break; |
| 2237 | case 3: |
| 2238 | offset = 0; |
| 2239 | break; |
| 2240 | default: |
| 2241 | g_assert_not_reached(); |
| 2242 | } |
| 2243 | tcg_gen_addi_i32(addr, addr, offset); |
| 2244 | gen_helper_set_r13_banked(tcg_env, tcg_constant_i32(mode), addr); |
| 2245 | } |
| 2246 | s->base.is_jmp = DISAS_UPDATE_EXIT; |
| 2247 | } |
| 2248 | |
| 2249 | /* Skip this instruction if the ARM condition is false */ |
| 2250 | static void arm_skip_unless(DisasContext *s, uint32_t cond) |
| 2251 | { |
| 2252 | arm_gen_condlabel(s); |
| 2253 | arm_gen_test_cc(cond ^ 1, s->condlabel.label); |
| 2254 | } |
| 2255 | |
| 2256 | |
| 2257 | /* |
| 2258 | * Constant expanders used by T16/T32 decode |
| 2259 | */ |
| 2260 | |
| 2261 | /* Return only the rotation part of T32ExpandImm. */ |
| 2262 | static int t32_expandimm_rot(DisasContext *s, int x) |
| 2263 | { |
| 2264 | return x & 0xc00 ? extract32(x, 7, 5) : 0; |
| 2265 | } |
| 2266 | |
| 2267 | /* Return the unrotated immediate from T32ExpandImm. */ |
| 2268 | static int t32_expandimm_imm(DisasContext *s, int x) |
| 2269 | { |
| 2270 | uint32_t imm = extract32(x, 0, 8); |
| 2271 | |
| 2272 | switch (extract32(x, 8, 4)) { |
| 2273 | case 0: /* XY */ |
| 2274 | /* Nothing to do. */ |
| 2275 | break; |
| 2276 | case 1: /* 00XY00XY */ |
| 2277 | imm *= 0x00010001; |
| 2278 | break; |
| 2279 | case 2: /* XY00XY00 */ |
| 2280 | imm *= 0x01000100; |
| 2281 | break; |
| 2282 | case 3: /* XYXYXYXY */ |
| 2283 | imm *= 0x01010101; |
| 2284 | break; |
| 2285 | default: |
| 2286 | /* Rotated constant. */ |
| 2287 | imm |= 0x80; |
| 2288 | break; |
| 2289 | } |
| 2290 | return imm; |
| 2291 | } |
| 2292 | |
| 2293 | static int t32_branch24(DisasContext *s, int x) |
| 2294 | { |
| 2295 | /* Convert J1:J2 at x[22:21] to I2:I1, which involves I=J^~S. */ |
| 2296 | x ^= !(x < 0) * (3 << 21); |
| 2297 | /* Append the final zero. */ |
| 2298 | return x << 1; |
| 2299 | } |
| 2300 | |
| 2301 | static int t16_setflags(DisasContext *s) |
| 2302 | { |
| 2303 | return s->condexec_mask == 0; |
| 2304 | } |
| 2305 | |
| 2306 | static int t16_push_list(DisasContext *s, int x) |
| 2307 | { |
| 2308 | return (x & 0xff) | (x & 0x100) << (14 - 8); |
| 2309 | } |
| 2310 | |
| 2311 | static int t16_pop_list(DisasContext *s, int x) |
| 2312 | { |
| 2313 | return (x & 0xff) | (x & 0x100) << (15 - 8); |
| 2314 | } |
| 2315 | |
| 2316 | /* |
| 2317 | * Include the generated decoders. |
| 2318 | */ |
| 2319 | |
| 2320 | #include "decode-a32.c.inc" |
| 2321 | #include "decode-a32-uncond.c.inc" |
| 2322 | #include "decode-t32.c.inc" |
| 2323 | #include "decode-t16.c.inc" |
| 2324 | |
| 2325 | static bool valid_cp(DisasContext *s, int cp) |
| 2326 | { |
| 2327 | /* |
| 2328 | * Return true if this coprocessor field indicates something |
| 2329 | * that's really a possible coprocessor. |
| 2330 | * For v7 and earlier, coprocessors 8..15 were reserved for Arm use, |
| 2331 | * and of those only cp14 and cp15 were used for registers. |
| 2332 | * cp10 and cp11 were used for VFP and Neon, whose decode is |
| 2333 | * dealt with elsewhere. With the advent of fp16, cp9 is also |
| 2334 | * now part of VFP. |
| 2335 | * For v8A and later, the encoding has been tightened so that |
| 2336 | * only cp14 and cp15 are valid, and other values aren't considered |
| 2337 | * to be in the coprocessor-instruction space at all. v8M still |
| 2338 | * permits coprocessors 0..7. |
| 2339 | */ |
| 2340 | if (arm_dc_feature(s, ARM_FEATURE_V8) && |
| 2341 | !arm_dc_feature(s, ARM_FEATURE_M)) { |
| 2342 | return cp >= 14; |
| 2343 | } |
| 2344 | return cp < 8 || cp >= 14; |
| 2345 | } |
| 2346 | |
| 2347 | static bool trans_MCR(DisasContext *s, arg_MCR *a) |
| 2348 | { |
| 2349 | if (!valid_cp(s, a->cp)) { |
| 2350 | return false; |
| 2351 | } |
| 2352 | do_coproc_insn(s, a->cp, false, a->opc1, a->crn, a->crm, a->opc2, |
| 2353 | false, a->rt, 0); |
| 2354 | return true; |
| 2355 | } |
| 2356 | |
| 2357 | static bool trans_MRC(DisasContext *s, arg_MRC *a) |
| 2358 | { |
| 2359 | if (!valid_cp(s, a->cp)) { |
| 2360 | return false; |
| 2361 | } |
| 2362 | do_coproc_insn(s, a->cp, false, a->opc1, a->crn, a->crm, a->opc2, |
| 2363 | true, a->rt, 0); |
| 2364 | return true; |
| 2365 | } |
| 2366 | |
| 2367 | static bool trans_MCRR(DisasContext *s, arg_MCRR *a) |
| 2368 | { |
| 2369 | if (!valid_cp(s, a->cp)) { |
| 2370 | return false; |
| 2371 | } |
| 2372 | do_coproc_insn(s, a->cp, true, a->opc1, 0, a->crm, 0, |
| 2373 | false, a->rt, a->rt2); |
| 2374 | return true; |
| 2375 | } |
| 2376 | |
| 2377 | static bool trans_MRRC(DisasContext *s, arg_MRRC *a) |
| 2378 | { |
| 2379 | if (!valid_cp(s, a->cp)) { |
| 2380 | return false; |
| 2381 | } |
| 2382 | do_coproc_insn(s, a->cp, true, a->opc1, 0, a->crm, 0, |
| 2383 | true, a->rt, a->rt2); |
| 2384 | return true; |
| 2385 | } |
| 2386 | |
| 2387 | /* Helpers to swap operands for reverse-subtract. */ |
| 2388 | static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) |
| 2389 | { |
| 2390 | tcg_gen_sub_i32(dst, b, a); |
| 2391 | } |
| 2392 | |
| 2393 | static void gen_rsb_CC(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) |
| 2394 | { |
| 2395 | gen_sub_CC(dst, b, a); |
| 2396 | } |
| 2397 | |
| 2398 | static void gen_rsc(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) |
| 2399 | { |
| 2400 | gen_sub_carry(dest, b, a); |
| 2401 | } |
| 2402 | |
| 2403 | static void gen_rsc_CC(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) |
| 2404 | { |
| 2405 | gen_sbc_CC(dest, b, a); |
| 2406 | } |
| 2407 | |
| 2408 | /* |
| 2409 | * Helpers for the data processing routines. |
| 2410 | * |
| 2411 | * After the computation store the results back. |
| 2412 | * This may be suppressed altogether (STREG_NONE), require a runtime |
| 2413 | * check against the stack limits (STREG_SP_CHECK), or generate an |
| 2414 | * exception return. Oh, or store into a register. |
| 2415 | * |
| 2416 | * Always return true, indicating success for a trans_* function. |
| 2417 | */ |
| 2418 | typedef enum { |
| 2419 | STREG_NONE, |
| 2420 | STREG_NORMAL, |
| 2421 | STREG_SP_CHECK, |
| 2422 | STREG_EXC_RET, |
| 2423 | } StoreRegKind; |
| 2424 | |
| 2425 | static bool store_reg_kind(DisasContext *s, int rd, |
| 2426 | TCGv_i32 val, StoreRegKind kind) |
| 2427 | { |
| 2428 | switch (kind) { |
| 2429 | case STREG_NONE: |
| 2430 | return true; |
| 2431 | case STREG_NORMAL: |
| 2432 | /* See ALUWritePC: Interworking only from a32 mode. */ |
| 2433 | if (s->thumb) { |
| 2434 | store_reg(s, rd, val); |
| 2435 | } else { |
| 2436 | store_reg_bx(s, rd, val); |
| 2437 | } |
| 2438 | return true; |
| 2439 | case STREG_SP_CHECK: |
| 2440 | store_sp_checked(s, val); |
| 2441 | return true; |
| 2442 | case STREG_EXC_RET: |
| 2443 | gen_exception_return(s, val); |
| 2444 | return true; |
| 2445 | } |
| 2446 | g_assert_not_reached(); |
| 2447 | } |
| 2448 | |
| 2449 | /* |
| 2450 | * Data Processing (register) |
| 2451 | * |
| 2452 | * Operate, with set flags, one register source, |
| 2453 | * one immediate shifted register source, and a destination. |
| 2454 | */ |
| 2455 | static bool op_s_rrr_shi(DisasContext *s, arg_s_rrr_shi *a, |
| 2456 | void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), |
| 2457 | int logic_cc, StoreRegKind kind) |
| 2458 | { |
| 2459 | TCGv_i32 tmp1, tmp2; |
| 2460 | |
| 2461 | tmp2 = load_reg(s, a->rm); |
| 2462 | gen_arm_shift_im(tmp2, a->shty, a->shim, logic_cc); |
| 2463 | tmp1 = load_reg(s, a->rn); |
| 2464 | |
| 2465 | gen(tmp1, tmp1, tmp2); |
| 2466 | |
| 2467 | if (logic_cc) { |
| 2468 | gen_logic_CC(tmp1); |
| 2469 | } |
| 2470 | return store_reg_kind(s, a->rd, tmp1, kind); |
| 2471 | } |
| 2472 | |
| 2473 | static bool op_s_rxr_shi(DisasContext *s, arg_s_rrr_shi *a, |
| 2474 | void (*gen)(TCGv_i32, TCGv_i32), |
| 2475 | int logic_cc, StoreRegKind kind) |
| 2476 | { |
| 2477 | TCGv_i32 tmp; |
| 2478 | |
| 2479 | tmp = load_reg(s, a->rm); |
| 2480 | gen_arm_shift_im(tmp, a->shty, a->shim, logic_cc); |
| 2481 | |
| 2482 | gen(tmp, tmp); |
| 2483 | if (logic_cc) { |
| 2484 | gen_logic_CC(tmp); |
| 2485 | } |
| 2486 | return store_reg_kind(s, a->rd, tmp, kind); |
| 2487 | } |
| 2488 | |
| 2489 | /* |
| 2490 | * Data-processing (register-shifted register) |
| 2491 | * |
| 2492 | * Operate, with set flags, one register source, |
| 2493 | * one register shifted register source, and a destination. |
| 2494 | */ |
| 2495 | static bool op_s_rrr_shr(DisasContext *s, arg_s_rrr_shr *a, |
| 2496 | void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), |
| 2497 | int logic_cc, StoreRegKind kind) |
| 2498 | { |
| 2499 | TCGv_i32 tmp1, tmp2; |
| 2500 | |
| 2501 | tmp1 = load_reg(s, a->rs); |
| 2502 | tmp2 = load_reg(s, a->rm); |
| 2503 | gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); |
| 2504 | tmp1 = load_reg(s, a->rn); |
| 2505 | |
| 2506 | gen(tmp1, tmp1, tmp2); |
| 2507 | |
| 2508 | if (logic_cc) { |
| 2509 | gen_logic_CC(tmp1); |
| 2510 | } |
| 2511 | return store_reg_kind(s, a->rd, tmp1, kind); |
| 2512 | } |
| 2513 | |
| 2514 | static bool op_s_rxr_shr(DisasContext *s, arg_s_rrr_shr *a, |
| 2515 | void (*gen)(TCGv_i32, TCGv_i32), |
| 2516 | int logic_cc, StoreRegKind kind) |
| 2517 | { |
| 2518 | TCGv_i32 tmp1, tmp2; |
| 2519 | |
| 2520 | tmp1 = load_reg(s, a->rs); |
| 2521 | tmp2 = load_reg(s, a->rm); |
| 2522 | gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); |
| 2523 | |
| 2524 | gen(tmp2, tmp2); |
| 2525 | if (logic_cc) { |
| 2526 | gen_logic_CC(tmp2); |
| 2527 | } |
| 2528 | return store_reg_kind(s, a->rd, tmp2, kind); |
| 2529 | } |
| 2530 | |
| 2531 | /* |
| 2532 | * Data-processing (immediate) |
| 2533 | * |
| 2534 | * Operate, with set flags, one register source, |
| 2535 | * one rotated immediate, and a destination. |
| 2536 | * |
| 2537 | * Note that logic_cc && a->rot setting CF based on the msb of the |
| 2538 | * immediate is the reason why we must pass in the unrotated form |
| 2539 | * of the immediate. |
| 2540 | */ |
| 2541 | static bool op_s_rri_rot(DisasContext *s, arg_s_rri_rot *a, |
| 2542 | void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), |
| 2543 | int logic_cc, StoreRegKind kind) |
| 2544 | { |
| 2545 | TCGv_i32 tmp1; |
| 2546 | uint32_t imm; |
| 2547 | |
| 2548 | imm = ror32(a->imm, a->rot); |
| 2549 | if (logic_cc && a->rot) { |
| 2550 | tcg_gen_movi_i32(cpu_CF, imm >> 31); |
| 2551 | } |
| 2552 | tmp1 = load_reg(s, a->rn); |
| 2553 | |
| 2554 | gen(tmp1, tmp1, tcg_constant_i32(imm)); |
| 2555 | |
| 2556 | if (logic_cc) { |
| 2557 | gen_logic_CC(tmp1); |
| 2558 | } |
| 2559 | return store_reg_kind(s, a->rd, tmp1, kind); |
| 2560 | } |
| 2561 | |
| 2562 | static bool op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a, |
| 2563 | void (*gen)(TCGv_i32, TCGv_i32), |
| 2564 | int logic_cc, StoreRegKind kind) |
| 2565 | { |
| 2566 | TCGv_i32 tmp; |
| 2567 | uint32_t imm; |
| 2568 | |
| 2569 | imm = ror32(a->imm, a->rot); |
| 2570 | if (logic_cc && a->rot) { |
| 2571 | tcg_gen_movi_i32(cpu_CF, imm >> 31); |
| 2572 | } |
| 2573 | |
| 2574 | tmp = tcg_temp_new_i32(); |
| 2575 | gen(tmp, tcg_constant_i32(imm)); |
| 2576 | |
| 2577 | if (logic_cc) { |
| 2578 | gen_logic_CC(tmp); |
| 2579 | } |
| 2580 | return store_reg_kind(s, a->rd, tmp, kind); |
| 2581 | } |
| 2582 | |
| 2583 | #define DO_ANY3(NAME, OP, L, K) \ |
| 2584 | static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ |
| 2585 | { StoreRegKind k = (K); return op_s_rrr_shi(s, a, OP, L, k); } \ |
| 2586 | static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \ |
| 2587 | { StoreRegKind k = (K); return op_s_rrr_shr(s, a, OP, L, k); } \ |
| 2588 | static bool trans_##NAME##_rri(DisasContext *s, arg_s_rri_rot *a) \ |
| 2589 | { StoreRegKind k = (K); return op_s_rri_rot(s, a, OP, L, k); } |
| 2590 | |
| 2591 | #define DO_ANY2(NAME, OP, L, K) \ |
| 2592 | static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ |
| 2593 | { StoreRegKind k = (K); return op_s_rxr_shi(s, a, OP, L, k); } \ |
| 2594 | static bool trans_##NAME##_rxrr(DisasContext *s, arg_s_rrr_shr *a) \ |
| 2595 | { StoreRegKind k = (K); return op_s_rxr_shr(s, a, OP, L, k); } \ |
| 2596 | static bool trans_##NAME##_rxi(DisasContext *s, arg_s_rri_rot *a) \ |
| 2597 | { StoreRegKind k = (K); return op_s_rxi_rot(s, a, OP, L, k); } |
| 2598 | |
| 2599 | #define DO_CMP2(NAME, OP, L) \ |
| 2600 | static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ |
| 2601 | { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } \ |
| 2602 | static bool trans_##NAME##_xrrr(DisasContext *s, arg_s_rrr_shr *a) \ |
| 2603 | { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } \ |
| 2604 | static bool trans_##NAME##_xri(DisasContext *s, arg_s_rri_rot *a) \ |
| 2605 | { return op_s_rri_rot(s, a, OP, L, STREG_NONE); } |
| 2606 | |
| 2607 | DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) |
| 2608 | DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) |
| 2609 | DO_ANY3(ORR, tcg_gen_or_i32, a->s, STREG_NORMAL) |
| 2610 | DO_ANY3(BIC, tcg_gen_andc_i32, a->s, STREG_NORMAL) |
| 2611 | |
| 2612 | DO_ANY3(RSB, a->s ? gen_rsb_CC : gen_rsb, false, STREG_NORMAL) |
| 2613 | DO_ANY3(ADC, a->s ? gen_adc_CC : gen_add_carry, false, STREG_NORMAL) |
| 2614 | DO_ANY3(SBC, a->s ? gen_sbc_CC : gen_sub_carry, false, STREG_NORMAL) |
| 2615 | DO_ANY3(RSC, a->s ? gen_rsc_CC : gen_rsc, false, STREG_NORMAL) |
| 2616 | |
| 2617 | DO_CMP2(TST, tcg_gen_and_i32, true) |
| 2618 | DO_CMP2(TEQ, tcg_gen_xor_i32, true) |
| 2619 | DO_CMP2(CMN, gen_add_CC, false) |
| 2620 | DO_CMP2(CMP, gen_sub_CC, false) |
| 2621 | |
| 2622 | DO_ANY3(ADD, a->s ? gen_add_CC : tcg_gen_add_i32, false, |
| 2623 | a->rd == 13 && a->rn == 13 ? STREG_SP_CHECK : STREG_NORMAL) |
| 2624 | |
| 2625 | /* |
| 2626 | * Note for the computation of StoreRegKind we return out of the |
| 2627 | * middle of the functions that are expanded by DO_ANY3, and that |
| 2628 | * we modify a->s via that parameter before it is used by OP. |
| 2629 | */ |
| 2630 | DO_ANY3(SUB, a->s ? gen_sub_CC : tcg_gen_sub_i32, false, |
| 2631 | ({ |
| 2632 | StoreRegKind ret = STREG_NORMAL; |
| 2633 | if (a->rd == 15 && a->s) { |
| 2634 | /* |
| 2635 | * See ALUExceptionReturn: |
| 2636 | * In User mode, UNPREDICTABLE; we choose UNDEF. |
| 2637 | * In Hyp mode, UNDEFINED. |
| 2638 | */ |
| 2639 | if (IS_USER(s) || s->current_el == 2) { |
| 2640 | unallocated_encoding(s); |
| 2641 | return true; |
| 2642 | } |
| 2643 | /* There is no writeback of nzcv to PSTATE. */ |
| 2644 | a->s = 0; |
| 2645 | ret = STREG_EXC_RET; |
| 2646 | } else if (a->rd == 13 && a->rn == 13) { |
| 2647 | ret = STREG_SP_CHECK; |
| 2648 | } |
| 2649 | ret; |
| 2650 | })) |
| 2651 | |
| 2652 | DO_ANY2(MOV, tcg_gen_mov_i32, a->s, |
| 2653 | ({ |
| 2654 | StoreRegKind ret = STREG_NORMAL; |
| 2655 | if (a->rd == 15 && a->s) { |
| 2656 | /* |
| 2657 | * See ALUExceptionReturn: |
| 2658 | * In User mode, UNPREDICTABLE; we choose UNDEF. |
| 2659 | * In Hyp mode, UNDEFINED. |
| 2660 | */ |
| 2661 | if (IS_USER(s) || s->current_el == 2) { |
| 2662 | unallocated_encoding(s); |
| 2663 | return true; |
| 2664 | } |
| 2665 | /* There is no writeback of nzcv to PSTATE. */ |
| 2666 | a->s = 0; |
| 2667 | ret = STREG_EXC_RET; |
| 2668 | } else if (a->rd == 13) { |
| 2669 | ret = STREG_SP_CHECK; |
| 2670 | } |
| 2671 | ret; |
| 2672 | })) |
| 2673 | |
| 2674 | DO_ANY2(MVN, tcg_gen_not_i32, a->s, STREG_NORMAL) |
| 2675 | |
| 2676 | /* |
| 2677 | * ORN is only available with T32, so there is no register-shifted-register |
| 2678 | * form of the insn. Using the DO_ANY3 macro would create an unused function. |
| 2679 | */ |
| 2680 | static bool trans_ORN_rrri(DisasContext *s, arg_s_rrr_shi *a) |
| 2681 | { |
| 2682 | return op_s_rrr_shi(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); |
| 2683 | } |
| 2684 | |
| 2685 | static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a) |
| 2686 | { |
| 2687 | return op_s_rri_rot(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); |
| 2688 | } |
| 2689 | |
| 2690 | #undef DO_ANY3 |
| 2691 | #undef DO_ANY2 |
| 2692 | #undef DO_CMP2 |
| 2693 | |
| 2694 | static bool trans_ADR(DisasContext *s, arg_ri *a) |
| 2695 | { |
| 2696 | store_reg_bx(s, a->rd, add_reg_for_lit(s, 15, a->imm)); |
| 2697 | return true; |
| 2698 | } |
| 2699 | |
| 2700 | static bool trans_MOVW(DisasContext *s, arg_MOVW *a) |
| 2701 | { |
| 2702 | if (!ENABLE_ARCH_6T2) { |
| 2703 | return false; |
| 2704 | } |
| 2705 | |
| 2706 | store_reg(s, a->rd, tcg_constant_i32(a->imm)); |
| 2707 | return true; |
| 2708 | } |
| 2709 | |
| 2710 | static bool trans_MOVT(DisasContext *s, arg_MOVW *a) |
| 2711 | { |
| 2712 | TCGv_i32 tmp; |
| 2713 | |
| 2714 | if (!ENABLE_ARCH_6T2) { |
| 2715 | return false; |
| 2716 | } |
| 2717 | |
| 2718 | tmp = load_reg(s, a->rd); |
| 2719 | tcg_gen_ext16u_i32(tmp, tmp); |
| 2720 | tcg_gen_ori_i32(tmp, tmp, a->imm << 16); |
| 2721 | store_reg(s, a->rd, tmp); |
| 2722 | return true; |
| 2723 | } |
| 2724 | |
| 2725 | /* |
| 2726 | * v8.1M MVE wide-shifts |
| 2727 | */ |
| 2728 | static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a, |
| 2729 | WideShiftImmFn *fn) |
| 2730 | { |
| 2731 | TCGv_i64 rda; |
| 2732 | TCGv_i32 rdalo, rdahi; |
| 2733 | |
| 2734 | if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { |
| 2735 | /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ |
| 2736 | return false; |
| 2737 | } |
| 2738 | if (a->rdahi == 15) { |
| 2739 | /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */ |
| 2740 | return false; |
| 2741 | } |
| 2742 | if (!dc_isar_feature(aa32_mve, s) || |
| 2743 | !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || |
| 2744 | a->rdahi == 13) { |
| 2745 | /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */ |
| 2746 | unallocated_encoding(s); |
| 2747 | return true; |
| 2748 | } |
| 2749 | |
| 2750 | if (a->shim == 0) { |
| 2751 | a->shim = 32; |
| 2752 | } |
| 2753 | |
| 2754 | rda = tcg_temp_new_i64(); |
| 2755 | rdalo = load_reg(s, a->rdalo); |
| 2756 | rdahi = load_reg(s, a->rdahi); |
| 2757 | tcg_gen_concat_i32_i64(rda, rdalo, rdahi); |
| 2758 | |
| 2759 | fn(rda, rda, a->shim); |
| 2760 | |
| 2761 | tcg_gen_extrl_i64_i32(rdalo, rda); |
| 2762 | tcg_gen_extrh_i64_i32(rdahi, rda); |
| 2763 | store_reg(s, a->rdalo, rdalo); |
| 2764 | store_reg(s, a->rdahi, rdahi); |
| 2765 | |
| 2766 | return true; |
| 2767 | } |
| 2768 | |
| 2769 | static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a) |
| 2770 | { |
| 2771 | return do_mve_shl_ri(s, a, tcg_gen_sari_i64); |
| 2772 | } |
| 2773 | |
| 2774 | static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a) |
| 2775 | { |
| 2776 | return do_mve_shl_ri(s, a, tcg_gen_shli_i64); |
| 2777 | } |
| 2778 | |
| 2779 | static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a) |
| 2780 | { |
| 2781 | return do_mve_shl_ri(s, a, tcg_gen_shri_i64); |
| 2782 | } |
| 2783 | |
| 2784 | static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) |
| 2785 | { |
| 2786 | gen_helper_mve_sqshll(r, tcg_env, n, tcg_constant_i32(shift)); |
| 2787 | } |
| 2788 | |
| 2789 | static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) |
| 2790 | { |
| 2791 | return do_mve_shl_ri(s, a, gen_mve_sqshll); |
| 2792 | } |
| 2793 | |
| 2794 | static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) |
| 2795 | { |
| 2796 | gen_helper_mve_uqshll(r, tcg_env, n, tcg_constant_i32(shift)); |
| 2797 | } |
| 2798 | |
| 2799 | static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) |
| 2800 | { |
| 2801 | return do_mve_shl_ri(s, a, gen_mve_uqshll); |
| 2802 | } |
| 2803 | |
| 2804 | static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) |
| 2805 | { |
| 2806 | return do_mve_shl_ri(s, a, gen_srshr64_i64); |
| 2807 | } |
| 2808 | |
| 2809 | static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) |
| 2810 | { |
| 2811 | return do_mve_shl_ri(s, a, gen_urshr64_i64); |
| 2812 | } |
| 2813 | |
| 2814 | static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn) |
| 2815 | { |
| 2816 | TCGv_i64 rda; |
| 2817 | TCGv_i32 rdalo, rdahi; |
| 2818 | |
| 2819 | if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { |
| 2820 | /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ |
| 2821 | return false; |
| 2822 | } |
| 2823 | if (a->rdahi == 15) { |
| 2824 | /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */ |
| 2825 | return false; |
| 2826 | } |
| 2827 | if (!dc_isar_feature(aa32_mve, s) || |
| 2828 | !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || |
| 2829 | a->rdahi == 13 || a->rm == 13 || a->rm == 15 || |
| 2830 | a->rm == a->rdahi || a->rm == a->rdalo) { |
| 2831 | /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */ |
| 2832 | unallocated_encoding(s); |
| 2833 | return true; |
| 2834 | } |
| 2835 | |
| 2836 | rda = tcg_temp_new_i64(); |
| 2837 | rdalo = load_reg(s, a->rdalo); |
| 2838 | rdahi = load_reg(s, a->rdahi); |
| 2839 | tcg_gen_concat_i32_i64(rda, rdalo, rdahi); |
| 2840 | |
| 2841 | /* The helper takes care of the sign-extension of the low 8 bits of Rm */ |
| 2842 | fn(rda, tcg_env, rda, cpu_R[a->rm]); |
| 2843 | |
| 2844 | tcg_gen_extrl_i64_i32(rdalo, rda); |
| 2845 | tcg_gen_extrh_i64_i32(rdahi, rda); |
| 2846 | store_reg(s, a->rdalo, rdalo); |
| 2847 | store_reg(s, a->rdahi, rdahi); |
| 2848 | |
| 2849 | return true; |
| 2850 | } |
| 2851 | |
| 2852 | static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a) |
| 2853 | { |
| 2854 | return do_mve_shl_rr(s, a, gen_helper_mve_ushll); |
| 2855 | } |
| 2856 | |
| 2857 | static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a) |
| 2858 | { |
| 2859 | return do_mve_shl_rr(s, a, gen_helper_mve_sshrl); |
| 2860 | } |
| 2861 | |
| 2862 | static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a) |
| 2863 | { |
| 2864 | return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll); |
| 2865 | } |
| 2866 | |
| 2867 | static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a) |
| 2868 | { |
| 2869 | return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl); |
| 2870 | } |
| 2871 | |
| 2872 | static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a) |
| 2873 | { |
| 2874 | return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48); |
| 2875 | } |
| 2876 | |
| 2877 | static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a) |
| 2878 | { |
| 2879 | return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48); |
| 2880 | } |
| 2881 | |
| 2882 | static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn) |
| 2883 | { |
| 2884 | if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { |
| 2885 | /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ |
| 2886 | return false; |
| 2887 | } |
| 2888 | if (!dc_isar_feature(aa32_mve, s) || |
| 2889 | !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || |
| 2890 | a->rda == 13 || a->rda == 15) { |
| 2891 | /* These rda cases are UNPREDICTABLE; we choose to UNDEF */ |
| 2892 | unallocated_encoding(s); |
| 2893 | return true; |
| 2894 | } |
| 2895 | |
| 2896 | if (a->shim == 0) { |
| 2897 | a->shim = 32; |
| 2898 | } |
| 2899 | fn(cpu_R[a->rda], cpu_R[a->rda], a->shim); |
| 2900 | |
| 2901 | return true; |
| 2902 | } |
| 2903 | |
| 2904 | static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a) |
| 2905 | { |
| 2906 | return do_mve_sh_ri(s, a, gen_urshr32_i32); |
| 2907 | } |
| 2908 | |
| 2909 | static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a) |
| 2910 | { |
| 2911 | return do_mve_sh_ri(s, a, gen_srshr32_i32); |
| 2912 | } |
| 2913 | |
| 2914 | static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) |
| 2915 | { |
| 2916 | gen_helper_mve_sqshl(r, tcg_env, n, tcg_constant_i32(shift)); |
| 2917 | } |
| 2918 | |
| 2919 | static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) |
| 2920 | { |
| 2921 | return do_mve_sh_ri(s, a, gen_mve_sqshl); |
| 2922 | } |
| 2923 | |
| 2924 | static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) |
| 2925 | { |
| 2926 | gen_helper_mve_uqshl(r, tcg_env, n, tcg_constant_i32(shift)); |
| 2927 | } |
| 2928 | |
| 2929 | static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) |
| 2930 | { |
| 2931 | return do_mve_sh_ri(s, a, gen_mve_uqshl); |
| 2932 | } |
| 2933 | |
| 2934 | static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn) |
| 2935 | { |
| 2936 | if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { |
| 2937 | /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ |
| 2938 | return false; |
| 2939 | } |
| 2940 | if (!dc_isar_feature(aa32_mve, s) || |
| 2941 | !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || |
| 2942 | a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 || |
| 2943 | a->rm == a->rda) { |
| 2944 | /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */ |
| 2945 | unallocated_encoding(s); |
| 2946 | return true; |
| 2947 | } |
| 2948 | |
| 2949 | /* The helper takes care of the sign-extension of the low 8 bits of Rm */ |
| 2950 | fn(cpu_R[a->rda], tcg_env, cpu_R[a->rda], cpu_R[a->rm]); |
| 2951 | return true; |
| 2952 | } |
| 2953 | |
| 2954 | static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a) |
| 2955 | { |
| 2956 | return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr); |
| 2957 | } |
| 2958 | |
| 2959 | static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a) |
| 2960 | { |
| 2961 | return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl); |
| 2962 | } |
| 2963 | |
| 2964 | /* |
| 2965 | * Multiply and multiply accumulate |
| 2966 | */ |
| 2967 | |
| 2968 | static bool op_mla(DisasContext *s, arg_s_rrrr *a, bool add) |
| 2969 | { |
| 2970 | TCGv_i32 t1, t2; |
| 2971 | |
| 2972 | t1 = load_reg(s, a->rn); |
| 2973 | t2 = load_reg(s, a->rm); |
| 2974 | tcg_gen_mul_i32(t1, t1, t2); |
| 2975 | if (add) { |
| 2976 | t2 = load_reg(s, a->ra); |
| 2977 | tcg_gen_add_i32(t1, t1, t2); |
| 2978 | } |
| 2979 | if (a->s) { |
| 2980 | gen_logic_CC(t1); |
| 2981 | } |
| 2982 | store_reg(s, a->rd, t1); |
| 2983 | return true; |
| 2984 | } |
| 2985 | |
| 2986 | static bool trans_MUL(DisasContext *s, arg_MUL *a) |
| 2987 | { |
| 2988 | return op_mla(s, a, false); |
| 2989 | } |
| 2990 | |
| 2991 | static bool trans_MLA(DisasContext *s, arg_MLA *a) |
| 2992 | { |
| 2993 | return op_mla(s, a, true); |
| 2994 | } |
| 2995 | |
| 2996 | static bool trans_MLS(DisasContext *s, arg_MLS *a) |
| 2997 | { |
| 2998 | TCGv_i32 t1, t2; |
| 2999 | |
| 3000 | if (!ENABLE_ARCH_6T2) { |
| 3001 | return false; |
| 3002 | } |
| 3003 | t1 = load_reg(s, a->rn); |
| 3004 | t2 = load_reg(s, a->rm); |
| 3005 | tcg_gen_mul_i32(t1, t1, t2); |
| 3006 | t2 = load_reg(s, a->ra); |
| 3007 | tcg_gen_sub_i32(t1, t2, t1); |
| 3008 | store_reg(s, a->rd, t1); |
| 3009 | return true; |
| 3010 | } |
| 3011 | |
| 3012 | static bool op_mlal(DisasContext *s, arg_s_rrrr *a, bool uns, bool add) |
| 3013 | { |
| 3014 | TCGv_i32 t0, t1, t2, t3; |
| 3015 | |
| 3016 | t0 = load_reg(s, a->rm); |
| 3017 | t1 = load_reg(s, a->rn); |
| 3018 | if (uns) { |
| 3019 | tcg_gen_mulu2_i32(t0, t1, t0, t1); |
| 3020 | } else { |
| 3021 | tcg_gen_muls2_i32(t0, t1, t0, t1); |
| 3022 | } |
| 3023 | if (add) { |
| 3024 | t2 = load_reg(s, a->ra); |
| 3025 | t3 = load_reg(s, a->rd); |
| 3026 | tcg_gen_add2_i32(t0, t1, t0, t1, t2, t3); |
| 3027 | } |
| 3028 | if (a->s) { |
| 3029 | gen_logicq_cc(t0, t1); |
| 3030 | } |
| 3031 | store_reg(s, a->ra, t0); |
| 3032 | store_reg(s, a->rd, t1); |
| 3033 | return true; |
| 3034 | } |
| 3035 | |
| 3036 | static bool trans_UMULL(DisasContext *s, arg_UMULL *a) |
| 3037 | { |
| 3038 | return op_mlal(s, a, true, false); |
| 3039 | } |
| 3040 | |
| 3041 | static bool trans_SMULL(DisasContext *s, arg_SMULL *a) |
| 3042 | { |
| 3043 | return op_mlal(s, a, false, false); |
| 3044 | } |
| 3045 | |
| 3046 | static bool trans_UMLAL(DisasContext *s, arg_UMLAL *a) |
| 3047 | { |
| 3048 | return op_mlal(s, a, true, true); |
| 3049 | } |
| 3050 | |
| 3051 | static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) |
| 3052 | { |
| 3053 | return op_mlal(s, a, false, true); |
| 3054 | } |
| 3055 | |
| 3056 | static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) |
| 3057 | { |
| 3058 | TCGv_i32 t0, t1, t2, zero; |
| 3059 | |
| 3060 | if (s->thumb |
| 3061 | ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) |
| 3062 | : !ENABLE_ARCH_6) { |
| 3063 | return false; |
| 3064 | } |
| 3065 | |
| 3066 | t0 = load_reg(s, a->rm); |
| 3067 | t1 = load_reg(s, a->rn); |
| 3068 | tcg_gen_mulu2_i32(t0, t1, t0, t1); |
| 3069 | zero = tcg_constant_i32(0); |
| 3070 | t2 = load_reg(s, a->ra); |
| 3071 | tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); |
| 3072 | t2 = load_reg(s, a->rd); |
| 3073 | tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); |
| 3074 | store_reg(s, a->ra, t0); |
| 3075 | store_reg(s, a->rd, t1); |
| 3076 | return true; |
| 3077 | } |
| 3078 | |
| 3079 | /* |
| 3080 | * Saturating addition and subtraction |
| 3081 | */ |
| 3082 | |
| 3083 | static bool op_qaddsub(DisasContext *s, arg_rrr *a, bool add, bool doub) |
| 3084 | { |
| 3085 | TCGv_i32 t0, t1; |
| 3086 | |
| 3087 | if (s->thumb |
| 3088 | ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) |
| 3089 | : !ENABLE_ARCH_5TE) { |
| 3090 | return false; |
| 3091 | } |
| 3092 | |
| 3093 | t0 = load_reg(s, a->rm); |
| 3094 | t1 = load_reg(s, a->rn); |
| 3095 | if (doub) { |
| 3096 | gen_helper_add_saturate(t1, tcg_env, t1, t1); |
| 3097 | } |
| 3098 | if (add) { |
| 3099 | gen_helper_add_saturate(t0, tcg_env, t0, t1); |
| 3100 | } else { |
| 3101 | gen_helper_sub_saturate(t0, tcg_env, t0, t1); |
| 3102 | } |
| 3103 | store_reg(s, a->rd, t0); |
| 3104 | return true; |
| 3105 | } |
| 3106 | |
| 3107 | #define DO_QADDSUB(NAME, ADD, DOUB) \ |
| 3108 | static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ |
| 3109 | { \ |
| 3110 | return op_qaddsub(s, a, ADD, DOUB); \ |
| 3111 | } |
| 3112 | |
| 3113 | DO_QADDSUB(QADD, true, false) |
| 3114 | DO_QADDSUB(QSUB, false, false) |
| 3115 | DO_QADDSUB(QDADD, true, true) |
| 3116 | DO_QADDSUB(QDSUB, false, true) |
| 3117 | |
| 3118 | #undef DO_QADDSUB |
| 3119 | |
| 3120 | /* |
| 3121 | * Halfword multiply and multiply accumulate |
| 3122 | */ |
| 3123 | |
| 3124 | static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, |
| 3125 | int add_long, bool nt, bool mt) |
| 3126 | { |
| 3127 | TCGv_i32 t0, t1, tl, th; |
| 3128 | |
| 3129 | if (s->thumb |
| 3130 | ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) |
| 3131 | : !ENABLE_ARCH_5TE) { |
| 3132 | return false; |
| 3133 | } |
| 3134 | |
| 3135 | t0 = load_reg(s, a->rn); |
| 3136 | t1 = load_reg(s, a->rm); |
| 3137 | gen_mulxy(t0, t1, nt, mt); |
| 3138 | |
| 3139 | switch (add_long) { |
| 3140 | case 0: |
| 3141 | store_reg(s, a->rd, t0); |
| 3142 | break; |
| 3143 | case 1: |
| 3144 | t1 = load_reg(s, a->ra); |
| 3145 | gen_helper_add_setq(t0, tcg_env, t0, t1); |
| 3146 | store_reg(s, a->rd, t0); |
| 3147 | break; |
| 3148 | case 2: |
| 3149 | tl = load_reg(s, a->ra); |
| 3150 | th = load_reg(s, a->rd); |
| 3151 | /* Sign-extend the 32-bit product to 64 bits. */ |
| 3152 | t1 = tcg_temp_new_i32(); |
| 3153 | tcg_gen_sari_i32(t1, t0, 31); |
| 3154 | tcg_gen_add2_i32(tl, th, tl, th, t0, t1); |
| 3155 | store_reg(s, a->ra, tl); |
| 3156 | store_reg(s, a->rd, th); |
| 3157 | break; |
| 3158 | default: |
| 3159 | g_assert_not_reached(); |
| 3160 | } |
| 3161 | return true; |
| 3162 | } |
| 3163 | |
| 3164 | #define DO_SMLAX(NAME, add, nt, mt) \ |
| 3165 | static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ |
| 3166 | { \ |
| 3167 | return op_smlaxxx(s, a, add, nt, mt); \ |
| 3168 | } |
| 3169 | |
| 3170 | DO_SMLAX(SMULBB, 0, 0, 0) |
| 3171 | DO_SMLAX(SMULBT, 0, 0, 1) |
| 3172 | DO_SMLAX(SMULTB, 0, 1, 0) |
| 3173 | DO_SMLAX(SMULTT, 0, 1, 1) |
| 3174 | |
| 3175 | DO_SMLAX(SMLABB, 1, 0, 0) |
| 3176 | DO_SMLAX(SMLABT, 1, 0, 1) |
| 3177 | DO_SMLAX(SMLATB, 1, 1, 0) |
| 3178 | DO_SMLAX(SMLATT, 1, 1, 1) |
| 3179 | |
| 3180 | DO_SMLAX(SMLALBB, 2, 0, 0) |
| 3181 | DO_SMLAX(SMLALBT, 2, 0, 1) |
| 3182 | DO_SMLAX(SMLALTB, 2, 1, 0) |
| 3183 | DO_SMLAX(SMLALTT, 2, 1, 1) |
| 3184 | |
| 3185 | #undef DO_SMLAX |
| 3186 | |
| 3187 | static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) |
| 3188 | { |
| 3189 | TCGv_i32 t0, t1; |
| 3190 | |
| 3191 | if (!ENABLE_ARCH_5TE) { |
| 3192 | return false; |
| 3193 | } |
| 3194 | |
| 3195 | t0 = load_reg(s, a->rn); |
| 3196 | t1 = load_reg(s, a->rm); |
| 3197 | /* |
| 3198 | * Since the nominal result is product<47:16>, shift the 16-bit |
| 3199 | * input up by 16 bits, so that the result is at product<63:32>. |
| 3200 | */ |
| 3201 | if (mt) { |
| 3202 | tcg_gen_andi_i32(t1, t1, 0xffff0000); |
| 3203 | } else { |
| 3204 | tcg_gen_shli_i32(t1, t1, 16); |
| 3205 | } |
| 3206 | tcg_gen_muls2_i32(t0, t1, t0, t1); |
| 3207 | if (add) { |
| 3208 | t0 = load_reg(s, a->ra); |
| 3209 | gen_helper_add_setq(t1, tcg_env, t1, t0); |
| 3210 | } |
| 3211 | store_reg(s, a->rd, t1); |
| 3212 | return true; |
| 3213 | } |
| 3214 | |
| 3215 | #define DO_SMLAWX(NAME, add, mt) \ |
| 3216 | static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ |
| 3217 | { \ |
| 3218 | return op_smlawx(s, a, add, mt); \ |
| 3219 | } |
| 3220 | |
| 3221 | DO_SMLAWX(SMULWB, 0, 0) |
| 3222 | DO_SMLAWX(SMULWT, 0, 1) |
| 3223 | DO_SMLAWX(SMLAWB, 1, 0) |
| 3224 | DO_SMLAWX(SMLAWT, 1, 1) |
| 3225 | |
| 3226 | #undef DO_SMLAWX |
| 3227 | |
| 3228 | /* |
| 3229 | * MSR (immediate) and hints |
| 3230 | */ |
| 3231 | |
| 3232 | static bool trans_YIELD(DisasContext *s, arg_YIELD *a) |
| 3233 | { |
| 3234 | /* |
| 3235 | * When running single-threaded TCG code, use the helper to ensure that |
| 3236 | * the next round-robin scheduled vCPU gets a crack. When running in |
| 3237 | * MTTCG we don't generate jumps to the helper as it won't affect the |
| 3238 | * scheduling of other vCPUs. |
| 3239 | * This is a NOP hint on older architectures. |
| 3240 | */ |
| 3241 | if (arm_dc_feature(s, ARM_FEATURE_M) || |
| 3242 | arm_dc_feature(s, ARM_FEATURE_V6K)) { |
| 3243 | if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { |
| 3244 | gen_update_pc(s, curr_insn_len(s)); |
| 3245 | s->base.is_jmp = DISAS_YIELD; |
| 3246 | } |
| 3247 | } |
| 3248 | return true; |
| 3249 | } |
| 3250 | |
| 3251 | static bool trans_SEV(DisasContext *s, arg_SEV *a) |
| 3252 | { |
| 3253 | /* |
| 3254 | * SEV is a NOP for user-mode emulation. The instruction is |
| 3255 | * also a NOP hint on cores that pre-date the architectural |
| 3256 | * feature that adds it: |
| 3257 | * - M-profile always has SEV |
| 3258 | * - for A/R profile, it exists from v6K onward |
| 3259 | * The v7A Arm ARM is not entirely clear about whether v6K has the |
| 3260 | * Thumb SEV or not; we make the condition the same, to be |
| 3261 | * conservative. (If guests try to execute the Thumb SEV insn it |
| 3262 | * will be because they want SEV, not because they want a NOP.) |
| 3263 | */ |
| 3264 | #ifndef CONFIG_USER_ONLY |
| 3265 | if (arm_dc_feature(s, ARM_FEATURE_M) || |
| 3266 | arm_dc_feature(s, ARM_FEATURE_V6K)) { |
| 3267 | gen_helper_sev(tcg_env); |
| 3268 | } |
| 3269 | #endif |
| 3270 | return true; |
| 3271 | } |
| 3272 | |
| 3273 | static bool trans_SEVL(DisasContext *s, arg_SEV *a) |
| 3274 | { |
| 3275 | /* |
| 3276 | * SEVL only exists for v8A; for M-profile and v7A and earlier |
| 3277 | * this encoding is an unallocated must-NOP hint. |
| 3278 | */ |
| 3279 | if (!arm_dc_feature(s, ARM_FEATURE_M) && |
| 3280 | arm_dc_feature(s, ARM_FEATURE_V8)) { |
| 3281 | gen_event_reg(); |
| 3282 | } |
| 3283 | return true; |
| 3284 | } |
| 3285 | |
| 3286 | static bool trans_WFE(DisasContext *s, arg_WFE *a) |
| 3287 | { |
| 3288 | /* |
| 3289 | * For WFE, halt the vCPU until an event. This is a NOP |
| 3290 | * hint on older architectures, with the same conditions |
| 3291 | * as SEV. |
| 3292 | */ |
| 3293 | if (arm_dc_feature(s, ARM_FEATURE_M) || |
| 3294 | arm_dc_feature(s, ARM_FEATURE_V6K)) { |
| 3295 | gen_update_pc(s, curr_insn_len(s)); |
| 3296 | s->base.is_jmp = DISAS_WFE; |
| 3297 | } |
| 3298 | return true; |
| 3299 | } |
| 3300 | |
| 3301 | static bool trans_WFI(DisasContext *s, arg_WFI *a) |
| 3302 | { |
| 3303 | /* |
| 3304 | * For WFI, halt the vCPU until an IRQ. This is a NOP |
| 3305 | * hint on older architectures. |
| 3306 | */ |
| 3307 | if (arm_dc_feature(s, ARM_FEATURE_M) || |
| 3308 | arm_dc_feature(s, ARM_FEATURE_V6K)) { |
| 3309 | gen_update_pc(s, curr_insn_len(s)); |
| 3310 | s->base.is_jmp = DISAS_WFI; |
| 3311 | } |
| 3312 | return true; |
| 3313 | } |
| 3314 | |
| 3315 | static bool trans_ESB(DisasContext *s, arg_ESB *a) |
| 3316 | { |
| 3317 | /* |
| 3318 | * For M-profile, minimal-RAS ESB can be a NOP. |
| 3319 | * Without RAS, we must implement this as NOP. |
| 3320 | */ |
| 3321 | if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) { |
| 3322 | /* |
| 3323 | * QEMU does not have a source of physical SErrors, |
| 3324 | * so we are only concerned with virtual SErrors. |
| 3325 | * The pseudocode in the ARM for this case is |
| 3326 | * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then |
| 3327 | * AArch32.vESBOperation(); |
| 3328 | * Most of the condition can be evaluated at translation time. |
| 3329 | * Test for EL2 present, and defer test for SEL2 to runtime. |
| 3330 | */ |
| 3331 | if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { |
| 3332 | gen_helper_vesb(tcg_env); |
| 3333 | } |
| 3334 | } |
| 3335 | return true; |
| 3336 | } |
| 3337 | |
| 3338 | static bool trans_NOP(DisasContext *s, arg_NOP *a) |
| 3339 | { |
| 3340 | return true; |
| 3341 | } |
| 3342 | |
| 3343 | static bool trans_MAYBE_UNDEF_T1_HINT(DisasContext *s, |
| 3344 | arg_MAYBE_UNDEF_T1_HINT *a) |
| 3345 | { |
| 3346 | /* |
| 3347 | * The Thumb T1 encoding hint space was only defined starting |
| 3348 | * in v6T2 for A-profile. For M-profile it always exists, even |
| 3349 | * in v6M. |
| 3350 | */ |
| 3351 | if (arm_dc_feature(s, ARM_FEATURE_M) || |
| 3352 | arm_dc_feature(s, ARM_FEATURE_THUMB2)) { |
| 3353 | /* Allow decode to fall through to the hint insns and NOP space */ |
| 3354 | return false; |
| 3355 | } |
| 3356 | /* On the earlier cores, we must UNDEF */ |
| 3357 | unallocated_encoding(s); |
| 3358 | return true; |
| 3359 | } |
| 3360 | |
| 3361 | static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) |
| 3362 | { |
| 3363 | uint32_t val = ror32(a->imm, a->rot * 2); |
| 3364 | uint32_t mask = msr_mask(s, a->mask, a->r); |
| 3365 | |
| 3366 | if (gen_set_psr_im(s, mask, a->r, val)) { |
| 3367 | unallocated_encoding(s); |
| 3368 | } |
| 3369 | return true; |
| 3370 | } |
| 3371 | |
| 3372 | /* |
| 3373 | * Cyclic Redundancy Check |
| 3374 | */ |
| 3375 | |
| 3376 | static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, MemOp sz) |
| 3377 | { |
| 3378 | TCGv_i32 t1, t2, t3; |
| 3379 | |
| 3380 | if (!dc_isar_feature(aa32_crc32, s)) { |
| 3381 | return false; |
| 3382 | } |
| 3383 | |
| 3384 | t1 = load_reg(s, a->rn); |
| 3385 | t2 = load_reg(s, a->rm); |
| 3386 | switch (sz) { |
| 3387 | case MO_8: |
| 3388 | gen_uxtb(t2); |
| 3389 | break; |
| 3390 | case MO_16: |
| 3391 | gen_uxth(t2); |
| 3392 | break; |
| 3393 | case MO_32: |
| 3394 | break; |
| 3395 | default: |
| 3396 | g_assert_not_reached(); |
| 3397 | } |
| 3398 | t3 = tcg_constant_i32(1 << sz); |
| 3399 | if (c) { |
| 3400 | gen_helper_crc32c(t1, t1, t2, t3); |
| 3401 | } else { |
| 3402 | gen_helper_crc32(t1, t1, t2, t3); |
| 3403 | } |
| 3404 | store_reg(s, a->rd, t1); |
| 3405 | return true; |
| 3406 | } |
| 3407 | |
| 3408 | #define DO_CRC32(NAME, c, sz) \ |
| 3409 | static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ |
| 3410 | { return op_crc32(s, a, c, sz); } |
| 3411 | |
| 3412 | DO_CRC32(CRC32B, false, MO_8) |
| 3413 | DO_CRC32(CRC32H, false, MO_16) |
| 3414 | DO_CRC32(CRC32W, false, MO_32) |
| 3415 | DO_CRC32(CRC32CB, true, MO_8) |
| 3416 | DO_CRC32(CRC32CH, true, MO_16) |
| 3417 | DO_CRC32(CRC32CW, true, MO_32) |
| 3418 | |
| 3419 | #undef DO_CRC32 |
| 3420 | |
| 3421 | /* |
| 3422 | * Miscellaneous instructions |
| 3423 | */ |
| 3424 | |
| 3425 | static bool trans_MRS_bank(DisasContext *s, arg_MRS_bank *a) |
| 3426 | { |
| 3427 | if (arm_dc_feature(s, ARM_FEATURE_M)) { |
| 3428 | return false; |
| 3429 | } |
| 3430 | gen_mrs_banked(s, a->r, a->sysm, a->rd); |
| 3431 | return true; |
| 3432 | } |
| 3433 | |
| 3434 | static bool trans_MSR_bank(DisasContext *s, arg_MSR_bank *a) |
| 3435 | { |
| 3436 | if (arm_dc_feature(s, ARM_FEATURE_M)) { |
| 3437 | return false; |
| 3438 | } |
| 3439 | gen_msr_banked(s, a->r, a->sysm, a->rn); |
| 3440 | return true; |
| 3441 | } |
| 3442 | |
| 3443 | static bool trans_MRS_reg(DisasContext *s, arg_MRS_reg *a) |
| 3444 | { |
| 3445 | TCGv_i32 tmp; |
| 3446 | |
| 3447 | if (arm_dc_feature(s, ARM_FEATURE_M)) { |
| 3448 | return false; |
| 3449 | } |
| 3450 | if (a->r) { |
| 3451 | if (IS_USER(s)) { |
| 3452 | unallocated_encoding(s); |
| 3453 | return true; |
| 3454 | } |
| 3455 | tmp = load_cpu_field(spsr); |
| 3456 | } else { |
| 3457 | tmp = tcg_temp_new_i32(); |
| 3458 | gen_helper_cpsr_read(tmp, tcg_env); |
| 3459 | } |
| 3460 | store_reg(s, a->rd, tmp); |
| 3461 | return true; |
| 3462 | } |
| 3463 | |
| 3464 | static bool trans_MSR_reg(DisasContext *s, arg_MSR_reg *a) |
| 3465 | { |
| 3466 | TCGv_i32 tmp; |
| 3467 | uint32_t mask = msr_mask(s, a->mask, a->r); |
| 3468 | |
| 3469 | if (arm_dc_feature(s, ARM_FEATURE_M)) { |
| 3470 | return false; |
| 3471 | } |
| 3472 | tmp = load_reg(s, a->rn); |
| 3473 | if (gen_set_psr(s, mask, a->r, tmp)) { |
| 3474 | unallocated_encoding(s); |
| 3475 | } |
| 3476 | return true; |
| 3477 | } |
| 3478 | |
| 3479 | static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) |
| 3480 | { |
| 3481 | TCGv_i32 tmp; |
| 3482 | |
| 3483 | if (!arm_dc_feature(s, ARM_FEATURE_M)) { |
| 3484 | return false; |
| 3485 | } |
| 3486 | tmp = tcg_temp_new_i32(); |
| 3487 | gen_helper_v7m_mrs(tmp, tcg_env, tcg_constant_i32(a->sysm)); |
| 3488 | store_reg(s, a->rd, tmp); |
| 3489 | return true; |
| 3490 | } |
| 3491 | |
| 3492 | static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) |
| 3493 | { |
| 3494 | TCGv_i32 addr, reg; |
| 3495 | |
| 3496 | if (!arm_dc_feature(s, ARM_FEATURE_M)) { |
| 3497 | return false; |
| 3498 | } |
| 3499 | addr = tcg_constant_i32((a->mask << 10) | a->sysm); |
| 3500 | reg = load_reg(s, a->rn); |
| 3501 | gen_helper_v7m_msr(tcg_env, addr, reg); |
| 3502 | /* If we wrote to CONTROL, the EL might have changed */ |
| 3503 | gen_rebuild_hflags(s, true); |
| 3504 | gen_lookup_tb(s); |
| 3505 | return true; |
| 3506 | } |
| 3507 | |
| 3508 | static bool trans_BX(DisasContext *s, arg_BX *a) |
| 3509 | { |
| 3510 | if (!ENABLE_ARCH_4T) { |
| 3511 | return false; |
| 3512 | } |
| 3513 | gen_bx_excret(s, load_reg(s, a->rm)); |
| 3514 | return true; |
| 3515 | } |
| 3516 | |
| 3517 | static bool trans_BXJ(DisasContext *s, arg_BXJ *a) |
| 3518 | { |
| 3519 | if (!ENABLE_ARCH_5J || arm_dc_feature(s, ARM_FEATURE_M)) { |
| 3520 | return false; |
| 3521 | } |
| 3522 | /* |
| 3523 | * v7A allows BXJ to be trapped via HSTR.TJDBX. We don't waste a |
| 3524 | * TBFLAGS bit on a basically-never-happens case, so call a helper |
| 3525 | * function to check for the trap and raise the exception if needed |
| 3526 | * (passing it the register number for the syndrome value). |
| 3527 | * v8A doesn't have this HSTR bit. |
| 3528 | */ |
| 3529 | if (!arm_dc_feature(s, ARM_FEATURE_V8) && |
| 3530 | arm_dc_feature(s, ARM_FEATURE_EL2) && |
| 3531 | s->current_el < 2 && s->ns) { |
| 3532 | gen_helper_check_bxj_trap(tcg_env, tcg_constant_i32(a->rm)); |
| 3533 | } |
| 3534 | /* Trivial implementation equivalent to bx. */ |
| 3535 | gen_bx(s, load_reg(s, a->rm)); |
| 3536 | return true; |
| 3537 | } |
| 3538 | |
| 3539 | static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) |
| 3540 | { |
| 3541 | TCGv_i32 tmp; |
| 3542 | |
| 3543 | if (!ENABLE_ARCH_5) { |
| 3544 | return false; |
| 3545 | } |
| 3546 | tmp = load_reg(s, a->rm); |
| 3547 | gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb); |
| 3548 | gen_bx(s, tmp); |
| 3549 | return true; |
| 3550 | } |
| 3551 | |
| 3552 | /* |
| 3553 | * BXNS/BLXNS: only exist for v8M with the security extensions, |
| 3554 | * and always UNDEF if NonSecure. We don't implement these in |
| 3555 | * the user-only mode either (in theory you can use them from |
| 3556 | * Secure User mode but they are too tied in to system emulation). |
| 3557 | */ |
| 3558 | static bool trans_BXNS(DisasContext *s, arg_BXNS *a) |
| 3559 | { |
| 3560 | if (!s->v8m_secure || IS_USER_ONLY) { |
| 3561 | unallocated_encoding(s); |
| 3562 | } else { |
| 3563 | gen_bxns(s, a->rm); |
| 3564 | } |
| 3565 | return true; |
| 3566 | } |
| 3567 | |
| 3568 | static bool trans_BLXNS(DisasContext *s, arg_BLXNS *a) |
| 3569 | { |
| 3570 | if (!s->v8m_secure || IS_USER_ONLY) { |
| 3571 | unallocated_encoding(s); |
| 3572 | } else { |
| 3573 | gen_blxns(s, a->rm); |
| 3574 | } |
| 3575 | return true; |
| 3576 | } |
| 3577 | |
| 3578 | static bool trans_CLZ(DisasContext *s, arg_CLZ *a) |
| 3579 | { |
| 3580 | TCGv_i32 tmp; |
| 3581 | |
| 3582 | if (!ENABLE_ARCH_5) { |
| 3583 | return false; |
| 3584 | } |
| 3585 | tmp = load_reg(s, a->rm); |
| 3586 | tcg_gen_clzi_i32(tmp, tmp, 32); |
| 3587 | store_reg(s, a->rd, tmp); |
| 3588 | return true; |
| 3589 | } |
| 3590 | |
| 3591 | static bool trans_ERET(DisasContext *s, arg_ERET *a) |
| 3592 | { |
| 3593 | TCGv_i32 tmp; |
| 3594 | |
| 3595 | if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) { |
| 3596 | return false; |
| 3597 | } |
| 3598 | if (IS_USER(s)) { |
| 3599 | unallocated_encoding(s); |
| 3600 | return true; |
| 3601 | } |
| 3602 | if (s->current_el == 2) { |
| 3603 | /* ERET from Hyp uses ELR_Hyp, not LR */ |
| 3604 | tmp = load_cpu_field_low32(elr_el[2]); |
| 3605 | } else { |
| 3606 | tmp = load_reg(s, 14); |
| 3607 | } |
| 3608 | gen_exception_return(s, tmp); |
| 3609 | return true; |
| 3610 | } |
| 3611 | |
| 3612 | static bool trans_HLT(DisasContext *s, arg_HLT *a) |
| 3613 | { |
| 3614 | gen_hlt(s, a->imm); |
| 3615 | return true; |
| 3616 | } |
| 3617 | |
| 3618 | static bool trans_BKPT(DisasContext *s, arg_BKPT *a) |
| 3619 | { |
| 3620 | if (!ENABLE_ARCH_5) { |
| 3621 | return false; |
| 3622 | } |
| 3623 | /* BKPT is OK with ECI set and leaves it untouched */ |
| 3624 | s->eci_handled = true; |
| 3625 | if (arm_dc_feature(s, ARM_FEATURE_M) && |
| 3626 | semihosting_enabled(s->current_el == 0) && |
| 3627 | (a->imm == 0xab)) { |
| 3628 | gen_exception_internal_insn(s, EXCP_SEMIHOST); |
| 3629 | } else { |
| 3630 | gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, curr_insn_len(s) == 2)); |
| 3631 | } |
| 3632 | return true; |
| 3633 | } |
| 3634 | |
| 3635 | static bool trans_HVC(DisasContext *s, arg_HVC *a) |
| 3636 | { |
| 3637 | if (!ENABLE_ARCH_7 || arm_dc_feature(s, ARM_FEATURE_M)) { |
| 3638 | return false; |
| 3639 | } |
| 3640 | if (IS_USER(s)) { |
| 3641 | unallocated_encoding(s); |
| 3642 | } else { |
| 3643 | gen_hvc(s, a->imm); |
| 3644 | } |
| 3645 | return true; |
| 3646 | } |
| 3647 | |
| 3648 | static bool trans_SMC(DisasContext *s, arg_SMC *a) |
| 3649 | { |
| 3650 | if (!ENABLE_ARCH_6K || arm_dc_feature(s, ARM_FEATURE_M)) { |
| 3651 | return false; |
| 3652 | } |
| 3653 | if (IS_USER(s)) { |
| 3654 | unallocated_encoding(s); |
| 3655 | } else { |
| 3656 | gen_smc(s); |
| 3657 | } |
| 3658 | return true; |
| 3659 | } |
| 3660 | |
| 3661 | static bool trans_SG(DisasContext *s, arg_SG *a) |
| 3662 | { |
| 3663 | if (!arm_dc_feature(s, ARM_FEATURE_M) || |
| 3664 | !arm_dc_feature(s, ARM_FEATURE_V8)) { |
| 3665 | return false; |
| 3666 | } |
| 3667 | /* |
| 3668 | * SG (v8M only) |
| 3669 | * The bulk of the behaviour for this instruction is implemented |
| 3670 | * in v7m_handle_execute_nsc(), which deals with the insn when |
| 3671 | * it is executed by a CPU in non-secure state from memory |
| 3672 | * which is Secure & NonSecure-Callable. |
| 3673 | * Here we only need to handle the remaining cases: |
| 3674 | * * in NS memory (including the "security extension not |
| 3675 | * implemented" case) : NOP |
| 3676 | * * in S memory but CPU already secure (clear IT bits) |
| 3677 | * We know that the attribute for the memory this insn is |
| 3678 | * in must match the current CPU state, because otherwise |
| 3679 | * get_phys_addr_pmsav8 would have generated an exception. |
| 3680 | */ |
| 3681 | if (s->v8m_secure) { |
| 3682 | /* Like the IT insn, we don't need to generate any code */ |
| 3683 | s->condexec_cond = 0; |
| 3684 | s->condexec_mask = 0; |
| 3685 | } |
| 3686 | return true; |
| 3687 | } |
| 3688 | |
| 3689 | static bool trans_TT(DisasContext *s, arg_TT *a) |
| 3690 | { |
| 3691 | TCGv_i32 addr, tmp; |
| 3692 | |
| 3693 | if (!arm_dc_feature(s, ARM_FEATURE_M) || |
| 3694 | !arm_dc_feature(s, ARM_FEATURE_V8)) { |
| 3695 | return false; |
| 3696 | } |
| 3697 | if (a->rd == 13 || a->rd == 15 || a->rn == 15) { |
| 3698 | /* We UNDEF for these UNPREDICTABLE cases */ |
| 3699 | unallocated_encoding(s); |
| 3700 | return true; |
| 3701 | } |
| 3702 | if (a->A && !s->v8m_secure) { |
| 3703 | /* This case is UNDEFINED. */ |
| 3704 | unallocated_encoding(s); |
| 3705 | return true; |
| 3706 | } |
| 3707 | |
| 3708 | addr = load_reg(s, a->rn); |
| 3709 | tmp = tcg_temp_new_i32(); |
| 3710 | gen_helper_v7m_tt(tmp, tcg_env, addr, tcg_constant_i32((a->A << 1) | a->T)); |
| 3711 | store_reg(s, a->rd, tmp); |
| 3712 | return true; |
| 3713 | } |
| 3714 | |
| 3715 | /* |
| 3716 | * Load/store register index |
| 3717 | */ |
| 3718 | |
| 3719 | static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w) |
| 3720 | { |
| 3721 | ISSInfo ret; |
| 3722 | |
| 3723 | /* ISS not valid if writeback */ |
| 3724 | if (p && !w) { |
| 3725 | ret = rd; |
| 3726 | if (curr_insn_len(s) == 2) { |
| 3727 | ret |= ISSIs16Bit; |
| 3728 | } |
| 3729 | } else { |
| 3730 | ret = ISSInvalid; |
| 3731 | } |
| 3732 | return ret; |
| 3733 | } |
| 3734 | |
| 3735 | static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a) |
| 3736 | { |
| 3737 | TCGv_i32 addr = load_reg(s, a->rn); |
| 3738 | |
| 3739 | if (s->v8m_stackcheck && a->rn == 13 && a->w) { |
| 3740 | gen_helper_v8m_stackcheck(tcg_env, addr); |
| 3741 | } |
| 3742 | |
| 3743 | if (a->p) { |
| 3744 | TCGv_i32 ofs = load_reg(s, a->rm); |
| 3745 | gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); |
| 3746 | if (a->u) { |
| 3747 | tcg_gen_add_i32(addr, addr, ofs); |
| 3748 | } else { |
| 3749 | tcg_gen_sub_i32(addr, addr, ofs); |
| 3750 | } |
| 3751 | } |
| 3752 | return addr; |
| 3753 | } |
| 3754 | |
| 3755 | static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a, |
| 3756 | TCGv_i32 addr) |
| 3757 | { |
| 3758 | if (!a->p) { |
| 3759 | TCGv_i32 ofs = load_reg(s, a->rm); |
| 3760 | gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); |
| 3761 | if (a->u) { |
| 3762 | tcg_gen_add_i32(addr, addr, ofs); |
| 3763 | } else { |
| 3764 | tcg_gen_sub_i32(addr, addr, ofs); |
| 3765 | } |
| 3766 | } else if (!a->w) { |
| 3767 | return; |
| 3768 | } |
| 3769 | store_reg(s, a->rn, addr); |
| 3770 | } |
| 3771 | |
| 3772 | static bool op_load_rr(DisasContext *s, arg_ldst_rr *a, |
| 3773 | MemOp mop, int mem_idx) |
| 3774 | { |
| 3775 | ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w); |
| 3776 | TCGv_i32 addr, tmp; |
| 3777 | |
| 3778 | addr = op_addr_rr_pre(s, a); |
| 3779 | |
| 3780 | tmp = tcg_temp_new_i32(); |
| 3781 | gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop); |
| 3782 | disas_set_da_iss(s, mop, issinfo); |
| 3783 | |
| 3784 | /* |
| 3785 | * Perform base writeback before the loaded value to |
| 3786 | * ensure correct behavior with overlapping index registers. |
| 3787 | */ |
| 3788 | op_addr_rr_post(s, a, addr); |
| 3789 | store_reg_from_load(s, a->rt, tmp); |
| 3790 | return true; |
| 3791 | } |
| 3792 | |
| 3793 | static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, |
| 3794 | MemOp mop, int mem_idx) |
| 3795 | { |
| 3796 | ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; |
| 3797 | TCGv_i32 addr, tmp; |
| 3798 | |
| 3799 | /* |
| 3800 | * In Thumb encodings of stores Rn=1111 is UNDEF; for Arm it |
| 3801 | * is either UNPREDICTABLE or has defined behaviour |
| 3802 | */ |
| 3803 | if (s->thumb && a->rn == 15) { |
| 3804 | return false; |
| 3805 | } |
| 3806 | |
| 3807 | addr = op_addr_rr_pre(s, a); |
| 3808 | |
| 3809 | tmp = load_reg(s, a->rt); |
| 3810 | gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); |
| 3811 | disas_set_da_iss(s, mop, issinfo); |
| 3812 | |
| 3813 | op_addr_rr_post(s, a, addr); |
| 3814 | return true; |
| 3815 | } |
| 3816 | |
| 3817 | static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2) |
| 3818 | { |
| 3819 | /* |
| 3820 | * LDRD is required to be an atomic 64-bit access if the |
| 3821 | * address is 8-aligned, two atomic 32-bit accesses if |
| 3822 | * it's only 4-aligned, and to give an alignment fault |
| 3823 | * if it's not 4-aligned. This is MO_ALIGN_4 | MO_ATOM_SUBALIGN. |
| 3824 | * Rt is always the word from the lower address, and Rt2 the |
| 3825 | * data from the higher address, regardless of endianness. |
| 3826 | * So (like gen_load_exclusive) we avoid gen_aa32_ld_i64() |
| 3827 | * so we don't get its SCTLR_B check, and instead do a 64-bit access |
| 3828 | * using MO_BE if appropriate and then split the two halves. |
| 3829 | * |
| 3830 | * For M-profile, and for A-profile before LPAE, the 64-bit |
| 3831 | * atomicity is not required. We could model that using |
| 3832 | * the looser MO_ATOM_IFALIGN_PAIR, but providing a higher |
| 3833 | * level of atomicity than required is harmless (we would not |
| 3834 | * currently generate better code for IFALIGN_PAIR here). |
| 3835 | * |
| 3836 | * This also gives us the correct behaviour of not updating |
| 3837 | * rt if the load of rt2 faults; this is required for cases |
| 3838 | * like "ldrd r2, r3, [r2]" where rt is also the base register. |
| 3839 | */ |
| 3840 | int mem_idx = get_mem_index(s); |
| 3841 | MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data; |
| 3842 | TCGv_va taddr = gen_aa32_addr(s, addr, opc); |
| 3843 | TCGv_i64 t64 = tcg_temp_new_i64(); |
| 3844 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 3845 | TCGv_i32 tmp2 = tcg_temp_new_i32(); |
| 3846 | |
| 3847 | tcg_gen_qemu_ld_i64(t64, taddr, mem_idx, opc); |
| 3848 | if (s->be_data == MO_BE) { |
| 3849 | tcg_gen_extr_i64_i32(tmp2, tmp, t64); |
| 3850 | } else { |
| 3851 | tcg_gen_extr_i64_i32(tmp, tmp2, t64); |
| 3852 | } |
| 3853 | store_reg(s, rt, tmp); |
| 3854 | store_reg(s, rt2, tmp2); |
| 3855 | } |
| 3856 | |
| 3857 | static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) |
| 3858 | { |
| 3859 | TCGv_i32 addr; |
| 3860 | |
| 3861 | if (!ENABLE_ARCH_5TE) { |
| 3862 | return false; |
| 3863 | } |
| 3864 | if (a->rt & 1) { |
| 3865 | unallocated_encoding(s); |
| 3866 | return true; |
| 3867 | } |
| 3868 | addr = op_addr_rr_pre(s, a); |
| 3869 | |
| 3870 | do_ldrd_load(s, addr, a->rt, a->rt + 1); |
| 3871 | |
| 3872 | /* LDRD w/ base writeback is undefined if the registers overlap. */ |
| 3873 | op_addr_rr_post(s, a, addr); |
| 3874 | return true; |
| 3875 | } |
| 3876 | |
| 3877 | static void do_strd_store(DisasContext *s, TCGv_i32 addr, int rt, int rt2) |
| 3878 | { |
| 3879 | /* |
| 3880 | * STRD is required to be an atomic 64-bit access if the |
| 3881 | * address is 8-aligned, two atomic 32-bit accesses if |
| 3882 | * it's only 4-aligned, and to give an alignment fault |
| 3883 | * if it's not 4-aligned. |
| 3884 | * Rt is always the word from the lower address, and Rt2 the |
| 3885 | * data from the higher address, regardless of endianness. |
| 3886 | * So (like gen_store_exclusive) we avoid gen_aa32_ld_i64() |
| 3887 | * so we don't get its SCTLR_B check, and instead do a 64-bit access |
| 3888 | * using MO_BE if appropriate, using a value constructed |
| 3889 | * by putting the two halves together in the right order. |
| 3890 | * |
| 3891 | * As with LDRD, the 64-bit atomicity is not required for |
| 3892 | * M-profile, or for A-profile before LPAE, and we provide |
| 3893 | * the higher guarantee always for simplicity. |
| 3894 | */ |
| 3895 | int mem_idx = get_mem_index(s); |
| 3896 | MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data; |
| 3897 | TCGv_va taddr = gen_aa32_addr(s, addr, opc); |
| 3898 | TCGv_i32 t1 = load_reg(s, rt); |
| 3899 | TCGv_i32 t2 = load_reg(s, rt2); |
| 3900 | TCGv_i64 t64 = tcg_temp_new_i64(); |
| 3901 | |
| 3902 | if (s->be_data == MO_BE) { |
| 3903 | tcg_gen_concat_i32_i64(t64, t2, t1); |
| 3904 | } else { |
| 3905 | tcg_gen_concat_i32_i64(t64, t1, t2); |
| 3906 | } |
| 3907 | tcg_gen_qemu_st_i64(t64, taddr, mem_idx, opc); |
| 3908 | } |
| 3909 | |
| 3910 | static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) |
| 3911 | { |
| 3912 | TCGv_i32 addr; |
| 3913 | |
| 3914 | if (!ENABLE_ARCH_5TE) { |
| 3915 | return false; |
| 3916 | } |
| 3917 | if (a->rt & 1) { |
| 3918 | unallocated_encoding(s); |
| 3919 | return true; |
| 3920 | } |
| 3921 | addr = op_addr_rr_pre(s, a); |
| 3922 | |
| 3923 | do_strd_store(s, addr, a->rt, a->rt + 1); |
| 3924 | |
| 3925 | op_addr_rr_post(s, a, addr); |
| 3926 | return true; |
| 3927 | } |
| 3928 | |
| 3929 | /* |
| 3930 | * Load/store immediate index |
| 3931 | */ |
| 3932 | |
| 3933 | static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a) |
| 3934 | { |
| 3935 | int ofs = a->imm; |
| 3936 | |
| 3937 | if (!a->u) { |
| 3938 | ofs = -ofs; |
| 3939 | } |
| 3940 | |
| 3941 | if (s->v8m_stackcheck && a->rn == 13 && a->w) { |
| 3942 | /* |
| 3943 | * Stackcheck. Here we know 'addr' is the current SP; |
| 3944 | * U is set if we're moving SP up, else down. It is |
| 3945 | * UNKNOWN whether the limit check triggers when SP starts |
| 3946 | * below the limit and ends up above it; we chose to do so. |
| 3947 | */ |
| 3948 | if (!a->u) { |
| 3949 | TCGv_i32 newsp = tcg_temp_new_i32(); |
| 3950 | tcg_gen_addi_i32(newsp, cpu_R[13], ofs); |
| 3951 | gen_helper_v8m_stackcheck(tcg_env, newsp); |
| 3952 | } else { |
| 3953 | gen_helper_v8m_stackcheck(tcg_env, cpu_R[13]); |
| 3954 | } |
| 3955 | } |
| 3956 | |
| 3957 | return add_reg_for_lit(s, a->rn, a->p ? ofs : 0); |
| 3958 | } |
| 3959 | |
| 3960 | static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a, |
| 3961 | TCGv_i32 addr) |
| 3962 | { |
| 3963 | int address_offset = 0; |
| 3964 | if (!a->p) { |
| 3965 | if (a->u) { |
| 3966 | address_offset = a->imm; |
| 3967 | } else { |
| 3968 | address_offset = -a->imm; |
| 3969 | } |
| 3970 | } else if (!a->w) { |
| 3971 | return; |
| 3972 | } |
| 3973 | tcg_gen_addi_i32(addr, addr, address_offset); |
| 3974 | store_reg(s, a->rn, addr); |
| 3975 | } |
| 3976 | |
| 3977 | static bool op_load_ri(DisasContext *s, arg_ldst_ri *a, |
| 3978 | MemOp mop, int mem_idx) |
| 3979 | { |
| 3980 | ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w); |
| 3981 | TCGv_i32 addr, tmp; |
| 3982 | |
| 3983 | addr = op_addr_ri_pre(s, a); |
| 3984 | |
| 3985 | tmp = tcg_temp_new_i32(); |
| 3986 | gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop); |
| 3987 | disas_set_da_iss(s, mop, issinfo); |
| 3988 | |
| 3989 | /* |
| 3990 | * Perform base writeback before the loaded value to |
| 3991 | * ensure correct behavior with overlapping index registers. |
| 3992 | */ |
| 3993 | op_addr_ri_post(s, a, addr); |
| 3994 | store_reg_from_load(s, a->rt, tmp); |
| 3995 | return true; |
| 3996 | } |
| 3997 | |
| 3998 | static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, |
| 3999 | MemOp mop, int mem_idx) |
| 4000 | { |
| 4001 | ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; |
| 4002 | TCGv_i32 addr, tmp; |
| 4003 | |
| 4004 | /* |
| 4005 | * In Thumb encodings of stores Rn=1111 is UNDEF; for Arm it |
| 4006 | * is either UNPREDICTABLE or has defined behaviour |
| 4007 | */ |
| 4008 | if (s->thumb && a->rn == 15) { |
| 4009 | return false; |
| 4010 | } |
| 4011 | |
| 4012 | addr = op_addr_ri_pre(s, a); |
| 4013 | |
| 4014 | tmp = load_reg(s, a->rt); |
| 4015 | gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); |
| 4016 | disas_set_da_iss(s, mop, issinfo); |
| 4017 | |
| 4018 | op_addr_ri_post(s, a, addr); |
| 4019 | return true; |
| 4020 | } |
| 4021 | |
| 4022 | static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) |
| 4023 | { |
| 4024 | TCGv_i32 addr; |
| 4025 | |
| 4026 | addr = op_addr_ri_pre(s, a); |
| 4027 | |
| 4028 | do_ldrd_load(s, addr, a->rt, rt2); |
| 4029 | |
| 4030 | /* LDRD w/ base writeback is undefined if the registers overlap. */ |
| 4031 | op_addr_ri_post(s, a, addr); |
| 4032 | return true; |
| 4033 | } |
| 4034 | |
| 4035 | static bool trans_LDRD_ri_a32(DisasContext *s, arg_ldst_ri *a) |
| 4036 | { |
| 4037 | if (!ENABLE_ARCH_5TE || (a->rt & 1)) { |
| 4038 | return false; |
| 4039 | } |
| 4040 | return op_ldrd_ri(s, a, a->rt + 1); |
| 4041 | } |
| 4042 | |
| 4043 | static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) |
| 4044 | { |
| 4045 | arg_ldst_ri b = { |
| 4046 | .u = a->u, .w = a->w, .p = a->p, |
| 4047 | .rn = a->rn, .rt = a->rt, .imm = a->imm |
| 4048 | }; |
| 4049 | return op_ldrd_ri(s, &b, a->rt2); |
| 4050 | } |
| 4051 | |
| 4052 | static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) |
| 4053 | { |
| 4054 | TCGv_i32 addr; |
| 4055 | |
| 4056 | addr = op_addr_ri_pre(s, a); |
| 4057 | |
| 4058 | do_strd_store(s, addr, a->rt, rt2); |
| 4059 | |
| 4060 | op_addr_ri_post(s, a, addr); |
| 4061 | return true; |
| 4062 | } |
| 4063 | |
| 4064 | static bool trans_STRD_ri_a32(DisasContext *s, arg_ldst_ri *a) |
| 4065 | { |
| 4066 | if (!ENABLE_ARCH_5TE || (a->rt & 1)) { |
| 4067 | return false; |
| 4068 | } |
| 4069 | return op_strd_ri(s, a, a->rt + 1); |
| 4070 | } |
| 4071 | |
| 4072 | static bool trans_STRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) |
| 4073 | { |
| 4074 | arg_ldst_ri b = { |
| 4075 | .u = a->u, .w = a->w, .p = a->p, |
| 4076 | .rn = a->rn, .rt = a->rt, .imm = a->imm |
| 4077 | }; |
| 4078 | return op_strd_ri(s, &b, a->rt2); |
| 4079 | } |
| 4080 | |
| 4081 | #define DO_LDST(NAME, WHICH, MEMOP) \ |
| 4082 | static bool trans_##NAME##_ri(DisasContext *s, arg_ldst_ri *a) \ |
| 4083 | { \ |
| 4084 | return op_##WHICH##_ri(s, a, MEMOP, get_mem_index(s)); \ |
| 4085 | } \ |
| 4086 | static bool trans_##NAME##T_ri(DisasContext *s, arg_ldst_ri *a) \ |
| 4087 | { \ |
| 4088 | return op_##WHICH##_ri(s, a, MEMOP, get_a32_user_mem_index(s)); \ |
| 4089 | } \ |
| 4090 | static bool trans_##NAME##_rr(DisasContext *s, arg_ldst_rr *a) \ |
| 4091 | { \ |
| 4092 | return op_##WHICH##_rr(s, a, MEMOP, get_mem_index(s)); \ |
| 4093 | } \ |
| 4094 | static bool trans_##NAME##T_rr(DisasContext *s, arg_ldst_rr *a) \ |
| 4095 | { \ |
| 4096 | return op_##WHICH##_rr(s, a, MEMOP, get_a32_user_mem_index(s)); \ |
| 4097 | } |
| 4098 | |
| 4099 | DO_LDST(LDR, load, MO_UL) |
| 4100 | DO_LDST(LDRB, load, MO_UB) |
| 4101 | DO_LDST(LDRH, load, MO_UW) |
| 4102 | DO_LDST(LDRSB, load, MO_SB) |
| 4103 | DO_LDST(LDRSH, load, MO_SW) |
| 4104 | |
| 4105 | DO_LDST(STR, store, MO_UL) |
| 4106 | DO_LDST(STRB, store, MO_UB) |
| 4107 | DO_LDST(STRH, store, MO_UW) |
| 4108 | |
| 4109 | #undef DO_LDST |
| 4110 | |
| 4111 | /* |
| 4112 | * Synchronization primitives |
| 4113 | */ |
| 4114 | |
| 4115 | static bool op_swp(DisasContext *s, arg_SWP *a, MemOp opc) |
| 4116 | { |
| 4117 | TCGv_i32 addr, tmp; |
| 4118 | TCGv_va taddr; |
| 4119 | |
| 4120 | opc |= s->be_data; |
| 4121 | addr = load_reg(s, a->rn); |
| 4122 | taddr = gen_aa32_addr(s, addr, opc); |
| 4123 | |
| 4124 | tmp = load_reg(s, a->rt2); |
| 4125 | tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, get_mem_index(s), opc); |
| 4126 | |
| 4127 | store_reg(s, a->rt, tmp); |
| 4128 | return true; |
| 4129 | } |
| 4130 | |
| 4131 | static bool trans_SWP(DisasContext *s, arg_SWP *a) |
| 4132 | { |
| 4133 | return op_swp(s, a, MO_UL | MO_ALIGN); |
| 4134 | } |
| 4135 | |
| 4136 | static bool trans_SWPB(DisasContext *s, arg_SWP *a) |
| 4137 | { |
| 4138 | return op_swp(s, a, MO_UB); |
| 4139 | } |
| 4140 | |
| 4141 | /* |
| 4142 | * Load/Store Exclusive and Load-Acquire/Store-Release |
| 4143 | */ |
| 4144 | |
| 4145 | static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel) |
| 4146 | { |
| 4147 | TCGv_i32 addr; |
| 4148 | /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */ |
| 4149 | bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M); |
| 4150 | |
| 4151 | /* We UNDEF for these UNPREDICTABLE cases. */ |
| 4152 | if (a->rd == 15 || a->rn == 15 || a->rt == 15 |
| 4153 | || a->rd == a->rn || a->rd == a->rt |
| 4154 | || (!v8a && s->thumb && (a->rd == 13 || a->rt == 13)) |
| 4155 | || (mop == MO_64 |
| 4156 | && (a->rt2 == 15 |
| 4157 | || a->rd == a->rt2 |
| 4158 | || (!v8a && s->thumb && a->rt2 == 13)))) { |
| 4159 | unallocated_encoding(s); |
| 4160 | return true; |
| 4161 | } |
| 4162 | |
| 4163 | if (rel) { |
| 4164 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); |
| 4165 | } |
| 4166 | |
| 4167 | addr = tcg_temp_new_i32(); |
| 4168 | load_reg_var(s, addr, a->rn); |
| 4169 | tcg_gen_addi_i32(addr, addr, a->imm); |
| 4170 | |
| 4171 | gen_store_exclusive(s, a->rd, a->rt, a->rt2, addr, mop); |
| 4172 | return true; |
| 4173 | } |
| 4174 | |
| 4175 | static bool trans_STREX(DisasContext *s, arg_STREX *a) |
| 4176 | { |
| 4177 | if (!ENABLE_ARCH_6) { |
| 4178 | return false; |
| 4179 | } |
| 4180 | return op_strex(s, a, MO_32, false); |
| 4181 | } |
| 4182 | |
| 4183 | static bool trans_STREXD_a32(DisasContext *s, arg_STREX *a) |
| 4184 | { |
| 4185 | if (!ENABLE_ARCH_6K) { |
| 4186 | return false; |
| 4187 | } |
| 4188 | /* We UNDEF for these UNPREDICTABLE cases. */ |
| 4189 | if (a->rt & 1) { |
| 4190 | unallocated_encoding(s); |
| 4191 | return true; |
| 4192 | } |
| 4193 | a->rt2 = a->rt + 1; |
| 4194 | return op_strex(s, a, MO_64, false); |
| 4195 | } |
| 4196 | |
| 4197 | static bool trans_STREXD_t32(DisasContext *s, arg_STREX *a) |
| 4198 | { |
| 4199 | return op_strex(s, a, MO_64, false); |
| 4200 | } |
| 4201 | |
| 4202 | static bool trans_STREXB(DisasContext *s, arg_STREX *a) |
| 4203 | { |
| 4204 | if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { |
| 4205 | return false; |
| 4206 | } |
| 4207 | return op_strex(s, a, MO_8, false); |
| 4208 | } |
| 4209 | |
| 4210 | static bool trans_STREXH(DisasContext *s, arg_STREX *a) |
| 4211 | { |
| 4212 | if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { |
| 4213 | return false; |
| 4214 | } |
| 4215 | return op_strex(s, a, MO_16, false); |
| 4216 | } |
| 4217 | |
| 4218 | static bool trans_STLEX(DisasContext *s, arg_STREX *a) |
| 4219 | { |
| 4220 | if (!ENABLE_ARCH_8) { |
| 4221 | return false; |
| 4222 | } |
| 4223 | return op_strex(s, a, MO_32, true); |
| 4224 | } |
| 4225 | |
| 4226 | static bool trans_STLEXD_a32(DisasContext *s, arg_STREX *a) |
| 4227 | { |
| 4228 | if (!ENABLE_ARCH_8) { |
| 4229 | return false; |
| 4230 | } |
| 4231 | /* We UNDEF for these UNPREDICTABLE cases. */ |
| 4232 | if (a->rt & 1) { |
| 4233 | unallocated_encoding(s); |
| 4234 | return true; |
| 4235 | } |
| 4236 | a->rt2 = a->rt + 1; |
| 4237 | return op_strex(s, a, MO_64, true); |
| 4238 | } |
| 4239 | |
| 4240 | static bool trans_STLEXD_t32(DisasContext *s, arg_STREX *a) |
| 4241 | { |
| 4242 | if (!ENABLE_ARCH_8) { |
| 4243 | return false; |
| 4244 | } |
| 4245 | return op_strex(s, a, MO_64, true); |
| 4246 | } |
| 4247 | |
| 4248 | static bool trans_STLEXB(DisasContext *s, arg_STREX *a) |
| 4249 | { |
| 4250 | if (!ENABLE_ARCH_8) { |
| 4251 | return false; |
| 4252 | } |
| 4253 | return op_strex(s, a, MO_8, true); |
| 4254 | } |
| 4255 | |
| 4256 | static bool trans_STLEXH(DisasContext *s, arg_STREX *a) |
| 4257 | { |
| 4258 | if (!ENABLE_ARCH_8) { |
| 4259 | return false; |
| 4260 | } |
| 4261 | return op_strex(s, a, MO_16, true); |
| 4262 | } |
| 4263 | |
| 4264 | static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop) |
| 4265 | { |
| 4266 | TCGv_i32 addr, tmp; |
| 4267 | |
| 4268 | if (!ENABLE_ARCH_8) { |
| 4269 | return false; |
| 4270 | } |
| 4271 | /* We UNDEF for these UNPREDICTABLE cases. */ |
| 4272 | if (a->rn == 15 || a->rt == 15) { |
| 4273 | unallocated_encoding(s); |
| 4274 | return true; |
| 4275 | } |
| 4276 | |
| 4277 | addr = load_reg(s, a->rn); |
| 4278 | tmp = load_reg(s, a->rt); |
| 4279 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); |
| 4280 | gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN); |
| 4281 | disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); |
| 4282 | |
| 4283 | return true; |
| 4284 | } |
| 4285 | |
| 4286 | static bool trans_STL(DisasContext *s, arg_STL *a) |
| 4287 | { |
| 4288 | return op_stl(s, a, MO_UL); |
| 4289 | } |
| 4290 | |
| 4291 | static bool trans_STLB(DisasContext *s, arg_STL *a) |
| 4292 | { |
| 4293 | return op_stl(s, a, MO_UB); |
| 4294 | } |
| 4295 | |
| 4296 | static bool trans_STLH(DisasContext *s, arg_STL *a) |
| 4297 | { |
| 4298 | return op_stl(s, a, MO_UW); |
| 4299 | } |
| 4300 | |
| 4301 | static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq) |
| 4302 | { |
| 4303 | TCGv_i32 addr; |
| 4304 | /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */ |
| 4305 | bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M); |
| 4306 | |
| 4307 | /* We UNDEF for these UNPREDICTABLE cases. */ |
| 4308 | if (a->rn == 15 || a->rt == 15 |
| 4309 | || (!v8a && s->thumb && a->rt == 13) |
| 4310 | || (mop == MO_64 |
| 4311 | && (a->rt2 == 15 || a->rt == a->rt2 |
| 4312 | || (!v8a && s->thumb && a->rt2 == 13)))) { |
| 4313 | unallocated_encoding(s); |
| 4314 | return true; |
| 4315 | } |
| 4316 | |
| 4317 | addr = tcg_temp_new_i32(); |
| 4318 | load_reg_var(s, addr, a->rn); |
| 4319 | tcg_gen_addi_i32(addr, addr, a->imm); |
| 4320 | |
| 4321 | gen_load_exclusive(s, a->rt, a->rt2, addr, mop); |
| 4322 | |
| 4323 | if (acq) { |
| 4324 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); |
| 4325 | } |
| 4326 | return true; |
| 4327 | } |
| 4328 | |
| 4329 | static bool trans_LDREX(DisasContext *s, arg_LDREX *a) |
| 4330 | { |
| 4331 | if (!ENABLE_ARCH_6) { |
| 4332 | return false; |
| 4333 | } |
| 4334 | return op_ldrex(s, a, MO_32, false); |
| 4335 | } |
| 4336 | |
| 4337 | static bool trans_LDREXD_a32(DisasContext *s, arg_LDREX *a) |
| 4338 | { |
| 4339 | if (!ENABLE_ARCH_6K) { |
| 4340 | return false; |
| 4341 | } |
| 4342 | /* We UNDEF for these UNPREDICTABLE cases. */ |
| 4343 | if (a->rt & 1) { |
| 4344 | unallocated_encoding(s); |
| 4345 | return true; |
| 4346 | } |
| 4347 | a->rt2 = a->rt + 1; |
| 4348 | return op_ldrex(s, a, MO_64, false); |
| 4349 | } |
| 4350 | |
| 4351 | static bool trans_LDREXD_t32(DisasContext *s, arg_LDREX *a) |
| 4352 | { |
| 4353 | return op_ldrex(s, a, MO_64, false); |
| 4354 | } |
| 4355 | |
| 4356 | static bool trans_LDREXB(DisasContext *s, arg_LDREX *a) |
| 4357 | { |
| 4358 | if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { |
| 4359 | return false; |
| 4360 | } |
| 4361 | return op_ldrex(s, a, MO_8, false); |
| 4362 | } |
| 4363 | |
| 4364 | static bool trans_LDREXH(DisasContext *s, arg_LDREX *a) |
| 4365 | { |
| 4366 | if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { |
| 4367 | return false; |
| 4368 | } |
| 4369 | return op_ldrex(s, a, MO_16, false); |
| 4370 | } |
| 4371 | |
| 4372 | static bool trans_LDAEX(DisasContext *s, arg_LDREX *a) |
| 4373 | { |
| 4374 | if (!ENABLE_ARCH_8) { |
| 4375 | return false; |
| 4376 | } |
| 4377 | return op_ldrex(s, a, MO_32, true); |
| 4378 | } |
| 4379 | |
| 4380 | static bool trans_LDAEXD_a32(DisasContext *s, arg_LDREX *a) |
| 4381 | { |
| 4382 | if (!ENABLE_ARCH_8) { |
| 4383 | return false; |
| 4384 | } |
| 4385 | /* We UNDEF for these UNPREDICTABLE cases. */ |
| 4386 | if (a->rt & 1) { |
| 4387 | unallocated_encoding(s); |
| 4388 | return true; |
| 4389 | } |
| 4390 | a->rt2 = a->rt + 1; |
| 4391 | return op_ldrex(s, a, MO_64, true); |
| 4392 | } |
| 4393 | |
| 4394 | static bool trans_LDAEXD_t32(DisasContext *s, arg_LDREX *a) |
| 4395 | { |
| 4396 | if (!ENABLE_ARCH_8) { |
| 4397 | return false; |
| 4398 | } |
| 4399 | return op_ldrex(s, a, MO_64, true); |
| 4400 | } |
| 4401 | |
| 4402 | static bool trans_LDAEXB(DisasContext *s, arg_LDREX *a) |
| 4403 | { |
| 4404 | if (!ENABLE_ARCH_8) { |
| 4405 | return false; |
| 4406 | } |
| 4407 | return op_ldrex(s, a, MO_8, true); |
| 4408 | } |
| 4409 | |
| 4410 | static bool trans_LDAEXH(DisasContext *s, arg_LDREX *a) |
| 4411 | { |
| 4412 | if (!ENABLE_ARCH_8) { |
| 4413 | return false; |
| 4414 | } |
| 4415 | return op_ldrex(s, a, MO_16, true); |
| 4416 | } |
| 4417 | |
| 4418 | static bool op_lda(DisasContext *s, arg_LDA *a, MemOp mop) |
| 4419 | { |
| 4420 | TCGv_i32 addr, tmp; |
| 4421 | |
| 4422 | if (!ENABLE_ARCH_8) { |
| 4423 | return false; |
| 4424 | } |
| 4425 | /* We UNDEF for these UNPREDICTABLE cases. */ |
| 4426 | if (a->rn == 15 || a->rt == 15) { |
| 4427 | unallocated_encoding(s); |
| 4428 | return true; |
| 4429 | } |
| 4430 | |
| 4431 | addr = load_reg(s, a->rn); |
| 4432 | tmp = tcg_temp_new_i32(); |
| 4433 | gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN); |
| 4434 | disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); |
| 4435 | |
| 4436 | store_reg(s, a->rt, tmp); |
| 4437 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); |
| 4438 | return true; |
| 4439 | } |
| 4440 | |
| 4441 | static bool trans_LDA(DisasContext *s, arg_LDA *a) |
| 4442 | { |
| 4443 | return op_lda(s, a, MO_UL); |
| 4444 | } |
| 4445 | |
| 4446 | static bool trans_LDAB(DisasContext *s, arg_LDA *a) |
| 4447 | { |
| 4448 | return op_lda(s, a, MO_UB); |
| 4449 | } |
| 4450 | |
| 4451 | static bool trans_LDAH(DisasContext *s, arg_LDA *a) |
| 4452 | { |
| 4453 | return op_lda(s, a, MO_UW); |
| 4454 | } |
| 4455 | |
| 4456 | /* |
| 4457 | * Media instructions |
| 4458 | */ |
| 4459 | |
| 4460 | static bool trans_USADA8(DisasContext *s, arg_USADA8 *a) |
| 4461 | { |
| 4462 | TCGv_i32 t1, t2; |
| 4463 | |
| 4464 | if (!ENABLE_ARCH_6) { |
| 4465 | return false; |
| 4466 | } |
| 4467 | |
| 4468 | t1 = load_reg(s, a->rn); |
| 4469 | t2 = load_reg(s, a->rm); |
| 4470 | gen_helper_usad8(t1, t1, t2); |
| 4471 | if (a->ra != 15) { |
| 4472 | t2 = load_reg(s, a->ra); |
| 4473 | tcg_gen_add_i32(t1, t1, t2); |
| 4474 | } |
| 4475 | store_reg(s, a->rd, t1); |
| 4476 | return true; |
| 4477 | } |
| 4478 | |
| 4479 | static bool op_bfx(DisasContext *s, arg_UBFX *a, bool u) |
| 4480 | { |
| 4481 | TCGv_i32 tmp; |
| 4482 | int width = a->widthm1 + 1; |
| 4483 | int shift = a->lsb; |
| 4484 | |
| 4485 | if (!ENABLE_ARCH_6T2) { |
| 4486 | return false; |
| 4487 | } |
| 4488 | if (shift + width > 32) { |
| 4489 | /* UNPREDICTABLE; we choose to UNDEF */ |
| 4490 | unallocated_encoding(s); |
| 4491 | return true; |
| 4492 | } |
| 4493 | |
| 4494 | tmp = load_reg(s, a->rn); |
| 4495 | if (u) { |
| 4496 | tcg_gen_extract_i32(tmp, tmp, shift, width); |
| 4497 | } else { |
| 4498 | tcg_gen_sextract_i32(tmp, tmp, shift, width); |
| 4499 | } |
| 4500 | store_reg(s, a->rd, tmp); |
| 4501 | return true; |
| 4502 | } |
| 4503 | |
| 4504 | static bool trans_SBFX(DisasContext *s, arg_SBFX *a) |
| 4505 | { |
| 4506 | return op_bfx(s, a, false); |
| 4507 | } |
| 4508 | |
| 4509 | static bool trans_UBFX(DisasContext *s, arg_UBFX *a) |
| 4510 | { |
| 4511 | return op_bfx(s, a, true); |
| 4512 | } |
| 4513 | |
| 4514 | static bool trans_BFCI(DisasContext *s, arg_BFCI *a) |
| 4515 | { |
| 4516 | int msb = a->msb, lsb = a->lsb; |
| 4517 | TCGv_i32 t_in, t_rd; |
| 4518 | int width; |
| 4519 | |
| 4520 | if (!ENABLE_ARCH_6T2) { |
| 4521 | return false; |
| 4522 | } |
| 4523 | if (msb < lsb) { |
| 4524 | /* UNPREDICTABLE; we choose to UNDEF */ |
| 4525 | unallocated_encoding(s); |
| 4526 | return true; |
| 4527 | } |
| 4528 | |
| 4529 | width = msb + 1 - lsb; |
| 4530 | if (a->rn == 15) { |
| 4531 | /* BFC */ |
| 4532 | t_in = tcg_constant_i32(0); |
| 4533 | } else { |
| 4534 | /* BFI */ |
| 4535 | t_in = load_reg(s, a->rn); |
| 4536 | } |
| 4537 | t_rd = load_reg(s, a->rd); |
| 4538 | tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width); |
| 4539 | store_reg(s, a->rd, t_rd); |
| 4540 | return true; |
| 4541 | } |
| 4542 | |
| 4543 | static bool trans_UDF(DisasContext *s, arg_UDF *a) |
| 4544 | { |
| 4545 | unallocated_encoding(s); |
| 4546 | return true; |
| 4547 | } |
| 4548 | |
| 4549 | /* |
| 4550 | * Parallel addition and subtraction |
| 4551 | */ |
| 4552 | |
| 4553 | static bool op_par_addsub(DisasContext *s, arg_rrr *a, |
| 4554 | void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) |
| 4555 | { |
| 4556 | TCGv_i32 t0, t1; |
| 4557 | |
| 4558 | if (s->thumb |
| 4559 | ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) |
| 4560 | : !ENABLE_ARCH_6) { |
| 4561 | return false; |
| 4562 | } |
| 4563 | |
| 4564 | t0 = load_reg(s, a->rn); |
| 4565 | t1 = load_reg(s, a->rm); |
| 4566 | |
| 4567 | gen(t0, t0, t1); |
| 4568 | |
| 4569 | store_reg(s, a->rd, t0); |
| 4570 | return true; |
| 4571 | } |
| 4572 | |
| 4573 | static bool op_par_addsub_ge(DisasContext *s, arg_rrr *a, |
| 4574 | void (*gen)(TCGv_i32, TCGv_i32, |
| 4575 | TCGv_i32, TCGv_ptr)) |
| 4576 | { |
| 4577 | TCGv_i32 t0, t1; |
| 4578 | TCGv_ptr ge; |
| 4579 | |
| 4580 | if (s->thumb |
| 4581 | ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) |
| 4582 | : !ENABLE_ARCH_6) { |
| 4583 | return false; |
| 4584 | } |
| 4585 | |
| 4586 | t0 = load_reg(s, a->rn); |
| 4587 | t1 = load_reg(s, a->rm); |
| 4588 | |
| 4589 | ge = tcg_temp_new_ptr(); |
| 4590 | tcg_gen_addi_ptr(ge, tcg_env, offsetof(CPUARMState, GE)); |
| 4591 | gen(t0, t0, t1, ge); |
| 4592 | |
| 4593 | store_reg(s, a->rd, t0); |
| 4594 | return true; |
| 4595 | } |
| 4596 | |
| 4597 | #define DO_PAR_ADDSUB(NAME, helper) \ |
| 4598 | static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ |
| 4599 | { \ |
| 4600 | return op_par_addsub(s, a, helper); \ |
| 4601 | } |
| 4602 | |
| 4603 | #define DO_PAR_ADDSUB_GE(NAME, helper) \ |
| 4604 | static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ |
| 4605 | { \ |
| 4606 | return op_par_addsub_ge(s, a, helper); \ |
| 4607 | } |
| 4608 | |
| 4609 | DO_PAR_ADDSUB_GE(SADD16, gen_helper_sadd16) |
| 4610 | DO_PAR_ADDSUB_GE(SASX, gen_helper_saddsubx) |
| 4611 | DO_PAR_ADDSUB_GE(SSAX, gen_helper_ssubaddx) |
| 4612 | DO_PAR_ADDSUB_GE(SSUB16, gen_helper_ssub16) |
| 4613 | DO_PAR_ADDSUB_GE(SADD8, gen_helper_sadd8) |
| 4614 | DO_PAR_ADDSUB_GE(SSUB8, gen_helper_ssub8) |
| 4615 | |
| 4616 | DO_PAR_ADDSUB_GE(UADD16, gen_helper_uadd16) |
| 4617 | DO_PAR_ADDSUB_GE(UASX, gen_helper_uaddsubx) |
| 4618 | DO_PAR_ADDSUB_GE(USAX, gen_helper_usubaddx) |
| 4619 | DO_PAR_ADDSUB_GE(USUB16, gen_helper_usub16) |
| 4620 | DO_PAR_ADDSUB_GE(UADD8, gen_helper_uadd8) |
| 4621 | DO_PAR_ADDSUB_GE(USUB8, gen_helper_usub8) |
| 4622 | |
| 4623 | DO_PAR_ADDSUB(QADD16, gen_helper_qadd16) |
| 4624 | DO_PAR_ADDSUB(QASX, gen_helper_qaddsubx) |
| 4625 | DO_PAR_ADDSUB(QSAX, gen_helper_qsubaddx) |
| 4626 | DO_PAR_ADDSUB(QSUB16, gen_helper_qsub16) |
| 4627 | DO_PAR_ADDSUB(QADD8, gen_helper_qadd8) |
| 4628 | DO_PAR_ADDSUB(QSUB8, gen_helper_qsub8) |
| 4629 | |
| 4630 | DO_PAR_ADDSUB(UQADD16, gen_helper_uqadd16) |
| 4631 | DO_PAR_ADDSUB(UQASX, gen_helper_uqaddsubx) |
| 4632 | DO_PAR_ADDSUB(UQSAX, gen_helper_uqsubaddx) |
| 4633 | DO_PAR_ADDSUB(UQSUB16, gen_helper_uqsub16) |
| 4634 | DO_PAR_ADDSUB(UQADD8, gen_helper_uqadd8) |
| 4635 | DO_PAR_ADDSUB(UQSUB8, gen_helper_uqsub8) |
| 4636 | |
| 4637 | DO_PAR_ADDSUB(SHADD16, gen_helper_shadd16) |
| 4638 | DO_PAR_ADDSUB(SHASX, gen_helper_shaddsubx) |
| 4639 | DO_PAR_ADDSUB(SHSAX, gen_helper_shsubaddx) |
| 4640 | DO_PAR_ADDSUB(SHSUB16, gen_helper_shsub16) |
| 4641 | DO_PAR_ADDSUB(SHADD8, gen_helper_shadd8) |
| 4642 | DO_PAR_ADDSUB(SHSUB8, gen_helper_shsub8) |
| 4643 | |
| 4644 | DO_PAR_ADDSUB(UHADD16, gen_helper_uhadd16) |
| 4645 | DO_PAR_ADDSUB(UHASX, gen_helper_uhaddsubx) |
| 4646 | DO_PAR_ADDSUB(UHSAX, gen_helper_uhsubaddx) |
| 4647 | DO_PAR_ADDSUB(UHSUB16, gen_helper_uhsub16) |
| 4648 | DO_PAR_ADDSUB(UHADD8, gen_helper_uhadd8) |
| 4649 | DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8) |
| 4650 | |
| 4651 | #undef DO_PAR_ADDSUB |
| 4652 | #undef DO_PAR_ADDSUB_GE |
| 4653 | |
| 4654 | /* |
| 4655 | * Packing, unpacking, saturation, and reversal |
| 4656 | */ |
| 4657 | |
| 4658 | static bool trans_PKH(DisasContext *s, arg_PKH *a) |
| 4659 | { |
| 4660 | TCGv_i32 tn, tm; |
| 4661 | int shift = a->imm; |
| 4662 | |
| 4663 | if (s->thumb |
| 4664 | ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) |
| 4665 | : !ENABLE_ARCH_6) { |
| 4666 | return false; |
| 4667 | } |
| 4668 | |
| 4669 | tn = load_reg(s, a->rn); |
| 4670 | tm = load_reg(s, a->rm); |
| 4671 | if (a->tb) { |
| 4672 | /* PKHTB */ |
| 4673 | if (shift == 0) { |
| 4674 | shift = 31; |
| 4675 | } |
| 4676 | tcg_gen_sari_i32(tm, tm, shift); |
| 4677 | tcg_gen_deposit_i32(tn, tn, tm, 0, 16); |
| 4678 | } else { |
| 4679 | /* PKHBT */ |
| 4680 | tcg_gen_shli_i32(tm, tm, shift); |
| 4681 | tcg_gen_deposit_i32(tn, tm, tn, 0, 16); |
| 4682 | } |
| 4683 | store_reg(s, a->rd, tn); |
| 4684 | return true; |
| 4685 | } |
| 4686 | |
| 4687 | static bool op_sat(DisasContext *s, arg_sat *a, |
| 4688 | void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) |
| 4689 | { |
| 4690 | TCGv_i32 tmp; |
| 4691 | int shift = a->imm; |
| 4692 | |
| 4693 | if (!ENABLE_ARCH_6) { |
| 4694 | return false; |
| 4695 | } |
| 4696 | |
| 4697 | tmp = load_reg(s, a->rn); |
| 4698 | if (a->sh) { |
| 4699 | tcg_gen_sari_i32(tmp, tmp, shift ? shift : 31); |
| 4700 | } else { |
| 4701 | tcg_gen_shli_i32(tmp, tmp, shift); |
| 4702 | } |
| 4703 | |
| 4704 | gen(tmp, tcg_env, tmp, tcg_constant_i32(a->satimm)); |
| 4705 | |
| 4706 | store_reg(s, a->rd, tmp); |
| 4707 | return true; |
| 4708 | } |
| 4709 | |
| 4710 | static bool trans_SSAT(DisasContext *s, arg_sat *a) |
| 4711 | { |
| 4712 | return op_sat(s, a, gen_helper_ssat); |
| 4713 | } |
| 4714 | |
| 4715 | static bool trans_USAT(DisasContext *s, arg_sat *a) |
| 4716 | { |
| 4717 | return op_sat(s, a, gen_helper_usat); |
| 4718 | } |
| 4719 | |
| 4720 | static bool trans_SSAT16(DisasContext *s, arg_sat *a) |
| 4721 | { |
| 4722 | if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { |
| 4723 | return false; |
| 4724 | } |
| 4725 | return op_sat(s, a, gen_helper_ssat16); |
| 4726 | } |
| 4727 | |
| 4728 | static bool trans_USAT16(DisasContext *s, arg_sat *a) |
| 4729 | { |
| 4730 | if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { |
| 4731 | return false; |
| 4732 | } |
| 4733 | return op_sat(s, a, gen_helper_usat16); |
| 4734 | } |
| 4735 | |
| 4736 | static bool op_xta(DisasContext *s, arg_rrr_rot *a, |
| 4737 | void (*gen_extract)(TCGv_i32, TCGv_i32), |
| 4738 | void (*gen_add)(TCGv_i32, TCGv_i32, TCGv_i32)) |
| 4739 | { |
| 4740 | TCGv_i32 tmp; |
| 4741 | |
| 4742 | if (!ENABLE_ARCH_6) { |
| 4743 | return false; |
| 4744 | } |
| 4745 | |
| 4746 | tmp = load_reg(s, a->rm); |
| 4747 | /* |
| 4748 | * TODO: In many cases we could do a shift instead of a rotate. |
| 4749 | * Combined with a simple extend, that becomes an extract. |
| 4750 | */ |
| 4751 | tcg_gen_rotri_i32(tmp, tmp, a->rot * 8); |
| 4752 | gen_extract(tmp, tmp); |
| 4753 | |
| 4754 | if (a->rn != 15) { |
| 4755 | TCGv_i32 tmp2 = load_reg(s, a->rn); |
| 4756 | gen_add(tmp, tmp, tmp2); |
| 4757 | } |
| 4758 | store_reg(s, a->rd, tmp); |
| 4759 | return true; |
| 4760 | } |
| 4761 | |
| 4762 | static bool trans_SXTAB(DisasContext *s, arg_rrr_rot *a) |
| 4763 | { |
| 4764 | return op_xta(s, a, tcg_gen_ext8s_i32, tcg_gen_add_i32); |
| 4765 | } |
| 4766 | |
| 4767 | static bool trans_SXTAH(DisasContext *s, arg_rrr_rot *a) |
| 4768 | { |
| 4769 | return op_xta(s, a, tcg_gen_ext16s_i32, tcg_gen_add_i32); |
| 4770 | } |
| 4771 | |
| 4772 | static bool trans_SXTAB16(DisasContext *s, arg_rrr_rot *a) |
| 4773 | { |
| 4774 | if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { |
| 4775 | return false; |
| 4776 | } |
| 4777 | return op_xta(s, a, gen_helper_sxtb16, gen_add16); |
| 4778 | } |
| 4779 | |
| 4780 | static bool trans_UXTAB(DisasContext *s, arg_rrr_rot *a) |
| 4781 | { |
| 4782 | return op_xta(s, a, tcg_gen_ext8u_i32, tcg_gen_add_i32); |
| 4783 | } |
| 4784 | |
| 4785 | static bool trans_UXTAH(DisasContext *s, arg_rrr_rot *a) |
| 4786 | { |
| 4787 | return op_xta(s, a, tcg_gen_ext16u_i32, tcg_gen_add_i32); |
| 4788 | } |
| 4789 | |
| 4790 | static bool trans_UXTAB16(DisasContext *s, arg_rrr_rot *a) |
| 4791 | { |
| 4792 | if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { |
| 4793 | return false; |
| 4794 | } |
| 4795 | return op_xta(s, a, gen_helper_uxtb16, gen_add16); |
| 4796 | } |
| 4797 | |
| 4798 | static bool trans_SEL(DisasContext *s, arg_rrr *a) |
| 4799 | { |
| 4800 | TCGv_i32 t1, t2, t3; |
| 4801 | |
| 4802 | if (s->thumb |
| 4803 | ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) |
| 4804 | : !ENABLE_ARCH_6) { |
| 4805 | return false; |
| 4806 | } |
| 4807 | |
| 4808 | t1 = load_reg(s, a->rn); |
| 4809 | t2 = load_reg(s, a->rm); |
| 4810 | t3 = tcg_temp_new_i32(); |
| 4811 | tcg_gen_ld_i32(t3, tcg_env, offsetof(CPUARMState, GE)); |
| 4812 | gen_helper_sel_flags(t1, t3, t1, t2); |
| 4813 | store_reg(s, a->rd, t1); |
| 4814 | return true; |
| 4815 | } |
| 4816 | |
| 4817 | static bool op_rr(DisasContext *s, arg_rr *a, |
| 4818 | void (*gen)(TCGv_i32, TCGv_i32)) |
| 4819 | { |
| 4820 | TCGv_i32 tmp; |
| 4821 | |
| 4822 | tmp = load_reg(s, a->rm); |
| 4823 | gen(tmp, tmp); |
| 4824 | store_reg(s, a->rd, tmp); |
| 4825 | return true; |
| 4826 | } |
| 4827 | |
| 4828 | static bool trans_REV(DisasContext *s, arg_rr *a) |
| 4829 | { |
| 4830 | if (!ENABLE_ARCH_6) { |
| 4831 | return false; |
| 4832 | } |
| 4833 | return op_rr(s, a, tcg_gen_bswap32_i32); |
| 4834 | } |
| 4835 | |
| 4836 | static bool trans_REV16(DisasContext *s, arg_rr *a) |
| 4837 | { |
| 4838 | if (!ENABLE_ARCH_6) { |
| 4839 | return false; |
| 4840 | } |
| 4841 | return op_rr(s, a, gen_rev16); |
| 4842 | } |
| 4843 | |
| 4844 | static bool trans_REVSH(DisasContext *s, arg_rr *a) |
| 4845 | { |
| 4846 | if (!ENABLE_ARCH_6) { |
| 4847 | return false; |
| 4848 | } |
| 4849 | return op_rr(s, a, gen_revsh); |
| 4850 | } |
| 4851 | |
| 4852 | static bool trans_RBIT(DisasContext *s, arg_rr *a) |
| 4853 | { |
| 4854 | if (!ENABLE_ARCH_6T2) { |
| 4855 | return false; |
| 4856 | } |
| 4857 | return op_rr(s, a, tcg_gen_revbit32_i32); |
| 4858 | } |
| 4859 | |
| 4860 | /* |
| 4861 | * Signed multiply, signed and unsigned divide |
| 4862 | */ |
| 4863 | |
| 4864 | static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) |
| 4865 | { |
| 4866 | TCGv_i32 t1, t2; |
| 4867 | |
| 4868 | if (!ENABLE_ARCH_6) { |
| 4869 | return false; |
| 4870 | } |
| 4871 | |
| 4872 | t1 = load_reg(s, a->rn); |
| 4873 | t2 = load_reg(s, a->rm); |
| 4874 | if (m_swap) { |
| 4875 | gen_swap_half(t2, t2); |
| 4876 | } |
| 4877 | gen_smul_dual(t1, t2); |
| 4878 | |
| 4879 | if (sub) { |
| 4880 | /* |
| 4881 | * This subtraction cannot overflow, so we can do a simple |
| 4882 | * 32-bit subtraction and then a possible 32-bit saturating |
| 4883 | * addition of Ra. |
| 4884 | */ |
| 4885 | tcg_gen_sub_i32(t1, t1, t2); |
| 4886 | |
| 4887 | if (a->ra != 15) { |
| 4888 | t2 = load_reg(s, a->ra); |
| 4889 | gen_helper_add_setq(t1, tcg_env, t1, t2); |
| 4890 | } |
| 4891 | } else if (a->ra == 15) { |
| 4892 | /* Single saturation-checking addition */ |
| 4893 | gen_helper_add_setq(t1, tcg_env, t1, t2); |
| 4894 | } else { |
| 4895 | /* |
| 4896 | * We need to add the products and Ra together and then |
| 4897 | * determine whether the final result overflowed. Doing |
| 4898 | * this as two separate add-and-check-overflow steps incorrectly |
| 4899 | * sets Q for cases like (-32768 * -32768) + (-32768 * -32768) + -1. |
| 4900 | * Do all the arithmetic at 64-bits and then check for overflow. |
| 4901 | */ |
| 4902 | TCGv_i64 p64, q64; |
| 4903 | TCGv_i32 t3, qf, one; |
| 4904 | |
| 4905 | p64 = tcg_temp_new_i64(); |
| 4906 | q64 = tcg_temp_new_i64(); |
| 4907 | tcg_gen_ext_i32_i64(p64, t1); |
| 4908 | tcg_gen_ext_i32_i64(q64, t2); |
| 4909 | tcg_gen_add_i64(p64, p64, q64); |
| 4910 | load_reg_var(s, t2, a->ra); |
| 4911 | tcg_gen_ext_i32_i64(q64, t2); |
| 4912 | tcg_gen_add_i64(p64, p64, q64); |
| 4913 | |
| 4914 | tcg_gen_extr_i64_i32(t1, t2, p64); |
| 4915 | /* |
| 4916 | * t1 is the low half of the result which goes into Rd. |
| 4917 | * We have overflow and must set Q if the high half (t2) |
| 4918 | * is different from the sign-extension of t1. |
| 4919 | */ |
| 4920 | t3 = tcg_temp_new_i32(); |
| 4921 | tcg_gen_sari_i32(t3, t1, 31); |
| 4922 | qf = load_cpu_field(QF); |
| 4923 | one = tcg_constant_i32(1); |
| 4924 | tcg_gen_movcond_i32(TCG_COND_NE, qf, t2, t3, one, qf); |
| 4925 | store_cpu_field(qf, QF); |
| 4926 | } |
| 4927 | store_reg(s, a->rd, t1); |
| 4928 | return true; |
| 4929 | } |
| 4930 | |
| 4931 | static bool trans_SMLAD(DisasContext *s, arg_rrrr *a) |
| 4932 | { |
| 4933 | return op_smlad(s, a, false, false); |
| 4934 | } |
| 4935 | |
| 4936 | static bool trans_SMLADX(DisasContext *s, arg_rrrr *a) |
| 4937 | { |
| 4938 | return op_smlad(s, a, true, false); |
| 4939 | } |
| 4940 | |
| 4941 | static bool trans_SMLSD(DisasContext *s, arg_rrrr *a) |
| 4942 | { |
| 4943 | return op_smlad(s, a, false, true); |
| 4944 | } |
| 4945 | |
| 4946 | static bool trans_SMLSDX(DisasContext *s, arg_rrrr *a) |
| 4947 | { |
| 4948 | return op_smlad(s, a, true, true); |
| 4949 | } |
| 4950 | |
| 4951 | static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) |
| 4952 | { |
| 4953 | TCGv_i32 t1, t2; |
| 4954 | TCGv_i64 l1, l2; |
| 4955 | |
| 4956 | if (!ENABLE_ARCH_6) { |
| 4957 | return false; |
| 4958 | } |
| 4959 | |
| 4960 | t1 = load_reg(s, a->rn); |
| 4961 | t2 = load_reg(s, a->rm); |
| 4962 | if (m_swap) { |
| 4963 | gen_swap_half(t2, t2); |
| 4964 | } |
| 4965 | gen_smul_dual(t1, t2); |
| 4966 | |
| 4967 | l1 = tcg_temp_new_i64(); |
| 4968 | l2 = tcg_temp_new_i64(); |
| 4969 | tcg_gen_ext_i32_i64(l1, t1); |
| 4970 | tcg_gen_ext_i32_i64(l2, t2); |
| 4971 | |
| 4972 | if (sub) { |
| 4973 | tcg_gen_sub_i64(l1, l1, l2); |
| 4974 | } else { |
| 4975 | tcg_gen_add_i64(l1, l1, l2); |
| 4976 | } |
| 4977 | |
| 4978 | gen_addq(s, l1, a->ra, a->rd); |
| 4979 | gen_storeq_reg(s, a->ra, a->rd, l1); |
| 4980 | return true; |
| 4981 | } |
| 4982 | |
| 4983 | static bool trans_SMLALD(DisasContext *s, arg_rrrr *a) |
| 4984 | { |
| 4985 | return op_smlald(s, a, false, false); |
| 4986 | } |
| 4987 | |
| 4988 | static bool trans_SMLALDX(DisasContext *s, arg_rrrr *a) |
| 4989 | { |
| 4990 | return op_smlald(s, a, true, false); |
| 4991 | } |
| 4992 | |
| 4993 | static bool trans_SMLSLD(DisasContext *s, arg_rrrr *a) |
| 4994 | { |
| 4995 | return op_smlald(s, a, false, true); |
| 4996 | } |
| 4997 | |
| 4998 | static bool trans_SMLSLDX(DisasContext *s, arg_rrrr *a) |
| 4999 | { |
| 5000 | return op_smlald(s, a, true, true); |
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