| 1 | #ifndef TARGET_ARM_TRANSLATE_H |
| 2 | #define TARGET_ARM_TRANSLATE_H |
| 3 | |
| 4 | #include "cpu.h" |
| 5 | #include "tcg/tcg-op-common.h" |
| 6 | #include "tcg/tcg-op-gvec-common.h" |
| 7 | #include "exec/translator.h" |
| 8 | #include "exec/translation-block.h" |
| 9 | #include "helper.h" |
| 10 | #include "internals.h" |
| 11 | #include "cpu-features.h" |
| 12 | |
| 13 | /* internal defines */ |
| 14 | |
| 15 | /* |
| 16 | * Save pc_save across a branch, so that we may restore the value from |
| 17 | * before the branch at the point the label is emitted. |
| 18 | */ |
| 19 | typedef struct DisasLabel { |
| 20 | TCGLabel *label; |
| 21 | vaddr pc_save; |
| 22 | } DisasLabel; |
| 23 | |
| 24 | /* |
| 25 | * Emit an exception call out of line. |
| 26 | */ |
| 27 | typedef struct DisasDelayException { |
| 28 | struct DisasDelayException *next; |
| 29 | TCGLabel *lab; |
| 30 | vaddr pc_curr; |
| 31 | vaddr pc_save; |
| 32 | int condexec_mask; |
| 33 | int condexec_cond; |
| 34 | uint32_t excp; |
| 35 | uint32_t syn; |
| 36 | uint32_t target_el; |
| 37 | } DisasDelayException; |
| 38 | |
| 39 | typedef struct DisasContext { |
| 40 | DisasContextBase base; |
| 41 | const ARMISARegisters *isar; |
| 42 | DisasDelayException *delay_excp_list; |
| 43 | |
| 44 | /* The address of the current instruction being translated. */ |
| 45 | vaddr pc_curr; |
| 46 | /* |
| 47 | * For CF_PCREL, the full value of cpu_pc is not known |
| 48 | * (although the page offset is known). For convenience, the |
| 49 | * translation loop uses the full virtual address that triggered |
| 50 | * the translation, from base.pc_start through pc_curr. |
| 51 | * For efficiency, we do not update cpu_pc for every instruction. |
| 52 | * Instead, pc_save has the value of pc_curr at the time of the |
| 53 | * last update to cpu_pc, which allows us to compute the addend |
| 54 | * needed to bring cpu_pc current: pc_curr - pc_save. |
| 55 | * If cpu_pc now contains the destination of an indirect branch, |
| 56 | * pc_save contains -1 to indicate that relative updates are no |
| 57 | * longer possible. |
| 58 | */ |
| 59 | vaddr pc_save; |
| 60 | vaddr page_start; |
| 61 | uint32_t insn; |
| 62 | /* Nonzero if this instruction has been conditionally skipped. */ |
| 63 | int condjmp; |
| 64 | /* The label that will be jumped to when the instruction is skipped. */ |
| 65 | DisasLabel condlabel; |
| 66 | /* Thumb-2 conditional execution bits. */ |
| 67 | int condexec_mask; |
| 68 | int condexec_cond; |
| 69 | /* M-profile ECI/ICI exception-continuable instruction state */ |
| 70 | int eci; |
| 71 | /* |
| 72 | * trans_ functions for insns which are continuable should set this true |
| 73 | * after decode (ie after any UNDEF checks) |
| 74 | */ |
| 75 | bool eci_handled; |
| 76 | int sctlr_b; |
| 77 | MemOp be_data; |
| 78 | #if !defined(CONFIG_USER_ONLY) |
| 79 | int user; |
| 80 | #endif |
| 81 | ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ |
| 82 | uint8_t tbii; /* TBI1|TBI0 for insns */ |
| 83 | uint8_t tbid; /* TBI1|TBI0 for data */ |
| 84 | uint8_t tcma; /* TCMA1|TCMA0 for MTE */ |
| 85 | uint8_t mtx; /* MTX1|MTX0 for MTE */ |
| 86 | bool ns; /* Use non-secure CPREG bank on access */ |
| 87 | int fp_excp_el; /* FP exception EL or 0 if enabled */ |
| 88 | int sve_excp_el; /* SVE exception EL or 0 if enabled */ |
| 89 | int sme_excp_el; /* SME exception EL or 0 if enabled */ |
| 90 | int zt0_excp_el; /* ZT0 exception EL or 0 if enabled */ |
| 91 | int neon_excp_el; /* A32 Neon exception EL or 0 if enabled */ |
| 92 | int vl; /* current vector length in bytes */ |
| 93 | int svl; /* current streaming vector length in bytes */ |
| 94 | int max_svl; /* maximum implemented streaming vector length */ |
| 95 | int max_any_vl; /* maximum implemented vector length */ |
| 96 | bool vfp_enabled; /* FP enabled via FPSCR.EN */ |
| 97 | int invalid_vfp_dreg_mask; /* mask for whether VFP D16..D31 should UNDEF */ |
| 98 | int invalid_neon_dreg_mask; /* ditto, for Neon */ |
| 99 | int vec_len; |
| 100 | int vec_stride; |
| 101 | bool v7m_handler_mode; |
| 102 | bool v8m_secure; /* true if v8M and we're in Secure mode */ |
| 103 | bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */ |
| 104 | bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */ |
| 105 | bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */ |
| 106 | bool v7m_lspact; /* FPCCR.LSPACT set */ |
| 107 | /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI |
| 108 | * so that top level loop can generate correct syndrome information. |
| 109 | */ |
| 110 | uint32_t svc_imm; |
| 111 | int current_el; |
| 112 | GHashTable *cp_regs; |
| 113 | uint64_t features; /* CPU features bits */ |
| 114 | bool aarch64; |
| 115 | bool thumb; |
| 116 | bool lse2; |
| 117 | /* |
| 118 | * Because unallocated encodings generate different exception syndrome |
| 119 | * information from traps due to FP being disabled, we can't do a single |
| 120 | * "is fp access disabled" check at a high level in the decode tree. |
| 121 | * To help in catching bugs where the access check was forgotten in some |
| 122 | * code path, we set this flag when the access check is done, and assert |
| 123 | * that it is set at the point where we actually touch the FP regs. |
| 124 | * 0: not checked, |
| 125 | * 1: checked, access ok |
| 126 | * -1: checked, access denied |
| 127 | */ |
| 128 | int8_t fp_access_checked; |
| 129 | int8_t sve_access_checked; |
| 130 | /* ARMv8 single-step state (this is distinct from the QEMU gdbstub |
| 131 | * single-step support). |
| 132 | */ |
| 133 | bool ss_active; |
| 134 | bool pstate_ss; |
| 135 | /* True if the insn just emitted was a load-exclusive instruction |
| 136 | * (necessary for syndrome information for single step exceptions), |
| 137 | * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. |
| 138 | */ |
| 139 | bool is_ldex; |
| 140 | /* True if AccType_UNPRIV should be used for LDTR et al */ |
| 141 | bool unpriv; |
| 142 | /* True if v8.3-PAuth is active. */ |
| 143 | bool pauth_active; |
| 144 | /* True if v8.5-MTE access to tags is enabled; index with is_unpriv. */ |
| 145 | bool ata[2]; |
| 146 | /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */ |
| 147 | bool mte_active[2]; |
| 148 | /* True if v8.5-MTE tag checks disabled for reads; index with is_unpriv. */ |
| 149 | bool mte_store_only[2]; |
| 150 | /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ |
| 151 | bool bt; |
| 152 | /* True if any CP15 access is trapped by HSTR_EL2 */ |
| 153 | bool hstr_active; |
| 154 | /* True if memory operations require alignment */ |
| 155 | bool align_mem; |
| 156 | /* True if PSTATE.IL is set */ |
| 157 | bool pstate_il; |
| 158 | /* True if PSTATE.SM is set. */ |
| 159 | bool pstate_sm; |
| 160 | /* True if PSTATE.ZA is set. */ |
| 161 | bool pstate_za; |
| 162 | /* True if non-streaming insns should raise an SME Streaming exception. */ |
| 163 | bool sme_trap_nonstreaming; |
| 164 | /* True if the current instruction is non-streaming. */ |
| 165 | bool is_nonstreaming; |
| 166 | /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ |
| 167 | bool mve_no_pred; |
| 168 | /* True if fine-grained traps are active */ |
| 169 | bool fgt_active; |
| 170 | /* True if fine-grained trap on SVC is enabled */ |
| 171 | bool fgt_svc; |
| 172 | /* True if a trap on ERET is enabled (FGT or NV) */ |
| 173 | bool trap_eret; |
| 174 | /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */ |
| 175 | bool naa; |
| 176 | /* True if HCR_EL2.E2H is set */ |
| 177 | bool e2h; |
| 178 | /* True if FEAT_NV HCR_EL2.NV is enabled */ |
| 179 | bool nv; |
| 180 | /* True if NV enabled and HCR_EL2.NV1 is set */ |
| 181 | bool nv1; |
| 182 | /* True if NV enabled and HCR_EL2.NV2 is set */ |
| 183 | bool nv2; |
| 184 | /* True if NV2 enabled and NV2 RAM accesses use EL2&0 translation regime */ |
| 185 | bool nv2_mem_e20; |
| 186 | /* True if NV2 enabled and NV2 RAM accesses are big-endian */ |
| 187 | bool nv2_mem_be; |
| 188 | /* True if FPCR.AH is 1 (alternate floating point handling) */ |
| 189 | bool fpcr_ah; |
| 190 | /* True if FPCR.NEP is 1 (FEAT_AFP scalar upper-element result handling) */ |
| 191 | bool fpcr_nep; |
| 192 | /* True if GCSEnabled. */ |
| 193 | bool gcs_en; |
| 194 | /* True if GCSReturnValueCheckEnabled. */ |
| 195 | bool gcs_rvcen; |
| 196 | /* GCSSTR exception EL or 0 if enabled */ |
| 197 | uint8_t gcsstr_el; |
| 198 | /* |
| 199 | * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. |
| 200 | * < 0, set by the current instruction. |
| 201 | */ |
| 202 | int8_t btype; |
| 203 | /* A copy of DCZID_EL0.BS. */ |
| 204 | uint8_t dcz_blocksize; |
| 205 | /* A copy of cpu->gm_blocksize. */ |
| 206 | uint8_t gm_blocksize; |
| 207 | /* True if the current insn_start has been updated. */ |
| 208 | bool insn_start_updated; |
| 209 | /* FPMR access exception EL or 0 if enabled. */ |
| 210 | uint8_t fpmr_el; |
| 211 | /* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */ |
| 212 | uint32_t nv2_redirect_offset; |
| 213 | } DisasContext; |
| 214 | |
| 215 | typedef struct DisasCompare { |
| 216 | TCGCond cond; |
| 217 | TCGv_i32 value; |
| 218 | } DisasCompare; |
| 219 | |
| 220 | /* Share the TCG temporaries common between 32 and 64 bit modes. */ |
| 221 | extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; |
| 222 | extern TCGv_i64 cpu_exclusive_addr; |
| 223 | extern TCGv_i64 cpu_exclusive_val; |
| 224 | |
| 225 | /* |
| 226 | * Constant expanders for the decoders. |
| 227 | */ |
| 228 | |
| 229 | static inline int negate(DisasContext *s, int x) |
| 230 | { |
| 231 | return -x; |
| 232 | } |
| 233 | |
| 234 | static inline int plus_1(DisasContext *s, int x) |
| 235 | { |
| 236 | return x + 1; |
| 237 | } |
| 238 | |
| 239 | static inline int plus_2(DisasContext *s, int x) |
| 240 | { |
| 241 | return x + 2; |
| 242 | } |
| 243 | |
| 244 | static inline int plus_8(DisasContext *s, int x) |
| 245 | { |
| 246 | return x + 8; |
| 247 | } |
| 248 | |
| 249 | static inline int plus_12(DisasContext *s, int x) |
| 250 | { |
| 251 | return x + 12; |
| 252 | } |
| 253 | |
| 254 | static inline int times_2(DisasContext *s, int x) |
| 255 | { |
| 256 | return x * 2; |
| 257 | } |
| 258 | |
| 259 | static inline int times_4(DisasContext *s, int x) |
| 260 | { |
| 261 | return x * 4; |
| 262 | } |
| 263 | |
| 264 | static inline int times_8(DisasContext *s, int x) |
| 265 | { |
| 266 | return x * 8; |
| 267 | } |
| 268 | |
| 269 | static inline int times_2_plus_1(DisasContext *s, int x) |
| 270 | { |
| 271 | return x * 2 + 1; |
| 272 | } |
| 273 | |
| 274 | static inline int times_2_plus_16(DisasContext *s, int x) |
| 275 | { |
| 276 | return x * 2 + 16; |
| 277 | } |
| 278 | |
| 279 | static inline int rsub_64(DisasContext *s, int x) |
| 280 | { |
| 281 | return 64 - x; |
| 282 | } |
| 283 | |
| 284 | static inline int rsub_32(DisasContext *s, int x) |
| 285 | { |
| 286 | return 32 - x; |
| 287 | } |
| 288 | |
| 289 | static inline int rsub_16(DisasContext *s, int x) |
| 290 | { |
| 291 | return 16 - x; |
| 292 | } |
| 293 | |
| 294 | static inline int rsub_8(DisasContext *s, int x) |
| 295 | { |
| 296 | return 8 - x; |
| 297 | } |
| 298 | |
| 299 | static inline int shl_12(DisasContext *s, int x) |
| 300 | { |
| 301 | return x << 12; |
| 302 | } |
| 303 | |
| 304 | static inline int xor_2(DisasContext *s, int x) |
| 305 | { |
| 306 | return x ^ 2; |
| 307 | } |
| 308 | |
| 309 | static inline int neon_3same_fp_size(DisasContext *s, int x) |
| 310 | { |
| 311 | /* Convert 0==fp32, 1==fp16 into a MO_* value */ |
| 312 | return MO_32 - x; |
| 313 | } |
| 314 | |
| 315 | static inline int arm_dc_feature(DisasContext *dc, int feature) |
| 316 | { |
| 317 | return (dc->features & (1ULL << feature)) != 0; |
| 318 | } |
| 319 | |
| 320 | static inline int get_mem_index(DisasContext *s) |
| 321 | { |
| 322 | return arm_to_core_mmu_idx(s->mmu_idx); |
| 323 | } |
| 324 | |
| 325 | static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) |
| 326 | { |
| 327 | /* We don't need to save all of the syndrome so we mask and shift |
| 328 | * out unneeded bits to help the sleb128 encoder do a better job. |
| 329 | */ |
| 330 | syn &= ARM_INSN_START_WORD2_MASK; |
| 331 | syn >>= ARM_INSN_START_WORD2_SHIFT; |
| 332 | |
| 333 | /* Check for multiple updates. */ |
| 334 | assert(!s->insn_start_updated); |
| 335 | s->insn_start_updated = true; |
| 336 | tcg_set_insn_start_param(s->base.insn_start, 2, syn); |
| 337 | } |
| 338 | |
| 339 | static inline int curr_insn_len(DisasContext *s) |
| 340 | { |
| 341 | return s->base.pc_next - s->pc_curr; |
| 342 | } |
| 343 | |
| 344 | /* is_jmp field values */ |
| 345 | #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ |
| 346 | /* CPU state was modified dynamically; exit to main loop for interrupts. */ |
| 347 | #define DISAS_UPDATE_EXIT DISAS_TARGET_1 |
| 348 | /* These instructions trap after executing, so the A32/T32 decoder must |
| 349 | * defer them until after the conditional execution state has been updated. |
| 350 | * WFI also needs special handling when single-stepping. |
| 351 | */ |
| 352 | #define DISAS_WFI DISAS_TARGET_2 |
| 353 | #define DISAS_SWI DISAS_TARGET_3 |
| 354 | /* WFE */ |
| 355 | #define DISAS_WFE DISAS_TARGET_4 |
| 356 | #define DISAS_HVC DISAS_TARGET_5 |
| 357 | #define DISAS_SMC DISAS_TARGET_6 |
| 358 | #define DISAS_YIELD DISAS_TARGET_7 |
| 359 | /* M profile branch which might be an exception return (and so needs |
| 360 | * custom end-of-TB code) |
| 361 | */ |
| 362 | #define DISAS_BX_EXCRET DISAS_TARGET_8 |
| 363 | /* |
| 364 | * For instructions which want an immediate exit to the main loop, as opposed |
| 365 | * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this |
| 366 | * doesn't write the PC on exiting the translation loop so you need to ensure |
| 367 | * something (gen_a64_update_pc or runtime helper) has done so before we reach |
| 368 | * return from cpu_tb_exec. |
| 369 | */ |
| 370 | #define DISAS_EXIT DISAS_TARGET_9 |
| 371 | /* CPU state was modified dynamically; no need to exit, but do not chain. */ |
| 372 | #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10 |
| 373 | |
| 374 | void a64_translate_init(void); |
| 375 | void gen_a64_update_pc(DisasContext *s, int64_t diff); |
| 376 | extern const TranslatorOps aarch64_translator_ops; |
| 377 | |
| 378 | void arm_test_cc(DisasCompare *cmp, int cc); |
| 379 | void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); |
| 380 | void arm_gen_test_cc(int cc, TCGLabel *label); |
| 381 | MemOp pow2_align(unsigned i); |
| 382 | void unallocated_encoding(DisasContext *s); |
| 383 | void gen_exception_internal(int excp); |
| 384 | void gen_exception_insn_el(DisasContext *s, int64_t pc_diff, int excp, |
| 385 | uint32_t syn, uint32_t target_el); |
| 386 | void gen_exception_insn(DisasContext *s, int64_t pc_diff, |
| 387 | int excp, uint32_t syn); |
| 388 | TCGLabel *delay_exception_el(DisasContext *s, int excp, |
| 389 | uint32_t syn, uint32_t target_el); |
| 390 | TCGLabel *delay_exception(DisasContext *s, int excp, uint32_t syn); |
| 391 | void emit_delayed_exceptions(DisasContext *s); |
| 392 | |
| 393 | /* Return state of Alternate Half-precision flag, caller frees result */ |
| 394 | static inline TCGv_i32 get_ahp_flag(void) |
| 395 | { |
| 396 | TCGv_i32 ret = tcg_temp_new_i32(); |
| 397 | |
| 398 | tcg_gen_ld_i32(ret, tcg_env, offsetoflow32(CPUARMState, vfp.fpcr)); |
| 399 | tcg_gen_extract_i32(ret, ret, 26, 1); |
| 400 | |
| 401 | return ret; |
| 402 | } |
| 403 | |
| 404 | /* Set bits within PSTATE. */ |
| 405 | static inline void set_pstate_bits(uint64_t bits) |
| 406 | { |
| 407 | TCGv_i64 p = tcg_temp_new_i64(); |
| 408 | |
| 409 | tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); |
| 410 | |
| 411 | tcg_gen_ld_i64(p, tcg_env, offsetof(CPUARMState, pstate)); |
| 412 | tcg_gen_ori_i64(p, p, bits); |
| 413 | tcg_gen_st_i64(p, tcg_env, offsetof(CPUARMState, pstate)); |
| 414 | } |
| 415 | |
| 416 | /* Clear bits within PSTATE. */ |
| 417 | static inline void clear_pstate_bits(uint64_t bits) |
| 418 | { |
| 419 | TCGv_i64 p = tcg_temp_new_i64(); |
| 420 | |
| 421 | tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); |
| 422 | |
| 423 | tcg_gen_ld_i64(p, tcg_env, offsetof(CPUARMState, pstate)); |
| 424 | tcg_gen_andi_i64(p, p, ~bits); |
| 425 | tcg_gen_st_i64(p, tcg_env, offsetof(CPUARMState, pstate)); |
| 426 | } |
| 427 | |
| 428 | /* If the singlestep state is Active-not-pending, advance to Active-pending. */ |
| 429 | static inline void gen_ss_advance(DisasContext *s) |
| 430 | { |
| 431 | if (s->ss_active) { |
| 432 | s->pstate_ss = 0; |
| 433 | clear_pstate_bits(PSTATE_SS); |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | /* Generate an architectural singlestep exception */ |
| 438 | static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) |
| 439 | { |
| 440 | /* Fill in the same_el field of the syndrome in the helper. */ |
| 441 | uint32_t syn = syn_swstep(false, isv, ex); |
| 442 | gen_helper_exception_swstep(tcg_env, tcg_constant_i32(syn)); |
| 443 | } |
| 444 | |
| 445 | /* |
| 446 | * Given a VFP floating point constant encoded into an 8 bit immediate in an |
| 447 | * instruction, expand it to the actual constant value of the specified |
| 448 | * size, as per the VFPExpandImm() pseudocode in the Arm ARM. |
| 449 | */ |
| 450 | uint64_t vfp_expand_imm(int size, uint8_t imm8); |
| 451 | |
| 452 | static inline void gen_vfp_absh(TCGv_i32 d, TCGv_i32 s) |
| 453 | { |
| 454 | tcg_gen_andi_i32(d, s, INT16_MAX); |
| 455 | } |
| 456 | |
| 457 | static inline void gen_vfp_abss(TCGv_i32 d, TCGv_i32 s) |
| 458 | { |
| 459 | tcg_gen_andi_i32(d, s, INT32_MAX); |
| 460 | } |
| 461 | |
| 462 | static inline void gen_vfp_absd(TCGv_i64 d, TCGv_i64 s) |
| 463 | { |
| 464 | tcg_gen_andi_i64(d, s, INT64_MAX); |
| 465 | } |
| 466 | |
| 467 | static inline void gen_vfp_negh(TCGv_i32 d, TCGv_i32 s) |
| 468 | { |
| 469 | tcg_gen_xori_i32(d, s, 1u << 15); |
| 470 | } |
| 471 | |
| 472 | static inline void gen_vfp_negs(TCGv_i32 d, TCGv_i32 s) |
| 473 | { |
| 474 | tcg_gen_xori_i32(d, s, 1u << 31); |
| 475 | } |
| 476 | |
| 477 | static inline void gen_vfp_negd(TCGv_i64 d, TCGv_i64 s) |
| 478 | { |
| 479 | tcg_gen_xori_i64(d, s, 1ull << 63); |
| 480 | } |
| 481 | |
| 482 | /* Vector operations shared between ARM and AArch64. */ |
| 483 | void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 484 | uint32_t opr_sz, uint32_t max_sz); |
| 485 | void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 486 | uint32_t opr_sz, uint32_t max_sz); |
| 487 | void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 488 | uint32_t opr_sz, uint32_t max_sz); |
| 489 | void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 490 | uint32_t opr_sz, uint32_t max_sz); |
| 491 | void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 492 | uint32_t opr_sz, uint32_t max_sz); |
| 493 | |
| 494 | void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 495 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 496 | void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 497 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 498 | |
| 499 | void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 500 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 501 | void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 502 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 503 | void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 504 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 505 | void gen_gvec_srshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 506 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 507 | void gen_gvec_urshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 508 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 509 | void gen_neon_sqshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 510 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 511 | void gen_neon_uqshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 512 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 513 | void gen_neon_sqrshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 514 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 515 | void gen_neon_uqrshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 516 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 517 | |
| 518 | void gen_neon_sqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 519 | int64_t c, uint32_t opr_sz, uint32_t max_sz); |
| 520 | void gen_neon_uqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 521 | int64_t c, uint32_t opr_sz, uint32_t max_sz); |
| 522 | void gen_neon_sqshlui(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 523 | int64_t c, uint32_t opr_sz, uint32_t max_sz); |
| 524 | |
| 525 | void gen_gvec_shadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 526 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 527 | void gen_gvec_uhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 528 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 529 | void gen_gvec_shsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 530 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 531 | void gen_gvec_uhsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 532 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 533 | void gen_gvec_srhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 534 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 535 | void gen_gvec_urhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 536 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 537 | |
| 538 | void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); |
| 539 | void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); |
| 540 | void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); |
| 541 | void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); |
| 542 | void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); |
| 543 | |
| 544 | void gen_uqadd_bhs(TCGv_i64 res, TCGv_i64 qc, |
| 545 | TCGv_i64 a, TCGv_i64 b, MemOp esz); |
| 546 | void gen_uqadd_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); |
| 547 | void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 548 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 549 | |
| 550 | void gen_sqadd_bhs(TCGv_i64 res, TCGv_i64 qc, |
| 551 | TCGv_i64 a, TCGv_i64 b, MemOp esz); |
| 552 | void gen_sqadd_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); |
| 553 | void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 554 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 555 | |
| 556 | void gen_uqsub_bhs(TCGv_i64 res, TCGv_i64 qc, |
| 557 | TCGv_i64 a, TCGv_i64 b, MemOp esz); |
| 558 | void gen_uqsub_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); |
| 559 | void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 560 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 561 | |
| 562 | void gen_sqsub_bhs(TCGv_i64 res, TCGv_i64 qc, |
| 563 | TCGv_i64 a, TCGv_i64 b, MemOp esz); |
| 564 | void gen_sqsub_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); |
| 565 | void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 566 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 567 | |
| 568 | void gen_gvec_sshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 569 | int64_t shift, uint32_t opr_sz, uint32_t max_sz); |
| 570 | void gen_gvec_ushr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 571 | int64_t shift, uint32_t opr_sz, uint32_t max_sz); |
| 572 | |
| 573 | void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 574 | int64_t shift, uint32_t opr_sz, uint32_t max_sz); |
| 575 | void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 576 | int64_t shift, uint32_t opr_sz, uint32_t max_sz); |
| 577 | |
| 578 | void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh); |
| 579 | void gen_srshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh); |
| 580 | void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh); |
| 581 | void gen_urshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh); |
| 582 | |
| 583 | void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 584 | int64_t shift, uint32_t opr_sz, uint32_t max_sz); |
| 585 | void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 586 | int64_t shift, uint32_t opr_sz, uint32_t max_sz); |
| 587 | void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 588 | int64_t shift, uint32_t opr_sz, uint32_t max_sz); |
| 589 | void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 590 | int64_t shift, uint32_t opr_sz, uint32_t max_sz); |
| 591 | |
| 592 | void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 593 | int64_t shift, uint32_t opr_sz, uint32_t max_sz); |
| 594 | void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, |
| 595 | int64_t shift, uint32_t opr_sz, uint32_t max_sz); |
| 596 | |
| 597 | void gen_gvec_sqdmulh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 598 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 599 | void gen_gvec_sqrdmulh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 600 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 601 | void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 602 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 603 | void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 604 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 605 | |
| 606 | void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 607 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 608 | void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 609 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 610 | |
| 611 | void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 612 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 613 | void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 614 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 615 | |
| 616 | void gen_gvec_addp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 617 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 618 | void gen_gvec_smaxp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 619 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 620 | void gen_gvec_sminp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 621 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 622 | void gen_gvec_umaxp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 623 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 624 | void gen_gvec_uminp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 625 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
| 626 | |
| 627 | void gen_gvec_cls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 628 | uint32_t opr_sz, uint32_t max_sz); |
| 629 | void gen_gvec_clz(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 630 | uint32_t opr_sz, uint32_t max_sz); |
| 631 | void gen_gvec_cnt(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 632 | uint32_t opr_sz, uint32_t max_sz); |
| 633 | void gen_gvec_rbit(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 634 | uint32_t opr_sz, uint32_t max_sz); |
| 635 | void gen_gvec_rev16(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 636 | uint32_t opr_sz, uint32_t max_sz); |
| 637 | void gen_gvec_rev32(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 638 | uint32_t opr_sz, uint32_t max_sz); |
| 639 | void gen_gvec_rev64(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 640 | uint32_t opr_sz, uint32_t max_sz); |
| 641 | |
| 642 | void gen_gvec_saddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 643 | uint32_t opr_sz, uint32_t max_sz); |
| 644 | void gen_gvec_sadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 645 | uint32_t opr_sz, uint32_t max_sz); |
| 646 | void gen_gvec_uaddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 647 | uint32_t opr_sz, uint32_t max_sz); |
| 648 | void gen_gvec_uadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 649 | uint32_t opr_sz, uint32_t max_sz); |
| 650 | |
| 651 | /* These exclusively manipulate the sign bit. */ |
| 652 | void gen_gvec_fabs(unsigned vece, uint32_t dofs, uint32_t aofs, |
| 653 | uint32_t oprsz, uint32_t maxsz); |
| 654 | void gen_gvec_fneg(unsigned vece, uint32_t dofs, uint32_t aofs, |
| 655 | uint32_t oprsz, uint32_t maxsz); |
| 656 | |
| 657 | void gen_gvec_urecpe(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 658 | uint32_t opr_sz, uint32_t max_sz); |
| 659 | void gen_gvec_ursqrte(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
| 660 | uint32_t opr_sz, uint32_t max_sz); |
| 661 | |
| 662 | /* |
| 663 | * Forward to the isar_feature_* tests given a DisasContext pointer. |
| 664 | */ |
| 665 | #define dc_isar_feature(name, ctx) \ |
| 666 | ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); }) |
| 667 | |
| 668 | /* Note that the gvec expanders operate on offsets + sizes. */ |
| 669 | typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); |
| 670 | typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, |
| 671 | uint32_t, uint32_t); |
| 672 | typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, |
| 673 | uint32_t, uint32_t, uint32_t); |
| 674 | typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t, |
| 675 | uint32_t, uint32_t, uint32_t); |
| 676 | typedef void GVecGen3FnVar(unsigned, TCGv_ptr, uint32_t, TCGv_ptr, uint32_t, |
| 677 | TCGv_ptr, uint32_t, uint32_t, uint32_t); |
| 678 | |
| 679 | /* Function prototype for gen_ functions for calling Neon helpers */ |
| 680 | typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32); |
| 681 | typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); |
| 682 | typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); |
| 683 | typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); |
| 684 | typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, |
| 685 | TCGv_i32, TCGv_i32); |
| 686 | typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); |
| 687 | typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); |
| 688 | typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); |
| 689 | typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); |
| 690 | typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); |
| 691 | typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr); |
| 692 | typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); |
| 693 | typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); |
| 694 | typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64); |
| 695 | typedef void NeonGenOne64OpEnvFn(TCGv_i64, TCGv_env, TCGv_i64); |
| 696 | typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); |
| 697 | typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); |
| 698 | typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); |
| 699 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); |
| 700 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); |
| 701 | typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); |
| 702 | typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); |
| 703 | typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); |
| 704 | |
| 705 | /** |
| 706 | * arm_tbflags_from_tb: |
| 707 | * @tb: the TranslationBlock |
| 708 | * |
| 709 | * Extract the flag values from @tb. |
| 710 | */ |
| 711 | static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) |
| 712 | { |
| 713 | return (CPUARMTBFlags){ tb->flags, tb->cs_base }; |
| 714 | } |
| 715 | |
| 716 | /** |
| 717 | * fpstatus_ptr: return TCGv_ptr to the specified fp_status field |
| 718 | * |
| 719 | * We have multiple softfloat float_status fields in the Arm CPU state struct |
| 720 | * (see the comment in cpu.h for details). Return a TCGv_ptr which has |
| 721 | * been set up to point to the requested field in the CPU state struct. |
| 722 | */ |
| 723 | static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) |
| 724 | { |
| 725 | TCGv_ptr statusptr = tcg_temp_new_ptr(); |
| 726 | int offset = offsetof(CPUARMState, vfp.fp_status[flavour]); |
| 727 | |
| 728 | tcg_gen_addi_ptr(statusptr, tcg_env, offset); |
| 729 | return statusptr; |
| 730 | } |
| 731 | |
| 732 | /** |
| 733 | * finalize_memop_atom: |
| 734 | * @s: DisasContext |
| 735 | * @opc: size+sign+align of the memory operation |
| 736 | * @atom: atomicity of the memory operation |
| 737 | * |
| 738 | * Build the complete MemOp for a memory operation, including alignment, |
| 739 | * endianness, and atomicity. |
| 740 | * |
| 741 | * If (op & MO_AMASK) then the operation already contains the required |
| 742 | * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally |
| 743 | * unaligned operation, e.g. for AccType_NORMAL. |
| 744 | * |
| 745 | * In the latter case, there are configuration bits that require alignment, |
| 746 | * and this is applied here. Note that there is no way to indicate that |
| 747 | * no alignment should ever be enforced; this must be handled manually. |
| 748 | */ |
| 749 | static inline MemOp finalize_memop_atom(DisasContext *s, MemOp opc, MemOp atom) |
| 750 | { |
| 751 | if (!(opc & MO_AMASK)) { |
| 752 | opc |= MO_ALIGN | (s->align_mem ? 0 : MO_ALIGN_TLB_ONLY); |
| 753 | } |
| 754 | return opc | atom | s->be_data; |
| 755 | } |
| 756 | |
| 757 | /** |
| 758 | * finalize_memop: |
| 759 | * @s: DisasContext |
| 760 | * @opc: size+sign+align of the memory operation |
| 761 | * |
| 762 | * Like finalize_memop_atom, but with default atomicity. |
| 763 | */ |
| 764 | static inline MemOp finalize_memop(DisasContext *s, MemOp opc) |
| 765 | { |
| 766 | MemOp atom = s->lse2 ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN; |
| 767 | return finalize_memop_atom(s, opc, atom); |
| 768 | } |
| 769 | |
| 770 | /** |
| 771 | * finalize_memop_pair: |
| 772 | * @s: DisasContext |
| 773 | * @opc: size+sign+align of the memory operation |
| 774 | * |
| 775 | * Like finalize_memop_atom, but with atomicity for a pair. |
| 776 | * C.f. Pseudocode for Mem[], operand ispair. |
| 777 | */ |
| 778 | static inline MemOp finalize_memop_pair(DisasContext *s, MemOp opc) |
| 779 | { |
| 780 | MemOp atom = s->lse2 ? MO_ATOM_WITHIN16_PAIR : MO_ATOM_IFALIGN_PAIR; |
| 781 | return finalize_memop_atom(s, opc, atom); |
| 782 | } |
| 783 | |
| 784 | /** |
| 785 | * finalize_memop_asimd: |
| 786 | * @s: DisasContext |
| 787 | * @opc: size+sign+align of the memory operation |
| 788 | * |
| 789 | * Like finalize_memop_atom, but with atomicity of AccessType_ASIMD. |
| 790 | */ |
| 791 | static inline MemOp finalize_memop_asimd(DisasContext *s, MemOp opc) |
| 792 | { |
| 793 | /* |
| 794 | * In the pseudocode for Mem[], with AccessType_ASIMD, size == 16, |
| 795 | * if IsAligned(8), the first case provides separate atomicity for |
| 796 | * the pair of 64-bit accesses. If !IsAligned(8), the middle cases |
| 797 | * do not apply, and we're left with the final case of no atomicity. |
| 798 | * Thus MO_ATOM_IFALIGN_PAIR. |
| 799 | * |
| 800 | * For other sizes, normal LSE2 rules apply. |
| 801 | */ |
| 802 | if ((opc & MO_SIZE) == MO_128) { |
| 803 | return finalize_memop_atom(s, opc, MO_ATOM_IFALIGN_PAIR); |
| 804 | } |
| 805 | return finalize_memop(s, opc); |
| 806 | } |
| 807 | |
| 808 | /** |
| 809 | * asimd_imm_const: Expand an encoded SIMD constant value |
| 810 | * |
| 811 | * Expand a SIMD constant value. This is essentially the pseudocode |
| 812 | * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for |
| 813 | * VMVN and VBIC (when cmode < 14 && op == 1). |
| 814 | * |
| 815 | * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; |
| 816 | * callers must catch this; we return the 64-bit constant value defined |
| 817 | * for AArch64. |
| 818 | * |
| 819 | * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but |
| 820 | * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; |
| 821 | * we produce an immediate constant value of 0 in these cases. |
| 822 | */ |
| 823 | uint64_t asimd_imm_const(uint32_t imm, int cmode, int op); |
| 824 | |
| 825 | /* |
| 826 | * gen_disas_label: |
| 827 | * Create a label and cache a copy of pc_save. |
| 828 | */ |
| 829 | static inline DisasLabel gen_disas_label(DisasContext *s) |
| 830 | { |
| 831 | return (DisasLabel){ |
| 832 | .label = gen_new_label(), |
| 833 | .pc_save = s->pc_save, |
| 834 | }; |
| 835 | } |
| 836 | |
| 837 | /* |
| 838 | * set_disas_label: |
| 839 | * Emit a label and restore the cached copy of pc_save. |
| 840 | */ |
| 841 | static inline void set_disas_label(DisasContext *s, DisasLabel l) |
| 842 | { |
| 843 | gen_set_label(l.label); |
| 844 | s->pc_save = l.pc_save; |
| 845 | } |
| 846 | |
| 847 | static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key) |
| 848 | { |
| 849 | TCGv_ptr ret = tcg_temp_new_ptr(); |
| 850 | gen_helper_lookup_cp_reg(ret, tcg_env, tcg_constant_i32(key)); |
| 851 | return ret; |
| 852 | } |
| 853 | |
| 854 | /* |
| 855 | * Set and reset rounding mode around another operation. |
| 856 | */ |
| 857 | static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst) |
| 858 | { |
| 859 | TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode)); |
| 860 | TCGv_i32 old = tcg_temp_new_i32(); |
| 861 | |
| 862 | gen_helper_set_rmode(old, new, fpst); |
| 863 | return old; |
| 864 | } |
| 865 | |
| 866 | static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst) |
| 867 | { |
| 868 | gen_helper_set_rmode(old, old, fpst); |
| 869 | } |
| 870 | |
| 871 | /* |
| 872 | * Event Register signalling. |
| 873 | * |
| 874 | * A bunch of activities trigger events, we just need to latch on to |
| 875 | * true. The event eventually gets consumed by WFE/WFET. |
| 876 | * |
| 877 | * user-mode treats these as NOPs. |
| 878 | */ |
| 879 | |
| 880 | static inline void gen_event_reg(void) |
| 881 | { |
| 882 | #ifndef CONFIG_USER_ONLY |
| 883 | TCGv_i32 set_event = tcg_constant_i32(1); |
| 884 | QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, event_register) != 1); |
| 885 | tcg_gen_st8_i32(set_event, tcg_env, offsetof(CPUARMState, event_register)); |
| 886 | #endif |
| 887 | } |
| 888 | |
| 889 | /* |
| 890 | * Helpers for implementing sets of trans_* functions. |
| 891 | * Defer the implementation of NAME to FUNC, with optional extra arguments. |
| 892 | */ |
| 893 | #define TRANS(NAME, FUNC, ...) \ |
| 894 | static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ |
| 895 | { return FUNC(s, __VA_ARGS__); } |
| 896 | #define TRANS_FEAT(NAME, FEAT, FUNC, ...) \ |
| 897 | static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ |
| 898 | { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); } |
| 899 | |
| 900 | /* For SVE insns which are not valid in Streaming SVE mode */ |
| 901 | #define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \ |
| 902 | static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ |
| 903 | { \ |
| 904 | s->is_nonstreaming = true; \ |
| 905 | return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \ |
| 906 | } |
| 907 | |
| 908 | /* |
| 909 | * For SVE insns which are only valid in Streaming SVE mode when |
| 910 | * FEAT_STREAM is implemented. |
| 911 | */ |
| 912 | #define TRANS_FEAT_STREAMING_IF(NAME, FEAT, FEAT_STREAM, FUNC, ...) \ |
| 913 | static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ |
| 914 | { \ |
| 915 | s->is_nonstreaming = !dc_isar_feature(FEAT_STREAM, s); \ |
| 916 | return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \ |
| 917 | } |
| 918 | |
| 919 | #endif /* TARGET_ARM_TRANSLATE_H */ |