@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
h 243 lines 6.29 KB
Raw
1 /*
2 * QEMU AVR CPU
3 *
4 * Copyright (c) 2016-2020 Michael Rolnik
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21 #ifndef QEMU_AVR_CPU_H
22 #define QEMU_AVR_CPU_H
23
24 #include "cpu-qom.h"
25 #include "exec/cpu-common.h"
26 #include "exec/cpu-interrupt.h"
27 #include "system/memory.h"
28
29 #ifdef CONFIG_USER_ONLY
30 #error "AVR 8-bit does not support user mode"
31 #endif
32
33 #define CPU_RESOLVING_TYPE TYPE_AVR_CPU
34
35 /*
36 * AVR has two memory spaces, data & code.
37 * e.g. both have 0 address
38 * ST/LD instructions access data space
39 * LPM/SPM and instruction fetching access code memory space
40 */
41 #define MMU_CODE_IDX 0
42 #define MMU_DATA_IDX 1
43
44 #define EXCP_RESET 1
45 #define EXCP_INT(n) (EXCP_RESET + (n) + 1)
46
47 /* Number of CPU registers */
48 #define NUMBER_OF_CPU_REGISTERS 32
49
50 /* CPU registers mapped into i/o ports 0x38-0x3f. */
51 #define REG_38_RAMPD 0
52 #define REG_38_RAMPX 1
53 #define REG_38_RAMPY 2
54 #define REG_38_RAMPZ 3
55 #define REG_38_EIDN 4
56 #define REG_38_SPL 5
57 #define REG_38_SPH 6
58 #define REG_38_SREG 7
59
60 /*
61 * Offsets of AVR memory regions in host memory space.
62 *
63 * This is needed because the AVR has separate code and data address
64 * spaces that both have start from zero but have to go somewhere in
65 * host memory.
66 *
67 * It's also useful to know where some things are, like the IO registers.
68 */
69 /* Flash program memory */
70 #define OFFSET_CODE 0x00000000
71 /* CPU registers, IO registers, and SRAM */
72 #define OFFSET_DATA 0x00800000
73 /*
74 * IO registers, including status register, stack pointer, and memory
75 * mapped peripherals, mapped just after CPU registers
76 */
77 #define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS)
78
79 typedef enum AVRFeature {
80 AVR_FEATURE_SRAM,
81
82 AVR_FEATURE_1_BYTE_PC,
83 AVR_FEATURE_2_BYTE_PC,
84 AVR_FEATURE_3_BYTE_PC,
85
86 AVR_FEATURE_1_BYTE_SP,
87 AVR_FEATURE_2_BYTE_SP,
88
89 AVR_FEATURE_BREAK,
90 AVR_FEATURE_DES,
91 AVR_FEATURE_RMW, /* Read Modify Write - XCH LAC LAS LAT */
92
93 AVR_FEATURE_EIJMP_EICALL,
94 AVR_FEATURE_IJMP_ICALL,
95 AVR_FEATURE_JMP_CALL,
96
97 AVR_FEATURE_ADIW_SBIW,
98
99 AVR_FEATURE_SPM,
100 AVR_FEATURE_SPMX,
101
102 AVR_FEATURE_ELPMX,
103 AVR_FEATURE_ELPM,
104 AVR_FEATURE_LPMX,
105 AVR_FEATURE_LPM,
106
107 AVR_FEATURE_MOVW,
108 AVR_FEATURE_MUL,
109 AVR_FEATURE_RAMPD,
110 AVR_FEATURE_RAMPX,
111 AVR_FEATURE_RAMPY,
112 AVR_FEATURE_RAMPZ,
113 } AVRFeature;
114
115 typedef struct CPUArchState {
116 uint32_t pc_w; /* 0x003fffff up to 22 bits */
117
118 uint32_t sregC; /* 0x00000001 1 bit */
119 uint32_t sregZ; /* 0x00000001 1 bit */
120 uint32_t sregN; /* 0x00000001 1 bit */
121 uint32_t sregV; /* 0x00000001 1 bit */
122 uint32_t sregS; /* 0x00000001 1 bit */
123 uint32_t sregH; /* 0x00000001 1 bit */
124 uint32_t sregT; /* 0x00000001 1 bit */
125 uint32_t sregI; /* 0x00000001 1 bit */
126
127 uint32_t rampD; /* 0x00ff0000 8 bits */
128 uint32_t rampX; /* 0x00ff0000 8 bits */
129 uint32_t rampY; /* 0x00ff0000 8 bits */
130 uint32_t rampZ; /* 0x00ff0000 8 bits */
131 uint32_t eind; /* 0x00ff0000 8 bits */
132
133 uint32_t r[NUMBER_OF_CPU_REGISTERS]; /* 8 bits each */
134 uint32_t sp; /* 16 bits */
135
136 uint32_t skip; /* if set skip instruction */
137
138 uint64_t intsrc; /* interrupt sources */
139 bool fullacc; /* CPU/MEM if true MEM only otherwise */
140
141 uint64_t features;
142 } CPUAVRState;
143
144 /**
145 * AVRCPU:
146 * @env: #CPUAVRState
147 *
148 * A AVR CPU.
149 */
150 struct ArchCPU {
151 CPUState parent_obj;
152
153 CPUAVRState env;
154
155 MemoryRegion cpu_reg1;
156 MemoryRegion cpu_reg2;
157
158 /* Initial value of stack pointer */
159 uint32_t init_sp;
160 };
161
162 /**
163 * AVRCPUClass:
164 * @parent_realize: The parent class' realize handler.
165 * @parent_phases: The parent class' reset phase handlers.
166 *
167 * A AVR CPU model.
168 */
169 struct AVRCPUClass {
170 CPUClass parent_class;
171
172 DeviceRealize parent_realize;
173 ResettablePhases parent_phases;
174 };
175
176 extern const struct VMStateDescription vms_avr_cpu;
177
178 void avr_cpu_do_interrupt(CPUState *cpu);
179 bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
180 hwaddr avr_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
181 int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
182 int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
183 int avr_print_insn(bfd_vma addr, disassemble_info *info);
184 vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr);
185
186 static inline int avr_feature(CPUAVRState *env, AVRFeature feature)
187 {
188 return (env->features & (1U << feature)) != 0;
189 }
190
191 static inline void set_avr_feature(CPUAVRState *env, int feature)
192 {
193 env->features |= (1U << feature);
194 }
195
196 void avr_cpu_tcg_init(void);
197 void avr_cpu_translate_code(CPUState *cs, TranslationBlock *tb,
198 int *max_insns, vaddr pc, void *host_pc);
199
200 int cpu_avr_exec(CPUState *cpu);
201
202 enum {
203 TB_FLAGS_FULL_ACCESS = 1,
204 TB_FLAGS_SKIP = 2,
205 };
206
207 static inline int cpu_interrupts_enabled(CPUAVRState *env)
208 {
209 return env->sregI != 0;
210 }
211
212 static inline uint8_t cpu_get_sreg(CPUAVRState *env)
213 {
214 return (env->sregC) << 0
215 | (env->sregZ) << 1
216 | (env->sregN) << 2
217 | (env->sregV) << 3
218 | (env->sregS) << 4
219 | (env->sregH) << 5
220 | (env->sregT) << 6
221 | (env->sregI) << 7;
222 }
223
224 static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg)
225 {
226 env->sregC = (sreg >> 0) & 0x01;
227 env->sregZ = (sreg >> 1) & 0x01;
228 env->sregN = (sreg >> 2) & 0x01;
229 env->sregV = (sreg >> 3) & 0x01;
230 env->sregS = (sreg >> 4) & 0x01;
231 env->sregH = (sreg >> 5) & 0x01;
232 env->sregT = (sreg >> 6) & 0x01;
233 env->sregI = (sreg >> 7) & 0x01;
234 }
235
236 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
237 MMUAccessType access_type, int mmu_idx,
238 bool probe, uintptr_t retaddr);
239
240 extern const MemoryRegionOps avr_cpu_reg1;
241 extern const MemoryRegionOps avr_cpu_reg2;
242
243 #endif /* QEMU_AVR_CPU_H */