| 1 | /* |
| 2 | * QEMU AVR CPU helpers |
| 3 | * |
| 4 | * Copyright (c) 2016-2020 Michael Rolnik |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see |
| 18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qemu/log.h" |
| 23 | #include "qemu/error-report.h" |
| 24 | #include "cpu.h" |
| 25 | #include "accel/tcg/cpu-ops.h" |
| 26 | #include "accel/tcg/cpu-loop.h" |
| 27 | #include "exec/cputlb.h" |
| 28 | #include "exec/page-protection.h" |
| 29 | #include "exec/target_page.h" |
| 30 | #include "accel/tcg/cpu-ldst.h" |
| 31 | #include "exec/helper-proto.h" |
| 32 | #include "qemu/plugin.h" |
| 33 | |
| 34 | bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
| 35 | { |
| 36 | CPUAVRState *env = cpu_env(cs); |
| 37 | |
| 38 | /* |
| 39 | * We cannot separate a skip from the next instruction, |
| 40 | * as the skip would not be preserved across the interrupt. |
| 41 | * Separating the two insn normally only happens at page boundaries. |
| 42 | */ |
| 43 | if (env->skip) { |
| 44 | return false; |
| 45 | } |
| 46 | |
| 47 | if (interrupt_request & CPU_INTERRUPT_RESET) { |
| 48 | if (cpu_interrupts_enabled(env)) { |
| 49 | cs->exception_index = EXCP_RESET; |
| 50 | avr_cpu_do_interrupt(cs); |
| 51 | |
| 52 | cpu_reset_interrupt(cs, CPU_INTERRUPT_RESET); |
| 53 | return true; |
| 54 | } |
| 55 | } |
| 56 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 57 | if (cpu_interrupts_enabled(env) && env->intsrc != 0) { |
| 58 | int index = ctz64(env->intsrc); |
| 59 | cs->exception_index = EXCP_INT(index); |
| 60 | avr_cpu_do_interrupt(cs); |
| 61 | |
| 62 | env->intsrc &= env->intsrc - 1; /* clear the interrupt */ |
| 63 | if (!env->intsrc) { |
| 64 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
| 65 | } |
| 66 | return true; |
| 67 | } |
| 68 | } |
| 69 | return false; |
| 70 | } |
| 71 | |
| 72 | static void do_stb(CPUAVRState *env, uint32_t addr, uint8_t data, uintptr_t ra) |
| 73 | { |
| 74 | cpu_stb_mmuidx_ra(env, addr, data, MMU_DATA_IDX, ra); |
| 75 | } |
| 76 | |
| 77 | void avr_cpu_do_interrupt(CPUState *cs) |
| 78 | { |
| 79 | CPUAVRState *env = cpu_env(cs); |
| 80 | |
| 81 | uint32_t ret = env->pc_w; |
| 82 | int vector = 0; |
| 83 | int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1; |
| 84 | int base = 0; |
| 85 | |
| 86 | if (cs->exception_index == EXCP_RESET) { |
| 87 | vector = 0; |
| 88 | } else if (env->intsrc != 0) { |
| 89 | vector = ctz64(env->intsrc) + 1; |
| 90 | } |
| 91 | |
| 92 | if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { |
| 93 | do_stb(env, env->sp--, ret, 0); |
| 94 | do_stb(env, env->sp--, ret >> 8, 0); |
| 95 | do_stb(env, env->sp--, ret >> 16, 0); |
| 96 | } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { |
| 97 | do_stb(env, env->sp--, ret, 0); |
| 98 | do_stb(env, env->sp--, ret >> 8, 0); |
| 99 | } else { |
| 100 | do_stb(env, env->sp--, ret, 0); |
| 101 | } |
| 102 | |
| 103 | env->pc_w = base + vector * size; |
| 104 | env->sregI = 0; /* clear Global Interrupt Flag */ |
| 105 | |
| 106 | cs->exception_index = -1; |
| 107 | |
| 108 | qemu_plugin_vcpu_interrupt_cb(cs, ret); |
| 109 | } |
| 110 | |
| 111 | hwaddr avr_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) |
| 112 | { |
| 113 | return addr; /* I assume 1:1 address correspondence */ |
| 114 | } |
| 115 | |
| 116 | bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 117 | MMUAccessType access_type, int mmu_idx, |
| 118 | bool probe, uintptr_t retaddr) |
| 119 | { |
| 120 | int prot; |
| 121 | uint32_t paddr; |
| 122 | |
| 123 | address &= TARGET_PAGE_MASK; |
| 124 | |
| 125 | if (mmu_idx == MMU_CODE_IDX) { |
| 126 | /* Access to code in flash. */ |
| 127 | paddr = OFFSET_CODE + address; |
| 128 | prot = PAGE_READ | PAGE_EXEC; |
| 129 | if (paddr >= OFFSET_DATA) { |
| 130 | /* |
| 131 | * This should not be possible via any architectural operations. |
| 132 | * There is certainly not an exception that we can deliver. |
| 133 | * Accept probing that might come from generic code. |
| 134 | */ |
| 135 | if (probe) { |
| 136 | return false; |
| 137 | } |
| 138 | error_report("execution left flash memory"); |
| 139 | abort(); |
| 140 | } |
| 141 | } else { |
| 142 | /* Access to memory. */ |
| 143 | paddr = OFFSET_DATA + address; |
| 144 | prot = PAGE_READ | PAGE_WRITE; |
| 145 | } |
| 146 | |
| 147 | tlb_set_page(cs, address, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); |
| 148 | return true; |
| 149 | } |
| 150 | |
| 151 | /* |
| 152 | * helpers |
| 153 | */ |
| 154 | |
| 155 | void helper_sleep(CPUAVRState *env) |
| 156 | { |
| 157 | CPUState *cs = env_cpu(env); |
| 158 | |
| 159 | cs->exception_index = EXCP_HLT; |
| 160 | cpu_loop_exit(cs); |
| 161 | } |
| 162 | |
| 163 | void helper_unsupported(CPUAVRState *env) |
| 164 | { |
| 165 | CPUState *cs = env_cpu(env); |
| 166 | |
| 167 | /* |
| 168 | * I count not find what happens on the real platform, so |
| 169 | * it's EXCP_DEBUG for meanwhile |
| 170 | */ |
| 171 | cs->exception_index = EXCP_DEBUG; |
| 172 | if (qemu_loglevel_mask(LOG_UNIMP)) { |
| 173 | qemu_log("UNSUPPORTED\n"); |
| 174 | cpu_dump_state(cs, stderr, 0); |
| 175 | } |
| 176 | cpu_loop_exit(cs); |
| 177 | } |
| 178 | |
| 179 | void helper_debug(CPUAVRState *env) |
| 180 | { |
| 181 | CPUState *cs = env_cpu(env); |
| 182 | |
| 183 | cs->exception_index = EXCP_DEBUG; |
| 184 | cpu_loop_exit(cs); |
| 185 | } |
| 186 | |
| 187 | void helper_break(CPUAVRState *env) |
| 188 | { |
| 189 | CPUState *cs = env_cpu(env); |
| 190 | |
| 191 | cs->exception_index = EXCP_DEBUG; |
| 192 | cpu_loop_exit(cs); |
| 193 | } |
| 194 | |
| 195 | void helper_wdr(CPUAVRState *env) |
| 196 | { |
| 197 | qemu_log_mask(LOG_UNIMP, "WDG reset (not implemented)\n"); |
| 198 | } |
| 199 | |
| 200 | /* |
| 201 | * The first 32 bytes of the data space are mapped to the cpu regs. |
| 202 | * We cannot write these from normal store operations because TCG |
| 203 | * does not expect global temps to be modified -- a global may be |
| 204 | * live in a host cpu register across the store. We can however |
| 205 | * read these, as TCG does make sure the global temps are saved |
| 206 | * in case the load operation traps. |
| 207 | */ |
| 208 | |
| 209 | static uint64_t avr_cpu_reg1_read(void *opaque, hwaddr addr, unsigned size) |
| 210 | { |
| 211 | CPUAVRState *env = opaque; |
| 212 | |
| 213 | assert(addr < 32); |
| 214 | return env->r[addr]; |
| 215 | } |
| 216 | |
| 217 | /* |
| 218 | * The range 0x38-0x3f of the i/o space is mapped to cpu regs. |
| 219 | * As above, we cannot write these from normal store operations. |
| 220 | */ |
| 221 | |
| 222 | static uint64_t avr_cpu_reg2_read(void *opaque, hwaddr addr, unsigned size) |
| 223 | { |
| 224 | CPUAVRState *env = opaque; |
| 225 | |
| 226 | switch (addr) { |
| 227 | case REG_38_RAMPD: |
| 228 | return 0xff & (env->rampD >> 16); |
| 229 | case REG_38_RAMPX: |
| 230 | return 0xff & (env->rampX >> 16); |
| 231 | case REG_38_RAMPY: |
| 232 | return 0xff & (env->rampY >> 16); |
| 233 | case REG_38_RAMPZ: |
| 234 | return 0xff & (env->rampZ >> 16); |
| 235 | case REG_38_EIDN: |
| 236 | return 0xff & (env->eind >> 16); |
| 237 | case REG_38_SPL: |
| 238 | return env->sp & 0x00ff; |
| 239 | case REG_38_SPH: |
| 240 | return 0xff & (env->sp >> 8); |
| 241 | case REG_38_SREG: |
| 242 | return cpu_get_sreg(env); |
| 243 | } |
| 244 | g_assert_not_reached(); |
| 245 | } |
| 246 | |
| 247 | static void avr_cpu_trap_write(void *opaque, hwaddr addr, |
| 248 | uint64_t data64, unsigned size) |
| 249 | { |
| 250 | CPUAVRState *env = opaque; |
| 251 | CPUState *cs = env_cpu(env); |
| 252 | |
| 253 | env->fullacc = true; |
| 254 | cpu_loop_exit_restore(cs, cs->mem_io_pc); |
| 255 | } |
| 256 | |
| 257 | const MemoryRegionOps avr_cpu_reg1 = { |
| 258 | .read = avr_cpu_reg1_read, |
| 259 | .write = avr_cpu_trap_write, |
| 260 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 261 | .valid.min_access_size = 1, |
| 262 | .valid.max_access_size = 1, |
| 263 | }; |
| 264 | |
| 265 | const MemoryRegionOps avr_cpu_reg2 = { |
| 266 | .read = avr_cpu_reg2_read, |
| 267 | .write = avr_cpu_trap_write, |
| 268 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 269 | .valid.min_access_size = 1, |
| 270 | .valid.max_access_size = 1, |
| 271 | }; |
| 272 | |
| 273 | /* |
| 274 | * this function implements ST instruction when there is a possibility to write |
| 275 | * into a CPU register |
| 276 | */ |
| 277 | void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr) |
| 278 | { |
| 279 | env->fullacc = false; |
| 280 | |
| 281 | switch (addr) { |
| 282 | case 0 ... 31: |
| 283 | /* CPU registers */ |
| 284 | env->r[addr] = data; |
| 285 | break; |
| 286 | |
| 287 | case REG_38_RAMPD + 0x38 + NUMBER_OF_CPU_REGISTERS: |
| 288 | if (avr_feature(env, AVR_FEATURE_RAMPD)) { |
| 289 | env->rampD = data << 16; |
| 290 | } |
| 291 | break; |
| 292 | case REG_38_RAMPX + 0x38 + NUMBER_OF_CPU_REGISTERS: |
| 293 | if (avr_feature(env, AVR_FEATURE_RAMPX)) { |
| 294 | env->rampX = data << 16; |
| 295 | } |
| 296 | break; |
| 297 | case REG_38_RAMPY + 0x38 + NUMBER_OF_CPU_REGISTERS: |
| 298 | if (avr_feature(env, AVR_FEATURE_RAMPY)) { |
| 299 | env->rampY = data << 16; |
| 300 | } |
| 301 | break; |
| 302 | case REG_38_RAMPZ + 0x38 + NUMBER_OF_CPU_REGISTERS: |
| 303 | if (avr_feature(env, AVR_FEATURE_RAMPZ)) { |
| 304 | env->rampZ = data << 16; |
| 305 | } |
| 306 | break; |
| 307 | case REG_38_EIDN + 0x38 + NUMBER_OF_CPU_REGISTERS: |
| 308 | env->eind = data << 16; |
| 309 | break; |
| 310 | case REG_38_SPL + 0x38 + NUMBER_OF_CPU_REGISTERS: |
| 311 | env->sp = (env->sp & 0xff00) | data; |
| 312 | break; |
| 313 | case REG_38_SPH + 0x38 + NUMBER_OF_CPU_REGISTERS: |
| 314 | if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { |
| 315 | env->sp = (env->sp & 0x00ff) | (data << 8); |
| 316 | } |
| 317 | break; |
| 318 | case REG_38_SREG + 0x38 + NUMBER_OF_CPU_REGISTERS: |
| 319 | cpu_set_sreg(env, data); |
| 320 | break; |
| 321 | |
| 322 | default: |
| 323 | do_stb(env, addr, data, GETPC()); |
| 324 | break; |
| 325 | } |
| 326 | } |