| 1 | /* |
| 2 | * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | /* Keep this as the first attribute: */ |
| 19 | DEF_ATTRIB(AA_DUMMY, "Dummy Zeroth Attribute", "", "") |
| 20 | |
| 21 | /* Misc */ |
| 22 | DEF_ATTRIB(EXTENSION, "Extension instruction", "", "") |
| 23 | |
| 24 | DEF_ATTRIB(PRIV, "Not available in user or guest mode", "", "") |
| 25 | DEF_ATTRIB(GUEST, "Not available in user mode", "", "") |
| 26 | |
| 27 | DEF_ATTRIB(FPOP, "Floating Point Operation", "", "") |
| 28 | |
| 29 | DEF_ATTRIB(EXTENDABLE, "Immediate may be extended", "", "") |
| 30 | |
| 31 | DEF_ATTRIB(ARCHV2, "V2 architecture", "", "") |
| 32 | DEF_ATTRIB(ARCHV3, "V3 architecture", "", "") |
| 33 | DEF_ATTRIB(ARCHV4, "V4 architecture", "", "") |
| 34 | DEF_ATTRIB(ARCHV5, "V5 architecture", "", "") |
| 35 | |
| 36 | DEF_ATTRIB(SUBINSN, "sub-instruction", "", "") |
| 37 | |
| 38 | /* Load and Store attributes */ |
| 39 | DEF_ATTRIB(LOAD, "Loads from memory", "", "") |
| 40 | DEF_ATTRIB(STORE, "Stores to memory", "", "") |
| 41 | DEF_ATTRIB(STOREIMMED, "Stores immed to memory", "", "") |
| 42 | DEF_ATTRIB(MEMSIZE_0B, "Memory width is 0 byte", "", "") |
| 43 | DEF_ATTRIB(MEMSIZE_1B, "Memory width is 1 byte", "", "") |
| 44 | DEF_ATTRIB(MEMSIZE_2B, "Memory width is 2 bytes", "", "") |
| 45 | DEF_ATTRIB(MEMSIZE_4B, "Memory width is 4 bytes", "", "") |
| 46 | DEF_ATTRIB(MEMSIZE_8B, "Memory width is 8 bytes", "", "") |
| 47 | DEF_ATTRIB(SCALAR_LOAD, "Load is scalar", "", "") |
| 48 | DEF_ATTRIB(SCALAR_STORE, "Store is scalar", "", "") |
| 49 | DEF_ATTRIB(REGWRSIZE_1B, "Memory width is 1 byte", "", "") |
| 50 | DEF_ATTRIB(REGWRSIZE_2B, "Memory width is 2 bytes", "", "") |
| 51 | DEF_ATTRIB(REGWRSIZE_4B, "Memory width is 4 bytes", "", "") |
| 52 | DEF_ATTRIB(REGWRSIZE_8B, "Memory width is 8 bytes", "", "") |
| 53 | DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "") |
| 54 | DEF_ATTRIB(MEMLIKE_PACKET_RULES, "follows Memory-like packet rules", "", "") |
| 55 | DEF_ATTRIB(CACHEOP, "Cache operation", "", "") |
| 56 | DEF_ATTRIB(COPBYADDRESS, "Cache operation by address", "", "") |
| 57 | DEF_ATTRIB(COPBYIDX, "Cache operation by index", "", "") |
| 58 | DEF_ATTRIB(RELEASE, "Releases a lock", "", "") |
| 59 | DEF_ATTRIB(ACQUIRE, "Acquires a lock", "", "") |
| 60 | |
| 61 | DEF_ATTRIB(RLS_INNER, "Store release inner visibility", "", "") |
| 62 | DEF_ATTRIB(RLS_ALL_THREAD, "Store release among all threads", "", "") |
| 63 | DEF_ATTRIB(RLS_SAME_THREAD, "Store release with the same thread", "", "") |
| 64 | |
| 65 | /* V6 Vector attributes */ |
| 66 | DEF_ATTRIB(CVI, "Executes on the HVX extension", "", "") |
| 67 | |
| 68 | DEF_ATTRIB(CVI_NEW, "New value memory instruction executes on HVX", "", "") |
| 69 | DEF_ATTRIB(CVI_VM, "Memory instruction executes on HVX", "", "") |
| 70 | DEF_ATTRIB(CVI_VP, "Permute instruction executes on HVX", "", "") |
| 71 | DEF_ATTRIB(CVI_VP_VS, "Double vector permute/shft insn executes on HVX", "", "") |
| 72 | DEF_ATTRIB(CVI_VX, "Multiply instruction executes on HVX", "", "") |
| 73 | DEF_ATTRIB(CVI_VX_DV, "Double vector multiply insn executes on HVX", "", "") |
| 74 | DEF_ATTRIB(CVI_VS, "Shift instruction executes on HVX", "", "") |
| 75 | DEF_ATTRIB(CVI_VS_3SRC, "This shift needs to borrow a source register", "", "") |
| 76 | DEF_ATTRIB(CVI_VS_VX, "Permute/shift and multiply insn executes on HVX", "", "") |
| 77 | DEF_ATTRIB(CVI_VA, "ALU instruction executes on HVX", "", "") |
| 78 | DEF_ATTRIB(CVI_VA_DV, "Double vector alu instruction executes on HVX", "", "") |
| 79 | DEF_ATTRIB(CVI_4SLOT, "Consumes all the vector execution resources", "", "") |
| 80 | DEF_ATTRIB(CVI_TMP, "Transient Memory Load not written to register", "", "") |
| 81 | DEF_ATTRIB(CVI_REMAP, "Register Renaming not written to register file", "", "") |
| 82 | DEF_ATTRIB(CVI_GATHER, "CVI Gather operation", "", "") |
| 83 | DEF_ATTRIB(CVI_SCATTER, "CVI Scatter operation", "", "") |
| 84 | DEF_ATTRIB(CVI_SCATTER_RELEASE, "CVI Store Release for scatter", "", "") |
| 85 | DEF_ATTRIB(CVI_TMP_DST, "CVI instruction that doesn't write a register", "", "") |
| 86 | DEF_ATTRIB(CVI_SLOT23, "Can execute in slot 2 or slot 3 (HVX)", "", "") |
| 87 | DEF_ATTRIB(CVI_VA_2SRC, "Execs on multimedia vector engine; requires two srcs", "", "") |
| 88 | |
| 89 | DEF_ATTRIB(VTCM_ALLBANK_ACCESS, "Allocates in all VTCM schedulers.", "", "") |
| 90 | |
| 91 | /* Change-of-flow attributes */ |
| 92 | DEF_ATTRIB(JUMP, "Jump-type instruction", "", "") |
| 93 | DEF_ATTRIB(INDIRECT, "Absolute register jump", "", "") |
| 94 | DEF_ATTRIB(CALL, "Function call instruction", "", "") |
| 95 | DEF_ATTRIB(COF, "Change-of-flow instruction", "", "") |
| 96 | DEF_ATTRIB(HINTED_COF, "This instruction is a hinted change-of-flow", "", "") |
| 97 | DEF_ATTRIB(CONDEXEC, "May be cancelled by a predicate", "", "") |
| 98 | DEF_ATTRIB(DOTNEWVALUE, "Uses a register value generated in this pkt", "", "") |
| 99 | DEF_ATTRIB(NEWCMPJUMP, "Compound compare and jump", "", "") |
| 100 | DEF_ATTRIB(NVSTORE, "New-value store", "", "") |
| 101 | DEF_ATTRIB(MEMOP, "memop", "", "") |
| 102 | |
| 103 | DEF_ATTRIB(ROPS_2, "Compound instruction worth 2 RISC-ops", "", "") |
| 104 | DEF_ATTRIB(ROPS_3, "Compound instruction worth 3 RISC-ops", "", "") |
| 105 | |
| 106 | /* access to implicit registers */ |
| 107 | DEF_ATTRIB(IMPLICIT_WRITES_LR, "Writes the link register", "", "UREG.LR") |
| 108 | DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the program counter", "UREG.PC", "") |
| 109 | DEF_ATTRIB(IMPLICIT_WRITES_SP, "Writes the stack pointer", "", "UREG.SP") |
| 110 | DEF_ATTRIB(IMPLICIT_READS_SP, "Reads the stack pointer", "UREG.SP", "") |
| 111 | DEF_ATTRIB(IMPLICIT_WRITES_FP, "Writes the frame pointer", "", "UREG.FP") |
| 112 | DEF_ATTRIB(IMPLICIT_WRITES_LC0, "Writes loop count for loop 0", "", "UREG.LC0") |
| 113 | DEF_ATTRIB(IMPLICIT_WRITES_LC1, "Writes loop count for loop 1", "", "UREG.LC1") |
| 114 | DEF_ATTRIB(IMPLICIT_WRITES_SA0, "Writes start addr for loop 0", "", "UREG.SA0") |
| 115 | DEF_ATTRIB(IMPLICIT_WRITES_SA1, "Writes start addr for loop 1", "", "UREG.SA1") |
| 116 | DEF_ATTRIB(IMPLICIT_WRITES_P0, "Writes Predicate 0", "", "UREG.P0") |
| 117 | DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", "UREG.P1") |
| 118 | DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2") |
| 119 | DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3") |
| 120 | DEF_ATTRIB(IMPLICIT_READS_P0, "Reads Predicate 0", "UREG.P0", "") |
| 121 | DEF_ATTRIB(IMPLICIT_READS_P1, "Reads Predicate 1", "UREG.P1", "") |
| 122 | DEF_ATTRIB(IMPLICIT_READS_P3, "Reads Predicate 3", "UREG.P3", "") |
| 123 | DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "") |
| 124 | DEF_ATTRIB(IMPLICIT_WRITES_CCR, "Writes CCR register", "", "UREG.CCR") |
| 125 | DEF_ATTRIB(IMPLICIT_WRITES_GOSP, "Writes GOSP register", "", "UREG.GOSP") |
| 126 | DEF_ATTRIB(IMPLICIT_WRITES_SSR, "Writes SSR register", "", "UREG.SSR") |
| 127 | DEF_ATTRIB(IMPLICIT_WRITES_SGP0, "Writes SGP0 register", "", "UREG.SGP0") |
| 128 | DEF_ATTRIB(IMPLICIT_WRITES_SGP1, "Writes SGP1 register", "", "UREG.SGP1") |
| 129 | DEF_ATTRIB(IMPLICIT_WRITES_IMASK_ANYTHREAD, |
| 130 | "Writes IMASK for any thread", "", "") |
| 131 | DEF_ATTRIB(IMPLICIT_WRITES_STID_PRIO_ANYTHREAD, |
| 132 | "Writes STID priority for any thread", "", "") |
| 133 | DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "") |
| 134 | DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "") |
| 135 | DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "") |
| 136 | |
| 137 | DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "") |
| 138 | DEF_ATTRIB(IT_NOP, "nop instruction", "", "") |
| 139 | DEF_ATTRIB(IT_EXTENDER, "constant extender instruction", "", "") |
| 140 | |
| 141 | |
| 142 | /* Restrictions to make note of */ |
| 143 | DEF_ATTRIB(RESTRICT_COF_MAX1, "One change-of-flow per packet", "", "") |
| 144 | DEF_ATTRIB(RESTRICT_NOPACKET, "Not allowed in a packet", "", "") |
| 145 | DEF_ATTRIB(RESTRICT_SLOT0ONLY, "Must execute on slot0", "", "") |
| 146 | DEF_ATTRIB(RESTRICT_SLOT1ONLY, "Must execute on slot1", "", "") |
| 147 | DEF_ATTRIB(RESTRICT_SLOT2ONLY, "Must execute on slot2", "", "") |
| 148 | DEF_ATTRIB(RESTRICT_SLOT3ONLY, "Must execute on slot3", "", "") |
| 149 | DEF_ATTRIB(RESTRICT_NOSLOT1, "No slot 1 instruction in parallel", "", "") |
| 150 | DEF_ATTRIB(RESTRICT_PREFERSLOT0, "Try to encode into slot 0", "", "") |
| 151 | DEF_ATTRIB(RESTRICT_PACKET_AXOK, "May exist with A-type or X-type", "", "") |
| 152 | DEF_ATTRIB(RESTRICT_SLOT1_AOK, "Slot 1 is allowed", "", "") |
| 153 | |
| 154 | DEF_ATTRIB(ICOP, "Instruction cache op", "", "") |
| 155 | |
| 156 | DEF_ATTRIB(EXCEPTION_SWI, "Software interrupt exception", "", "") |
| 157 | DEF_ATTRIB(DMA, "DMA instruction", "", "") |
| 158 | DEF_ATTRIB(NO_TIMING_LOG, "Does not get logged to the timing model", "", "") |
| 159 | |
| 160 | DEF_ATTRIB(HWLOOP0_END, "Ends HW loop0", "", "") |
| 161 | DEF_ATTRIB(HWLOOP1_END, "Ends HW loop1", "", "") |
| 162 | DEF_ATTRIB(RET_TYPE, "return type", "", "") |
| 163 | DEF_ATTRIB(DCZEROA, "dczeroa type", "", "") |
| 164 | DEF_ATTRIB(ICFLUSHOP, "icflush op type", "", "") |
| 165 | DEF_ATTRIB(DCFLUSHOP, "dcflush op type", "", "") |
| 166 | DEF_ATTRIB(L2FLUSHOP, "l2flush op type", "", "") |
| 167 | DEF_ATTRIB(DCFETCH, "dcfetch type", "", "") |
| 168 | |
| 169 | DEF_ATTRIB(L2FETCH, "Instruction is l2fetch type", "", "") |
| 170 | |
| 171 | DEF_ATTRIB(DCTAGOP, "Data cache tag operation", "", "") |
| 172 | DEF_ATTRIB(ICTAGOP, "Instruction cache tag operation", "", "") |
| 173 | DEF_ATTRIB(L2TAGOP, "L2 cache tag operation", "", "") |
| 174 | |
| 175 | DEF_ATTRIB(ICINVA, "icinva", "", "") |
| 176 | DEF_ATTRIB(DCCLEANINVA, "dccleaninva", "", "") |
| 177 | |
| 178 | DEF_ATTRIB(NO_INTRINSIC, "Don't generate an intrisic", "", "") |
| 179 | |
| 180 | /* Documentation Notes */ |
| 181 | DEF_ATTRIB(NOTE_CONDITIONAL, "can be conditionally executed", "", "") |
| 182 | DEF_ATTRIB(NOTE_NEWVAL_SLOT0, "New-value oprnd must execute on slot 0", "", "") |
| 183 | DEF_ATTRIB(NOTE_PRIV, "Monitor-level feature", "", "") |
| 184 | DEF_ATTRIB(NOTE_NOPACKET, "solo instruction", "", "") |
| 185 | DEF_ATTRIB(NOTE_AXOK, "May only be grouped with ALU32 or non-FP XTYPE.", "", "") |
| 186 | DEF_ATTRIB(NOTE_LATEPRED, "The predicate can not be used as a .new", "", "") |
| 187 | DEF_ATTRIB(NOTE_NVSLOT0, "Can execute only in slot 0 (ST)", "", "") |
| 188 | DEF_ATTRIB(NOTE_NOVP, "Cannot be paired with a HVX permute instruction", "", "") |
| 189 | DEF_ATTRIB(NOTE_VA_UNARY, "Combined with HVX ALU op (must be unary)", "", "") |
| 190 | DEF_ATTRIB(NOTE_SLOT1_AOK, "Slot 1 is allowed", "", "") |
| 191 | DEF_ATTRIB(NOTE_GUEST, "Guest mode instruction", "", "") |
| 192 | DEF_ATTRIB(NOTE_BADTAG_UNDEF, "Bad tag results in undefined behavior", "", "") |
| 193 | |
| 194 | /* V6 MMVector Notes for Documentation */ |
| 195 | DEF_ATTRIB(NOTE_SHIFT_RESOURCE, "Uses the HVX shift resource.", "", "") |
| 196 | /* Restrictions to make note of */ |
| 197 | DEF_ATTRIB(RESTRICT_NOSLOT1_STORE, "Packet must not have slot 1 store", "", "") |
| 198 | DEF_ATTRIB(RESTRICT_LATEPRED, "Predicate can not be used as a .new.", "", "") |
| 199 | |
| 200 | /* HVX IEEE FP extension attributes */ |
| 201 | DEF_ATTRIB(HVX_IEEE_FP, "HVX IEEE FP extension instruction", "", "") |
| 202 | DEF_ATTRIB(HVX_IEEE_FP_ACC, "HVX IEEE FP accumulate instruction", "", "") |
| 203 | DEF_ATTRIB(HVX_IEEE_FP_OUT_16, "HVX IEEE FP 16-bit output", "", "") |
| 204 | DEF_ATTRIB(HVX_IEEE_FP_OUT_32, "HVX IEEE FP 32-bit output", "", "") |
| 205 | DEF_ATTRIB(CVI_VX_NO_TMP_LD, "HVX multiply without tmp load", "", "") |
| 206 | DEF_ATTRIB(HVX_FLT, "This a floating point HVX instruction.", "", "") |
| 207 | |
| 208 | /* Keep this as the last attribute: */ |
| 209 | DEF_ATTRIB(ZZ_LASTATTRIB, "Last attribute in the file", "", "") |