| 1 | /* |
| 2 | * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | #ifndef HEXAGON_CPU_H |
| 19 | #define HEXAGON_CPU_H |
| 20 | |
| 21 | #include "fpu/softfloat-types.h" |
| 22 | |
| 23 | #ifndef CONFIG_USER_ONLY |
| 24 | #define NUM_GREGS 32 |
| 25 | #define GREG_WRITES_MAX 2 |
| 26 | #define NUM_SREGS 64 |
| 27 | #define SREG_WRITES_MAX 2 |
| 28 | #endif |
| 29 | |
| 30 | typedef struct HexagonTLBState HexagonTLBState; |
| 31 | typedef struct HexagonGlobalRegState HexagonGlobalRegState; |
| 32 | |
| 33 | #include "cpu-qom.h" |
| 34 | #include "exec/cpu-common.h" |
| 35 | #include "exec/target_long.h" |
| 36 | #include "hex_regs.h" |
| 37 | #include "mmvec/mmvec.h" |
| 38 | #include "hw/core/registerfields.h" |
| 39 | #include "qemu/bitmap.h" |
| 40 | |
| 41 | #include "target/hexagon/reg_fields.h" |
| 42 | #include "hw/intc/hex-l2vic.h" |
| 43 | |
| 44 | #define NUM_PREGS 4 |
| 45 | #define TOTAL_PER_THREAD_REGS 64 |
| 46 | |
| 47 | #define SLOTS_MAX 4 |
| 48 | #define STORES_MAX 2 |
| 49 | #define REG_WRITES_MAX 32 |
| 50 | #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ |
| 51 | #define VSTORES_MAX 2 |
| 52 | #define MAX_TLB_ENTRIES 1024 |
| 53 | #define THREADS_MAX 8 |
| 54 | |
| 55 | #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU |
| 56 | #ifndef CONFIG_USER_ONLY |
| 57 | #define CPU_INTERRUPT_SWI CPU_INTERRUPT_TGT_INT_0 |
| 58 | #define CPU_INTERRUPT_K0_UNLOCK CPU_INTERRUPT_TGT_INT_1 |
| 59 | #define CPU_INTERRUPT_TLB_UNLOCK CPU_INTERRUPT_TGT_INT_2 |
| 60 | |
| 61 | #define HEX_CPU_MODE_USER 1 |
| 62 | #define HEX_CPU_MODE_GUEST 2 |
| 63 | #define HEX_CPU_MODE_MONITOR 3 |
| 64 | |
| 65 | #define HEX_EXE_MODE_OFF 1 |
| 66 | #define HEX_EXE_MODE_RUN 2 |
| 67 | #define HEX_EXE_MODE_WAIT 3 |
| 68 | #define HEX_EXE_MODE_DEBUG 4 |
| 69 | #endif |
| 70 | |
| 71 | #define MMU_USER_IDX 0 |
| 72 | #ifndef CONFIG_USER_ONLY |
| 73 | #define MMU_GUEST_IDX 1 |
| 74 | #define MMU_KERNEL_IDX 2 |
| 75 | |
| 76 | typedef enum { |
| 77 | HEX_LOCK_UNLOCKED = 0, |
| 78 | HEX_LOCK_WAITING = 1, |
| 79 | HEX_LOCK_OWNER = 2, |
| 80 | HEX_LOCK_QUEUED = 3 |
| 81 | } hex_lock_state_t; |
| 82 | #endif |
| 83 | |
| 84 | |
| 85 | #define HEXAGON_CPU_IRQ_0 0 |
| 86 | #define HEXAGON_CPU_IRQ_1 1 |
| 87 | #define HEXAGON_CPU_IRQ_2 2 |
| 88 | #define HEXAGON_CPU_IRQ_3 3 |
| 89 | #define HEXAGON_CPU_IRQ_4 4 |
| 90 | #define HEXAGON_CPU_IRQ_5 5 |
| 91 | #define HEXAGON_CPU_IRQ_6 6 |
| 92 | #define HEXAGON_CPU_IRQ_7 7 |
| 93 | |
| 94 | typedef struct { |
| 95 | target_ulong va; |
| 96 | uint32_t width; |
| 97 | uint32_t data32; |
| 98 | uint64_t data64; |
| 99 | } MemLog; |
| 100 | |
| 101 | typedef struct { |
| 102 | target_ulong va; |
| 103 | int size; |
| 104 | DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16); |
| 105 | MMVector data QEMU_ALIGNED(16); |
| 106 | } VStoreLog; |
| 107 | |
| 108 | #define EXEC_STATUS_OK 0x0000 |
| 109 | #define EXEC_STATUS_STOP 0x0002 |
| 110 | #define EXEC_STATUS_REPLAY 0x0010 |
| 111 | #define EXEC_STATUS_LOCKED 0x0020 |
| 112 | #define EXEC_STATUS_EXCEPTION 0x0100 |
| 113 | |
| 114 | |
| 115 | #define EXCEPTION_DETECTED (env->status & EXEC_STATUS_EXCEPTION) |
| 116 | #define REPLAY_DETECTED (env->status & EXEC_STATUS_REPLAY) |
| 117 | #define CLEAR_EXCEPTION (env->status &= (~EXEC_STATUS_EXCEPTION)) |
| 118 | #define SET_EXCEPTION (env->status |= EXEC_STATUS_EXCEPTION) |
| 119 | |
| 120 | /* Maximum number of vector temps in a packet */ |
| 121 | #define VECTOR_TEMPS_MAX 4 |
| 122 | |
| 123 | typedef struct CPUArchState { |
| 124 | target_ulong gpr[TOTAL_PER_THREAD_REGS]; |
| 125 | target_ulong pred[NUM_PREGS]; |
| 126 | uint32_t cause_code; |
| 127 | |
| 128 | /* For comparing with LLDB on target - see adjust_stack_ptrs function */ |
| 129 | target_ulong last_pc_dumped; |
| 130 | target_ulong stack_start; |
| 131 | |
| 132 | uint8_t slot_cancelled; |
| 133 | |
| 134 | #ifndef CONFIG_USER_ONLY |
| 135 | /* Some system registers are per thread and some are global. */ |
| 136 | uint32_t t_sreg[NUM_SREGS]; |
| 137 | |
| 138 | uint32_t greg[NUM_GREGS]; |
| 139 | uint32_t wait_next_pc; |
| 140 | |
| 141 | /* This alias of CPUState.cpu_index is used by imported sources: */ |
| 142 | uint32_t threadId; |
| 143 | hex_lock_state_t tlb_lock_state; |
| 144 | hex_lock_state_t k0_lock_state; |
| 145 | uint32_t tlb_lock_count; |
| 146 | uint32_t k0_lock_count; |
| 147 | uint64_t t_cycle_count; |
| 148 | #endif |
| 149 | uint32_t next_PC; |
| 150 | target_ulong new_value_usr; |
| 151 | |
| 152 | MemLog mem_log_stores[STORES_MAX]; |
| 153 | |
| 154 | float_status fp_status; |
| 155 | float_status hvx_fp_status; |
| 156 | |
| 157 | target_ulong llsc_addr; |
| 158 | target_ulong llsc_val; |
| 159 | uint64_t llsc_val_i64; |
| 160 | |
| 161 | MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16); |
| 162 | MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); |
| 163 | MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); |
| 164 | |
| 165 | MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16); |
| 166 | MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16); |
| 167 | |
| 168 | /* Temporaries used within instructions */ |
| 169 | MMVectorPair VuuV QEMU_ALIGNED(16); |
| 170 | MMVectorPair VvvV QEMU_ALIGNED(16); |
| 171 | MMVectorPair VxxV QEMU_ALIGNED(16); |
| 172 | MMVector vtmp QEMU_ALIGNED(16); |
| 173 | MMQReg qtmp QEMU_ALIGNED(16); |
| 174 | |
| 175 | VStoreLog vstore[VSTORES_MAX]; |
| 176 | target_ulong vstore_pending[VSTORES_MAX]; |
| 177 | bool vtcm_pending; |
| 178 | VTCMStoreLog vtcm_log; |
| 179 | } CPUHexagonState; |
| 180 | |
| 181 | typedef struct HexagonCPUClass { |
| 182 | CPUClass parent_class; |
| 183 | |
| 184 | DeviceRealize parent_realize; |
| 185 | ResettablePhases parent_phases; |
| 186 | |
| 187 | const HexagonCPUDef *hex_def; |
| 188 | } HexagonCPUClass; |
| 189 | |
| 190 | #include "cpu_bits.h" |
| 191 | |
| 192 | struct ArchCPU { |
| 193 | CPUState parent_obj; |
| 194 | |
| 195 | CPUHexagonState env; |
| 196 | HexagonCPUConfig cfg; |
| 197 | #ifndef CONFIG_USER_ONLY |
| 198 | HexagonTLBState *tlb; |
| 199 | uint32_t boot_addr; |
| 200 | HexagonGlobalRegState *globalregs; |
| 201 | uint32_t htid; |
| 202 | HexL2VicInterface *l2vic; |
| 203 | #endif |
| 204 | }; |
| 205 | |
| 206 | FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) |
| 207 | FIELD(TB_FLAGS, MMU_INDEX, 1, 3) |
| 208 | FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1) |
| 209 | |
| 210 | G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, |
| 211 | uint32_t exception, |
| 212 | uintptr_t pc); |
| 213 | |
| 214 | #ifndef CONFIG_USER_ONLY |
| 215 | /* |
| 216 | * @return true if the @a thread_env hardware thread is |
| 217 | * not stopped. |
| 218 | */ |
| 219 | bool hexagon_thread_is_enabled(CPUHexagonState *thread_env); |
| 220 | uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg); |
| 221 | void hexagon_cpu_soft_reset(CPUHexagonState *env); |
| 222 | #endif |
| 223 | |
| 224 | typedef HexagonCPU ArchCPU; |
| 225 | |
| 226 | void hexagon_translate_init(void); |
| 227 | void hexagon_translate_code(CPUState *cs, TranslationBlock *tb, |
| 228 | int *max_insns, vaddr pc, void *host_pc); |
| 229 | |
| 230 | #endif /* HEXAGON_CPU_H */ |