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1 /*
2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef HEXAGON_CPU_BITS_H
19 #define HEXAGON_CPU_BITS_H
20
21 #include "qemu/bitops.h"
22 #include "cpu-qom.h"
23
24 typedef struct HexagonCPUConfig {
25 bool lldb_compat;
26 uint32_t lldb_stack_adjust;
27 bool short_circuit;
28 bool ieee_fp_extension;
29 const HexagonCPUDef *hex_def;
30 } HexagonCPUConfig;
31
32 #define PCALIGN 4
33 #define PCALIGN_MASK (PCALIGN - 1)
34
35 enum hex_event {
36 HEX_EVENT_NONE = -1,
37 HEX_EVENT_RESET = 0x0,
38 HEX_EVENT_IMPRECISE = 0x1,
39 HEX_EVENT_PRECISE = 0x2,
40 HEX_EVENT_TLB_MISS_X = 0x4,
41 HEX_EVENT_TLB_MISS_RW = 0x6,
42 HEX_EVENT_TRAP0 = 0x8,
43 HEX_EVENT_TRAP1 = 0x9,
44 HEX_EVENT_FPTRAP = 0xb,
45 HEX_EVENT_DEBUG = 0xc,
46 HEX_EVENT_INT0 = 0x10,
47 HEX_EVENT_INT1 = 0x11,
48 HEX_EVENT_INT2 = 0x12,
49 HEX_EVENT_INT3 = 0x13,
50 HEX_EVENT_INT4 = 0x14,
51 HEX_EVENT_INT5 = 0x15,
52 HEX_EVENT_INT6 = 0x16,
53 HEX_EVENT_INT7 = 0x17,
54 HEX_EVENT_INT8 = 0x18,
55 HEX_EVENT_INT9 = 0x19,
56 HEX_EVENT_INTA = 0x1a,
57 HEX_EVENT_INTB = 0x1b,
58 HEX_EVENT_INTC = 0x1c,
59 HEX_EVENT_INTD = 0x1d,
60 HEX_EVENT_INTE = 0x1e,
61 HEX_EVENT_INTF = 0x1f,
62 };
63
64 enum hex_cause {
65 HEX_CAUSE_NONE = -1,
66 HEX_CAUSE_RESET = 0x000,
67 HEX_CAUSE_BIU_PRECISE = 0x001,
68 HEX_CAUSE_UNSUPPORTED_HVX_64B = 0x002, /* QEMU-specific */
69 HEX_CAUSE_DOUBLE_EXCEPT = 0x003,
70 HEX_CAUSE_TRAP0 = 0x008,
71 HEX_CAUSE_TRAP1 = 0x009,
72 HEX_CAUSE_FETCH_NO_XPAGE = 0x011,
73 HEX_CAUSE_FETCH_NO_UPAGE = 0x012,
74 HEX_CAUSE_INVALID_PACKET = 0x015,
75 HEX_CAUSE_INVALID_OPCODE = 0x015, /* alias: same cause as INVALID_PACKET */
76 HEX_CAUSE_NO_COPROC_ENABLE = 0x016,
77 HEX_CAUSE_NO_COPROC2_ENABLE = 0x018,
78 HEX_CAUSE_PRIV_USER_NO_GINSN = 0x01a,
79 HEX_CAUSE_PRIV_USER_NO_SINSN = 0x01b,
80 HEX_CAUSE_REG_WRITE_CONFLICT = 0x01d,
81 HEX_CAUSE_PC_NOT_ALIGNED = 0x01e,
82 HEX_CAUSE_MISALIGNED_LOAD = 0x020,
83 HEX_CAUSE_MISALIGNED_STORE = 0x021,
84 HEX_CAUSE_PRIV_NO_READ = 0x022,
85 HEX_CAUSE_PRIV_NO_WRITE = 0x023,
86 HEX_CAUSE_PRIV_NO_UREAD = 0x024,
87 HEX_CAUSE_PRIV_NO_UWRITE = 0x025,
88 HEX_CAUSE_COPROC_LDST = 0x026,
89 HEX_CAUSE_STACK_LIMIT = 0x027,
90 HEX_CAUSE_VWCTRL_WINDOW_MISS = 0x029,
91 HEX_CAUSE_IMPRECISE_NMI = 0x043,
92 HEX_CAUSE_IMPRECISE_MULTI_TLB_MATCH = 0x044,
93 HEX_CAUSE_TLBMISSX_CAUSE_NORMAL = 0x060,
94 HEX_CAUSE_TLBMISSX_CAUSE_NEXTPAGE = 0x061,
95 HEX_CAUSE_TLBMISSRW_CAUSE_READ = 0x070,
96 HEX_CAUSE_TLBMISSRW_CAUSE_WRITE = 0x071,
97 HEX_CAUSE_DEBUG_SINGLESTEP = 0x80,
98 HEX_CAUSE_FPTRAP_CAUSE_BADFLOAT = 0x0bf,
99 HEX_CAUSE_INT0 = 0x0c0,
100 HEX_CAUSE_INT1 = 0x0c1,
101 HEX_CAUSE_INT2 = 0x0c2,
102 HEX_CAUSE_INT3 = 0x0c3,
103 HEX_CAUSE_INT4 = 0x0c4,
104 HEX_CAUSE_INT5 = 0x0c5,
105 HEX_CAUSE_INT6 = 0x0c6,
106 HEX_CAUSE_INT7 = 0x0c7,
107 };
108
109 #define PACKET_WORDS_MAX 4
110
111 static inline uint32_t parse_bits(uint32_t encoding)
112 {
113 /* The parse bits are [15:14] */
114 return extract32(encoding, 14, 2);
115 }
116
117 static inline uint32_t iclass_bits(uint32_t encoding)
118 {
119 /* The instruction class is encoded in bits [31:28] */
120 uint32_t iclass = extract32(encoding, 28, 4);
121 /* If parse bits are zero, this is a duplex */
122 if (parse_bits(encoding) == 0) {
123 iclass += 16;
124 }
125 return iclass;
126 }
127
128 static inline bool is_packet_end(uint32_t endocing)
129 {
130 uint32_t bits = parse_bits(endocing);
131 return ((bits == 0x3) || (bits == 0x0));
132 }
133
134 int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc,
135 GString *buf, const HexagonCPUConfig *cfg);
136
137 #endif