| 1 | /* |
| 2 | * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | #ifndef HEXAGON_GEN_TCG_HVX_H |
| 19 | #define HEXAGON_GEN_TCG_HVX_H |
| 20 | |
| 21 | /* |
| 22 | * Histogram instructions |
| 23 | * |
| 24 | * Note that these instructions operate directly on the vector registers |
| 25 | * and therefore happen after commit. |
| 26 | * |
| 27 | * The generate_<tag> function is called twice |
| 28 | * The first time is during the normal TCG generation |
| 29 | * ctx->pre_commit is true |
| 30 | * In the masked cases, we save the mask to the qtmp temporary |
| 31 | * Otherwise, there is nothing to do |
| 32 | * The second call is at the end of gen_commit_packet |
| 33 | * ctx->pre_commit is false |
| 34 | * Generate the call to the helper |
| 35 | */ |
| 36 | |
| 37 | static inline void assert_vhist_tmp(DisasContext *ctx) |
| 38 | { |
| 39 | /* vhist instructions require exactly one .tmp to be defined */ |
| 40 | g_assert(ctx->tmp_vregs_idx == 1); |
| 41 | } |
| 42 | |
| 43 | #define fGEN_TCG_V6_vhist(SHORTCODE) \ |
| 44 | if (!ctx->pre_commit) { \ |
| 45 | assert_vhist_tmp(ctx); \ |
| 46 | gen_helper_vhist(tcg_env); \ |
| 47 | } |
| 48 | #define fGEN_TCG_V6_vhistq(SHORTCODE) \ |
| 49 | do { \ |
| 50 | if (ctx->pre_commit) { \ |
| 51 | intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \ |
| 52 | tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ |
| 53 | sizeof(MMVector), sizeof(MMVector)); \ |
| 54 | } else { \ |
| 55 | assert_vhist_tmp(ctx); \ |
| 56 | gen_helper_vhistq(tcg_env); \ |
| 57 | } \ |
| 58 | } while (0) |
| 59 | #define fGEN_TCG_V6_vwhist256(SHORTCODE) \ |
| 60 | if (!ctx->pre_commit) { \ |
| 61 | assert_vhist_tmp(ctx); \ |
| 62 | gen_helper_vwhist256(tcg_env); \ |
| 63 | } |
| 64 | #define fGEN_TCG_V6_vwhist256q(SHORTCODE) \ |
| 65 | do { \ |
| 66 | if (ctx->pre_commit) { \ |
| 67 | intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \ |
| 68 | tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ |
| 69 | sizeof(MMVector), sizeof(MMVector)); \ |
| 70 | } else { \ |
| 71 | assert_vhist_tmp(ctx); \ |
| 72 | gen_helper_vwhist256q(tcg_env); \ |
| 73 | } \ |
| 74 | } while (0) |
| 75 | #define fGEN_TCG_V6_vwhist256_sat(SHORTCODE) \ |
| 76 | if (!ctx->pre_commit) { \ |
| 77 | assert_vhist_tmp(ctx); \ |
| 78 | gen_helper_vwhist256_sat(tcg_env); \ |
| 79 | } |
| 80 | #define fGEN_TCG_V6_vwhist256q_sat(SHORTCODE) \ |
| 81 | do { \ |
| 82 | if (ctx->pre_commit) { \ |
| 83 | intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \ |
| 84 | tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ |
| 85 | sizeof(MMVector), sizeof(MMVector)); \ |
| 86 | } else { \ |
| 87 | assert_vhist_tmp(ctx); \ |
| 88 | gen_helper_vwhist256q_sat(tcg_env); \ |
| 89 | } \ |
| 90 | } while (0) |
| 91 | #define fGEN_TCG_V6_vwhist128(SHORTCODE) \ |
| 92 | if (!ctx->pre_commit) { \ |
| 93 | assert_vhist_tmp(ctx); \ |
| 94 | gen_helper_vwhist128(tcg_env); \ |
| 95 | } |
| 96 | #define fGEN_TCG_V6_vwhist128q(SHORTCODE) \ |
| 97 | do { \ |
| 98 | if (ctx->pre_commit) { \ |
| 99 | intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \ |
| 100 | tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ |
| 101 | sizeof(MMVector), sizeof(MMVector)); \ |
| 102 | } else { \ |
| 103 | assert_vhist_tmp(ctx); \ |
| 104 | gen_helper_vwhist128q(tcg_env); \ |
| 105 | } \ |
| 106 | } while (0) |
| 107 | #define fGEN_TCG_V6_vwhist128m(SHORTCODE) \ |
| 108 | if (!ctx->pre_commit) { \ |
| 109 | TCGv tcgv_uiV = tcg_constant_tl(uiV); \ |
| 110 | assert_vhist_tmp(ctx); \ |
| 111 | gen_helper_vwhist128m(tcg_env, tcgv_uiV); \ |
| 112 | } |
| 113 | #define fGEN_TCG_V6_vwhist128qm(SHORTCODE) \ |
| 114 | do { \ |
| 115 | if (ctx->pre_commit) { \ |
| 116 | intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \ |
| 117 | tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ |
| 118 | sizeof(MMVector), sizeof(MMVector)); \ |
| 119 | } else { \ |
| 120 | TCGv tcgv_uiV = tcg_constant_tl(uiV); \ |
| 121 | assert_vhist_tmp(ctx); \ |
| 122 | gen_helper_vwhist128qm(tcg_env, tcgv_uiV); \ |
| 123 | } \ |
| 124 | } while (0) |
| 125 | |
| 126 | |
| 127 | #define fGEN_TCG_V6_vassign(SHORTCODE) \ |
| 128 | tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \ |
| 129 | sizeof(MMVector), sizeof(MMVector)) |
| 130 | |
| 131 | #define fGEN_TCG_V6_vassign_tmp(SHORTCODE) \ |
| 132 | tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \ |
| 133 | sizeof(MMVector), sizeof(MMVector)) |
| 134 | |
| 135 | #define fGEN_TCG_V6_vcombine_tmp(SHORTCODE) \ |
| 136 | do { \ |
| 137 | tcg_gen_gvec_mov(MO_64, VddV_off, VvV_off, \ |
| 138 | sizeof(MMVector), sizeof(MMVector)); \ |
| 139 | tcg_gen_gvec_mov(MO_64, VddV_off + sizeof(MMVector), VuV_off, \ |
| 140 | sizeof(MMVector), sizeof(MMVector)); \ |
| 141 | } while (0) |
| 142 | |
| 143 | /* |
| 144 | * Vector combine |
| 145 | * |
| 146 | * Be careful that the source and dest don't overlap |
| 147 | */ |
| 148 | #define fGEN_TCG_V6_vcombine(SHORTCODE) \ |
| 149 | do { \ |
| 150 | if (VddV_off != VuV_off) { \ |
| 151 | tcg_gen_gvec_mov(MO_64, VddV_off, VvV_off, \ |
| 152 | sizeof(MMVector), sizeof(MMVector)); \ |
| 153 | tcg_gen_gvec_mov(MO_64, VddV_off + sizeof(MMVector), VuV_off, \ |
| 154 | sizeof(MMVector), sizeof(MMVector)); \ |
| 155 | } else { \ |
| 156 | intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \ |
| 157 | tcg_gen_gvec_mov(MO_64, tmpoff, VuV_off, \ |
| 158 | sizeof(MMVector), sizeof(MMVector)); \ |
| 159 | tcg_gen_gvec_mov(MO_64, VddV_off, VvV_off, \ |
| 160 | sizeof(MMVector), sizeof(MMVector)); \ |
| 161 | tcg_gen_gvec_mov(MO_64, VddV_off + sizeof(MMVector), tmpoff, \ |
| 162 | sizeof(MMVector), sizeof(MMVector)); \ |
| 163 | } \ |
| 164 | } while (0) |
| 165 | |
| 166 | /* Vector conditional move */ |
| 167 | #define fGEN_TCG_VEC_CMOV(PRED) \ |
| 168 | do { \ |
| 169 | TCGv lsb = tcg_temp_new(); \ |
| 170 | TCGLabel *false_label = gen_new_label(); \ |
| 171 | tcg_gen_andi_tl(lsb, PsV, 1); \ |
| 172 | tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \ |
| 173 | tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \ |
| 174 | sizeof(MMVector), sizeof(MMVector)); \ |
| 175 | gen_set_label(false_label); \ |
| 176 | } while (0) |
| 177 | |
| 178 | |
| 179 | /* Vector conditional move (true) */ |
| 180 | #define fGEN_TCG_V6_vcmov(SHORTCODE) \ |
| 181 | fGEN_TCG_VEC_CMOV(1) |
| 182 | |
| 183 | /* Vector conditional move (false) */ |
| 184 | #define fGEN_TCG_V6_vncmov(SHORTCODE) \ |
| 185 | fGEN_TCG_VEC_CMOV(0) |
| 186 | |
| 187 | /* Vector add - various forms */ |
| 188 | #define fGEN_TCG_V6_vaddb(SHORTCODE) \ |
| 189 | tcg_gen_gvec_add(MO_8, VdV_off, VuV_off, VvV_off, \ |
| 190 | sizeof(MMVector), sizeof(MMVector)) |
| 191 | |
| 192 | #define fGEN_TCG_V6_vaddh(SHORTCYDE) \ |
| 193 | tcg_gen_gvec_add(MO_16, VdV_off, VuV_off, VvV_off, \ |
| 194 | sizeof(MMVector), sizeof(MMVector)) |
| 195 | |
| 196 | #define fGEN_TCG_V6_vaddw(SHORTCODE) \ |
| 197 | tcg_gen_gvec_add(MO_32, VdV_off, VuV_off, VvV_off, \ |
| 198 | sizeof(MMVector), sizeof(MMVector)) |
| 199 | |
| 200 | #define fGEN_TCG_V6_vaddb_dv(SHORTCODE) \ |
| 201 | tcg_gen_gvec_add(MO_8, VddV_off, VuuV_off, VvvV_off, \ |
| 202 | sizeof(MMVector) * 2, sizeof(MMVector) * 2) |
| 203 | |
| 204 | #define fGEN_TCG_V6_vaddh_dv(SHORTCYDE) \ |
| 205 | tcg_gen_gvec_add(MO_16, VddV_off, VuuV_off, VvvV_off, \ |
| 206 | sizeof(MMVector) * 2, sizeof(MMVector) * 2) |
| 207 | |
| 208 | #define fGEN_TCG_V6_vaddw_dv(SHORTCODE) \ |
| 209 | tcg_gen_gvec_add(MO_32, VddV_off, VuuV_off, VvvV_off, \ |
| 210 | sizeof(MMVector) * 2, sizeof(MMVector) * 2) |
| 211 | |
| 212 | /* Vector sub - various forms */ |
| 213 | #define fGEN_TCG_V6_vsubb(SHORTCODE) \ |
| 214 | tcg_gen_gvec_sub(MO_8, VdV_off, VuV_off, VvV_off, \ |
| 215 | sizeof(MMVector), sizeof(MMVector)) |
| 216 | |
| 217 | #define fGEN_TCG_V6_vsubh(SHORTCODE) \ |
| 218 | tcg_gen_gvec_sub(MO_16, VdV_off, VuV_off, VvV_off, \ |
| 219 | sizeof(MMVector), sizeof(MMVector)) |
| 220 | |
| 221 | #define fGEN_TCG_V6_vsubw(SHORTCODE) \ |
| 222 | tcg_gen_gvec_sub(MO_32, VdV_off, VuV_off, VvV_off, \ |
| 223 | sizeof(MMVector), sizeof(MMVector)) |
| 224 | |
| 225 | #define fGEN_TCG_V6_vsubb_dv(SHORTCODE) \ |
| 226 | tcg_gen_gvec_sub(MO_8, VddV_off, VuuV_off, VvvV_off, \ |
| 227 | sizeof(MMVector) * 2, sizeof(MMVector) * 2) |
| 228 | |
| 229 | #define fGEN_TCG_V6_vsubh_dv(SHORTCODE) \ |
| 230 | tcg_gen_gvec_sub(MO_16, VddV_off, VuuV_off, VvvV_off, \ |
| 231 | sizeof(MMVector) * 2, sizeof(MMVector) * 2) |
| 232 | |
| 233 | #define fGEN_TCG_V6_vsubw_dv(SHORTCODE) \ |
| 234 | tcg_gen_gvec_sub(MO_32, VddV_off, VuuV_off, VvvV_off, \ |
| 235 | sizeof(MMVector) * 2, sizeof(MMVector) * 2) |
| 236 | |
| 237 | #define fGEN_TCG_V6_vaddbsat(SHORTCODE) \ |
| 238 | tcg_gen_gvec_ssadd(MO_8, VdV_off, VuV_off, VvV_off, \ |
| 239 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 240 | |
| 241 | #define fGEN_TCG_V6_vaddhsat(SHORTCODE) \ |
| 242 | tcg_gen_gvec_ssadd(MO_16, VdV_off, VuV_off, VvV_off, \ |
| 243 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 244 | |
| 245 | #define fGEN_TCG_V6_vaddwsat(SHORTCODE) \ |
| 246 | tcg_gen_gvec_ssadd(MO_32, VdV_off, VuV_off, VvV_off, \ |
| 247 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 248 | |
| 249 | #define fGEN_TCG_V6_vaddubsat(SHORTCODE) \ |
| 250 | tcg_gen_gvec_usadd(MO_8, VdV_off, VuV_off, VvV_off, \ |
| 251 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 252 | |
| 253 | #define fGEN_TCG_V6_vadduhsat(SHORTCODE) \ |
| 254 | tcg_gen_gvec_usadd(MO_16, VdV_off, VuV_off, VvV_off, \ |
| 255 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 256 | |
| 257 | #define fGEN_TCG_V6_vadduwsat(SHORTCODE) \ |
| 258 | tcg_gen_gvec_usadd(MO_32, VdV_off, VuV_off, VvV_off, \ |
| 259 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 260 | |
| 261 | #define fGEN_TCG_PAIR_ADDSUB(OP, VECE, DST, SRC_A, SRC_B) \ |
| 262 | tcg_gen_gvec_##OP(VECE, DST, SRC_A, SRC_B, \ |
| 263 | 2 * VECTOR_SIZE_BYTE, 2 * VECTOR_SIZE_BYTE) |
| 264 | |
| 265 | #define fGEN_TCG_V6_vaddbsat_dv(SHORTCODE) \ |
| 266 | fGEN_TCG_PAIR_ADDSUB(ssadd, MO_8, VddV_off, VuuV_off, VvvV_off) |
| 267 | |
| 268 | #define fGEN_TCG_V6_vaddhsat_dv(SHORTCODE) \ |
| 269 | fGEN_TCG_PAIR_ADDSUB(ssadd, MO_16, VddV_off, VuuV_off, VvvV_off) |
| 270 | |
| 271 | #define fGEN_TCG_V6_vaddwsat_dv(SHORTCODE) \ |
| 272 | fGEN_TCG_PAIR_ADDSUB(ssadd, MO_32, VddV_off, VuuV_off, VvvV_off) |
| 273 | |
| 274 | #define fGEN_TCG_V6_vaddubsat_dv(SHORTCODE) \ |
| 275 | fGEN_TCG_PAIR_ADDSUB(usadd, MO_8, VddV_off, VuuV_off, VvvV_off) |
| 276 | |
| 277 | #define fGEN_TCG_V6_vadduhsat_dv(SHORTCODE) \ |
| 278 | fGEN_TCG_PAIR_ADDSUB(usadd, MO_16, VddV_off, VuuV_off, VvvV_off) |
| 279 | |
| 280 | #define fGEN_TCG_V6_vadduwsat_dv(SHORTCODE) \ |
| 281 | fGEN_TCG_PAIR_ADDSUB(usadd, MO_32, VddV_off, VuuV_off, VvvV_off) |
| 282 | |
| 283 | #define fGEN_TCG_V6_vsubbsat(SHORTCODE) \ |
| 284 | tcg_gen_gvec_sssub(MO_8, VdV_off, VuV_off, VvV_off, \ |
| 285 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 286 | |
| 287 | #define fGEN_TCG_V6_vsubhsat(SHORTCODE) \ |
| 288 | tcg_gen_gvec_sssub(MO_16, VdV_off, VuV_off, VvV_off, \ |
| 289 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 290 | |
| 291 | #define fGEN_TCG_V6_vsubwsat(SHORTCODE) \ |
| 292 | tcg_gen_gvec_sssub(MO_32, VdV_off, VuV_off, VvV_off, \ |
| 293 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 294 | |
| 295 | #define fGEN_TCG_V6_vsububsat(SHORTCODE) \ |
| 296 | tcg_gen_gvec_ussub(MO_8, VdV_off, VuV_off, VvV_off, \ |
| 297 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 298 | |
| 299 | #define fGEN_TCG_V6_vsubuhsat(SHORTCODE) \ |
| 300 | tcg_gen_gvec_ussub(MO_16, VdV_off, VuV_off, VvV_off, \ |
| 301 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 302 | |
| 303 | #define fGEN_TCG_V6_vsubuwsat(SHORTCODE) \ |
| 304 | tcg_gen_gvec_ussub(MO_32, VdV_off, VuV_off, VvV_off, \ |
| 305 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 306 | |
| 307 | #define fGEN_TCG_V6_vsubbsat_dv(SHORTCODE) \ |
| 308 | fGEN_TCG_PAIR_ADDSUB(sssub, MO_8, VddV_off, VuuV_off, VvvV_off) |
| 309 | |
| 310 | #define fGEN_TCG_V6_vsubhsat_dv(SHORTCODE) \ |
| 311 | fGEN_TCG_PAIR_ADDSUB(sssub, MO_16, VddV_off, VuuV_off, VvvV_off) |
| 312 | |
| 313 | #define fGEN_TCG_V6_vsubwsat_dv(SHORTCODE) \ |
| 314 | fGEN_TCG_PAIR_ADDSUB(sssub, MO_32, VddV_off, VuuV_off, VvvV_off) |
| 315 | |
| 316 | #define fGEN_TCG_V6_vsububsat_dv(SHORTCODE) \ |
| 317 | fGEN_TCG_PAIR_ADDSUB(ussub, MO_8, VddV_off, VuuV_off, VvvV_off) |
| 318 | |
| 319 | #define fGEN_TCG_V6_vsubuhsat_dv(SHORTCODE) \ |
| 320 | fGEN_TCG_PAIR_ADDSUB(ussub, MO_16, VddV_off, VuuV_off, VvvV_off) |
| 321 | |
| 322 | #define fGEN_TCG_V6_vsubuwsat_dv(SHORTCODE) \ |
| 323 | fGEN_TCG_PAIR_ADDSUB(ussub, MO_32, VddV_off, VuuV_off, VvvV_off) |
| 324 | |
| 325 | #define fGEN_TCG_V6_vmpyih(SHORTCODE) \ |
| 326 | tcg_gen_gvec_mul(MO_16, VdV_off, VuV_off, VvV_off, \ |
| 327 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 328 | |
| 329 | #define fGEN_TCG_V6_vabsdiffub(SHORTCODE) \ |
| 330 | gen_gvec_uabsdiff(MO_8, VdV_off, VuV_off, VvV_off, \ |
| 331 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 332 | |
| 333 | #define fGEN_TCG_V6_vabsdiffuh(SHORTCODE) \ |
| 334 | gen_gvec_uabsdiff(MO_16, VdV_off, VuV_off, VvV_off, \ |
| 335 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 336 | |
| 337 | #define fGEN_TCG_V6_vabsdiffh(SHORTCODE) \ |
| 338 | gen_gvec_sabsdiff(MO_16, VdV_off, VuV_off, VvV_off, \ |
| 339 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 340 | |
| 341 | #define fGEN_TCG_V6_vabsdiffw(SHORTCODE) \ |
| 342 | gen_gvec_sabsdiff(MO_32, VdV_off, VuV_off, VvV_off, \ |
| 343 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) |
| 344 | |
| 345 | #define fGEN_TCG_VEC_AVG(VECE, SHIFT_FN) \ |
| 346 | do { \ |
| 347 | intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \ |
| 348 | tcg_gen_gvec_and(MO_64, tmpoff, VuV_off, VvV_off, \ |
| 349 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ |
| 350 | tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \ |
| 351 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ |
| 352 | SHIFT_FN(VECE, VdV_off, VdV_off, 1, \ |
| 353 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ |
| 354 | tcg_gen_gvec_add(VECE, VdV_off, tmpoff, VdV_off, \ |
| 355 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ |
| 356 | } while (0) |
| 357 | |
| 358 | #define fGEN_TCG_V6_vavgub(SHORTCODE) \ |
| 359 | fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_shri) |
| 360 | |
| 361 | #define fGEN_TCG_V6_vavguh(SHORTCODE) \ |
| 362 | fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_shri) |
| 363 | |
| 364 | #define fGEN_TCG_V6_vavguw(SHORTCODE) \ |
| 365 | fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_shri) |
| 366 | |
| 367 | #define fGEN_TCG_V6_vavgb(SHORTCODE) \ |
| 368 | fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_sari) |
| 369 | |
| 370 | #define fGEN_TCG_V6_vavgh(SHORTCODE) \ |
| 371 | fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_sari) |
| 372 | |
| 373 | #define fGEN_TCG_V6_vavgw(SHORTCODE) \ |
| 374 | fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_sari) |
| 375 | |
| 376 | #define fGEN_TCG_VEC_AVGRND(VECE, SHIFT_FN) \ |
| 377 | do { \ |
| 378 | intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \ |
| 379 | tcg_gen_gvec_or(MO_64, tmpoff, VuV_off, VvV_off, \ |
| 380 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ |
| 381 | tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \ |
| 382 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ |
| 383 | SHIFT_FN(VECE, VdV_off, VdV_off, 1, \ |
| 384 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ |
| 385 | tcg_gen_gvec_sub(VECE, VdV_off, tmpoff, VdV_off, \ |
| 386 | VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ |
| 387 | } while (0) |
| 388 | |
| 389 | #define fGEN_TCG_V6_vavgubrnd(SHORTCODE) \ |
| 390 | fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_shri) |
| 391 | |
| 392 | #define fGEN_TCG_V6_vavguhrnd(SHORTCODE) \ |
| 393 | fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_shri) |
| 394 | |
| 395 | #define fGEN_TCG_V6_vavguwrnd(SHORTCODE) \ |
| 396 | fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_shri) |
| 397 | |
| 398 | #define fGEN_TCG_V6_vavgbrnd(SHORTCODE) \ |
| 399 | fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_sari) |
| 400 | |
| 401 | #define fGEN_TCG_V6_vavghrnd(SHORTCODE) \ |
| 402 | fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_sari) |
| 403 | |
| 404 | #define fGEN_TCG_V6_vavgwrnd(SHORTCODE) \ |
| 405 | fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_sari) |
| 406 | |
| 407 | /* Vector shift right - various forms */ |
| 408 | #define fGEN_TCG_V6_vasrh(SHORTCODE) \ |
| 409 | do { \ |
| 410 | TCGv shift = tcg_temp_new(); \ |
| 411 | tcg_gen_andi_tl(shift, RtV, 15); \ |
| 412 | tcg_gen_gvec_sars(MO_16, VdV_off, VuV_off, shift, \ |
| 413 | sizeof(MMVector), sizeof(MMVector)); \ |
| 414 | } while (0) |
| 415 | |
| 416 | #define fGEN_TCG_V6_vasrh_acc(SHORTCODE) \ |
| 417 | do { \ |
| 418 | intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \ |
| 419 | TCGv shift = tcg_temp_new(); \ |
| 420 | tcg_gen_andi_tl(shift, RtV, 15); \ |
| 421 | tcg_gen_gvec_sars(MO_16, tmpoff, VuV_off, shift, \ |
| 422 | sizeof(MMVector), sizeof(MMVector)); \ |
| 423 | tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \ |
| 424 | sizeof(MMVector), sizeof(MMVector)); \ |
| 425 | } while (0) |
| 426 | |
| 427 | #define fGEN_TCG_V6_vasrw(SHORTCODE) \ |
| 428 | do { \ |
| 429 | TCGv shift = tcg_temp_new(); \ |
| 430 | tcg_gen_andi_tl(shift, RtV, 31); \ |
| 431 | tcg_gen_gvec_sars(MO_32, VdV_off, VuV_off, shift, \ |
| 432 | sizeof(MMVector), sizeof(MMVector)); \ |
| 433 | } while (0) |
| 434 | |
| 435 | #define fGEN_TCG_V6_vasrw_acc(SHORTCODE) \ |
| 436 | do { \ |
| 437 | intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \ |
| 438 | TCGv shift = tcg_temp_new(); \ |
| 439 | tcg_gen_andi_tl(shift, RtV, 31); \ |
| 440 | tcg_gen_gvec_sars(MO_32, tmpoff, VuV_off, shift, \ |
| 441 | sizeof(MMVector), sizeof(MMVector)); \ |
| 442 | tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \ |
| 443 | sizeof(MMVector), sizeof(MMVector)); \ |
| 444 | } while (0) |
| 445 | |
| 446 | #define fGEN_TCG_V6_vlsrb(SHORTCODE) \ |
| 447 | do { \ |
| 448 | TCGv shift = tcg_temp_new(); \ |
| 449 | tcg_gen_andi_tl(shift, RtV, 7); \ |
| 450 | tcg_gen_gvec_shrs(MO_8, VdV_off, VuV_off, shift, \ |
| 451 | sizeof(MMVector), sizeof(MMVector)); \ |
| 452 | } while (0) |
| 453 | |
| 454 | #define fGEN_TCG_V6_vlsrh(SHORTCODE) \ |
| 455 | do { \ |
| 456 | TCGv shift = tcg_temp_new(); \ |
| 457 | tcg_gen_andi_tl(shift, RtV, 15); \ |
| 458 | tcg_gen_gvec_shrs(MO_16, VdV_off, VuV_off, shift, \ |
| 459 | sizeof(MMVector), sizeof(MMVector)); \ |
| 460 | } while (0) |
| 461 | |
| 462 | #define fGEN_TCG_V6_vlsrw(SHORTCODE) \ |
| 463 | do { \ |
| 464 | TCGv shift = tcg_temp_new(); \ |
| 465 | tcg_gen_andi_tl(shift, RtV, 31); \ |
| 466 | tcg_gen_gvec_shrs(MO_32, VdV_off, VuV_off, shift, \ |
| 467 | sizeof(MMVector), sizeof(MMVector)); \ |
| 468 | } while (0) |
| 469 | |
| 470 | /* Vector shift left - various forms */ |
| 471 | #define fGEN_TCG_V6_vaslb(SHORTCODE) \ |
| 472 | do { \ |
| 473 | TCGv shift = tcg_temp_new(); \ |
| 474 | tcg_gen_andi_tl(shift, RtV, 7); \ |
| 475 | tcg_gen_gvec_shls(MO_8, VdV_off, VuV_off, shift, \ |
| 476 | sizeof(MMVector), sizeof(MMVector)); \ |
| 477 | } while (0) |
| 478 | |
| 479 | #define fGEN_TCG_V6_vaslh(SHORTCODE) \ |
| 480 | do { \ |
| 481 | TCGv shift = tcg_temp_new(); \ |
| 482 | tcg_gen_andi_tl(shift, RtV, 15); \ |
| 483 | tcg_gen_gvec_shls(MO_16, VdV_off, VuV_off, shift, \ |
| 484 | sizeof(MMVector), sizeof(MMVector)); \ |
| 485 | } while (0) |
| 486 | |
| 487 | #define fGEN_TCG_V6_vaslh_acc(SHORTCODE) \ |
| 488 | do { \ |
| 489 | intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \ |
| 490 | TCGv shift = tcg_temp_new(); \ |
| 491 | tcg_gen_andi_tl(shift, RtV, 15); \ |
| 492 | tcg_gen_gvec_shls(MO_16, tmpoff, VuV_off, shift, \ |
| 493 | sizeof(MMVector), sizeof(MMVector)); \ |
| 494 | tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \ |
| 495 | sizeof(MMVector), sizeof(MMVector)); \ |
| 496 | } while (0) |
| 497 | |
| 498 | #define fGEN_TCG_V6_vaslw(SHORTCODE) \ |
| 499 | do { \ |
| 500 | TCGv shift = tcg_temp_new(); \ |
| 501 | tcg_gen_andi_tl(shift, RtV, 31); \ |
| 502 | tcg_gen_gvec_shls(MO_32, VdV_off, VuV_off, shift, \ |
| 503 | sizeof(MMVector), sizeof(MMVector)); \ |
| 504 | } while (0) |
| 505 | |
| 506 | #define fGEN_TCG_V6_vaslw_acc(SHORTCODE) \ |
| 507 | do { \ |
| 508 | intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \ |
| 509 | TCGv shift = tcg_temp_new(); \ |
| 510 | tcg_gen_andi_tl(shift, RtV, 31); \ |
| 511 | tcg_gen_gvec_shls(MO_32, tmpoff, VuV_off, shift, \ |
| 512 | sizeof(MMVector), sizeof(MMVector)); \ |
| 513 | tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \ |
| 514 | sizeof(MMVector), sizeof(MMVector)); \ |
| 515 | } while (0) |
| 516 | |
| 517 | /* Vector max - various forms */ |
| 518 | #define fGEN_TCG_V6_vmaxw(SHORTCODE) \ |
| 519 | tcg_gen_gvec_smax(MO_32, VdV_off, VuV_off, VvV_off, \ |
| 520 | sizeof(MMVector), sizeof(MMVector)) |
| 521 | #define fGEN_TCG_V6_vmaxh(SHORTCODE) \ |
| 522 | tcg_gen_gvec_smax(MO_16, VdV_off, VuV_off, VvV_off, \ |
| 523 | sizeof(MMVector), sizeof(MMVector)) |
| 524 | #define fGEN_TCG_V6_vmaxuh(SHORTCODE) \ |
| 525 | tcg_gen_gvec_umax(MO_16, VdV_off, VuV_off, VvV_off, \ |
| 526 | sizeof(MMVector), sizeof(MMVector)) |
| 527 | #define fGEN_TCG_V6_vmaxb(SHORTCODE) \ |
| 528 | tcg_gen_gvec_smax(MO_8, VdV_off, VuV_off, VvV_off, \ |
| 529 | sizeof(MMVector), sizeof(MMVector)) |
| 530 | #define fGEN_TCG_V6_vmaxub(SHORTCODE) \ |
| 531 | tcg_gen_gvec_umax(MO_8, VdV_off, VuV_off, VvV_off, \ |
| 532 | sizeof(MMVector), sizeof(MMVector)) |
| 533 | |
| 534 | /* Vector min - various forms */ |
| 535 | #define fGEN_TCG_V6_vminw(SHORTCODE) \ |
| 536 | tcg_gen_gvec_smin(MO_32, VdV_off, VuV_off, VvV_off, \ |
| 537 | sizeof(MMVector), sizeof(MMVector)) |
| 538 | #define fGEN_TCG_V6_vminh(SHORTCODE) \ |
| 539 | tcg_gen_gvec_smin(MO_16, VdV_off, VuV_off, VvV_off, \ |
| 540 | sizeof(MMVector), sizeof(MMVector)) |
| 541 | #define fGEN_TCG_V6_vminuh(SHORTCODE) \ |
| 542 | tcg_gen_gvec_umin(MO_16, VdV_off, VuV_off, VvV_off, \ |
| 543 | sizeof(MMVector), sizeof(MMVector)) |
| 544 | #define fGEN_TCG_V6_vminb(SHORTCODE) \ |
| 545 | tcg_gen_gvec_smin(MO_8, VdV_off, VuV_off, VvV_off, \ |
| 546 | sizeof(MMVector), sizeof(MMVector)) |
| 547 | #define fGEN_TCG_V6_vminub(SHORTCODE) \ |
| 548 | tcg_gen_gvec_umin(MO_8, VdV_off, VuV_off, VvV_off, \ |
| 549 | sizeof(MMVector), sizeof(MMVector)) |
| 550 | |
| 551 | /* Vector logical ops */ |
| 552 | #define fGEN_TCG_V6_vxor(SHORTCODE) \ |
| 553 | tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \ |
| 554 | sizeof(MMVector), sizeof(MMVector)) |
| 555 | |
| 556 | #define fGEN_TCG_V6_vand(SHORTCODE) \ |
| 557 | tcg_gen_gvec_and(MO_64, VdV_off, VuV_off, VvV_off, \ |
| 558 | sizeof(MMVector), sizeof(MMVector)) |
| 559 | |
| 560 | #define fGEN_TCG_V6_vor(SHORTCODE) \ |
| 561 | tcg_gen_gvec_or(MO_64, VdV_off, VuV_off, VvV_off, \ |
| 562 | sizeof(MMVector), sizeof(MMVector)) |
| 563 | |
| 564 | #define fGEN_TCG_V6_vnot(SHORTCODE) \ |
| 565 | tcg_gen_gvec_not(MO_64, VdV_off, VuV_off, \ |
| 566 | sizeof(MMVector), sizeof(MMVector)) |
| 567 | |
| 568 | /* Q register logical ops */ |
| 569 | #define fGEN_TCG_V6_pred_or(SHORTCODE) \ |
| 570 | tcg_gen_gvec_or(MO_64, QdV_off, QsV_off, QtV_off, \ |
| 571 | sizeof(MMQReg), sizeof(MMQReg)) |
| 572 | |
| 573 | #define fGEN_TCG_V6_pred_and(SHORTCODE) \ |
| 574 | tcg_gen_gvec_and(MO_64, QdV_off, QsV_off, QtV_off, \ |
| 575 | sizeof(MMQReg), sizeof(MMQReg)) |
| 576 | |
| 577 | #define fGEN_TCG_V6_pred_xor(SHORTCODE) \ |
| 578 | tcg_gen_gvec_xor(MO_64, QdV_off, QsV_off, QtV_off, \ |
| 579 | sizeof(MMQReg), sizeof(MMQReg)) |
| 580 | |
| 581 | #define fGEN_TCG_V6_pred_or_n(SHORTCODE) \ |
| 582 | tcg_gen_gvec_orc(MO_64, QdV_off, QsV_off, QtV_off, \ |
| 583 | sizeof(MMQReg), sizeof(MMQReg)) |
| 584 | |
| 585 | #define fGEN_TCG_V6_pred_and_n(SHORTCODE) \ |
| 586 | tcg_gen_gvec_andc(MO_64, QdV_off, QsV_off, QtV_off, \ |
| 587 | sizeof(MMQReg), sizeof(MMQReg)) |
| 588 | |
| 589 | #define fGEN_TCG_V6_pred_not(SHORTCODE) \ |
| 590 | tcg_gen_gvec_not(MO_64, QdV_off, QsV_off, \ |
| 591 | sizeof(MMQReg), sizeof(MMQReg)) |
| 592 | |
| 593 | /* Vector compares */ |
| 594 | #define fGEN_TCG_VEC_CMP(COND, TYPE, SIZE) \ |
| 595 | do { \ |
| 596 | intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \ |
| 597 | tcg_gen_gvec_cmp(COND, TYPE, tmpoff, VuV_off, VvV_off, \ |
| 598 | sizeof(MMVector), sizeof(MMVector)); \ |
| 599 | vec_to_qvec(SIZE, QdV_off, tmpoff); \ |
| 600 | } while (0) |
| 601 | |
| 602 | #define fGEN_TCG_V6_vgtw(SHORTCODE) \ |
| 603 | fGEN_TCG_VEC_CMP(TCG_COND_GT, MO_32, 4) |
| 604 | #define fGEN_TCG_V6_vgth(SHORTCODE) \ |
| 605 | fGEN_TCG_VEC_CMP(TCG_COND_GT, MO_16, 2) |
| 606 | #define fGEN_TCG_V6_vgtb(SHORTCODE) \ |
| 607 | fGEN_TCG_VEC_CMP(TCG_COND_GT, MO_8, 1) |
| 608 | |
| 609 | #define fGEN_TCG_V6_vgtuw(SHORTCODE) \ |
| 610 | fGEN_TCG_VEC_CMP(TCG_COND_GTU, MO_32, 4) |
| 611 | #define fGEN_TCG_V6_vgtuh(SHORTCODE) \ |
| 612 | fGEN_TCG_VEC_CMP(TCG_COND_GTU, MO_16, 2) |
| 613 | #define fGEN_TCG_V6_vgtub(SHORTCODE) \ |
| 614 | fGEN_TCG_VEC_CMP(TCG_COND_GTU, MO_8, 1) |
| 615 | |
| 616 | #define fGEN_TCG_V6_veqw(SHORTCODE) \ |
| 617 | fGEN_TCG_VEC_CMP(TCG_COND_EQ, MO_32, 4) |
| 618 | #define fGEN_TCG_V6_veqh(SHORTCODE) \ |
| 619 | fGEN_TCG_VEC_CMP(TCG_COND_EQ, MO_16, 2) |
| 620 | #define fGEN_TCG_V6_veqb(SHORTCODE) \ |
| 621 | fGEN_TCG_VEC_CMP(TCG_COND_EQ, MO_8, 1) |
| 622 | |
| 623 | #define fGEN_TCG_VEC_CMP_OP(COND, TYPE, SIZE, OP) \ |
| 624 | do { \ |
| 625 | intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \ |
| 626 | intptr_t qoff = offsetof(CPUHexagonState, qtmp); \ |
| 627 | tcg_gen_gvec_cmp(COND, TYPE, tmpoff, VuV_off, VvV_off, \ |
| 628 | sizeof(MMVector), sizeof(MMVector)); \ |
| 629 | vec_to_qvec(SIZE, qoff, tmpoff); \ |
| 630 | OP(MO_64, QxV_off, QxV_off, qoff, sizeof(MMQReg), sizeof(MMQReg)); \ |
| 631 | } while (0) |
| 632 | |
| 633 | #define fGEN_TCG_V6_vgtw_and(SHORTCODE) \ |
| 634 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_and) |
| 635 | #define fGEN_TCG_V6_vgtw_or(SHORTCODE) \ |
| 636 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_or) |
| 637 | #define fGEN_TCG_V6_vgtw_xor(SHORTCODE) \ |
| 638 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_xor) |
| 639 | |
| 640 | #define fGEN_TCG_V6_vgtuw_and(SHORTCODE) \ |
| 641 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_and) |
| 642 | #define fGEN_TCG_V6_vgtuw_or(SHORTCODE) \ |
| 643 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_or) |
| 644 | #define fGEN_TCG_V6_vgtuw_xor(SHORTCODE) \ |
| 645 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_xor) |
| 646 | |
| 647 | #define fGEN_TCG_V6_vgth_and(SHORTCODE) \ |
| 648 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_and) |
| 649 | #define fGEN_TCG_V6_vgth_or(SHORTCODE) \ |
| 650 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_or) |
| 651 | #define fGEN_TCG_V6_vgth_xor(SHORTCODE) \ |
| 652 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_xor) |
| 653 | |
| 654 | #define fGEN_TCG_V6_vgtuh_and(SHORTCODE) \ |
| 655 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_and) |
| 656 | #define fGEN_TCG_V6_vgtuh_or(SHORTCODE) \ |
| 657 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_or) |
| 658 | #define fGEN_TCG_V6_vgtuh_xor(SHORTCODE) \ |
| 659 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_xor) |
| 660 | |
| 661 | #define fGEN_TCG_V6_vgtb_and(SHORTCODE) \ |
| 662 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_and) |
| 663 | #define fGEN_TCG_V6_vgtb_or(SHORTCODE) \ |
| 664 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_or) |
| 665 | #define fGEN_TCG_V6_vgtb_xor(SHORTCODE) \ |
| 666 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_xor) |
| 667 | |
| 668 | #define fGEN_TCG_V6_vgtub_and(SHORTCODE) \ |
| 669 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_and) |
| 670 | #define fGEN_TCG_V6_vgtub_or(SHORTCODE) \ |
| 671 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_or) |
| 672 | #define fGEN_TCG_V6_vgtub_xor(SHORTCODE) \ |
| 673 | fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_xor) |
| 674 | |
| 675 | #define fGEN_TCG_V6_veqw_and(SHORTCODE) \ |
| 676 | fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_and) |
| 677 | #define fGEN_TCG_V6_veqw_or(SHORTCODE) \ |
| 678 | fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_or) |
| 679 | #define fGEN_TCG_V6_veqw_xor(SHORTCODE) \ |
| 680 | fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_xor) |
| 681 | |
| 682 | #define fGEN_TCG_V6_veqh_and(SHORTCODE) \ |
| 683 | fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_and) |
| 684 | #define fGEN_TCG_V6_veqh_or(SHORTCODE) \ |
| 685 | fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_or) |
| 686 | #define fGEN_TCG_V6_veqh_xor(SHORTCODE) \ |
| 687 | fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_xor) |
| 688 | |
| 689 | #define fGEN_TCG_V6_veqb_and(SHORTCODE) \ |
| 690 | fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_and) |
| 691 | #define fGEN_TCG_V6_veqb_or(SHORTCODE) \ |
| 692 | fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_or) |
| 693 | #define fGEN_TCG_V6_veqb_xor(SHORTCODE) \ |
| 694 | fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_xor) |
| 695 | |
| 696 | /* Vector splat - various forms */ |
| 697 | #define fGEN_TCG_V6_lvsplatw(SHORTCODE) \ |
| 698 | tcg_gen_gvec_dup_i32(MO_32, VdV_off, \ |
| 699 | sizeof(MMVector), sizeof(MMVector), RtV) |
| 700 | |
| 701 | #define fGEN_TCG_V6_lvsplath(SHORTCODE) \ |
| 702 | tcg_gen_gvec_dup_i32(MO_16, VdV_off, \ |
| 703 | sizeof(MMVector), sizeof(MMVector), RtV) |
| 704 | |
| 705 | #define fGEN_TCG_V6_lvsplatb(SHORTCODE) \ |
| 706 | tcg_gen_gvec_dup_i32(MO_8, VdV_off, \ |
| 707 | sizeof(MMVector), sizeof(MMVector), RtV) |
| 708 | |
| 709 | /* Vector absolute value - various forms */ |
| 710 | #define fGEN_TCG_V6_vabsb(SHORTCODE) \ |
| 711 | tcg_gen_gvec_abs(MO_8, VdV_off, VuV_off, \ |
| 712 | sizeof(MMVector), sizeof(MMVector)) |
| 713 | |
| 714 | #define fGEN_TCG_V6_vabsh(SHORTCODE) \ |
| 715 | tcg_gen_gvec_abs(MO_16, VdV_off, VuV_off, \ |
| 716 | sizeof(MMVector), sizeof(MMVector)) |
| 717 | |
| 718 | #define fGEN_TCG_V6_vabsw(SHORTCODE) \ |
| 719 | tcg_gen_gvec_abs(MO_32, VdV_off, VuV_off, \ |
| 720 | sizeof(MMVector), sizeof(MMVector)) |
| 721 | |
| 722 | /* Vector loads */ |
| 723 | #define fGEN_TCG_V6_vL32b_pi(SHORTCODE) SHORTCODE |
| 724 | #define fGEN_TCG_V6_vL32Ub_pi(SHORTCODE) SHORTCODE |
| 725 | #define fGEN_TCG_V6_vL32b_cur_pi(SHORTCODE) SHORTCODE |
| 726 | #define fGEN_TCG_V6_vL32b_tmp_pi(SHORTCODE) SHORTCODE |
| 727 | #define fGEN_TCG_V6_vL32b_nt_pi(SHORTCODE) SHORTCODE |
| 728 | #define fGEN_TCG_V6_vL32b_nt_cur_pi(SHORTCODE) SHORTCODE |
| 729 | #define fGEN_TCG_V6_vL32b_nt_tmp_pi(SHORTCODE) SHORTCODE |
| 730 | #define fGEN_TCG_V6_vL32b_ai(SHORTCODE) SHORTCODE |
| 731 | #define fGEN_TCG_V6_vL32Ub_ai(SHORTCODE) SHORTCODE |
| 732 | #define fGEN_TCG_V6_vL32b_cur_ai(SHORTCODE) SHORTCODE |
| 733 | #define fGEN_TCG_V6_vL32b_tmp_ai(SHORTCODE) SHORTCODE |
| 734 | #define fGEN_TCG_V6_vL32b_nt_ai(SHORTCODE) SHORTCODE |
| 735 | #define fGEN_TCG_V6_vL32b_nt_cur_ai(SHORTCODE) SHORTCODE |
| 736 | #define fGEN_TCG_V6_vL32b_nt_tmp_ai(SHORTCODE) SHORTCODE |
| 737 | #define fGEN_TCG_V6_vL32b_ppu(SHORTCODE) SHORTCODE |
| 738 | #define fGEN_TCG_V6_vL32Ub_ppu(SHORTCODE) SHORTCODE |
| 739 | #define fGEN_TCG_V6_vL32b_cur_ppu(SHORTCODE) SHORTCODE |
| 740 | #define fGEN_TCG_V6_vL32b_tmp_ppu(SHORTCODE) SHORTCODE |
| 741 | #define fGEN_TCG_V6_vL32b_nt_ppu(SHORTCODE) SHORTCODE |
| 742 | #define fGEN_TCG_V6_vL32b_nt_cur_ppu(SHORTCODE) SHORTCODE |
| 743 | #define fGEN_TCG_V6_vL32b_nt_tmp_ppu(SHORTCODE) SHORTCODE |
| 744 | |
| 745 | /* Predicated vector loads */ |
| 746 | #define fGEN_TCG_PRED_VEC_LOAD(GET_EA, PRED, DSTOFF, INC) \ |
| 747 | do { \ |
| 748 | TCGv LSB = tcg_temp_new(); \ |
| 749 | TCGLabel *false_label = gen_new_label(); \ |
| 750 | GET_EA; \ |
| 751 | PRED; \ |
| 752 | tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \ |
| 753 | gen_vreg_load(ctx, DSTOFF, EA, true); \ |
| 754 | INC; \ |
| 755 | gen_set_label(false_label); \ |
| 756 | } while (0) |
| 757 | |
| 758 | #define fGEN_TCG_PRED_VEC_LOAD_pred_pi \ |
| 759 | fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \ |
| 760 | fEA_REG(RxV), \ |
| 761 | VdV_off, \ |
| 762 | fPM_I(RxV, siV * sizeof(MMVector))) |
| 763 | #define fGEN_TCG_PRED_VEC_LOAD_npred_pi \ |
| 764 | fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \ |
| 765 | fEA_REG(RxV), \ |
| 766 | VdV_off, \ |
| 767 | fPM_I(RxV, siV * sizeof(MMVector))) |
| 768 | |
| 769 | #define fGEN_TCG_V6_vL32b_pred_pi(SHORTCODE) \ |
| 770 | fGEN_TCG_PRED_VEC_LOAD_pred_pi |
| 771 | #define fGEN_TCG_V6_vL32b_npred_pi(SHORTCODE) \ |
| 772 | fGEN_TCG_PRED_VEC_LOAD_npred_pi |
| 773 | #define fGEN_TCG_V6_vL32b_cur_pred_pi(SHORTCODE) \ |
| 774 | fGEN_TCG_PRED_VEC_LOAD_pred_pi |
| 775 | #define fGEN_TCG_V6_vL32b_cur_npred_pi(SHORTCODE) \ |
| 776 | fGEN_TCG_PRED_VEC_LOAD_npred_pi |
| 777 | #define fGEN_TCG_V6_vL32b_tmp_pred_pi(SHORTCODE) \ |
| 778 | fGEN_TCG_PRED_VEC_LOAD_pred_pi |
| 779 | #define fGEN_TCG_V6_vL32b_tmp_npred_pi(SHORTCODE) \ |
| 780 | fGEN_TCG_PRED_VEC_LOAD_npred_pi |
| 781 | #define fGEN_TCG_V6_vL32b_nt_pred_pi(SHORTCODE) \ |
| 782 | fGEN_TCG_PRED_VEC_LOAD_pred_pi |
| 783 | #define fGEN_TCG_V6_vL32b_nt_npred_pi(SHORTCODE) \ |
| 784 | fGEN_TCG_PRED_VEC_LOAD_npred_pi |
| 785 | #define fGEN_TCG_V6_vL32b_nt_cur_pred_pi(SHORTCODE) \ |
| 786 | fGEN_TCG_PRED_VEC_LOAD_pred_pi |
| 787 | #define fGEN_TCG_V6_vL32b_nt_cur_npred_pi(SHORTCODE) \ |
| 788 | fGEN_TCG_PRED_VEC_LOAD_npred_pi |
| 789 | #define fGEN_TCG_V6_vL32b_nt_tmp_pred_pi(SHORTCODE) \ |
| 790 | fGEN_TCG_PRED_VEC_LOAD_pred_pi |
| 791 | #define fGEN_TCG_V6_vL32b_nt_tmp_npred_pi(SHORTCODE) \ |
| 792 | fGEN_TCG_PRED_VEC_LOAD_npred_pi |
| 793 | |
| 794 | #define fGEN_TCG_PRED_VEC_LOAD_pred_ai \ |
| 795 | fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \ |
| 796 | fEA_RI(RtV, siV * sizeof(MMVector)), \ |
| 797 | VdV_off, \ |
| 798 | do {} while (0)) |
| 799 | #define fGEN_TCG_PRED_VEC_LOAD_npred_ai \ |
| 800 | fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \ |
| 801 | fEA_RI(RtV, siV * sizeof(MMVector)), \ |
| 802 | VdV_off, \ |
| 803 | do {} while (0)) |
| 804 | |
| 805 | #define fGEN_TCG_V6_vL32b_pred_ai(SHORTCODE) \ |
| 806 | fGEN_TCG_PRED_VEC_LOAD_pred_ai |
| 807 | #define fGEN_TCG_V6_vL32b_npred_ai(SHORTCODE) \ |
| 808 | fGEN_TCG_PRED_VEC_LOAD_npred_ai |
| 809 | #define fGEN_TCG_V6_vL32b_cur_pred_ai(SHORTCODE) \ |
| 810 | fGEN_TCG_PRED_VEC_LOAD_pred_ai |
| 811 | #define fGEN_TCG_V6_vL32b_cur_npred_ai(SHORTCODE) \ |
| 812 | fGEN_TCG_PRED_VEC_LOAD_npred_ai |
| 813 | #define fGEN_TCG_V6_vL32b_tmp_pred_ai(SHORTCODE) \ |
| 814 | fGEN_TCG_PRED_VEC_LOAD_pred_ai |
| 815 | #define fGEN_TCG_V6_vL32b_tmp_npred_ai(SHORTCODE) \ |
| 816 | fGEN_TCG_PRED_VEC_LOAD_npred_ai |
| 817 | #define fGEN_TCG_V6_vL32b_nt_pred_ai(SHORTCODE) \ |
| 818 | fGEN_TCG_PRED_VEC_LOAD_pred_ai |
| 819 | #define fGEN_TCG_V6_vL32b_nt_npred_ai(SHORTCODE) \ |
| 820 | fGEN_TCG_PRED_VEC_LOAD_npred_ai |
| 821 | #define fGEN_TCG_V6_vL32b_nt_cur_pred_ai(SHORTCODE) \ |
| 822 | fGEN_TCG_PRED_VEC_LOAD_pred_ai |
| 823 | #define fGEN_TCG_V6_vL32b_nt_cur_npred_ai(SHORTCODE) \ |
| 824 | fGEN_TCG_PRED_VEC_LOAD_npred_ai |
| 825 | #define fGEN_TCG_V6_vL32b_nt_tmp_pred_ai(SHORTCODE) \ |
| 826 | fGEN_TCG_PRED_VEC_LOAD_pred_ai |
| 827 | #define fGEN_TCG_V6_vL32b_nt_tmp_npred_ai(SHORTCODE) \ |
| 828 | fGEN_TCG_PRED_VEC_LOAD_npred_ai |
| 829 | |
| 830 | #define fGEN_TCG_PRED_VEC_LOAD_pred_ppu \ |
| 831 | fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \ |
| 832 | fEA_REG(RxV), \ |
| 833 | VdV_off, \ |
| 834 | fPM_M(RxV, MuV)) |
| 835 | #define fGEN_TCG_PRED_VEC_LOAD_npred_ppu \ |
| 836 | fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \ |
| 837 | fEA_REG(RxV), \ |
| 838 | VdV_off, \ |
| 839 | fPM_M(RxV, MuV)) |
| 840 | |
| 841 | #define fGEN_TCG_V6_vL32b_pred_ppu(SHORTCODE) \ |
| 842 | fGEN_TCG_PRED_VEC_LOAD_pred_ppu |
| 843 | #define fGEN_TCG_V6_vL32b_npred_ppu(SHORTCODE) \ |
| 844 | fGEN_TCG_PRED_VEC_LOAD_npred_ppu |
| 845 | #define fGEN_TCG_V6_vL32b_cur_pred_ppu(SHORTCODE) \ |
| 846 | fGEN_TCG_PRED_VEC_LOAD_pred_ppu |
| 847 | #define fGEN_TCG_V6_vL32b_cur_npred_ppu(SHORTCODE) \ |
| 848 | fGEN_TCG_PRED_VEC_LOAD_npred_ppu |
| 849 | #define fGEN_TCG_V6_vL32b_tmp_pred_ppu(SHORTCODE) \ |
| 850 | fGEN_TCG_PRED_VEC_LOAD_pred_ppu |
| 851 | #define fGEN_TCG_V6_vL32b_tmp_npred_ppu(SHORTCODE) \ |
| 852 | fGEN_TCG_PRED_VEC_LOAD_npred_ppu |
| 853 | #define fGEN_TCG_V6_vL32b_nt_pred_ppu(SHORTCODE) \ |
| 854 | fGEN_TCG_PRED_VEC_LOAD_pred_ppu |
| 855 | #define fGEN_TCG_V6_vL32b_nt_npred_ppu(SHORTCODE) \ |
| 856 | fGEN_TCG_PRED_VEC_LOAD_npred_ppu |
| 857 | #define fGEN_TCG_V6_vL32b_nt_cur_pred_ppu(SHORTCODE) \ |
| 858 | fGEN_TCG_PRED_VEC_LOAD_pred_ppu |
| 859 | #define fGEN_TCG_V6_vL32b_nt_cur_npred_ppu(SHORTCODE) \ |
| 860 | fGEN_TCG_PRED_VEC_LOAD_npred_ppu |
| 861 | #define fGEN_TCG_V6_vL32b_nt_tmp_pred_ppu(SHORTCODE) \ |
| 862 | fGEN_TCG_PRED_VEC_LOAD_pred_ppu |
| 863 | #define fGEN_TCG_V6_vL32b_nt_tmp_npred_ppu(SHORTCODE) \ |
| 864 | fGEN_TCG_PRED_VEC_LOAD_npred_ppu |
| 865 | |
| 866 | /* Vector stores */ |
| 867 | #define fGEN_TCG_V6_vS32b_pi(SHORTCODE) SHORTCODE |
| 868 | #define fGEN_TCG_V6_vS32Ub_pi(SHORTCODE) SHORTCODE |
| 869 | #define fGEN_TCG_V6_vS32b_nt_pi(SHORTCODE) SHORTCODE |
| 870 | #define fGEN_TCG_V6_vS32b_ai(SHORTCODE) SHORTCODE |
| 871 | #define fGEN_TCG_V6_vS32Ub_ai(SHORTCODE) SHORTCODE |
| 872 | #define fGEN_TCG_V6_vS32b_nt_ai(SHORTCODE) SHORTCODE |
| 873 | #define fGEN_TCG_V6_vS32b_ppu(SHORTCODE) SHORTCODE |
| 874 | #define fGEN_TCG_V6_vS32Ub_ppu(SHORTCODE) SHORTCODE |
| 875 | #define fGEN_TCG_V6_vS32b_nt_ppu(SHORTCODE) SHORTCODE |
| 876 | |
| 877 | /* New value vector stores */ |
| 878 | #define fGEN_TCG_NEWVAL_VEC_STORE(GET_EA, INC) \ |
| 879 | do { \ |
| 880 | GET_EA; \ |
| 881 | gen_vreg_store(ctx, EA, OsN_off, insn->slot, true); \ |
| 882 | INC; \ |
| 883 | } while (0) |
| 884 | |
| 885 | #define fGEN_TCG_NEWVAL_VEC_STORE_pi \ |
| 886 | fGEN_TCG_NEWVAL_VEC_STORE(fEA_REG(RxV), fPM_I(RxV, siV * sizeof(MMVector))) |
| 887 | |
| 888 | #define fGEN_TCG_V6_vS32b_new_pi(SHORTCODE) \ |
| 889 | fGEN_TCG_NEWVAL_VEC_STORE_pi |
| 890 | #define fGEN_TCG_V6_vS32b_nt_new_pi(SHORTCODE) \ |
| 891 | fGEN_TCG_NEWVAL_VEC_STORE_pi |
| 892 | |
| 893 | #define fGEN_TCG_NEWVAL_VEC_STORE_ai \ |
| 894 | fGEN_TCG_NEWVAL_VEC_STORE(fEA_RI(RtV, siV * sizeof(MMVector)), \ |
| 895 | do { } while (0)) |
| 896 | |
| 897 | #define fGEN_TCG_V6_vS32b_new_ai(SHORTCODE) \ |
| 898 | fGEN_TCG_NEWVAL_VEC_STORE_ai |
| 899 | #define fGEN_TCG_V6_vS32b_nt_new_ai(SHORTCODE) \ |
| 900 | fGEN_TCG_NEWVAL_VEC_STORE_ai |
| 901 | |
| 902 | #define fGEN_TCG_NEWVAL_VEC_STORE_ppu \ |
| 903 | fGEN_TCG_NEWVAL_VEC_STORE(fEA_REG(RxV), fPM_M(RxV, MuV)) |
| 904 | |
| 905 | #define fGEN_TCG_V6_vS32b_new_ppu(SHORTCODE) \ |
| 906 | fGEN_TCG_NEWVAL_VEC_STORE_ppu |
| 907 | #define fGEN_TCG_V6_vS32b_nt_new_ppu(SHORTCODE) \ |
| 908 | fGEN_TCG_NEWVAL_VEC_STORE_ppu |
| 909 | |
| 910 | /* Predicated vector stores */ |
| 911 | #define fGEN_TCG_PRED_VEC_STORE(GET_EA, PRED, SRCOFF, ALIGN, INC) \ |
| 912 | do { \ |
| 913 | TCGv LSB = tcg_temp_new(); \ |
| 914 | TCGLabel *false_label = gen_new_label(); \ |
| 915 | GET_EA; \ |
| 916 | PRED; \ |
| 917 | tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \ |
| 918 | gen_vreg_store(ctx, EA, SRCOFF, insn->slot, ALIGN); \ |
| 919 | INC; \ |
| 920 | gen_set_label(false_label); \ |
| 921 | } while (0) |
| 922 | |
| 923 | #define fGEN_TCG_PRED_VEC_STORE_pred_pi(ALIGN) \ |
| 924 | fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ |
| 925 | fEA_REG(RxV), \ |
| 926 | VsV_off, ALIGN, \ |
| 927 | fPM_I(RxV, siV * sizeof(MMVector))) |
| 928 | #define fGEN_TCG_PRED_VEC_STORE_npred_pi(ALIGN) \ |
| 929 | fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ |
| 930 | fEA_REG(RxV), \ |
| 931 | VsV_off, ALIGN, \ |
| 932 | fPM_I(RxV, siV * sizeof(MMVector))) |
| 933 | #define fGEN_TCG_PRED_VEC_STORE_new_pred_pi \ |
| 934 | fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ |
| 935 | fEA_REG(RxV), \ |
| 936 | OsN_off, true, \ |
| 937 | fPM_I(RxV, siV * sizeof(MMVector))) |
| 938 | #define fGEN_TCG_PRED_VEC_STORE_new_npred_pi \ |
| 939 | fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ |
| 940 | fEA_REG(RxV), \ |
| 941 | OsN_off, true, \ |
| 942 | fPM_I(RxV, siV * sizeof(MMVector))) |
| 943 | |
| 944 | #define fGEN_TCG_V6_vS32b_pred_pi(SHORTCODE) \ |
| 945 | fGEN_TCG_PRED_VEC_STORE_pred_pi(true) |
| 946 | #define fGEN_TCG_V6_vS32b_npred_pi(SHORTCODE) \ |
| 947 | fGEN_TCG_PRED_VEC_STORE_npred_pi(true) |
| 948 | #define fGEN_TCG_V6_vS32Ub_pred_pi(SHORTCODE) \ |
| 949 | fGEN_TCG_PRED_VEC_STORE_pred_pi(false) |
| 950 | #define fGEN_TCG_V6_vS32Ub_npred_pi(SHORTCODE) \ |
| 951 | fGEN_TCG_PRED_VEC_STORE_npred_pi(false) |
| 952 | #define fGEN_TCG_V6_vS32b_nt_pred_pi(SHORTCODE) \ |
| 953 | fGEN_TCG_PRED_VEC_STORE_pred_pi(true) |
| 954 | #define fGEN_TCG_V6_vS32b_nt_npred_pi(SHORTCODE) \ |
| 955 | fGEN_TCG_PRED_VEC_STORE_npred_pi(true) |
| 956 | #define fGEN_TCG_V6_vS32b_new_pred_pi(SHORTCODE) \ |
| 957 | fGEN_TCG_PRED_VEC_STORE_new_pred_pi |
| 958 | #define fGEN_TCG_V6_vS32b_new_npred_pi(SHORTCODE) \ |
| 959 | fGEN_TCG_PRED_VEC_STORE_new_npred_pi |
| 960 | #define fGEN_TCG_V6_vS32b_nt_new_pred_pi(SHORTCODE) \ |
| 961 | fGEN_TCG_PRED_VEC_STORE_new_pred_pi |
| 962 | #define fGEN_TCG_V6_vS32b_nt_new_npred_pi(SHORTCODE) \ |
| 963 | fGEN_TCG_PRED_VEC_STORE_new_npred_pi |
| 964 | |
| 965 | #define fGEN_TCG_PRED_VEC_STORE_pred_ai(ALIGN) \ |
| 966 | fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ |
| 967 | fEA_RI(RtV, siV * sizeof(MMVector)), \ |
| 968 | VsV_off, ALIGN, \ |
| 969 | do { } while (0)) |
| 970 | #define fGEN_TCG_PRED_VEC_STORE_npred_ai(ALIGN) \ |
| 971 | fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ |
| 972 | fEA_RI(RtV, siV * sizeof(MMVector)), \ |
| 973 | VsV_off, ALIGN, \ |
| 974 | do { } while (0)) |
| 975 | #define fGEN_TCG_PRED_VEC_STORE_new_pred_ai \ |
| 976 | fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ |
| 977 | fEA_RI(RtV, siV * sizeof(MMVector)), \ |
| 978 | OsN_off, true, \ |
| 979 | do { } while (0)) |
| 980 | #define fGEN_TCG_PRED_VEC_STORE_new_npred_ai \ |
| 981 | fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ |
| 982 | fEA_RI(RtV, siV * sizeof(MMVector)), \ |
| 983 | OsN_off, true, \ |
| 984 | do { } while (0)) |
| 985 | |
| 986 | #define fGEN_TCG_V6_vS32b_pred_ai(SHORTCODE) \ |
| 987 | fGEN_TCG_PRED_VEC_STORE_pred_ai(true) |
| 988 | #define fGEN_TCG_V6_vS32b_npred_ai(SHORTCODE) \ |
| 989 | fGEN_TCG_PRED_VEC_STORE_npred_ai(true) |
| 990 | #define fGEN_TCG_V6_vS32Ub_pred_ai(SHORTCODE) \ |
| 991 | fGEN_TCG_PRED_VEC_STORE_pred_ai(false) |
| 992 | #define fGEN_TCG_V6_vS32Ub_npred_ai(SHORTCODE) \ |
| 993 | fGEN_TCG_PRED_VEC_STORE_npred_ai(false) |
| 994 | #define fGEN_TCG_V6_vS32b_nt_pred_ai(SHORTCODE) \ |
| 995 | fGEN_TCG_PRED_VEC_STORE_pred_ai(true) |
| 996 | #define fGEN_TCG_V6_vS32b_nt_npred_ai(SHORTCODE) \ |
| 997 | fGEN_TCG_PRED_VEC_STORE_npred_ai(true) |
| 998 | #define fGEN_TCG_V6_vS32b_new_pred_ai(SHORTCODE) \ |
| 999 | fGEN_TCG_PRED_VEC_STORE_new_pred_ai |
| 1000 | #define fGEN_TCG_V6_vS32b_new_npred_ai(SHORTCODE) \ |
| 1001 | fGEN_TCG_PRED_VEC_STORE_new_npred_ai |
| 1002 | #define fGEN_TCG_V6_vS32b_nt_new_pred_ai(SHORTCODE) \ |
| 1003 | fGEN_TCG_PRED_VEC_STORE_new_pred_ai |
| 1004 | #define fGEN_TCG_V6_vS32b_nt_new_npred_ai(SHORTCODE) \ |
| 1005 | fGEN_TCG_PRED_VEC_STORE_new_npred_ai |
| 1006 | |
| 1007 | #define fGEN_TCG_PRED_VEC_STORE_pred_ppu(ALIGN) \ |
| 1008 | fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ |
| 1009 | fEA_REG(RxV), \ |
| 1010 | VsV_off, ALIGN, \ |
| 1011 | fPM_M(RxV, MuV)) |
| 1012 | #define fGEN_TCG_PRED_VEC_STORE_npred_ppu(ALIGN) \ |
| 1013 | fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ |
| 1014 | fEA_REG(RxV), \ |
| 1015 | VsV_off, ALIGN, \ |
| 1016 | fPM_M(RxV, MuV)) |
| 1017 | #define fGEN_TCG_PRED_VEC_STORE_new_pred_ppu \ |
| 1018 | fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ |
| 1019 | fEA_REG(RxV), \ |
| 1020 | OsN_off, true, \ |
| 1021 | fPM_M(RxV, MuV)) |
| 1022 | #define fGEN_TCG_PRED_VEC_STORE_new_npred_ppu \ |
| 1023 | fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ |
| 1024 | fEA_REG(RxV), \ |
| 1025 | OsN_off, true, \ |
| 1026 | fPM_M(RxV, MuV)) |
| 1027 | |
| 1028 | #define fGEN_TCG_V6_vS32b_pred_ppu(SHORTCODE) \ |
| 1029 | fGEN_TCG_PRED_VEC_STORE_pred_ppu(true) |
| 1030 | #define fGEN_TCG_V6_vS32b_npred_ppu(SHORTCODE) \ |
| 1031 | fGEN_TCG_PRED_VEC_STORE_npred_ppu(true) |
| 1032 | #define fGEN_TCG_V6_vS32Ub_pred_ppu(SHORTCODE) \ |
| 1033 | fGEN_TCG_PRED_VEC_STORE_pred_ppu(false) |
| 1034 | #define fGEN_TCG_V6_vS32Ub_npred_ppu(SHORTCODE) \ |
| 1035 | fGEN_TCG_PRED_VEC_STORE_npred_ppu(false) |
| 1036 | #define fGEN_TCG_V6_vS32b_nt_pred_ppu(SHORTCODE) \ |
| 1037 | fGEN_TCG_PRED_VEC_STORE_pred_ppu(true) |
| 1038 | #define fGEN_TCG_V6_vS32b_nt_npred_ppu(SHORTCODE) \ |
| 1039 | fGEN_TCG_PRED_VEC_STORE_npred_ppu(true) |
| 1040 | #define fGEN_TCG_V6_vS32b_new_pred_ppu(SHORTCODE) \ |
| 1041 | fGEN_TCG_PRED_VEC_STORE_new_pred_ppu |
| 1042 | #define fGEN_TCG_V6_vS32b_new_npred_ppu(SHORTCODE) \ |
| 1043 | fGEN_TCG_PRED_VEC_STORE_new_npred_ppu |
| 1044 | #define fGEN_TCG_V6_vS32b_nt_new_pred_ppu(SHORTCODE) \ |
| 1045 | fGEN_TCG_PRED_VEC_STORE_new_pred_ppu |
| 1046 | #define fGEN_TCG_V6_vS32b_nt_new_npred_ppu(SHORTCODE) \ |
| 1047 | fGEN_TCG_PRED_VEC_STORE_new_npred_ppu |
| 1048 | |
| 1049 | /* Masked vector stores */ |
| 1050 | #define fGEN_TCG_V6_vS32b_qpred_pi(SHORTCODE) SHORTCODE |
| 1051 | #define fGEN_TCG_V6_vS32b_nt_qpred_pi(SHORTCODE) SHORTCODE |
| 1052 | #define fGEN_TCG_V6_vS32b_qpred_ai(SHORTCODE) SHORTCODE |
| 1053 | #define fGEN_TCG_V6_vS32b_nt_qpred_ai(SHORTCODE) SHORTCODE |
| 1054 | #define fGEN_TCG_V6_vS32b_qpred_ppu(SHORTCODE) SHORTCODE |
| 1055 | #define fGEN_TCG_V6_vS32b_nt_qpred_ppu(SHORTCODE) SHORTCODE |
| 1056 | #define fGEN_TCG_V6_vS32b_nqpred_pi(SHORTCODE) SHORTCODE |
| 1057 | #define fGEN_TCG_V6_vS32b_nt_nqpred_pi(SHORTCODE) SHORTCODE |
| 1058 | #define fGEN_TCG_V6_vS32b_nqpred_ai(SHORTCODE) SHORTCODE |
| 1059 | #define fGEN_TCG_V6_vS32b_nt_nqpred_ai(SHORTCODE) SHORTCODE |
| 1060 | #define fGEN_TCG_V6_vS32b_nqpred_ppu(SHORTCODE) SHORTCODE |
| 1061 | #define fGEN_TCG_V6_vS32b_nt_nqpred_ppu(SHORTCODE) SHORTCODE |
| 1062 | |
| 1063 | /* Store release not modelled in qemu, but need to suppress compiler warnings */ |
| 1064 | #define fGEN_TCG_V6_vS32b_srls_pi(SHORTCODE) \ |
| 1065 | do { \ |
| 1066 | siV = siV; \ |
| 1067 | } while (0) |
| 1068 | #define fGEN_TCG_V6_vS32b_srls_ai(SHORTCODE) \ |
| 1069 | do { \ |
| 1070 | RtV = RtV; \ |
| 1071 | siV = siV; \ |
| 1072 | } while (0) |
| 1073 | #define fGEN_TCG_V6_vS32b_srls_ppu(SHORTCODE) \ |
| 1074 | do { \ |
| 1075 | MuV = MuV; \ |
| 1076 | } while (0) |
| 1077 | |
| 1078 | #endif |