| 1 | /* |
| 2 | * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 5 | */ |
| 6 | |
| 7 | #ifndef HEXAGON_GEN_TCG_SYS_H |
| 8 | #define HEXAGON_GEN_TCG_SYS_H |
| 9 | |
| 10 | /* System mode instructions */ |
| 11 | #define fGEN_TCG_Y2_swi(SHORTCODE) \ |
| 12 | gen_helper_swi(tcg_env, RsV) |
| 13 | |
| 14 | #define fGEN_TCG_Y2_cswi(SHORTCODE) \ |
| 15 | gen_helper_cswi(tcg_env, RsV) |
| 16 | |
| 17 | #define fGEN_TCG_Y2_ciad(SHORTCODE) \ |
| 18 | gen_helper_ciad(tcg_env, RsV) |
| 19 | |
| 20 | #define fGEN_TCG_Y4_siad(SHORTCODE) \ |
| 21 | gen_helper_siad(tcg_env, RsV) |
| 22 | |
| 23 | #define fGEN_TCG_Y2_iassignw(SHORTCODE) \ |
| 24 | gen_helper_iassignw(tcg_env, RsV) |
| 25 | |
| 26 | #define fGEN_TCG_Y2_iassignr(SHORTCODE) \ |
| 27 | gen_helper_iassignr(RdV, tcg_env, RsV) |
| 28 | |
| 29 | #define fGEN_TCG_Y2_getimask(SHORTCODE) \ |
| 30 | gen_helper_getimask(RdV, tcg_env, RsV) |
| 31 | |
| 32 | #define fGEN_TCG_Y2_setimask(SHORTCODE) \ |
| 33 | gen_helper_setimask(tcg_env, PtV, RsV) |
| 34 | |
| 35 | #define fGEN_TCG_Y2_setprio(SHORTCODE) \ |
| 36 | gen_helper_setprio(tcg_env, PtV, RsV) |
| 37 | |
| 38 | #define fGEN_TCG_Y2_crswap0(SHORTCODE) \ |
| 39 | do { \ |
| 40 | TCGv_i32 tmp = tcg_temp_new_i32(); \ |
| 41 | tcg_gen_mov_tl(tmp, RxV); \ |
| 42 | tcg_gen_mov_tl(RxV, hex_t_sreg[HEX_SREG_SGP0]); \ |
| 43 | if (ctx->need_commit) { \ |
| 44 | tcg_gen_mov_tl(ctx->t_sreg_new_value[HEX_SREG_SGP0], tmp); \ |
| 45 | } else { \ |
| 46 | tcg_gen_mov_tl(hex_t_sreg[HEX_SREG_SGP0], tmp); \ |
| 47 | } \ |
| 48 | } while (0) |
| 49 | |
| 50 | #define fGEN_TCG_Y4_crswap1(SHORTCODE) \ |
| 51 | do { \ |
| 52 | TCGv_i32 tmp = tcg_temp_new_i32(); \ |
| 53 | tcg_gen_mov_tl(tmp, RxV); \ |
| 54 | tcg_gen_mov_tl(RxV, hex_t_sreg[HEX_SREG_SGP1]); \ |
| 55 | if (ctx->need_commit) { \ |
| 56 | tcg_gen_mov_tl(ctx->t_sreg_new_value[HEX_SREG_SGP1], tmp); \ |
| 57 | } else { \ |
| 58 | tcg_gen_mov_tl(hex_t_sreg[HEX_SREG_SGP1], tmp); \ |
| 59 | } \ |
| 60 | } while (0) |
| 61 | |
| 62 | #define fGEN_TCG_Y4_crswap10(SHORTCODE) \ |
| 63 | do { \ |
| 64 | TCGv_i64 tmp = tcg_temp_new_i64(); \ |
| 65 | tcg_gen_mov_i64(tmp, RxxV); \ |
| 66 | tcg_gen_concat_i32_i64(RxxV, \ |
| 67 | hex_t_sreg[HEX_SREG_SGP0], \ |
| 68 | hex_t_sreg[HEX_SREG_SGP1]); \ |
| 69 | if (ctx->need_commit) { \ |
| 70 | tcg_gen_extrl_i64_i32( \ |
| 71 | ctx->t_sreg_new_value[HEX_SREG_SGP0], tmp); \ |
| 72 | tcg_gen_extrh_i64_i32( \ |
| 73 | ctx->t_sreg_new_value[HEX_SREG_SGP1], tmp); \ |
| 74 | } else { \ |
| 75 | tcg_gen_extrl_i64_i32(hex_t_sreg[HEX_SREG_SGP0], tmp); \ |
| 76 | tcg_gen_extrh_i64_i32(hex_t_sreg[HEX_SREG_SGP1], tmp); \ |
| 77 | } \ |
| 78 | } while (0) |
| 79 | |
| 80 | #define fGEN_TCG_Y2_wait(SHORTCODE) \ |
| 81 | do { \ |
| 82 | RsV = RsV; \ |
| 83 | gen_helper_wait(tcg_env, tcg_constant_tl(ctx->pkt.pc)); \ |
| 84 | } while (0) |
| 85 | |
| 86 | #define fGEN_TCG_Y2_resume(SHORTCODE) \ |
| 87 | gen_helper_resume(tcg_env, RsV) |
| 88 | |
| 89 | #define fGEN_TCG_Y2_start(SHORTCODE) \ |
| 90 | gen_helper_start(tcg_env, RsV) |
| 91 | |
| 92 | #define fGEN_TCG_Y2_stop(SHORTCODE) \ |
| 93 | do { \ |
| 94 | RsV = RsV; \ |
| 95 | gen_helper_stop(tcg_env); \ |
| 96 | } while (0) |
| 97 | |
| 98 | #define fGEN_TCG_Y2_tfrscrr(SHORTCODE) \ |
| 99 | tcg_gen_mov_tl(RdV, SsV) |
| 100 | |
| 101 | #define fGEN_TCG_Y2_tfrsrcr(SHORTCODE) \ |
| 102 | tcg_gen_mov_tl(SdV, RsV) |
| 103 | |
| 104 | #define fGEN_TCG_Y4_tfrscpp(SHORTCODE) \ |
| 105 | tcg_gen_mov_i64(RddV, SssV) |
| 106 | |
| 107 | #define fGEN_TCG_Y4_tfrspcp(SHORTCODE) \ |
| 108 | tcg_gen_mov_i64(SddV, RssV) |
| 109 | |
| 110 | #define fGEN_TCG_G4_tfrgcrr(SHORTCODE) \ |
| 111 | tcg_gen_mov_tl(RdV, GsV) |
| 112 | |
| 113 | #define fGEN_TCG_G4_tfrgrcr(SHORTCODE) \ |
| 114 | tcg_gen_mov_tl(GdV, RsV) |
| 115 | |
| 116 | #define fGEN_TCG_G4_tfrgcpp(SHORTCODE) \ |
| 117 | tcg_gen_mov_i64(RddV, GssV) |
| 118 | |
| 119 | #define fGEN_TCG_G4_tfrgpcp(SHORTCODE) \ |
| 120 | tcg_gen_mov_i64(GddV, RssV) |
| 121 | |
| 122 | |
| 123 | /* |
| 124 | * rte (return from exception) |
| 125 | * Clear the EX bit in SSR |
| 126 | * Jump to ELR |
| 127 | */ |
| 128 | #define fGEN_TCG_J2_rte(SHORTCODE) \ |
| 129 | do { \ |
| 130 | TCGv_i32 new_ssr = tcg_temp_new_i32(); \ |
| 131 | tcg_gen_deposit_tl(new_ssr, hex_t_sreg[HEX_SREG_SSR], \ |
| 132 | tcg_constant_tl(0), \ |
| 133 | reg_field_info[SSR_EX].offset, \ |
| 134 | reg_field_info[SSR_EX].width); \ |
| 135 | gen_log_sreg_write(ctx, HEX_SREG_SSR, new_ssr); \ |
| 136 | gen_jumpr(ctx, hex_t_sreg[HEX_SREG_ELR]); \ |
| 137 | } while (0) |
| 138 | |
| 139 | #endif |