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1 /*
2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef HEXAGON_HEX_REGS_H
19 #define HEXAGON_HEX_REGS_H
20
21 enum {
22 HEX_REG_R00 = 0,
23 HEX_REG_R01 = 1,
24 HEX_REG_R02 = 2,
25 HEX_REG_R03 = 3,
26 HEX_REG_R04 = 4,
27 HEX_REG_R05 = 5,
28 HEX_REG_R06 = 6,
29 HEX_REG_R07 = 7,
30 HEX_REG_R08 = 8,
31 HEX_REG_R09 = 9,
32 HEX_REG_R10 = 10,
33 HEX_REG_R11 = 11,
34 HEX_REG_R12 = 12,
35 HEX_REG_R13 = 13,
36 HEX_REG_R14 = 14,
37 HEX_REG_R15 = 15,
38 HEX_REG_R16 = 16,
39 HEX_REG_R17 = 17,
40 HEX_REG_R18 = 18,
41 HEX_REG_R19 = 19,
42 HEX_REG_R20 = 20,
43 HEX_REG_R21 = 21,
44 HEX_REG_R22 = 22,
45 HEX_REG_R23 = 23,
46 HEX_REG_R24 = 24,
47 HEX_REG_R25 = 25,
48 HEX_REG_R26 = 26,
49 HEX_REG_R27 = 27,
50 HEX_REG_R28 = 28,
51 HEX_REG_R29 = 29,
52 HEX_REG_SP = 29,
53 HEX_REG_FP = 30,
54 HEX_REG_R30 = 30,
55 HEX_REG_LR = 31,
56 HEX_REG_R31 = 31,
57 HEX_REG_SA0 = 32,
58 HEX_REG_LC0 = 33,
59 HEX_REG_SA1 = 34,
60 HEX_REG_LC1 = 35,
61 HEX_REG_P3_0_ALIASED = 36,
62 HEX_REG_M0 = 38,
63 HEX_REG_M1 = 39,
64 HEX_REG_USR = 40,
65 HEX_REG_PC = 41,
66 HEX_REG_UGP = 42,
67 HEX_REG_GP = 43,
68 HEX_REG_CS0 = 44,
69 HEX_REG_CS1 = 45,
70 HEX_REG_UPCYCLELO = 46,
71 HEX_REG_UPCYCLEHI = 47,
72 HEX_REG_FRAMELIMIT = 48,
73 HEX_REG_FRAMEKEY = 49,
74 HEX_REG_PKTCNTLO = 50,
75 HEX_REG_PKTCNTHI = 51,
76 /* Use reserved control registers for qemu execution counts */
77 HEX_REG_QEMU_PKT_CNT = 52,
78 HEX_REG_QEMU_INSN_CNT = 53,
79 HEX_REG_QEMU_HVX_CNT = 54,
80 HEX_REG_UTIMERLO = 62,
81 HEX_REG_UTIMERHI = 63,
82 };
83
84 #ifndef CONFIG_USER_ONLY
85
86 #define HEX_GREG_VALUES \
87 DECL_HEX_GREG(G0, 0) \
88 DECL_HEX_GREG(GELR, 0) \
89 DECL_HEX_GREG(G1, 1) \
90 DECL_HEX_GREG(GSR, 1) \
91 DECL_HEX_GREG(G2, 2) \
92 DECL_HEX_GREG(GOSP, 2) \
93 DECL_HEX_GREG(G3, 3) \
94 DECL_HEX_GREG(GBADVA, 3) \
95 DECL_HEX_GREG(GCYCLE_1T, 10) \
96 DECL_HEX_GREG(GCYCLE_2T, 11) \
97 DECL_HEX_GREG(GCYCLE_3T, 12) \
98 DECL_HEX_GREG(GCYCLE_4T, 13) \
99 DECL_HEX_GREG(GCYCLE_5T, 14) \
100 DECL_HEX_GREG(GCYCLE_6T, 15) \
101 DECL_HEX_GREG(GPMUCNT4, 16) \
102 DECL_HEX_GREG(GPMUCNT5, 17) \
103 DECL_HEX_GREG(GPMUCNT6, 18) \
104 DECL_HEX_GREG(GPMUCNT7, 19) \
105 DECL_HEX_GREG(GPCYCLELO, 24) \
106 DECL_HEX_GREG(GPCYCLEHI, 25) \
107 DECL_HEX_GREG(GPMUCNT0, 26) \
108 DECL_HEX_GREG(GPMUCNT1, 27) \
109 DECL_HEX_GREG(GPMUCNT2, 28) \
110 DECL_HEX_GREG(GPMUCNT3, 29) \
111 DECL_HEX_GREG_DONE
112
113 #define DECL_HEX_GREG_DONE
114 #define DECL_HEX_GREG(name, val) HEX_GREG_ ##name = val,
115 enum hex_greg {
116 HEX_GREG_VALUES
117 };
118 #undef DECL_HEX_GREG
119 #undef DECL_HEX_GREG_DONE
120
121 #define DECL_HEX_GREG_DONE 0
122 #define DECL_HEX_GREG(_, val) (1 << val) |
123 static inline bool greg_implemented(enum hex_greg greg)
124 {
125 #if NUM_GREGS > 32
126 #error "NUM_GREGS too large for greg_implemented(): update `impl_bitmap`"
127 #endif
128 static int32_t impl_bitmap = HEX_GREG_VALUES;
129 return impl_bitmap & (1 << greg);
130 }
131 #undef DECL_HEX_GREG
132 #undef DECL_HEX_GREG_DONE
133
134 #endif /* CONFIG_USER_ONLY */
135
136 #ifndef CONFIG_USER_ONLY
137 enum {
138 HEX_SREG_SGP0 = 0,
139 HEX_SREG_SGP1 = 1,
140 HEX_SREG_STID = 2,
141 HEX_SREG_ELR = 3,
142 HEX_SREG_BADVA0 = 4,
143 HEX_SREG_BADVA1 = 5,
144 HEX_SREG_SSR = 6,
145 HEX_SREG_CCR = 7,
146 HEX_SREG_HTID = 8,
147 HEX_SREG_BADVA = 9,
148 HEX_SREG_IMASK = 10,
149 HEX_SREG_GEVB = 11,
150 HEX_SREG_GLB_START = 16,
151 HEX_SREG_EVB = 16,
152 HEX_SREG_MODECTL = 17,
153 HEX_SREG_SYSCFG = 18,
154 HEX_SREG_IPENDAD = 20,
155 HEX_SREG_VID = 21,
156 HEX_SREG_VID1 = 22,
157 HEX_SREG_BESTWAIT = 23,
158 HEX_SREG_IEL = 24,
159 HEX_SREG_SCHEDCFG = 25,
160 HEX_SREG_IAHL = 26,
161 HEX_SREG_CFGBASE = 27,
162 HEX_SREG_DIAG = 28,
163 HEX_SREG_REV = 29,
164 HEX_SREG_PCYCLELO = 30,
165 HEX_SREG_PCYCLEHI = 31,
166 HEX_SREG_ISDBST = 32,
167 HEX_SREG_ISDBCFG0 = 33,
168 HEX_SREG_ISDBCFG1 = 34,
169 HEX_SREG_LIVELOCK = 35,
170 HEX_SREG_BRKPTPC0 = 36,
171 HEX_SREG_BRKPTCFG0 = 37,
172 HEX_SREG_BRKPTPC1 = 38,
173 HEX_SREG_BRKPTCFG1 = 39,
174 HEX_SREG_ISDBMBXIN = 40,
175 HEX_SREG_ISDBMBXOUT = 41,
176 HEX_SREG_ISDBEN = 42,
177 HEX_SREG_ISDBGPR = 43,
178 HEX_SREG_PMUCNT4 = 44,
179 HEX_SREG_PMUCNT5 = 45,
180 HEX_SREG_PMUCNT6 = 46,
181 HEX_SREG_PMUCNT7 = 47,
182 HEX_SREG_PMUCNT0 = 48,
183 HEX_SREG_PMUCNT1 = 49,
184 HEX_SREG_PMUCNT2 = 50,
185 HEX_SREG_PMUCNT3 = 51,
186 HEX_SREG_PMUEVTCFG = 52,
187 HEX_SREG_PMUSTID0 = 53,
188 HEX_SREG_PMUEVTCFG1 = 54,
189 HEX_SREG_PMUSTID1 = 55,
190 HEX_SREG_TIMERLO = 56,
191 HEX_SREG_TIMERHI = 57,
192 HEX_SREG_PMUCFG = 58,
193 HEX_SREG_S59 = 59,
194 HEX_SREG_S60 = 60,
195 HEX_SREG_S61 = 61,
196 HEX_SREG_S62 = 62,
197 HEX_SREG_S63 = 63,
198 };
199 #endif /* !CONFIG_USER_ONLY */
200
201 #endif