| 1 | /* |
| 2 | * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | /* |
| 19 | * Encodings for 32 bit instructions |
| 20 | * |
| 21 | */ |
| 22 | |
| 23 | |
| 24 | |
| 25 | |
| 26 | DEF_CLASS32("---- ---- -------- PP------ --------",ALL_PP) |
| 27 | DEF_FIELD32("---- ---- -------- !!------ --------",Parse,"Packet/Loop parse bits") |
| 28 | DEF_FIELD32("!!!! ---- -------- PP------ --------",ICLASS,"Instruction Class") |
| 29 | |
| 30 | #define ICLASS_EXTENDER "0000" |
| 31 | #define ICLASS_CJ "0001" |
| 32 | #define ICLASS_NCJ "0010" |
| 33 | #define ICLASS_V4LDST "0011" |
| 34 | #define ICLASS_V2LDST "0100" |
| 35 | #define ICLASS_J "0101" |
| 36 | #define ICLASS_CR "0110" |
| 37 | #define ICLASS_ALU2op "0111" |
| 38 | #define ICLASS_S2op "1000" |
| 39 | #define ICLASS_LD "1001" |
| 40 | #define ICLASS_ST "1010" |
| 41 | #define ICLASS_ADDI "1011" |
| 42 | #define ICLASS_S3op "1100" |
| 43 | #define ICLASS_ALU64 "1101" |
| 44 | #define ICLASS_M "1110" |
| 45 | #define ICLASS_ALU3op "1111" |
| 46 | |
| 47 | |
| 48 | |
| 49 | /*******************************/ |
| 50 | /* */ |
| 51 | /* */ |
| 52 | /* V4 Immediate Payload */ |
| 53 | /* */ |
| 54 | /* */ |
| 55 | /*******************************/ |
| 56 | |
| 57 | DEF_CLASS32(ICLASS_EXTENDER" ---- -------- PP------ --------",EXTENDER) |
| 58 | DEF_ENC32(A4_ext, ICLASS_EXTENDER "iiii iiiiiiii PPiiiiii iiiiiiii") |
| 59 | |
| 60 | |
| 61 | |
| 62 | /*******************************/ |
| 63 | /* */ |
| 64 | /* */ |
| 65 | /* V2 PREDICATED LD/ST */ |
| 66 | /* */ |
| 67 | /* */ |
| 68 | /*******************************/ |
| 69 | |
| 70 | DEF_CLASS32(ICLASS_V2LDST" ---- -------- PP------ --------",V2LDST) |
| 71 | DEF_CLASS32(ICLASS_V2LDST" ---1 -------- PP------ --------",V2LD) |
| 72 | DEF_CLASS32(ICLASS_V2LDST" ---0 -------- PP------ --------",V2ST) |
| 73 | DEF_CLASS32(ICLASS_V2LDST" 0--1 -------- PP------ --------",PLD) |
| 74 | DEF_CLASS32(ICLASS_V2LDST" 0--0 -------- PP------ --------",PST) |
| 75 | DEF_CLASS32(ICLASS_V2LDST" 1--1 -------- PP------ --------",GPLD) |
| 76 | DEF_CLASS32(ICLASS_V2LDST" 1--0 -------- PP------ --------",GPST) |
| 77 | |
| 78 | DEF_FIELD32(ICLASS_V2LDST" 0!-- -------- PP------ --------",PMEM_Sense,"Sense") |
| 79 | DEF_FIELD32(ICLASS_V2LDST" 0-!- -------- PP------ --------",PMEM_PredNew,"PredNew") |
| 80 | DEF_FIELD32(ICLASS_V2LDST" ---1 !!------ PP------ --------",PMEML_Type,"Type") |
| 81 | DEF_FIELD32(ICLASS_V2LDST" ---1 --!----- PP------ --------",PMEML_UN,"Unsigned") |
| 82 | DEF_FIELD32(ICLASS_V2LDST" ---0 !!!----- PP------ --------",PMEMS_Type,"Type") |
| 83 | |
| 84 | #define STD_PLD_IOENC(TAG,OPC) \ |
| 85 | DEF_ENC32(L2_pload##TAG##t_io, ICLASS_V2LDST" 0001 "OPC" sssss PP0ttiii iiiddddd")\ |
| 86 | DEF_ENC32(L2_pload##TAG##f_io, ICLASS_V2LDST" 0101 "OPC" sssss PP0ttiii iiiddddd")\ |
| 87 | DEF_ENC32(L2_pload##TAG##tnew_io,ICLASS_V2LDST" 0011 "OPC" sssss PP0ttiii iiiddddd")\ |
| 88 | DEF_ENC32(L2_pload##TAG##fnew_io,ICLASS_V2LDST" 0111 "OPC" sssss PP0ttiii iiiddddd") |
| 89 | |
| 90 | STD_PLD_IOENC(rb, "000") |
| 91 | STD_PLD_IOENC(rub, "001") |
| 92 | STD_PLD_IOENC(rh, "010") |
| 93 | STD_PLD_IOENC(ruh, "011") |
| 94 | STD_PLD_IOENC(ri, "100") |
| 95 | STD_PLD_IOENC(rd, "110") /* note dest reg field LSB=0, 1 is reserved */ |
| 96 | |
| 97 | |
| 98 | |
| 99 | #define STD_PST_IOENC(TAG,OPC,SRC) \ |
| 100 | DEF_ENC32(S2_pstore##TAG##t_io, ICLASS_V2LDST" 0000 "OPC" sssss PPi"SRC" iiiii0vv")\ |
| 101 | DEF_ENC32(S2_pstore##TAG##f_io, ICLASS_V2LDST" 0100 "OPC" sssss PPi"SRC" iiiii0vv")\ |
| 102 | DEF_ENC32(S4_pstore##TAG##tnew_io,ICLASS_V2LDST" 0010 "OPC" sssss PPi"SRC" iiiii0vv")\ |
| 103 | DEF_ENC32(S4_pstore##TAG##fnew_io,ICLASS_V2LDST" 0110 "OPC" sssss PPi"SRC" iiiii0vv") |
| 104 | |
| 105 | STD_PST_IOENC(rb, "000","ttttt") |
| 106 | STD_PST_IOENC(rh, "010","ttttt") |
| 107 | STD_PST_IOENC(rf, "011","ttttt") |
| 108 | STD_PST_IOENC(ri, "100","ttttt") |
| 109 | STD_PST_IOENC(rd, "110","ttttt") |
| 110 | STD_PST_IOENC(rbnew, "101","00ttt") |
| 111 | STD_PST_IOENC(rhnew, "101","01ttt") |
| 112 | STD_PST_IOENC(rinew, "101","10ttt") |
| 113 | |
| 114 | |
| 115 | |
| 116 | |
| 117 | |
| 118 | /*******************************/ |
| 119 | /* */ |
| 120 | /* */ |
| 121 | /* V2 GP-RELATIVE LD/ST */ |
| 122 | /* */ |
| 123 | /* */ |
| 124 | /*******************************/ |
| 125 | #define STD_LD_GP(TAG,OPC) \ |
| 126 | DEF_ENC32(L2_load##TAG##gp, ICLASS_V2LDST" 1ii1 "OPC" iiiii PPiiiiii iiiddddd") |
| 127 | |
| 128 | STD_LD_GP(rb, "000") |
| 129 | STD_LD_GP(rub, "001") |
| 130 | STD_LD_GP(rh, "010") |
| 131 | STD_LD_GP(ruh, "011") |
| 132 | STD_LD_GP(ri, "100") |
| 133 | STD_LD_GP(rd, "110") /* note dest reg field LSB=0, 1 is reserved */ |
| 134 | |
| 135 | #define STD_ST_GP(TAG,OPC,SRC) \ |
| 136 | DEF_ENC32(S2_store##TAG##gp, ICLASS_V2LDST" 1ii0 "OPC" iiiii PPi"SRC" iiiiiiii") |
| 137 | |
| 138 | STD_ST_GP(rb, "000","ttttt") |
| 139 | STD_ST_GP(rh, "010","ttttt") |
| 140 | STD_ST_GP(rf, "011","ttttt") |
| 141 | STD_ST_GP(ri, "100","ttttt") |
| 142 | STD_ST_GP(rd, "110","ttttt") |
| 143 | STD_ST_GP(rbnew,"101","00ttt") |
| 144 | STD_ST_GP(rhnew,"101","01ttt") |
| 145 | STD_ST_GP(rinew,"101","10ttt") |
| 146 | |
| 147 | |
| 148 | |
| 149 | |
| 150 | |
| 151 | /*******************************/ |
| 152 | /* */ |
| 153 | /* */ |
| 154 | /* V4LDST */ |
| 155 | /* */ |
| 156 | /* */ |
| 157 | /*******************************/ |
| 158 | |
| 159 | |
| 160 | DEF_CLASS32(ICLASS_V4LDST" ---- -------- PP------ --------",V4LDST) |
| 161 | DEF_CLASS32(ICLASS_V4LDST" 0--- -------- PP------ --------",Pred_RplusR) |
| 162 | DEF_CLASS32(ICLASS_V4LDST" 100- -------- PP------ --------",Pred_StoreImmed) |
| 163 | DEF_CLASS32(ICLASS_V4LDST" 101- -------- PP------ --------",RplusR) |
| 164 | DEF_CLASS32(ICLASS_V4LDST" 110- -------- PP------ --------",StoreImmed) |
| 165 | DEF_CLASS32(ICLASS_V4LDST" 111- -------- PP------ --------",MemOp) |
| 166 | |
| 167 | |
| 168 | |
| 169 | |
| 170 | /*******************************/ |
| 171 | /* Pred (R+R) */ |
| 172 | /*******************************/ |
| 173 | |
| 174 | #define STD_PLD_RRENC(TAG,OPC) \ |
| 175 | DEF_ENC32(L4_pload##TAG##t_rr, ICLASS_V4LDST" 00 00 "OPC" sssss PPittttt ivvddddd")\ |
| 176 | DEF_ENC32(L4_pload##TAG##f_rr, ICLASS_V4LDST" 00 01 "OPC" sssss PPittttt ivvddddd")\ |
| 177 | DEF_ENC32(L4_pload##TAG##tnew_rr,ICLASS_V4LDST" 00 10 "OPC" sssss PPittttt ivvddddd")\ |
| 178 | DEF_ENC32(L4_pload##TAG##fnew_rr,ICLASS_V4LDST" 00 11 "OPC" sssss PPittttt ivvddddd") |
| 179 | |
| 180 | STD_PLD_RRENC(rb, "000") |
| 181 | STD_PLD_RRENC(rub, "001") |
| 182 | STD_PLD_RRENC(rh, "010") |
| 183 | STD_PLD_RRENC(ruh, "011") |
| 184 | STD_PLD_RRENC(ri, "100") |
| 185 | STD_PLD_RRENC(rd, "110") |
| 186 | |
| 187 | #define STD_PST_RRENC(TAG,OPC,SRC) \ |
| 188 | DEF_ENC32(S4_pstore##TAG##t_rr, ICLASS_V4LDST" 01 00 "OPC" sssss PPiuuuuu ivv"SRC)\ |
| 189 | DEF_ENC32(S4_pstore##TAG##f_rr, ICLASS_V4LDST" 01 01 "OPC" sssss PPiuuuuu ivv"SRC)\ |
| 190 | DEF_ENC32(S4_pstore##TAG##tnew_rr,ICLASS_V4LDST" 01 10 "OPC" sssss PPiuuuuu ivv"SRC)\ |
| 191 | DEF_ENC32(S4_pstore##TAG##fnew_rr,ICLASS_V4LDST" 01 11 "OPC" sssss PPiuuuuu ivv"SRC) |
| 192 | |
| 193 | STD_PST_RRENC(rb, "000","ttttt") |
| 194 | STD_PST_RRENC(rh, "010","ttttt") |
| 195 | STD_PST_RRENC(rf, "011","ttttt") |
| 196 | STD_PST_RRENC(ri, "100","ttttt") |
| 197 | STD_PST_RRENC(rd, "110","ttttt") |
| 198 | STD_PST_RRENC(rbnew, "101","00ttt") |
| 199 | STD_PST_RRENC(rhnew, "101","01ttt") |
| 200 | STD_PST_RRENC(rinew, "101","10ttt") |
| 201 | |
| 202 | |
| 203 | |
| 204 | /*******************************/ |
| 205 | /* Pred Store immediates */ |
| 206 | /*******************************/ |
| 207 | |
| 208 | #define V4_PSTI(TAG,OPC) \ |
| 209 | DEF_ENC32(S4_storei##TAG##t_io, ICLASS_V4LDST" 100 00 "OPC" sssss PPIiiiii ivvIIIII")\ |
| 210 | DEF_ENC32(S4_storei##TAG##f_io, ICLASS_V4LDST" 100 01 "OPC" sssss PPIiiiii ivvIIIII")\ |
| 211 | DEF_ENC32(S4_storei##TAG##tnew_io, ICLASS_V4LDST" 100 10 "OPC" sssss PPIiiiii ivvIIIII")\ |
| 212 | DEF_ENC32(S4_storei##TAG##fnew_io, ICLASS_V4LDST" 100 11 "OPC" sssss PPIiiiii ivvIIIII") |
| 213 | |
| 214 | V4_PSTI(rb, "00") |
| 215 | V4_PSTI(rh, "01") |
| 216 | V4_PSTI(ri, "10") |
| 217 | |
| 218 | |
| 219 | |
| 220 | /*******************************/ |
| 221 | /* (R+R) */ |
| 222 | /*******************************/ |
| 223 | |
| 224 | #define STD_LD_RRENC(TAG,OPC) \ |
| 225 | DEF_ENC32(L4_load##TAG##_rr, ICLASS_V4LDST" 1010 "OPC" sssss PPittttt i--ddddd") |
| 226 | |
| 227 | STD_LD_RRENC(rb, "000") |
| 228 | STD_LD_RRENC(rub, "001") |
| 229 | STD_LD_RRENC(rh, "010") |
| 230 | STD_LD_RRENC(ruh, "011") |
| 231 | STD_LD_RRENC(ri, "100") |
| 232 | STD_LD_RRENC(rd, "110") |
| 233 | |
| 234 | #define STD_ST_RRENC(TAG,OPC,SRC) \ |
| 235 | DEF_ENC32(S4_store##TAG##_rr, ICLASS_V4LDST" 1011 "OPC" sssss PPiuuuuu i--"SRC) |
| 236 | |
| 237 | STD_ST_RRENC(rb, "000","ttttt") |
| 238 | STD_ST_RRENC(rh, "010","ttttt") |
| 239 | STD_ST_RRENC(rf, "011","ttttt") |
| 240 | STD_ST_RRENC(ri, "100","ttttt") |
| 241 | STD_ST_RRENC(rd, "110","ttttt") |
| 242 | STD_ST_RRENC(rbnew, "101","00ttt") |
| 243 | STD_ST_RRENC(rhnew, "101","01ttt") |
| 244 | STD_ST_RRENC(rinew, "101","10ttt") |
| 245 | |
| 246 | |
| 247 | |
| 248 | |
| 249 | /*******************************/ |
| 250 | /* Store immediates */ |
| 251 | /*******************************/ |
| 252 | |
| 253 | #define V4_STI(TAG,OPC) \ |
| 254 | DEF_ENC32(S4_storei##TAG##_io, ICLASS_V4LDST" 110 -- "OPC" sssss PPIiiiii iIIIIIII") |
| 255 | |
| 256 | |
| 257 | V4_STI(rb, "00") |
| 258 | V4_STI(rh, "01") |
| 259 | V4_STI(ri, "10") |
| 260 | |
| 261 | |
| 262 | /*******************************/ |
| 263 | /* Memops */ |
| 264 | /*******************************/ |
| 265 | |
| 266 | #define MEMOPENC(TAG,OPC) \ |
| 267 | DEF_ENC32(L4_add_##TAG##_io, ICLASS_V4LDST" 111 0- " OPC "sssss PP0iiiii i00ttttt")\ |
| 268 | DEF_ENC32(L4_sub_##TAG##_io, ICLASS_V4LDST" 111 0- " OPC "sssss PP0iiiii i01ttttt")\ |
| 269 | DEF_ENC32(L4_and_##TAG##_io, ICLASS_V4LDST" 111 0- " OPC "sssss PP0iiiii i10ttttt")\ |
| 270 | DEF_ENC32(L4_or_##TAG##_io, ICLASS_V4LDST" 111 0- " OPC "sssss PP0iiiii i11ttttt")\ |
| 271 | \ |
| 272 | DEF_ENC32(L4_iadd_##TAG##_io, ICLASS_V4LDST" 111 1- " OPC "sssss PP0iiiii i00IIIII")\ |
| 273 | DEF_ENC32(L4_isub_##TAG##_io, ICLASS_V4LDST" 111 1- " OPC "sssss PP0iiiii i01IIIII")\ |
| 274 | DEF_ENC32(L4_iand_##TAG##_io, ICLASS_V4LDST" 111 1- " OPC "sssss PP0iiiii i10IIIII")\ |
| 275 | DEF_ENC32(L4_ior_##TAG##_io, ICLASS_V4LDST" 111 1- " OPC "sssss PP0iiiii i11IIIII") |
| 276 | |
| 277 | |
| 278 | |
| 279 | MEMOPENC(memopw,"10") |
| 280 | MEMOPENC(memoph,"01") |
| 281 | MEMOPENC(memopb,"00") |
| 282 | |
| 283 | |
| 284 | |
| 285 | |
| 286 | /*******************************/ |
| 287 | /* */ |
| 288 | /* */ |
| 289 | /* LOAD */ |
| 290 | /* */ |
| 291 | /* */ |
| 292 | /*******************************/ |
| 293 | DEF_CLASS32(ICLASS_LD" ---- -------- PP------ --------",LD) |
| 294 | |
| 295 | |
| 296 | DEF_CLASS32(ICLASS_LD" 0--- -------- PP------ --------",LD_ADDR_ROFFSET) |
| 297 | DEF_CLASS32(ICLASS_LD" 100- -------- PP----0- --------",LD_ADDR_POST_CIRC_IMMED) |
| 298 | DEF_CLASS32(ICLASS_LD" 101- -------- PP00---- --------",LD_ADDR_POST_IMMED) |
| 299 | DEF_CLASS32(ICLASS_LD" 101- -------- PP01---- --------",LD_ADDR_ABS_UPDATE_V4) |
| 300 | DEF_CLASS32(ICLASS_LD" 101- -------- PP1----- --------",LD_ADDR_POST_IMMED_PRED_V2) |
| 301 | DEF_CLASS32(ICLASS_LD" 110- -------- PP-0---- 0-------",LD_ADDR_POST_REG) |
| 302 | DEF_CLASS32(ICLASS_LD" 110- -------- PP-1---- --------",LD_ADDR_ABS_PLUS_REG_V4) |
| 303 | DEF_CLASS32(ICLASS_LD" 100- -------- PP----1- --------",LD_ADDR_POST_CREG_V2) |
| 304 | DEF_CLASS32(ICLASS_LD" 111- -------- PP------ 0-------",LD_ADDR_POST_BREV_REG) |
| 305 | DEF_CLASS32(ICLASS_LD" 111- -------- PP------ 1-------",LD_ADDR_PRED_ABS_V4) |
| 306 | |
| 307 | DEF_FIELD32(ICLASS_LD" !!!- -------- PP------ --------",LD_Amode,"Amode") |
| 308 | DEF_FIELD32(ICLASS_LD" ---! !!------ PP------ --------",LD_Type,"Type") |
| 309 | DEF_FIELD32(ICLASS_LD" ---- --!----- PP------ --------",LD_UN,"Unsigned") |
| 310 | |
| 311 | #define STD_LD_ENC(TAG,OPC) \ |
| 312 | DEF_ENC32(L2_load##TAG##_io, ICLASS_LD" 0 ii "OPC" sssss PPiiiiii iiiddddd")\ |
| 313 | DEF_ENC32(L2_load##TAG##_pci, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--0i iiiddddd")\ |
| 314 | DEF_ENC32(L2_load##TAG##_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP00---i iiiddddd")\ |
| 315 | DEF_ENC32(L4_load##TAG##_ap, ICLASS_LD" 1 01 "OPC" eeeee PP01IIII -IIddddd")\ |
| 316 | DEF_ENC32(L2_load##TAG##_pr, ICLASS_LD" 1 10 "OPC" xxxxx PPu0---- 0--ddddd")\ |
| 317 | DEF_ENC32(L4_load##TAG##_ur, ICLASS_LD" 1 10 "OPC" ttttt PPi1IIII iIIddddd")\ |
| 318 | DEF_ENC32(L2_load##TAG##_pcr, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--1- 0--ddddd")\ |
| 319 | DEF_ENC32(L2_load##TAG##_pbr, ICLASS_LD" 1 11 "OPC" xxxxx PPu0---- 0--ddddd") |
| 320 | |
| 321 | |
| 322 | #define STD_LDX_ENC(TAG,OPC) \ |
| 323 | DEF_ENC32(L2_load##TAG##_io, ICLASS_LD" 0 ii "OPC" sssss PPiiiiii iiiyyyyy")\ |
| 324 | DEF_ENC32(L2_load##TAG##_pci, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--0i iiiyyyyy")\ |
| 325 | DEF_ENC32(L2_load##TAG##_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP00---i iiiyyyyy")\ |
| 326 | DEF_ENC32(L4_load##TAG##_ap, ICLASS_LD" 1 01 "OPC" eeeee PP01IIII -IIyyyyy")\ |
| 327 | DEF_ENC32(L2_load##TAG##_pr, ICLASS_LD" 1 10 "OPC" xxxxx PPu0---- 0--yyyyy")\ |
| 328 | DEF_ENC32(L4_load##TAG##_ur, ICLASS_LD" 1 10 "OPC" ttttt PPi1IIII iIIyyyyy")\ |
| 329 | DEF_ENC32(L2_load##TAG##_pcr, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--1- 0--yyyyy")\ |
| 330 | DEF_ENC32(L2_load##TAG##_pbr, ICLASS_LD" 1 11 "OPC" xxxxx PPu0---- 0--yyyyy") |
| 331 | |
| 332 | |
| 333 | #define STD_PLD_ENC(TAG,OPC) \ |
| 334 | DEF_ENC32(L2_pload##TAG##t_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP100tti iiiddddd")\ |
| 335 | DEF_ENC32(L2_pload##TAG##f_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP101tti iiiddddd")\ |
| 336 | DEF_ENC32(L2_pload##TAG##tnew_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP110tti iiiddddd")\ |
| 337 | DEF_ENC32(L2_pload##TAG##fnew_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP111tti iiiddddd")\ |
| 338 | DEF_ENC32(L4_pload##TAG##t_abs, ICLASS_LD" 1 11 "OPC" iiiii PP100tti 1--ddddd")\ |
| 339 | DEF_ENC32(L4_pload##TAG##f_abs, ICLASS_LD" 1 11 "OPC" iiiii PP101tti 1--ddddd")\ |
| 340 | DEF_ENC32(L4_pload##TAG##tnew_abs,ICLASS_LD" 1 11 "OPC" iiiii PP110tti 1--ddddd")\ |
| 341 | DEF_ENC32(L4_pload##TAG##fnew_abs,ICLASS_LD" 1 11 "OPC" iiiii PP111tti 1--ddddd") |
| 342 | |
| 343 | |
| 344 | /* 0 000 misc: dealloc,loadw_locked,dcfetch */ |
| 345 | STD_LD_ENC(bzw4,"0 101") |
| 346 | STD_LD_ENC(bzw2,"0 011") |
| 347 | |
| 348 | STD_LD_ENC(bsw4,"0 111") |
| 349 | STD_LD_ENC(bsw2,"0 001") |
| 350 | |
| 351 | STD_LDX_ENC(alignh,"0 010") |
| 352 | STD_LDX_ENC(alignb,"0 100") |
| 353 | |
| 354 | STD_LD_ENC(rb, "1 000") |
| 355 | STD_LD_ENC(rub, "1 001") |
| 356 | STD_LD_ENC(rh, "1 010") |
| 357 | STD_LD_ENC(ruh, "1 011") |
| 358 | STD_LD_ENC(ri, "1 100") |
| 359 | STD_LD_ENC(rd, "1 110") /* note dest reg field LSB=0, 1 is reserved */ |
| 360 | |
| 361 | STD_PLD_ENC(rb, "1 000") |
| 362 | STD_PLD_ENC(rub, "1 001") |
| 363 | STD_PLD_ENC(rh, "1 010") |
| 364 | STD_PLD_ENC(ruh, "1 011") |
| 365 | STD_PLD_ENC(ri, "1 100") |
| 366 | STD_PLD_ENC(rd, "1 110") /* note dest reg field LSB=0, 1 is reserved */ |
| 367 | |
| 368 | |
| 369 | DEF_CLASS32( ICLASS_LD" 0--0 000----- PP------ --------",LD_MISC) |
| 370 | DEF_ANTICLASS32(ICLASS_LD" 0--0 000----- PP------ --------",LD_ADDR_ROFFSET) |
| 371 | DEF_ANTICLASS32(ICLASS_LD" 1000 000----- PP------ --------",LD_ADDR_POST_CIRC_IMMED) |
| 372 | DEF_ANTICLASS32(ICLASS_LD" 1010 000----- PP------ --------",LD_ADDR_POST_IMMED) |
| 373 | DEF_ANTICLASS32(ICLASS_LD" 1100 000----- PP------ --------",LD_ADDR_POST_REG) |
| 374 | DEF_ANTICLASS32(ICLASS_LD" 1110 000----- PP------ --------",LD_ADDR_POST_REG) |
| 375 | |
| 376 | DEF_ENC32(L2_deallocframe, ICLASS_LD" 000 0 000 sssss PP0----- ---ddddd") |
| 377 | DEF_ENC32(L4_return, ICLASS_LD" 011 0 000 sssss PP0000-- ---ddddd") |
| 378 | DEF_ENC32(L4_return_t, ICLASS_LD" 011 0 000 sssss PP0100vv ---ddddd") |
| 379 | DEF_ENC32(L4_return_f, ICLASS_LD" 011 0 000 sssss PP1100vv ---ddddd") |
| 380 | DEF_ENC32(L4_return_tnew_pt, ICLASS_LD" 011 0 000 sssss PP0110vv ---ddddd") |
| 381 | DEF_ENC32(L4_return_fnew_pt, ICLASS_LD" 011 0 000 sssss PP1110vv ---ddddd") |
| 382 | DEF_ENC32(L4_return_tnew_pnt, ICLASS_LD" 011 0 000 sssss PP0010vv ---ddddd") |
| 383 | DEF_ENC32(L4_return_fnew_pnt, ICLASS_LD" 011 0 000 sssss PP1010vv ---ddddd") |
| 384 | |
| 385 | /** Load Acquire Store Release Encoding **/ |
| 386 | |
| 387 | DEF_ENC32(L4_loadw_phys, ICLASS_LD" 001 0 000 sssss PP1ttttt -00ddddd") |
| 388 | DEF_ENC32(L2_loadw_locked, ICLASS_LD" 001 0 000 sssss PP000--- 000ddddd") |
| 389 | DEF_ENC32(L4_loadd_locked, ICLASS_LD" 001 0 000 sssss PP010--- 000ddddd") |
| 390 | |
| 391 | DEF_ENC32(L2_loadw_aq, ICLASS_LD" 001 0 000 sssss PP001--- 000ddddd") |
| 392 | DEF_ENC32(L4_loadd_aq, ICLASS_LD" 001 0 000 sssss PP011--- 000ddddd") |
| 393 | |
| 394 | |
| 395 | DEF_ENC32(S2_storew_locked, ICLASS_ST" 000 01 01sssss PP-ttttt ----00dd") |
| 396 | DEF_ENC32(S4_stored_locked, ICLASS_ST" 000 01 11sssss PP0ttttt ----00dd") |
| 397 | |
| 398 | |
| 399 | DEF_ENC32(S2_storew_rl_at_vi, ICLASS_ST" 000 01 01sssss PP-ttttt --0010dd") |
| 400 | DEF_ENC32(S2_storew_rl_st_vi, ICLASS_ST" 000 01 01sssss PP-ttttt --1010dd") |
| 401 | |
| 402 | DEF_ENC32(S4_stored_rl_at_vi, ICLASS_ST" 000 01 11sssss PP0ttttt --0010dd") |
| 403 | DEF_ENC32(S4_stored_rl_st_vi, ICLASS_ST" 000 01 11sssss PP0ttttt --1010dd") |
| 404 | |
| 405 | DEF_ENC32(R6_release_at_vi, ICLASS_ST" 000 01 11sssss PP0ttttt --0011dd") |
| 406 | DEF_ENC32(R6_release_st_vi, ICLASS_ST" 000 01 11sssss PP0ttttt --1011dd") |
| 407 | |
| 408 | DEF_EXT_SPACE(EXTRACTW, ICLASS_LD" 001 0 000 iiiii PP0iiiii 001iiiii") |
| 409 | DEF_ENC32(Y2_dcfetchbo, ICLASS_LD" 010 0 000 sssss PP0--iii iiiiiiii") |
| 410 | |
| 411 | |
| 412 | |
| 413 | |
| 414 | /*******************************/ |
| 415 | /* */ |
| 416 | /* */ |
| 417 | /* STORE */ |
| 418 | /* */ |
| 419 | /* */ |
| 420 | /*******************************/ |
| 421 | |
| 422 | DEF_CLASS32(ICLASS_ST" ---- -------- PP------ --------",ST) |
| 423 | |
| 424 | DEF_FIELD32(ICLASS_ST" !!!- -------- PP------ --------",ST_Amode,"Amode") |
| 425 | DEF_FIELD32(ICLASS_ST" ---! !!------ PP------ --------",ST_Type,"Type") |
| 426 | DEF_FIELD32(ICLASS_ST" ---- --!----- PP------ --------",ST_UN,"Unsigned") |
| 427 | |
| 428 | DEF_CLASS32(ICLASS_ST" 0--1 -------- PP------ --------",ST_ADDR_ROFFSET) |
| 429 | DEF_CLASS32(ICLASS_ST" 1001 -------- PP------ ------0-",ST_ADDR_POST_CIRC_IMMED) |
| 430 | DEF_CLASS32(ICLASS_ST" 1011 -------- PP0----- 0-----0-",ST_ADDR_POST_IMMED) |
| 431 | DEF_CLASS32(ICLASS_ST" 1011 -------- PP0----- 1-------",ST_ADDR_ABS_UPDATE_V4) |
| 432 | DEF_CLASS32(ICLASS_ST" 1011 -------- PP1----- --------",ST_ADDR_POST_IMMED_PRED_V2) |
| 433 | DEF_CLASS32(ICLASS_ST" 1111 -------- PP------ 1-------",ST_ADDR_PRED_ABS_V4) |
| 434 | DEF_CLASS32(ICLASS_ST" 1101 -------- PP------ 0-------",ST_ADDR_POST_REG) |
| 435 | DEF_CLASS32(ICLASS_ST" 1101 -------- PP------ 1-------",ST_ADDR_ABS_PLUS_REG_V4) |
| 436 | DEF_CLASS32(ICLASS_ST" 1001 -------- PP------ ------1-",ST_ADDR_POST_CREG_V2) |
| 437 | DEF_CLASS32(ICLASS_ST" 1111 -------- PP------ 0-------",ST_ADDR_POST_BREV_REG) |
| 438 | DEF_CLASS32(ICLASS_ST" 0--0 1------- PP------ --------",ST_MISC_STORELIKE) |
| 439 | DEF_CLASS32(ICLASS_ST" 1--0 0------- PP------ --------",ST_MISC_BUSOP) |
| 440 | DEF_CLASS32(ICLASS_ST" 0--0 0------- PP------ --------",ST_MISC_CACHEOP) |
| 441 | |
| 442 | |
| 443 | #define STD_ST_ENC(TAG,OPC,SRC) \ |
| 444 | DEF_ENC32(S2_store##TAG##_io, ICLASS_ST" 0 ii "OPC" sssss PPi"SRC" iiiiiiii")\ |
| 445 | DEF_ENC32(S2_store##TAG##_pci, ICLASS_ST" 1 00 "OPC" xxxxx PPu"SRC" 0iiii-0-")\ |
| 446 | DEF_ENC32(S2_store##TAG##_pi, ICLASS_ST" 1 01 "OPC" xxxxx PP0"SRC" 0iiii-0-")\ |
| 447 | DEF_ENC32(S4_store##TAG##_ap, ICLASS_ST" 1 01 "OPC" eeeee PP0"SRC" 1-IIIIII")\ |
| 448 | DEF_ENC32(S2_store##TAG##_pr, ICLASS_ST" 1 10 "OPC" xxxxx PPu"SRC" 0-------")\ |
| 449 | DEF_ENC32(S4_store##TAG##_ur, ICLASS_ST" 1 10 "OPC" uuuuu PPi"SRC" 1iIIIIII")\ |
| 450 | DEF_ENC32(S2_store##TAG##_pcr, ICLASS_ST" 1 00 "OPC" xxxxx PPu"SRC" 0-----1-")\ |
| 451 | DEF_ENC32(S2_store##TAG##_pbr, ICLASS_ST" 1 11 "OPC" xxxxx PPu"SRC" 0-------") |
| 452 | |
| 453 | |
| 454 | #define STD_PST_ENC(TAG,OPC,SRC) \ |
| 455 | DEF_ENC32(S2_pstore##TAG##t_pi, ICLASS_ST" 1 01 "OPC" xxxxx PP1"SRC" 0iiii0vv")\ |
| 456 | DEF_ENC32(S2_pstore##TAG##f_pi, ICLASS_ST" 1 01 "OPC" xxxxx PP1"SRC" 0iiii1vv")\ |
| 457 | DEF_ENC32(S2_pstore##TAG##tnew_pi, ICLASS_ST" 1 01 "OPC" xxxxx PP1"SRC" 1iiii0vv")\ |
| 458 | DEF_ENC32(S2_pstore##TAG##fnew_pi, ICLASS_ST" 1 01 "OPC" xxxxx PP1"SRC" 1iiii1vv")\ |
| 459 | DEF_ENC32(S4_pstore##TAG##t_abs, ICLASS_ST" 1 11 "OPC" ---ii PP0"SRC" 1iiii0vv")\ |
| 460 | DEF_ENC32(S4_pstore##TAG##f_abs, ICLASS_ST" 1 11 "OPC" ---ii PP0"SRC" 1iiii1vv")\ |
| 461 | DEF_ENC32(S4_pstore##TAG##tnew_abs,ICLASS_ST" 1 11 "OPC" ---ii PP1"SRC" 1iiii0vv")\ |
| 462 | DEF_ENC32(S4_pstore##TAG##fnew_abs,ICLASS_ST" 1 11 "OPC" ---ii PP1"SRC" 1iiii1vv") |
| 463 | |
| 464 | |
| 465 | /* 0 0-- Store Misc */ |
| 466 | /* 0 1xx Available */ |
| 467 | STD_ST_ENC(rb, "1 000","ttttt") |
| 468 | STD_ST_ENC(rh, "1 010","ttttt") |
| 469 | STD_ST_ENC(rf, "1 011","ttttt") |
| 470 | STD_ST_ENC(ri, "1 100","ttttt") |
| 471 | STD_ST_ENC(rd, "1 110","ttttt") |
| 472 | STD_ST_ENC(rbnew, "1 101","00ttt") |
| 473 | STD_ST_ENC(rhnew, "1 101","01ttt") |
| 474 | STD_ST_ENC(rinew, "1 101","10ttt") |
| 475 | |
| 476 | STD_PST_ENC(rb, "1 000","ttttt") |
| 477 | STD_PST_ENC(rh, "1 010","ttttt") |
| 478 | STD_PST_ENC(rf, "1 011","ttttt") |
| 479 | STD_PST_ENC(ri, "1 100","ttttt") |
| 480 | STD_PST_ENC(rd, "1 110","ttttt") |
| 481 | STD_PST_ENC(rbnew, "1 101","00ttt") |
| 482 | STD_PST_ENC(rhnew, "1 101","01ttt") |
| 483 | STD_PST_ENC(rinew, "1 101","10ttt") |
| 484 | |
| 485 | |
| 486 | |
| 487 | /* User */ |
| 488 | /* xx - st_misc */ |
| 489 | /* */ |
| 490 | /* x bus/cache */ |
| 491 | /* x store/cache */ |
| 492 | DEF_ENC32(S2_allocframe, ICLASS_ST" 000 01 00xxxxx PP000iii iiiiiiii") |
| 493 | DEF_ENC32(Y5_l2locka, ICLASS_ST" 000 01 11sssss PP1----- ------dd") |
| 494 | DEF_ENC32(Y2_dczeroa, ICLASS_ST" 000 01 10sssss PP0----- --------") |
| 495 | |
| 496 | |
| 497 | DEF_ENC32(Y2_barrier, ICLASS_ST" 100 00 00----- PP------ 000-----") |
| 498 | DEF_ENC32(Y2_syncht, ICLASS_ST" 100 00 10----- PP------ --------") |
| 499 | DEF_ENC32(Y2_l2kill, ICLASS_ST" 100 00 01----- PP-000-- --------") |
| 500 | DEF_ENC32(Y5_l2gunlock, ICLASS_ST" 100 00 01----- PP-010-- --------") |
| 501 | DEF_ENC32(Y5_l2gclean, ICLASS_ST" 100 00 01----- PP-100-- --------") |
| 502 | DEF_ENC32(Y5_l2gcleaninv, ICLASS_ST" 100 00 01----- PP-110-- --------") |
| 503 | DEF_ENC32(Y2_l2cleaninvidx,ICLASS_ST" 100 00 11sssss PP------ --------") |
| 504 | |
| 505 | |
| 506 | |
| 507 | DEF_ENC32(Y2_dccleana, ICLASS_ST" 000 00 00sssss PP------ --------") |
| 508 | DEF_ENC32(Y2_dcinva, ICLASS_ST" 000 00 01sssss PP------ --------") |
| 509 | DEF_ENC32(Y2_dccleaninva, ICLASS_ST" 000 00 10sssss PP------ --------") |
| 510 | |
| 511 | /* Super */ |
| 512 | DEF_ENC32(Y2_dckill, ICLASS_ST" 001 00 00----- PP------ --------") |
| 513 | DEF_ENC32(Y2_dccleanidx, ICLASS_ST" 001 00 01sssss PP------ --------") |
| 514 | DEF_ENC32(Y2_dcinvidx, ICLASS_ST" 001 00 10sssss PP------ --------") |
| 515 | DEF_ENC32(Y2_dccleaninvidx,ICLASS_ST" 001 00 11sssss PP------ --------") |
| 516 | |
| 517 | DEF_ENC32(Y2_dctagw ,ICLASS_ST" 010 00 00sssss PP-ttttt --------") |
| 518 | DEF_ENC32(Y2_dctagr ,ICLASS_ST" 010 00 01sssss PP------ ---ddddd") |
| 519 | |
| 520 | DEF_ENC32(Y4_l2tagw ,ICLASS_ST" 010 00 10sssss PP0ttttt --------") |
| 521 | DEF_ENC32(Y4_l2tagr ,ICLASS_ST" 010 00 11sssss PP------ ---ddddd") |
| 522 | |
| 523 | DEF_ENC32(Y4_l2fetch, ICLASS_ST" 011 00 00sssss PP-ttttt 000-----") |
| 524 | DEF_ENC32(Y5_l2cleanidx, ICLASS_ST" 011 00 01sssss PP------ --------") |
| 525 | DEF_ENC32(Y5_l2invidx, ICLASS_ST" 011 00 10sssss PP------ --------") |
| 526 | DEF_ENC32(Y5_l2unlocka, ICLASS_ST" 011 00 11sssss PP------ --------") |
| 527 | DEF_ENC32(Y5_l2fetch, ICLASS_ST" 011 01 00sssss PP-ttttt --------") |
| 528 | |
| 529 | DEF_ENC32(Y6_l2gcleanpa, ICLASS_ST" 011 01 01----- PP-ttttt --------") |
| 530 | DEF_ENC32(Y6_l2gcleaninvpa,ICLASS_ST" 011 01 10----- PP-ttttt --------") |
| 531 | |
| 532 | |
| 533 | /*******************************/ |
| 534 | /* */ |
| 535 | /* */ |
| 536 | /* JUMP */ |
| 537 | /* */ |
| 538 | /* */ |
| 539 | /*******************************/ |
| 540 | |
| 541 | DEF_CLASS32(ICLASS_J" ---- -------- PP------ --------",J) |
| 542 | DEF_CLASS32(ICLASS_J" 0--- -------- PP------ --------",JUMPR_MISC) |
| 543 | DEF_CLASS32(ICLASS_J" 10-- -------- PP------ --------",UCJUMP) |
| 544 | DEF_CLASS32(ICLASS_J" 110- -------- PP------ --------",CJUMP) |
| 545 | DEF_FIELD32(ICLASS_J" 110- -------- PP--!--- --------",J_DN,"Dot-new") |
| 546 | DEF_FIELD32(ICLASS_J" 110- -------- PP-!---- --------",J_PT,"Predict-taken") |
| 547 | |
| 548 | |
| 549 | |
| 550 | DEF_FIELDROW_DESC32(ICLASS_J" 0000 -------- PP------ --------","[#0] PC=(Rs), R31=return") |
| 551 | DEF_ENC32(J2_callr, ICLASS_J" 0000 101sssss PP------ --------") |
| 552 | DEF_ENC32(J2_callrh, ICLASS_J" 0000 110sssss PP------ --------") |
| 553 | |
| 554 | DEF_FIELDROW_DESC32(ICLASS_J" 0001 -------- PP------ --------","[#1] if (Pu) PC=(Rs), R31=return") |
| 555 | DEF_ENC32(J2_callrt, ICLASS_J" 0001 000sssss PP----uu --------") |
| 556 | DEF_ENC32(J2_callrf, ICLASS_J" 0001 001sssss PP----uu --------") |
| 557 | |
| 558 | DEF_FIELDROW_DESC32(ICLASS_J" 0010 -------- PP------ --------","[#2] PC=(Rs); ") |
| 559 | DEF_ENC32(J2_jumpr, ICLASS_J" 0010 100sssss PP------ --------") |
| 560 | DEF_ENC32(J2_jumprh, ICLASS_J" 0010 110sssss PP------ --------") |
| 561 | DEF_ENC32(J4_hintjumpr, ICLASS_J" 0010 101sssss PP------ --------") |
| 562 | |
| 563 | DEF_FIELDROW_DESC32(ICLASS_J" 0011 -------- PP------ --------","[#3] if (Pu) PC=(Rs) ") |
| 564 | DEF_ENC32(J2_jumprt, ICLASS_J" 0011 010sssss PP-00-uu --------") |
| 565 | DEF_ENC32(J2_jumprf, ICLASS_J" 0011 011sssss PP-00-uu --------") |
| 566 | DEF_ENC32(J2_jumprtpt, ICLASS_J" 0011 010sssss PP-10-uu --------") |
| 567 | DEF_ENC32(J2_jumprfpt, ICLASS_J" 0011 011sssss PP-10-uu --------") |
| 568 | DEF_ENC32(J2_jumprtnew, ICLASS_J" 0011 010sssss PP-01-uu --------") |
| 569 | DEF_ENC32(J2_jumprfnew, ICLASS_J" 0011 011sssss PP-01-uu --------") |
| 570 | DEF_ENC32(J2_jumprtnewpt, ICLASS_J" 0011 010sssss PP-11-uu --------") |
| 571 | DEF_ENC32(J2_jumprfnewpt, ICLASS_J" 0011 011sssss PP-11-uu --------") |
| 572 | |
| 573 | DEF_FIELDROW_DESC32(ICLASS_J" 0100 -------- PP------ --------","[#4] (#u8) ") |
| 574 | DEF_ENC32(J2_trap0, ICLASS_J" 0100 00------ PP-iiiii ---iii--") |
| 575 | DEF_ENC32(J2_trap1, ICLASS_J" 0100 10-xxxxx PP-iiiii ---iii--") |
| 576 | DEF_ENC32(J2_pause, ICLASS_J" 0100 01----ii PP-iiiii ---iii--") |
| 577 | |
| 578 | DEF_FIELDROW_DESC32(ICLASS_J" 0101 -------- PP------ --------","[#5] Rd=(Rs) ") |
| 579 | DEF_ENC32(Y2_icdatar, ICLASS_J" 0101 101sssss PP------ ---ddddd") |
| 580 | DEF_ENC32(Y2_ictagr, ICLASS_J" 0101 111sssss PP------ ---ddddd") |
| 581 | DEF_ENC32(Y2_ictagw, ICLASS_J" 0101 110sssss PP0ttttt --------") |
| 582 | DEF_ENC32(Y2_icdataw, ICLASS_J" 0101 110sssss PP1ttttt --------") |
| 583 | |
| 584 | DEF_FIELDROW_DESC32(ICLASS_J" 0110 -------- PP------ --------","[#6] icop(Rs) ") |
| 585 | DEF_ENC32(Y2_icinva, ICLASS_J" 0110 110sssss PP000--- --------") |
| 586 | DEF_ENC32(Y2_icinvidx, ICLASS_J" 0110 110sssss PP001--- --------") |
| 587 | DEF_ENC32(Y2_ickill, ICLASS_J" 0110 110----- PP010--- --------") |
| 588 | |
| 589 | DEF_FIELDROW_DESC32(ICLASS_J" 0111 -------- PP------ --------","[#7] () ") |
| 590 | DEF_ENC32(Y2_isync, ICLASS_J" 0111 11000000 PP0---00 00000010") |
| 591 | DEF_ENC32(J2_rte, ICLASS_J" 0111 111----- PP00---- 000-----") |
| 592 | |
| 593 | /* JUMP */ |
| 594 | DEF_FIELDROW_DESC32(ICLASS_J" 100- -------- PP------ --------","[#8,9] PC=(#r22)") |
| 595 | DEF_ENC32(J2_jump, ICLASS_J" 100i iiiiiiii PPiiiiii iiiiiii-") |
| 596 | |
| 597 | DEF_FIELDROW_DESC32(ICLASS_J" 101- -------- PP------ --------","[#10,11] PC=(#r22), R31=return") |
| 598 | DEF_ENC32(J2_call, ICLASS_J" 101i iiiiiiii PPiiiiii iiiiiii0") |
| 599 | |
| 600 | DEF_FIELDROW_DESC32(ICLASS_J" 1100 -------- PP------ --------","[#12] if (Pu) PC=(#r15)") |
| 601 | DEF_ENC32(J2_jumpt, ICLASS_J" 1100 ii0iiiii PPi00-uu iiiiiii-") |
| 602 | DEF_ENC32(J2_jumpf, ICLASS_J" 1100 ii1iiiii PPi00-uu iiiiiii-") |
| 603 | DEF_ENC32(J2_jumptpt, ICLASS_J" 1100 ii0iiiii PPi10-uu iiiiiii-") |
| 604 | DEF_ENC32(J2_jumpfpt, ICLASS_J" 1100 ii1iiiii PPi10-uu iiiiiii-") |
| 605 | DEF_ENC32(J2_jumptnew, ICLASS_J" 1100 ii0iiiii PPi01-uu iiiiiii-") |
| 606 | DEF_ENC32(J2_jumpfnew, ICLASS_J" 1100 ii1iiiii PPi01-uu iiiiiii-") |
| 607 | DEF_ENC32(J2_jumptnewpt,ICLASS_J" 1100 ii0iiiii PPi11-uu iiiiiii-") |
| 608 | DEF_ENC32(J2_jumpfnewpt,ICLASS_J" 1100 ii1iiiii PPi11-uu iiiiiii-") |
| 609 | |
| 610 | DEF_FIELDROW_DESC32(ICLASS_J" 1101 -------- PP------ --------","[#13] if (Pu) PC=(#r15), R31=return") |
| 611 | DEF_ENC32(J2_callt, ICLASS_J" 1101 ii0iiiii PPi-0-uu iiiiiii-") |
| 612 | DEF_ENC32(J2_callf, ICLASS_J" 1101 ii1iiiii PPi-0-uu iiiiiii-") |
| 613 | |
| 614 | |
| 615 | |
| 616 | |
| 617 | |
| 618 | |
| 619 | |
| 620 | /*******************************/ |
| 621 | /* */ |
| 622 | /* V4 */ |
| 623 | /* COMPOUND COMPARE-JUMPS */ |
| 624 | /* */ |
| 625 | /* */ |
| 626 | /*******************************/ |
| 627 | |
| 628 | |
| 629 | /* EJP: this has to match what we have in htmldocs.py... so I will call it CJ, we can change it */ |
| 630 | DEF_CLASS32(ICLASS_CJ" 0--- -------- PP------ --------",CJ) |
| 631 | |
| 632 | DEF_FIELDROW_DESC32(ICLASS_CJ" 00-- -------- -------- --------","[#0-3] pd=cmp.xx(R,#u5) ; if ([!]p0.new) jump:[h] #s9:2 ") |
| 633 | DEF_FIELDROW_DESC32(ICLASS_CJ" 010- -------- -------- --------","[#4,5] pd=cmp.eq(R,R) ; if ([!]p0.new) jump:[h] #s9:2 ") |
| 634 | DEF_FIELDROW_DESC32(ICLASS_CJ" 0110 -------- -------- --------","[#6] Rd=#u6 ; jump #s9:2 ") |
| 635 | DEF_FIELDROW_DESC32(ICLASS_CJ" 0111 -------- -------- --------","[#7] Rd=Rs ; jump #s9:2 ") |
| 636 | |
| 637 | |
| 638 | #define CMPJMPI_ENC(TAG,OPC) \ |
| 639 | DEF_ENC32(TAG##i_tp0_jump_t, ICLASS_CJ" 00 0 "OPC" 0iissss PP1IIIII iiiiiii-") \ |
| 640 | DEF_ENC32(TAG##i_fp0_jump_t, ICLASS_CJ" 00 0 "OPC" 1iissss PP1IIIII iiiiiii-") \ |
| 641 | DEF_ENC32(TAG##i_tp0_jump_nt, ICLASS_CJ" 00 0 "OPC" 0iissss PP0IIIII iiiiiii-") \ |
| 642 | DEF_ENC32(TAG##i_fp0_jump_nt, ICLASS_CJ" 00 0 "OPC" 1iissss PP0IIIII iiiiiii-") \ |
| 643 | \ |
| 644 | DEF_ENC32(TAG##i_tp1_jump_t, ICLASS_CJ" 00 1 "OPC" 0iissss PP1IIIII iiiiiii-") \ |
| 645 | DEF_ENC32(TAG##i_fp1_jump_t, ICLASS_CJ" 00 1 "OPC" 1iissss PP1IIIII iiiiiii-") \ |
| 646 | DEF_ENC32(TAG##i_tp1_jump_nt, ICLASS_CJ" 00 1 "OPC" 0iissss PP0IIIII iiiiiii-") \ |
| 647 | DEF_ENC32(TAG##i_fp1_jump_nt, ICLASS_CJ" 00 1 "OPC" 1iissss PP0IIIII iiiiiii-") |
| 648 | |
| 649 | CMPJMPI_ENC(J4_cmpeq,"00") |
| 650 | CMPJMPI_ENC(J4_cmpgt,"01") |
| 651 | CMPJMPI_ENC(J4_cmpgtu,"10") |
| 652 | |
| 653 | |
| 654 | #define CMPJMP1I_ENC(TAG,OPC) \ |
| 655 | DEF_ENC32(TAG##_tp0_jump_t, ICLASS_CJ" 00 0 11 0iissss PP1---"OPC" iiiiiii-") \ |
| 656 | DEF_ENC32(TAG##_fp0_jump_t, ICLASS_CJ" 00 0 11 1iissss PP1---"OPC" iiiiiii-") \ |
| 657 | DEF_ENC32(TAG##_tp0_jump_nt, ICLASS_CJ" 00 0 11 0iissss PP0---"OPC" iiiiiii-") \ |
| 658 | DEF_ENC32(TAG##_fp0_jump_nt, ICLASS_CJ" 00 0 11 1iissss PP0---"OPC" iiiiiii-") \ |
| 659 | \ |
| 660 | DEF_ENC32(TAG##_tp1_jump_t, ICLASS_CJ" 00 1 11 0iissss PP1---"OPC" iiiiiii-") \ |
| 661 | DEF_ENC32(TAG##_fp1_jump_t, ICLASS_CJ" 00 1 11 1iissss PP1---"OPC" iiiiiii-") \ |
| 662 | DEF_ENC32(TAG##_tp1_jump_nt, ICLASS_CJ" 00 1 11 0iissss PP0---"OPC" iiiiiii-") \ |
| 663 | DEF_ENC32(TAG##_fp1_jump_nt, ICLASS_CJ" 00 1 11 1iissss PP0---"OPC" iiiiiii-") |
| 664 | |
| 665 | CMPJMP1I_ENC(J4_cmpeqn1,"00") |
| 666 | CMPJMP1I_ENC(J4_cmpgtn1,"01") |
| 667 | CMPJMP1I_ENC(J4_tstbit0,"11") |
| 668 | |
| 669 | |
| 670 | |
| 671 | #define CMPJMPR_ENC(TAG,OPC) \ |
| 672 | DEF_ENC32(TAG##_tp0_jump_t, ICLASS_CJ" 01 0 "OPC" 0iissss PP10tttt iiiiiii-") \ |
| 673 | DEF_ENC32(TAG##_fp0_jump_t, ICLASS_CJ" 01 0 "OPC" 1iissss PP10tttt iiiiiii-") \ |
| 674 | DEF_ENC32(TAG##_tp0_jump_nt, ICLASS_CJ" 01 0 "OPC" 0iissss PP00tttt iiiiiii-") \ |
| 675 | DEF_ENC32(TAG##_fp0_jump_nt, ICLASS_CJ" 01 0 "OPC" 1iissss PP00tttt iiiiiii-") \ |
| 676 | \ |
| 677 | DEF_ENC32(TAG##_tp1_jump_t, ICLASS_CJ" 01 0 "OPC" 0iissss PP11tttt iiiiiii-") \ |
| 678 | DEF_ENC32(TAG##_fp1_jump_t, ICLASS_CJ" 01 0 "OPC" 1iissss PP11tttt iiiiiii-") \ |
| 679 | DEF_ENC32(TAG##_tp1_jump_nt, ICLASS_CJ" 01 0 "OPC" 0iissss PP01tttt iiiiiii-") \ |
| 680 | DEF_ENC32(TAG##_fp1_jump_nt, ICLASS_CJ" 01 0 "OPC" 1iissss PP01tttt iiiiiii-") |
| 681 | |
| 682 | CMPJMPR_ENC(J4_cmpeq,"00") |
| 683 | CMPJMPR_ENC(J4_cmpgt,"01") |
| 684 | CMPJMPR_ENC(J4_cmpgtu,"10") |
| 685 | |
| 686 | |
| 687 | DEF_ENC32(J4_jumpseti, ICLASS_CJ" 0110 --iidddd PPIIIIII iiiiiii-") |
| 688 | DEF_ENC32(J4_jumpsetr, ICLASS_CJ" 0111 --iissss PP--dddd iiiiiii-") |
| 689 | |
| 690 | |
| 691 | DEF_EXT_SPACE(EXT_CJ, ICLASS_CJ"1 iii iiiiiiii PPiiiiii iiiiiiii") |
| 692 | |
| 693 | |
| 694 | |
| 695 | DEF_CLASS32(ICLASS_NCJ" 0--- -------- PP------ --------",NCJ) |
| 696 | DEF_FIELDROW_DESC32(ICLASS_NCJ" 00-- -------- -------- --------","[#0-3] if (cmp.xx(R.new,R)) jump:[h] #s9:2 ") |
| 697 | DEF_FIELDROW_DESC32(ICLASS_NCJ" 01-- -------- -------- --------","[#4-7] if (cmp.xx(R.new,#U5)) jump:[h] #s9:2 ") |
| 698 | |
| 699 | #define OPRJMP_ENC(TAG,OPC) \ |
| 700 | DEF_ENC32(TAG##_t_jumpnv_t, ICLASS_NCJ" 00 "OPC" 0ii-sss PP1ttttt iiiiiii-") \ |
| 701 | DEF_ENC32(TAG##_f_jumpnv_t, ICLASS_NCJ" 00 "OPC" 1ii-sss PP1ttttt iiiiiii-") \ |
| 702 | DEF_ENC32(TAG##_t_jumpnv_nt, ICLASS_NCJ" 00 "OPC" 0ii-sss PP0ttttt iiiiiii-") \ |
| 703 | DEF_ENC32(TAG##_f_jumpnv_nt, ICLASS_NCJ" 00 "OPC" 1ii-sss PP0ttttt iiiiiii-") |
| 704 | |
| 705 | OPRJMP_ENC(J4_cmpeq, "000") |
| 706 | OPRJMP_ENC(J4_cmpgt, "001") |
| 707 | OPRJMP_ENC(J4_cmpgtu, "010") |
| 708 | OPRJMP_ENC(J4_cmplt, "011") |
| 709 | OPRJMP_ENC(J4_cmpltu, "100") |
| 710 | |
| 711 | |
| 712 | #define OPIJMP_ENC(TAG,OPC) \ |
| 713 | DEF_ENC32(TAG##_t_jumpnv_t, ICLASS_NCJ" 01 "OPC" 0ii-sss PP1IIIII iiiiiii-") \ |
| 714 | DEF_ENC32(TAG##_f_jumpnv_t, ICLASS_NCJ" 01 "OPC" 1ii-sss PP1IIIII iiiiiii-") \ |
| 715 | DEF_ENC32(TAG##_t_jumpnv_nt, ICLASS_NCJ" 01 "OPC" 0ii-sss PP0IIIII iiiiiii-") \ |
| 716 | DEF_ENC32(TAG##_f_jumpnv_nt, ICLASS_NCJ" 01 "OPC" 1ii-sss PP0IIIII iiiiiii-") |
| 717 | |
| 718 | OPIJMP_ENC(J4_cmpeqi, "000") |
| 719 | OPIJMP_ENC(J4_cmpgti, "001") |
| 720 | OPIJMP_ENC(J4_cmpgtui, "010") |
| 721 | |
| 722 | |
| 723 | #define OPI1JMP_ENC(TAG,OPC) \ |
| 724 | DEF_ENC32(TAG##_t_jumpnv_t, ICLASS_NCJ" 01 "OPC" 0ii-sss PP1----- iiiiiii-") \ |
| 725 | DEF_ENC32(TAG##_f_jumpnv_t, ICLASS_NCJ" 01 "OPC" 1ii-sss PP1----- iiiiiii-") \ |
| 726 | DEF_ENC32(TAG##_t_jumpnv_nt, ICLASS_NCJ" 01 "OPC" 0ii-sss PP0----- iiiiiii-") \ |
| 727 | DEF_ENC32(TAG##_f_jumpnv_nt, ICLASS_NCJ" 01 "OPC" 1ii-sss PP0----- iiiiiii-") |
| 728 | |
| 729 | OPI1JMP_ENC(J4_cmpeqn1, "100") |
| 730 | OPI1JMP_ENC(J4_cmpgtn1, "101") |
| 731 | OPI1JMP_ENC(J4_tstbit0, "011") |
| 732 | |
| 733 | |
| 734 | DEF_EXT_SPACE(EXT_NCJ, ICLASS_NCJ"1 iii iiiiiiii PPiiiiii iiiiiiii") |
| 735 | |
| 736 | |
| 737 | |
| 738 | /*******************************/ |
| 739 | /* */ |
| 740 | /* */ |
| 741 | /* CR */ |
| 742 | /* */ |
| 743 | /* */ |
| 744 | /*******************************/ |
| 745 | |
| 746 | |
| 747 | |
| 748 | DEF_CLASS32(ICLASS_CR" ---- -------- PP------ --------",CR) |
| 749 | DEF_CLASS32(ICLASS_CR" -0-- -------- PP------ --------",CRUSER) |
| 750 | DEF_CLASS32(ICLASS_CR" -1-- -------- PP------ --------",CRSUPER) |
| 751 | |
| 752 | DEF_FIELD32(ICLASS_CR" -!-- -------- PP------ --------",CR_sm,"Supervisor mode only") |
| 753 | |
| 754 | /* User CR ops */ |
| 755 | |
| 756 | DEF_FIELDROW_DESC32( ICLASS_CR" 0000 -------- PP------ --------","[#0] (Rs,#r8)") |
| 757 | DEF_ENC32(J2_loop0r, ICLASS_CR" 0000 000sssss PP-iiiii ---ii---") |
| 758 | DEF_ENC32(J2_loop1r, ICLASS_CR" 0000 001sssss PP-iiiii ---ii---") |
| 759 | DEF_ENC32(J2_ploop1sr, ICLASS_CR" 0000 101sssss PP-iiiii ---ii---") |
| 760 | DEF_ENC32(J2_ploop2sr, ICLASS_CR" 0000 110sssss PP-iiiii ---ii---") |
| 761 | DEF_ENC32(J2_ploop3sr, ICLASS_CR" 0000 111sssss PP-iiiii ---ii---") |
| 762 | |
| 763 | DEF_FIELDROW_DESC32( ICLASS_CR" 0001 -------- PP------ --------","[#1] (Rs,#r13)") |
| 764 | DEF_ENC32(J2_jumprz, ICLASS_CR" 0001 00isssss PPi0iiii iiiiiii-") |
| 765 | DEF_ENC32(J2_jumprzpt, ICLASS_CR" 0001 00isssss PPi1iiii iiiiiii-") |
| 766 | DEF_ENC32(J2_jumprnz, ICLASS_CR" 0001 10isssss PPi0iiii iiiiiii-") |
| 767 | DEF_ENC32(J2_jumprnzpt, ICLASS_CR" 0001 10isssss PPi1iiii iiiiiii-") |
| 768 | |
| 769 | DEF_ENC32(J2_jumprgtez, ICLASS_CR" 0001 01isssss PPi0iiii iiiiiii-") |
| 770 | DEF_ENC32(J2_jumprgtezpt,ICLASS_CR" 0001 01isssss PPi1iiii iiiiiii-") |
| 771 | DEF_ENC32(J2_jumprltez, ICLASS_CR" 0001 11isssss PPi0iiii iiiiiii-") |
| 772 | DEF_ENC32(J2_jumprltezpt,ICLASS_CR" 0001 11isssss PPi1iiii iiiiiii-") |
| 773 | |
| 774 | DEF_FIELDROW_DESC32( ICLASS_CR" 0010 -------- PP------ --------","[#2] Cd=Rs ") |
| 775 | DEF_ENC32(A2_tfrrcr, ICLASS_CR" 0010 001sssss PP------ ---ddddd") |
| 776 | DEF_ENC32(G4_tfrgrcr, ICLASS_CR" 0010 000sssss PP------ ---ddddd") |
| 777 | DEF_ENC32(Y4_trace, ICLASS_CR" 0010 010sssss PP------ 000-----") |
| 778 | DEF_ENC32(Y6_diag, ICLASS_CR" 0010 010sssss PP------ 001-----") |
| 779 | DEF_ENC32(Y6_diag0, ICLASS_CR" 0010 010sssss PP-ttttt 010-----") |
| 780 | DEF_ENC32(Y6_diag1, ICLASS_CR" 0010 010sssss PP-ttttt 011-----") |
| 781 | |
| 782 | DEF_FIELDROW_DESC32( ICLASS_CR" 0011 -------- PP------ --------","[#3] Cdd=Rss ") |
| 783 | DEF_ENC32(A4_tfrpcp, ICLASS_CR" 0011 001sssss PP------ ---ddddd") |
| 784 | DEF_ENC32(G4_tfrgpcp, ICLASS_CR" 0011 000sssss PP------ ---ddddd") |
| 785 | |
| 786 | DEF_FIELDROW_DESC32( ICLASS_CR" 1000 -------- PP------ --------","[#8] Rdd=Css ") |
| 787 | DEF_ENC32(A4_tfrcpp, ICLASS_CR" 1000 000sssss PP------ ---ddddd") |
| 788 | DEF_ENC32(G4_tfrgcpp, ICLASS_CR" 1000 001sssss PP------ ---ddddd") |
| 789 | |
| 790 | DEF_FIELDROW_DESC32( ICLASS_CR" 1001 -------- PP------ --------","[#9] (#r8,#U10)") |
| 791 | DEF_ENC32(J2_ploop1si, ICLASS_CR" 1001 101IIIII PP-iiiii IIIii-II") |
| 792 | DEF_ENC32(J2_ploop2si, ICLASS_CR" 1001 110IIIII PP-iiiii IIIii-II") |
| 793 | DEF_ENC32(J2_ploop3si, ICLASS_CR" 1001 111IIIII PP-iiiii IIIii-II") |
| 794 | DEF_ENC32(J2_loop0i, ICLASS_CR" 1001 000IIIII PP-iiiii IIIii-II") |
| 795 | DEF_ENC32(J2_loop1i, ICLASS_CR" 1001 001IIIII PP-iiiii IIIii-II") |
| 796 | |
| 797 | DEF_FIELDROW_DESC32( ICLASS_CR" 1010 -------- PP------ --------","[#10] Rd=Cs ") |
| 798 | DEF_ENC32(A2_tfrcrr, ICLASS_CR" 1010 000sssss PP------ ---ddddd") |
| 799 | DEF_ENC32(G4_tfrgcrr, ICLASS_CR" 1010 001sssss PP------ ---ddddd") |
| 800 | DEF_ENC32(C4_addipc, ICLASS_CR" 1010 01001001 PP-iiiii i--ddddd") |
| 801 | |
| 802 | |
| 803 | DEF_FIELDROW_DESC32( ICLASS_CR" 1011 -------- PP0----- --------","[#11] Pd=(Ps,Pt,Pu)") |
| 804 | DEF_ENC32(C2_and, ICLASS_CR" 1011 0000--ss PP0---tt ------dd") |
| 805 | DEF_ENC32(C2_or, ICLASS_CR" 1011 0010--ss PP0---tt ------dd") |
| 806 | DEF_ENC32(C2_xor, ICLASS_CR" 1011 0100--ss PP0---tt ------dd") |
| 807 | DEF_ENC32(C2_andn, ICLASS_CR" 1011 0110--ss PP0---tt ------dd") |
| 808 | DEF_ENC32(C2_any8, ICLASS_CR" 1011 1000--ss PP0----- ------dd") |
| 809 | DEF_ENC32(C2_all8, ICLASS_CR" 1011 1010--ss PP0----- ------dd") |
| 810 | DEF_ENC32(C2_not, ICLASS_CR" 1011 1100--ss PP0----- ------dd") |
| 811 | DEF_ENC32(C2_orn, ICLASS_CR" 1011 1110--ss PP0---tt ------dd") |
| 812 | |
| 813 | DEF_ENC32(C4_and_and, ICLASS_CR" 1011 0001--ss PP0---tt uu----dd") |
| 814 | DEF_ENC32(C4_and_or, ICLASS_CR" 1011 0011--ss PP0---tt uu----dd") |
| 815 | DEF_ENC32(C4_or_and, ICLASS_CR" 1011 0101--ss PP0---tt uu----dd") |
| 816 | DEF_ENC32(C4_or_or, ICLASS_CR" 1011 0111--ss PP0---tt uu----dd") |
| 817 | DEF_ENC32(C4_and_andn, ICLASS_CR" 1011 1001--ss PP0---tt uu----dd") |
| 818 | DEF_ENC32(C4_and_orn, ICLASS_CR" 1011 1011--ss PP0---tt uu----dd") |
| 819 | DEF_ENC32(C4_or_andn, ICLASS_CR" 1011 1101--ss PP0---tt uu----dd") |
| 820 | DEF_ENC32(C4_or_orn, ICLASS_CR" 1011 1111--ss PP0---tt uu----dd") |
| 821 | |
| 822 | DEF_ENC32(C4_fastcorner9, ICLASS_CR"1011 0000--ss PP1---tt 1--1--dd") |
| 823 | DEF_ENC32(C4_fastcorner9_not, ICLASS_CR"1011 0001--ss PP1---tt 1--1--dd") |
| 824 | |
| 825 | |
| 826 | |
| 827 | /* Supervisor CR ops */ |
| 828 | /* Interrupts */ |
| 829 | DEF_FIELDROW_DESC32( ICLASS_CR" 0100 -------- PP------ --------","[#4] (Rs,Pt)") |
| 830 | DEF_ENC32(Y2_swi, ICLASS_CR" 0100 000sssss PP------ 000-----") |
| 831 | DEF_ENC32(Y2_cswi, ICLASS_CR" 0100 000sssss PP------ 001-----") |
| 832 | DEF_ENC32(Y2_iassignw, ICLASS_CR" 0100 000sssss PP------ 010-----") |
| 833 | DEF_ENC32(Y2_ciad, ICLASS_CR" 0100 000sssss PP------ 011-----") |
| 834 | DEF_ENC32(Y2_setimask, ICLASS_CR" 0100 100sssss PP----tt 000-----") |
| 835 | DEF_ENC32(Y2_setprio, ICLASS_CR" 0100 100sssss PP----tt 001-----") |
| 836 | DEF_ENC32(Y4_siad, ICLASS_CR" 0100 100sssss PP------ 011-----") |
| 837 | |
| 838 | DEF_ENC32(Y2_wait, ICLASS_CR" 0100 010sssss PP------ 000-----") |
| 839 | DEF_ENC32(Y2_resume, ICLASS_CR" 0100 010sssss PP------ 001-----") |
| 840 | DEF_ENC32(Y2_stop, ICLASS_CR" 0100 011sssss PP------ 000-----") |
| 841 | DEF_ENC32(Y2_start, ICLASS_CR" 0100 011sssss PP------ 001-----") |
| 842 | DEF_ENC32(Y4_nmi, ICLASS_CR" 0100 011sssss PP------ 010-----") |
| 843 | |
| 844 | DEF_FIELDROW_DESC32( ICLASS_CR" 0101 -------- PP------ --------","[#5] Rx ") |
| 845 | DEF_ENC32(Y2_crswap0, ICLASS_CR" 0101 000xxxxx PP------ --------") |
| 846 | DEF_ENC32(Y4_crswap1, ICLASS_CR" 0101 001xxxxx PP------ --------") |
| 847 | |
| 848 | DEF_FIELDROW_DESC32( ICLASS_CR" 0110 -------- PP------ --------","[#6] Rd=(Rs)") |
| 849 | DEF_ENC32(Y2_getimask, ICLASS_CR" 0110 000sssss PP------ ---ddddd") |
| 850 | DEF_ENC32(Y2_iassignr, ICLASS_CR" 0110 011sssss PP------ ---ddddd") |
| 851 | |
| 852 | DEF_FIELDROW_DESC32( ICLASS_CR" 0111 -------- PP------ --------","[#7] cr=Rs ") |
| 853 | DEF_ENC32(Y2_tfrsrcr, ICLASS_CR" 0111 00-sssss PP------ -ddddddd") |
| 854 | |
| 855 | DEF_FIELDROW_DESC32( ICLASS_CR" 1100 -------- PP------ --------","[#12] ") |
| 856 | DEF_ENC32(Y2_break, ICLASS_CR" 1100 001----- PP------ 000-----") |
| 857 | DEF_ENC32(Y2_tlblock, ICLASS_CR" 1100 001----- PP------ 001-----") |
| 858 | DEF_ENC32(Y2_tlbunlock,ICLASS_CR" 1100 001----- PP------ 010-----") |
| 859 | DEF_ENC32(Y2_k0lock, ICLASS_CR" 1100 001----- PP------ 011-----") |
| 860 | DEF_ENC32(Y2_k0unlock, ICLASS_CR" 1100 001----- PP------ 100-----") |
| 861 | DEF_ENC32(Y2_tlbp, ICLASS_CR" 1100 100sssss PP------ ---ddddd") |
| 862 | DEF_ENC32(Y5_tlboc, ICLASS_CR" 1100 111sssss PP------ ---ddddd") |
| 863 | DEF_ENC32(Y5_tlbasidi, ICLASS_CR" 1100 101sssss PP------ --------") |
| 864 | DEF_ENC32(Y2_tlbr, ICLASS_CR" 1100 010sssss PP------ ---ddddd") |
| 865 | DEF_ENC32(Y2_tlbw, ICLASS_CR" 1100 000sssss PP0ttttt --------") |
| 866 | DEF_ENC32(Y5_ctlbw, ICLASS_CR" 1100 110sssss PP0ttttt ---ddddd") |
| 867 | |
| 868 | DEF_FIELDROW_DESC32( ICLASS_CR" 1101 -------- PP------ --------","[#13] Rxx ") |
| 869 | DEF_ENC32(Y4_crswap10, ICLASS_CR" 1101 10-xxxxx PP------ ---00000") |
| 870 | DEF_ENC32(Y4_tfrspcp, ICLASS_CR" 1101 00-sssss PP------ -ddddddd") |
| 871 | |
| 872 | DEF_FIELDROW_DESC32( ICLASS_CR" 1110 -------- PP------ --------","[#14] Rd=cr ") |
| 873 | DEF_ENC32(Y2_tfrscrr, ICLASS_CR" 1110 1sssssss PP------ ---ddddd") |
| 874 | |
| 875 | DEF_FIELDROW_DESC32( ICLASS_CR" 1111 -------- PP------ --------","[#15] Rdd=Sss ") |
| 876 | DEF_ENC32(Y4_tfrscpp, ICLASS_CR" 1111 0sssssss PP------ ---ddddd") |
| 877 | |
| 878 | |
| 879 | |
| 880 | |
| 881 | |
| 882 | |
| 883 | |
| 884 | |
| 885 | /*******************************/ |
| 886 | /* */ |
| 887 | /* */ |
| 888 | /* M */ |
| 889 | /* */ |
| 890 | /* */ |
| 891 | /*******************************/ |
| 892 | |
| 893 | |
| 894 | DEF_CLASS32(ICLASS_M" ---- -------- PP------ --------",M) |
| 895 | DEF_FIELD32(ICLASS_M" !!!! -------- PP------ --------",M_RegType,"Register Type") |
| 896 | DEF_FIELD32(ICLASS_M" ---- !!!----- PP------ --------",M_MajOp,"Major Opcode") |
| 897 | DEF_FIELD32(ICLASS_M" ---- -------- PP------ !!!-----",M_MinOp,"Minor Opcode") |
| 898 | |
| 899 | |
| 900 | |
| 901 | #define SP_MPY(TAG,REGTYPE,DSTCHARS,SAT,RND,UNS)\ |
| 902 | DEF_ENC32(TAG##_ll_s0, ICLASS_M REGTYPE "0" UNS RND"sssss PP-ttttt "SAT"00" DSTCHARS)\ |
| 903 | DEF_ENC32(TAG##_lh_s0, ICLASS_M REGTYPE "0" UNS RND"sssss PP-ttttt "SAT"01" DSTCHARS)\ |
| 904 | DEF_ENC32(TAG##_hl_s0, ICLASS_M REGTYPE "0" UNS RND"sssss PP-ttttt "SAT"10" DSTCHARS)\ |
| 905 | DEF_ENC32(TAG##_hh_s0, ICLASS_M REGTYPE "0" UNS RND"sssss PP-ttttt "SAT"11" DSTCHARS)\ |
| 906 | DEF_ENC32(TAG##_ll_s1, ICLASS_M REGTYPE "1" UNS RND"sssss PP-ttttt "SAT"00" DSTCHARS)\ |
| 907 | DEF_ENC32(TAG##_lh_s1, ICLASS_M REGTYPE "1" UNS RND"sssss PP-ttttt "SAT"01" DSTCHARS)\ |
| 908 | DEF_ENC32(TAG##_hl_s1, ICLASS_M REGTYPE "1" UNS RND"sssss PP-ttttt "SAT"10" DSTCHARS)\ |
| 909 | DEF_ENC32(TAG##_hh_s1, ICLASS_M REGTYPE "1" UNS RND"sssss PP-ttttt "SAT"11" DSTCHARS) |
| 910 | |
| 911 | /* Double precision */ |
| 912 | #define MPY_ENC(TAG,REGTYPE,DSTCHARS,SAT,RNDNAC,UNS,SHFT,VMIN2)\ |
| 913 | DEF_ENC32(TAG, ICLASS_M REGTYPE SHFT UNS RNDNAC"sssss PP0ttttt "SAT VMIN2 DSTCHARS) |
| 914 | |
| 915 | #define MPYI_ENC(TAG,REGTYPE,DSTCHARS,RNDNAC,UNS,SHFT)\ |
| 916 | DEF_ENC32(TAG, ICLASS_M REGTYPE SHFT UNS RNDNAC"sssss PP0iiiii iii" DSTCHARS) |
| 917 | |
| 918 | |
| 919 | DEF_FIELDROW_DESC32(ICLASS_M" 0000 -------- PP------ --------","[#0] Rd=(Rs,#u8)") |
| 920 | MPYI_ENC(M2_mpysip, "0000","ddddd","-","-","0" ) |
| 921 | MPYI_ENC(M2_mpysin, "0000","ddddd","-","-","1" ) |
| 922 | |
| 923 | |
| 924 | DEF_FIELDROW_DESC32(ICLASS_M" 0001 -------- PP------ --------","[#1] Rx=(Rs,#u8)") |
| 925 | MPYI_ENC(M2_macsip, "0001","xxxxx","-","-","0" ) |
| 926 | MPYI_ENC(M2_macsin, "0001","xxxxx","-","-","1" ) |
| 927 | |
| 928 | |
| 929 | DEF_FIELDROW_DESC32(ICLASS_M" 0010 -------- PP------ --------","[#2] Rx=(Rs,#s8)") |
| 930 | MPYI_ENC(M2_accii, "0010","xxxxx","-","-","0" ) |
| 931 | MPYI_ENC(M2_naccii, "0010","xxxxx","-","-","1" ) |
| 932 | |
| 933 | |
| 934 | DEF_FIELDROW_DESC32(ICLASS_M" 0011 -------- PP------ --------","[#3] Ry=(Ru,(Rs,Ry)) ") |
| 935 | DEF_ENC32(M4_mpyrr_addr,ICLASS_M" 0011 000sssss PP-yyyyy ---uuuuu") |
| 936 | |
| 937 | |
| 938 | DEF_FIELDROW_DESC32(ICLASS_M" 0100 -------- PP------ --------","[#4] Rdd=(Rs,Rt)") |
| 939 | DEF_FIELD32(ICLASS_M" 0100 -------- PP------ --!-----",Ma_tH,"Rt is High") /*Rt high */ |
| 940 | DEF_FIELD32(ICLASS_M" 0100 -------- PP------ -!------",Ma_sH,"Rs is High") /* Rs high */ |
| 941 | SP_MPY(M2_mpyd, "0100","ddddd","-","0","0") |
| 942 | SP_MPY(M2_mpyd_rnd, "0100","ddddd","-","1","0") |
| 943 | SP_MPY(M2_mpyud, "0100","ddddd","-","0","1") |
| 944 | |
| 945 | |
| 946 | DEF_FIELDROW_DESC32(ICLASS_M" 0101 -------- PP------ --------","[#5] Rdd=(Rs,Rt)") |
| 947 | MPY_ENC(M2_dpmpyss_s0, "0101","ddddd","0","0","0","0","00") |
| 948 | MPY_ENC(M2_dpmpyuu_s0, "0101","ddddd","0","0","1","0","00") |
| 949 | MPY_ENC(M2_vmpy2s_s0, "0101","ddddd","1","0","0","0","01") |
| 950 | MPY_ENC(M2_vmpy2s_s1, "0101","ddddd","1","0","0","1","01") |
| 951 | MPY_ENC(M2_cmpyi_s0, "0101","ddddd","0","0","0","0","01") |
| 952 | MPY_ENC(M2_cmpyr_s0, "0101","ddddd","0","0","0","0","10") |
| 953 | MPY_ENC(M2_cmpys_s0, "0101","ddddd","1","0","0","0","10") |
| 954 | MPY_ENC(M2_cmpys_s1, "0101","ddddd","1","0","0","1","10") |
| 955 | MPY_ENC(M2_cmpysc_s0, "0101","ddddd","1","0","1","0","10") |
| 956 | MPY_ENC(M2_cmpysc_s1, "0101","ddddd","1","0","1","1","10") |
| 957 | MPY_ENC(M2_vmpy2su_s0, "0101","ddddd","1","0","0","0","11") |
| 958 | MPY_ENC(M2_vmpy2su_s1, "0101","ddddd","1","0","0","1","11") |
| 959 | MPY_ENC(M4_pmpyw, "0101","ddddd","1","0","1","0","11") |
| 960 | MPY_ENC(M4_vpmpyh, "0101","ddddd","1","0","1","1","11") |
| 961 | MPY_ENC(M5_vmpybuu, "0101","ddddd","0","0","0","1","01") |
| 962 | MPY_ENC(M5_vmpybsu, "0101","ddddd","0","0","1","0","01") |
| 963 | |
| 964 | |
| 965 | |
| 966 | |
| 967 | DEF_FIELDROW_DESC32(ICLASS_M" 0110 -------- PP------ --------","[#6] Rxx=(Rs,Rt)") |
| 968 | DEF_FIELD32(ICLASS_M" 0110 -------- PP------ --!-----",Mb_tH,"Rt is High") /*Rt high */ |
| 969 | DEF_FIELD32(ICLASS_M" 0110 -------- PP------ -!------",Mb_sH,"Rs is High") /* Rs high */ |
| 970 | SP_MPY(M2_mpyd_acc, "0110","xxxxx","0","0","0") |
| 971 | SP_MPY(M2_mpyud_acc, "0110","xxxxx","0","0","1") |
| 972 | SP_MPY(M2_mpyd_nac, "0110","xxxxx","0","1","0") |
| 973 | SP_MPY(M2_mpyud_nac, "0110","xxxxx","0","1","1") |
| 974 | |
| 975 | |
| 976 | DEF_FIELDROW_DESC32(ICLASS_M" 0111 -------- PP------ --------","[#7] Rxx=(Rs,Rt)") |
| 977 | MPY_ENC(M2_dpmpyss_acc_s0, "0111","xxxxx","0","0","0","0","00") |
| 978 | MPY_ENC(M2_dpmpyss_nac_s0, "0111","xxxxx","0","1","0","0","00") |
| 979 | MPY_ENC(M2_dpmpyuu_acc_s0, "0111","xxxxx","0","0","1","0","00") |
| 980 | MPY_ENC(M2_dpmpyuu_nac_s0, "0111","xxxxx","0","1","1","0","00") |
| 981 | MPY_ENC(M2_vmac2s_s0, "0111","xxxxx","1","0","0","0","01") |
| 982 | MPY_ENC(M2_vmac2s_s1, "0111","xxxxx","1","0","0","1","01") |
| 983 | MPY_ENC(M2_cmaci_s0, "0111","xxxxx","0","0","0","0","01") |
| 984 | MPY_ENC(M2_cmacr_s0, "0111","xxxxx","0","0","0","0","10") |
| 985 | MPY_ENC(M2_cmacs_s0, "0111","xxxxx","1","0","0","0","10") |
| 986 | MPY_ENC(M2_cmacs_s1, "0111","xxxxx","1","0","0","1","10") |
| 987 | MPY_ENC(M2_cmacsc_s0, "0111","xxxxx","1","0","1","0","10") |
| 988 | MPY_ENC(M2_cmacsc_s1, "0111","xxxxx","1","0","1","1","10") |
| 989 | MPY_ENC(M2_vmac2, "0111","xxxxx","0","1","0","0","01") |
| 990 | MPY_ENC(M2_cnacs_s0, "0111","xxxxx","1","0","0","0","11") |
| 991 | MPY_ENC(M2_cnacs_s1, "0111","xxxxx","1","0","0","1","11") |
| 992 | MPY_ENC(M2_cnacsc_s0, "0111","xxxxx","1","0","1","0","11") |
| 993 | MPY_ENC(M2_cnacsc_s1, "0111","xxxxx","1","0","1","1","11") |
| 994 | MPY_ENC(M2_vmac2su_s0, "0111","xxxxx","1","1","1","0","01") |
| 995 | MPY_ENC(M2_vmac2su_s1, "0111","xxxxx","1","1","1","1","01") |
| 996 | MPY_ENC(M4_pmpyw_acc, "0111","xxxxx","1","1","0","0","11") |
| 997 | MPY_ENC(M4_vpmpyh_acc, "0111","xxxxx","1","1","0","1","11") |
| 998 | MPY_ENC(M5_vmacbuu, "0111","xxxxx","0","0","0","1","01") |
| 999 | MPY_ENC(M5_vmacbsu, "0111","xxxxx","0","0","1","1","01") |
| 1000 | |
| 1001 | |
| 1002 | |
| 1003 | |
| 1004 | |
| 1005 | DEF_FIELDROW_DESC32(ICLASS_M" 1000 -------- PP------ --------","[#8] Rdd=(Rss,Rtt)") |
| 1006 | MPY_ENC(M2_vrcmpyi_s0, "1000","ddddd","0","0","0","0","00") |
| 1007 | MPY_ENC(M2_vdmpys_s0, "1000","ddddd","1","0","0","0","00") |
| 1008 | MPY_ENC(M2_vdmpys_s1, "1000","ddddd","1","0","0","1","00") |
| 1009 | MPY_ENC(M2_vrcmpyi_s0c, "1000","ddddd","0","0","1","0","00") |
| 1010 | MPY_ENC(M2_vabsdiffw, "1000","ddddd","0","1","0","0","00") |
| 1011 | MPY_ENC(M6_vabsdiffub, "1000","ddddd","0","1","0","1","00") |
| 1012 | MPY_ENC(M2_vabsdiffh, "1000","ddddd","0","1","1","0","00") |
| 1013 | MPY_ENC(M6_vabsdiffb, "1000","ddddd","0","1","1","1","00") |
| 1014 | MPY_ENC(M2_vrcmpys_s1_h, "1000","ddddd","1","1","0","1","00") |
| 1015 | MPY_ENC(M2_vrcmpys_s1_l, "1000","ddddd","1","1","1","1","00") |
| 1016 | MPY_ENC(M2_vrcmpyr_s0c, "1000","ddddd","0","1","1","0","01") |
| 1017 | MPY_ENC(M2_vrcmpyr_s0, "1000","ddddd","0","0","0","0","01") |
| 1018 | MPY_ENC(A2_vraddub, "1000","ddddd","0","0","1","0","01") |
| 1019 | MPY_ENC(M2_mmpyl_s0, "1000","ddddd","1","0","0","0","01") |
| 1020 | MPY_ENC(M2_mmpyl_s1, "1000","ddddd","1","0","0","1","01") |
| 1021 | MPY_ENC(M2_mmpyl_rs0, "1000","ddddd","1","1","0","0","01") |
| 1022 | MPY_ENC(M2_mmpyl_rs1, "1000","ddddd","1","1","0","1","01") |
| 1023 | MPY_ENC(M2_mmpyul_s0, "1000","ddddd","1","0","1","0","01") |
| 1024 | MPY_ENC(M2_mmpyul_s1, "1000","ddddd","1","0","1","1","01") |
| 1025 | MPY_ENC(M2_mmpyul_rs0, "1000","ddddd","1","1","1","0","01") |
| 1026 | MPY_ENC(M2_mmpyul_rs1, "1000","ddddd","1","1","1","1","01") |
| 1027 | MPY_ENC(M2_vrmpy_s0, "1000","ddddd","0","0","0","0","10") |
| 1028 | MPY_ENC(A2_vrsadub, "1000","ddddd","0","0","1","0","10") |
| 1029 | MPY_ENC(M2_vmpy2es_s0, "1000","ddddd","1","0","0","0","10") |
| 1030 | MPY_ENC(M2_vmpy2es_s1, "1000","ddddd","1","0","0","1","10") |
| 1031 | MPY_ENC(M2_vcmpy_s0_sat_i, "1000","ddddd","1","0","1","0","10") |
| 1032 | MPY_ENC(M2_vcmpy_s0_sat_r, "1000","ddddd","1","1","0","0","10") |
| 1033 | MPY_ENC(M2_vcmpy_s1_sat_i, "1000","ddddd","1","0","1","1","10") |
| 1034 | MPY_ENC(M2_vcmpy_s1_sat_r, "1000","ddddd","1","1","0","1","10") |
| 1035 | |
| 1036 | MPY_ENC(M2_mmpyh_s0, "1000","ddddd","1","0","0","0","11") |
| 1037 | MPY_ENC(M2_mmpyh_s1, "1000","ddddd","1","0","0","1","11") |
| 1038 | MPY_ENC(M2_mmpyh_rs0, "1000","ddddd","1","1","0","0","11") |
| 1039 | MPY_ENC(M2_mmpyh_rs1, "1000","ddddd","1","1","0","1","11") |
| 1040 | MPY_ENC(M2_mmpyuh_s0, "1000","ddddd","1","0","1","0","11") |
| 1041 | MPY_ENC(M2_mmpyuh_s1, "1000","ddddd","1","0","1","1","11") |
| 1042 | MPY_ENC(M2_mmpyuh_rs0, "1000","ddddd","1","1","1","0","11") |
| 1043 | MPY_ENC(M2_mmpyuh_rs1, "1000","ddddd","1","1","1","1","11") |
| 1044 | |
| 1045 | MPY_ENC(M4_vrmpyeh_s0, "1000","ddddd","1","0","1","0","00") |
| 1046 | MPY_ENC(M4_vrmpyeh_s1, "1000","ddddd","1","0","1","1","00") |
| 1047 | MPY_ENC(M4_vrmpyoh_s0, "1000","ddddd","0","1","0","0","10") |
| 1048 | MPY_ENC(M4_vrmpyoh_s1, "1000","ddddd","0","1","0","1","10") |
| 1049 | MPY_ENC(M5_vrmpybuu, "1000","ddddd","0","0","0","1","01") |
| 1050 | MPY_ENC(M5_vrmpybsu, "1000","ddddd","0","0","1","1","01") |
| 1051 | MPY_ENC(M5_vdmpybsu, "1000","ddddd","0","1","0","1","01") |
| 1052 | |
| 1053 | MPY_ENC(F2_dfadd, "1000","ddddd","0","0","0","0","11") |
| 1054 | MPY_ENC(F2_dfsub, "1000","ddddd","0","0","0","1","11") |
| 1055 | MPY_ENC(F2_dfmpyfix, "1000","ddddd","0","0","1","0","11") |
| 1056 | MPY_ENC(F2_dfmin, "1000","ddddd","0","0","1","1","11") |
| 1057 | MPY_ENC(F2_dfmax, "1000","ddddd","0","1","0","0","11") |
| 1058 | MPY_ENC(F2_dfmpyll, "1000","ddddd","0","1","0","1","11") |
| 1059 | |
| 1060 | MPY_ENC(M7_dcmpyrw, "1000","ddddd","0","0","0","1","10") |
| 1061 | MPY_ENC(M7_dcmpyrwc, "1000","ddddd","0","0","1","1","10") |
| 1062 | MPY_ENC(M7_dcmpyiw, "1000","ddddd","0","1","1","0","10") |
| 1063 | MPY_ENC(M7_dcmpyiwc, "1000","ddddd","0","1","1","1","10") |
| 1064 | |
| 1065 | |
| 1066 | |
| 1067 | DEF_FIELDROW_DESC32(ICLASS_M" 1001 -------- PP------ --------","[#9] Rd=(Rss,Rtt)") |
| 1068 | MPY_ENC(M2_vdmpyrs_s0, "1001","ddddd","0","0","0","0","00") |
| 1069 | MPY_ENC(M2_vdmpyrs_s1, "1001","ddddd","0","0","0","1","00") |
| 1070 | |
| 1071 | MPY_ENC(M7_wcmpyrw, "1001","ddddd","0","0","1","0","00") |
| 1072 | MPY_ENC(M7_wcmpyrw_rnd, "1001","ddddd","0","0","1","1","00") |
| 1073 | MPY_ENC(M7_wcmpyiw, "1001","ddddd","0","1","0","0","00") |
| 1074 | MPY_ENC(M7_wcmpyiw_rnd, "1001","ddddd","0","1","0","1","00") |
| 1075 | |
| 1076 | MPY_ENC(M7_wcmpyrwc, "1001","ddddd","0","1","1","0","00") |
| 1077 | MPY_ENC(M7_wcmpyrwc_rnd, "1001","ddddd","0","1","1","1","00") |
| 1078 | MPY_ENC(M7_wcmpyiwc, "1001","ddddd","1","0","0","0","00") |
| 1079 | MPY_ENC(M7_wcmpyiwc_rnd, "1001","ddddd","1","0","0","1","00") |
| 1080 | |
| 1081 | |
| 1082 | |
| 1083 | MPY_ENC(M2_vradduh, "1001","ddddd","-","-","-","0","01") |
| 1084 | MPY_ENC(M2_vrcmpys_s1rp_h, "1001","ddddd","1","1","-","1","10") |
| 1085 | MPY_ENC(M2_vrcmpys_s1rp_l, "1001","ddddd","1","1","-","1","11") |
| 1086 | MPY_ENC(M2_vraddh, "1001","ddddd","1","1","-","0","11") |
| 1087 | |
| 1088 | |
| 1089 | DEF_FIELDROW_DESC32(ICLASS_M" 1010 -------- PP------ --------","[#10] Rxx=(Rss,Rtt)") |
| 1090 | MPY_ENC(M2_vrcmaci_s0, "1010","xxxxx","0","0","0","0","00") |
| 1091 | MPY_ENC(M2_vdmacs_s0, "1010","xxxxx","1","0","0","0","00") |
| 1092 | MPY_ENC(M2_vdmacs_s1, "1010","xxxxx","1","0","0","1","00") |
| 1093 | MPY_ENC(M2_vrcmaci_s0c, "1010","xxxxx","0","0","1","0","00") |
| 1094 | MPY_ENC(M2_vcmac_s0_sat_i, "1010","xxxxx","1","0","1","0","00") |
| 1095 | MPY_ENC(M2_vcmac_s0_sat_r, "1010","xxxxx","1","1","0","0","00") |
| 1096 | MPY_ENC(M2_vrcmpys_acc_s1_h, "1010","xxxxx","1","1","0","1","00") |
| 1097 | MPY_ENC(M2_vrcmpys_acc_s1_l, "1010","xxxxx","1","1","1","1","00") |
| 1098 | MPY_ENC(M2_vrcmacr_s0, "1010","xxxxx","0","0","0","0","01") |
| 1099 | MPY_ENC(A2_vraddub_acc, "1010","xxxxx","0","0","1","0","01") |
| 1100 | MPY_ENC(M2_mmacls_s0, "1010","xxxxx","1","0","0","0","01") |
| 1101 | MPY_ENC(M2_mmacls_s1, "1010","xxxxx","1","0","0","1","01") |
| 1102 | MPY_ENC(M2_mmacls_rs0, "1010","xxxxx","1","1","0","0","01") |
| 1103 | MPY_ENC(M2_mmacls_rs1, "1010","xxxxx","1","1","0","1","01") |
| 1104 | MPY_ENC(M2_mmaculs_s0, "1010","xxxxx","1","0","1","0","01") |
| 1105 | MPY_ENC(M2_mmaculs_s1, "1010","xxxxx","1","0","1","1","01") |
| 1106 | MPY_ENC(M2_mmaculs_rs0, "1010","xxxxx","1","1","1","0","01") |
| 1107 | MPY_ENC(M2_mmaculs_rs1, "1010","xxxxx","1","1","1","1","01") |
| 1108 | MPY_ENC(M2_vrcmacr_s0c, "1010","xxxxx","0","1","1","0","01") |
| 1109 | MPY_ENC(M2_vrmac_s0, "1010","xxxxx","0","0","0","0","10") |
| 1110 | MPY_ENC(A2_vrsadub_acc, "1010","xxxxx","0","0","1","0","10") |
| 1111 | MPY_ENC(M2_vmac2es_s0, "1010","xxxxx","1","0","0","0","10") |
| 1112 | MPY_ENC(M2_vmac2es_s1, "1010","xxxxx","1","0","0","1","10") |
| 1113 | MPY_ENC(M2_vmac2es, "1010","xxxxx","0","1","0","0","10") |
| 1114 | MPY_ENC(M2_mmachs_s0, "1010","xxxxx","1","0","0","0","11") |
| 1115 | MPY_ENC(M2_mmachs_s1, "1010","xxxxx","1","0","0","1","11") |
| 1116 | MPY_ENC(M2_mmachs_rs0, "1010","xxxxx","1","1","0","0","11") |
| 1117 | MPY_ENC(M2_mmachs_rs1, "1010","xxxxx","1","1","0","1","11") |
| 1118 | MPY_ENC(M2_mmacuhs_s0, "1010","xxxxx","1","0","1","0","11") |
| 1119 | MPY_ENC(M2_mmacuhs_s1, "1010","xxxxx","1","0","1","1","11") |
| 1120 | MPY_ENC(M2_mmacuhs_rs0, "1010","xxxxx","1","1","1","0","11") |
| 1121 | MPY_ENC(M2_mmacuhs_rs1, "1010","xxxxx","1","1","1","1","11") |
| 1122 | MPY_ENC(M4_vrmpyeh_acc_s0, "1010","xxxxx","1","1","0","0","10") |
| 1123 | MPY_ENC(M4_vrmpyeh_acc_s1, "1010","xxxxx","1","1","0","1","10") |
| 1124 | MPY_ENC(M4_vrmpyoh_acc_s0, "1010","xxxxx","1","1","1","0","10") |
| 1125 | MPY_ENC(M4_vrmpyoh_acc_s1, "1010","xxxxx","1","1","1","1","10") |
| 1126 | MPY_ENC(M5_vrmacbuu, "1010","xxxxx","0","0","0","1","01") |
| 1127 | MPY_ENC(M5_vrmacbsu, "1010","xxxxx","0","0","1","1","01") |
| 1128 | MPY_ENC(M5_vdmacbsu, "1010","xxxxx","0","1","0","0","01") |
| 1129 | |
| 1130 | MPY_ENC(F2_dfmpylh, "1010","xxxxx","0","0","0","0","11") |
| 1131 | MPY_ENC(F2_dfmpyhh, "1010","xxxxx","0","0","0","1","11") |
| 1132 | |
| 1133 | |
| 1134 | MPY_ENC(M7_dcmpyrw_acc, "1010","xxxxx","0","0","0","1","10") |
| 1135 | MPY_ENC(M7_dcmpyrwc_acc, "1010","xxxxx","0","0","1","1","10") |
| 1136 | MPY_ENC(M7_dcmpyiw_acc, "1010","xxxxx","0","1","1","0","10") |
| 1137 | MPY_ENC(M7_dcmpyiwc_acc, "1010","xxxxx","1","0","1","0","10") |
| 1138 | |
| 1139 | |
| 1140 | |
| 1141 | |
| 1142 | MPY_ENC(A5_ACS, "1010","xxxxx","0","1","0","1","ee") |
| 1143 | MPY_ENC(A6_vminub_RdP, "1010","ddddd","0","1","1","1","ee") |
| 1144 | /* |
| 1145 | */ |
| 1146 | |
| 1147 | DEF_FIELDROW_DESC32(ICLASS_M" 1011 -------- PP------ --------","[#11] Reserved") |
| 1148 | MPY_ENC(F2_sfadd, "1011","ddddd","0","0","0","0","00") |
| 1149 | MPY_ENC(F2_sfsub, "1011","ddddd","0","0","0","0","01") |
| 1150 | MPY_ENC(F2_sfmax, "1011","ddddd","0","0","0","1","00") |
| 1151 | MPY_ENC(F2_sfmin, "1011","ddddd","0","0","0","1","01") |
| 1152 | MPY_ENC(F2_sfmpy, "1011","ddddd","0","0","1","0","00") |
| 1153 | MPY_ENC(F2_sffixupn, "1011","ddddd","0","0","1","1","00") |
| 1154 | MPY_ENC(F2_sffixupd, "1011","ddddd","0","0","1","1","01") |
| 1155 | MPY_ENC(F2_sfrecipa, "1011","ddddd","1","1","1","1","ee") |
| 1156 | |
| 1157 | DEF_FIELDROW_DESC32(ICLASS_M" 1100 -------- PP------ --------","[#12] Rd=(Rs,Rt)") |
| 1158 | DEF_FIELD32(ICLASS_M" 1100 -------- PP------ --!-----",Mc_tH,"Rt is High") /*Rt high */ |
| 1159 | DEF_FIELD32(ICLASS_M" 1100 -------- PP------ -!------",Mc_sH,"Rs is High") /* Rs high */ |
| 1160 | SP_MPY(M2_mpy, "1100","ddddd","0","0","0") |
| 1161 | SP_MPY(M2_mpy_sat, "1100","ddddd","1","0","0") |
| 1162 | SP_MPY(M2_mpy_rnd, "1100","ddddd","0","1","0") |
| 1163 | SP_MPY(M2_mpy_sat_rnd, "1100","ddddd","1","1","0") |
| 1164 | SP_MPY(M2_mpyu, "1100","ddddd","0","0","1") |
| 1165 | |
| 1166 | DEF_FIELDROW_DESC32(ICLASS_M" 1101 -------- PP------ --------","[#13] Rd=(Rs,Rt)") |
| 1167 | /* EJP: same as mpyi MPY_ENC(M2_mpyui, "1101","ddddd","0","0","1","0","00") */ |
| 1168 | MPY_ENC(M2_mpyi, "1101","ddddd","0","0","0","0","00") |
| 1169 | MPY_ENC(M2_mpy_up, "1101","ddddd","0","0","0","0","01") |
| 1170 | MPY_ENC(M2_mpyu_up, "1101","ddddd","0","0","1","0","01") |
| 1171 | MPY_ENC(M2_dpmpyss_rnd_s0, "1101","ddddd","0","1","0","0","01") |
| 1172 | MPY_ENC(M2_cmpyrs_s0, "1101","ddddd","1","1","0","0","10") |
| 1173 | MPY_ENC(M2_cmpyrs_s1, "1101","ddddd","1","1","0","1","10") |
| 1174 | MPY_ENC(M2_cmpyrsc_s0, "1101","ddddd","1","1","1","0","10") |
| 1175 | MPY_ENC(M2_cmpyrsc_s1, "1101","ddddd","1","1","1","1","10") |
| 1176 | MPY_ENC(M2_vmpy2s_s0pack, "1101","ddddd","1","1","0","0","11") |
| 1177 | MPY_ENC(M2_vmpy2s_s1pack, "1101","ddddd","1","1","0","1","11") |
| 1178 | MPY_ENC(M2_hmmpyh_rs1, "1101","ddddd","1","1","0","1","00") |
| 1179 | MPY_ENC(M2_hmmpyl_rs1, "1101","ddddd","1","1","1","1","00") |
| 1180 | |
| 1181 | MPY_ENC(M2_hmmpyh_s1, "1101","ddddd","0","1","0","1","00") |
| 1182 | MPY_ENC(M2_hmmpyl_s1, "1101","ddddd","0","1","0","1","01") |
| 1183 | MPY_ENC(M2_mpy_up_s1, "1101","ddddd","0","1","0","1","10") |
| 1184 | MPY_ENC(M2_mpy_up_s1_sat, "1101","ddddd","0","1","1","1","00") |
| 1185 | MPY_ENC(M2_mpysu_up, "1101","ddddd","0","1","1","0","01") |
| 1186 | |
| 1187 | |
| 1188 | DEF_FIELDROW_DESC32(ICLASS_M" 1110 -------- PP------ --------","[#14] Rx=(Rs,Rt)") |
| 1189 | DEF_FIELD32(ICLASS_M" 1110 -------- PP------ --!-----",Md_tH,"Rt is High") /*Rt high */ |
| 1190 | DEF_FIELD32(ICLASS_M" 1110 -------- PP------ -!------",Md_sH,"Rs is High") /* Rs high */ |
| 1191 | SP_MPY(M2_mpyu_acc, "1110","xxxxx","0","0","1") |
| 1192 | SP_MPY(M2_mpy_acc, "1110","xxxxx","0","0","0") |
| 1193 | SP_MPY(M2_mpy_acc_sat, "1110","xxxxx","1","0","0") |
| 1194 | SP_MPY(M2_mpyu_nac, "1110","xxxxx","0","1","1") |
| 1195 | SP_MPY(M2_mpy_nac, "1110","xxxxx","0","1","0") |
| 1196 | SP_MPY(M2_mpy_nac_sat, "1110","xxxxx","1","1","0") |
| 1197 | |
| 1198 | |
| 1199 | DEF_FIELDROW_DESC32(ICLASS_M" 1111 -------- PP------ --------","[#15] Rx=(Rs,Rt)") |
| 1200 | MPY_ENC(M2_maci, "1111","xxxxx","0","0","0","0","00") |
| 1201 | MPY_ENC(M2_mnaci, "1111","xxxxx","0","0","0","1","00") |
| 1202 | MPY_ENC(M2_acci, "1111","xxxxx","0","0","0","0","01") |
| 1203 | MPY_ENC(M2_nacci, "1111","xxxxx","0","0","0","1","01") |
| 1204 | MPY_ENC(M2_xor_xacc, "1111","xxxxx","0","0","0","1","11") |
| 1205 | MPY_ENC(M2_subacc, "1111","xxxxx","0","0","0","0","11") |
| 1206 | |
| 1207 | MPY_ENC(M4_mac_up_s1_sat, "1111","xxxxx","0","1","1","0","00") |
| 1208 | MPY_ENC(M4_nac_up_s1_sat, "1111","xxxxx","0","1","1","0","01") |
| 1209 | |
| 1210 | MPY_ENC(M4_and_and, "1111","xxxxx","0","0","1","0","00") |
| 1211 | MPY_ENC(M4_and_or, "1111","xxxxx","0","0","1","0","01") |
| 1212 | MPY_ENC(M4_and_xor, "1111","xxxxx","0","0","1","0","10") |
| 1213 | MPY_ENC(M4_or_and, "1111","xxxxx","0","0","1","0","11") |
| 1214 | MPY_ENC(M4_or_or, "1111","xxxxx","0","0","1","1","00") |
| 1215 | MPY_ENC(M4_or_xor, "1111","xxxxx","0","0","1","1","01") |
| 1216 | MPY_ENC(M4_xor_and, "1111","xxxxx","0","0","1","1","10") |
| 1217 | MPY_ENC(M4_xor_or, "1111","xxxxx","0","0","1","1","11") |
| 1218 | |
| 1219 | MPY_ENC(M4_or_andn, "1111","xxxxx","0","1","0","0","00") |
| 1220 | MPY_ENC(M4_and_andn, "1111","xxxxx","0","1","0","0","01") |
| 1221 | MPY_ENC(M4_xor_andn, "1111","xxxxx","0","1","0","0","10") |
| 1222 | |
| 1223 | MPY_ENC(F2_sffma, "1111","xxxxx","1","0","0","0","00") |
| 1224 | MPY_ENC(F2_sffms, "1111","xxxxx","1","0","0","0","01") |
| 1225 | |
| 1226 | MPY_ENC(F2_sffma_lib, "1111","xxxxx","1","0","0","0","10") |
| 1227 | MPY_ENC(F2_sffms_lib, "1111","xxxxx","1","0","0","0","11") |
| 1228 | |
| 1229 | MPY_ENC(F2_sffma_sc, "1111","xxxxx","1","1","1","0","uu") |
| 1230 | |
| 1231 | |
| 1232 | /*******************************/ |
| 1233 | /* */ |
| 1234 | /* */ |
| 1235 | /* ALU32_2op */ |
| 1236 | /* */ |
| 1237 | /* */ |
| 1238 | /*******************************/ |
| 1239 | DEF_CLASS32(ICLASS_ADDI" ---- -------- PP------ --------",ALU32_ADDI) |
| 1240 | |
| 1241 | DEF_CLASS32(ICLASS_ALU2op" ---- -------- PP------ --------",ALU32_2op) |
| 1242 | DEF_FIELD32(ICLASS_ALU2op" !--- -------- PP------ --------",A2_Rs,"No Rs read") |
| 1243 | DEF_FIELD32(ICLASS_ALU2op" -!!! -------- PP------ --------",A2_MajOp,"Major Opcode") |
| 1244 | DEF_FIELD32(ICLASS_ALU2op" ---- !!!----- PP------ --------",A2_MinOp,"Minor Opcode") |
| 1245 | |
| 1246 | DEF_FIELD32(ICLASS_ALU3op" -!!! -------- PP------ --------",A3_MajOp,"Major Opcode") |
| 1247 | DEF_FIELD32(ICLASS_ALU3op" ---- !!!----- PP------ --------",A3_MinOp,"Minor Opcode") |
| 1248 | DEF_CLASS32(ICLASS_ALU3op" ---- -------- PP------ --------",ALU32_3op) |
| 1249 | DEF_FIELD32(ICLASS_ALU3op" !--- -------- PP------ --------",A3_P,"Predicated") |
| 1250 | DEF_FIELD32(ICLASS_ALU3op" ---- -------- PP!----- --------",A3_DN,"Dot-new") |
| 1251 | DEF_FIELD32(ICLASS_ALU3op" ---- -------- PP------ !-------",A3_PS,"Predicate sense") |
| 1252 | |
| 1253 | |
| 1254 | /*************************/ |
| 1255 | /* Our good friend addi */ |
| 1256 | /*************************/ |
| 1257 | DEF_ENC32(A2_addi, ICLASS_ADDI" iiii iiisssss PPiiiiii iiiddddd") |
| 1258 | |
| 1259 | |
| 1260 | /*******************************/ |
| 1261 | /* Standard ALU32 insns */ |
| 1262 | /*******************************/ |
| 1263 | |
| 1264 | #define ALU32_IRR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ |
| 1265 | DEF_ENC32(TAG, ICLASS_ALU2op" "MAJ4" "MIN3"sssss PP"SMOD1"iiiii "VMIN3 DSTCHARS) |
| 1266 | |
| 1267 | #define ALU32_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ |
| 1268 | DEF_ENC32(TAG, ICLASS_ALU2op" "MAJ4" "MIN3"sssss PP"SMOD1"----- "VMIN3 DSTCHARS) |
| 1269 | |
| 1270 | #define CONDA32_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ |
| 1271 | DEF_ENC32(TAG##t, ICLASS_ALU2op" "MAJ4" "MIN3"sssss PP"SMOD1"-00uu "VMIN3 DSTCHARS)\ |
| 1272 | DEF_ENC32(TAG##f, ICLASS_ALU2op" "MAJ4" "MIN3"sssss PP"SMOD1"-10uu "VMIN3 DSTCHARS)\ |
| 1273 | DEF_ENC32(TAG##tnew,ICLASS_ALU2op" "MAJ4" "MIN3"sssss PP"SMOD1"-01uu "VMIN3 DSTCHARS)\ |
| 1274 | DEF_ENC32(TAG##fnew,ICLASS_ALU2op" "MAJ4" "MIN3"sssss PP"SMOD1"-11uu "VMIN3 DSTCHARS) |
| 1275 | |
| 1276 | |
| 1277 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0000 -------- PP------ --------","[#0] (Pu) Rd=(Rs)") |
| 1278 | DEF_FIELD32( ICLASS_ALU2op" 0000 -------- PP!----- --------",A32a_C,"Conditional") |
| 1279 | DEF_FIELD32( ICLASS_ALU2op" 0000 -------- PP--!--- --------",A32a_S,"Predicate sense") |
| 1280 | DEF_FIELD32( ICLASS_ALU2op" 0000 -------- PP---!-- --------",A32a_dn,"Dot-new") |
| 1281 | |
| 1282 | ALU32_RR_ENC(A2_aslh, "0000","000","0","---","ddddd") |
| 1283 | ALU32_RR_ENC(A2_asrh, "0000","001","0","---","ddddd") |
| 1284 | ALU32_RR_ENC(A2_tfr, "0000","011","0","---","ddddd") |
| 1285 | ALU32_RR_ENC(A2_sxtb, "0000","101","0","---","ddddd") |
| 1286 | ALU32_RR_ENC(A2_zxth, "0000","110","0","---","ddddd") |
| 1287 | ALU32_RR_ENC(A2_sxth, "0000","111","0","---","ddddd") |
| 1288 | |
| 1289 | CONDA32_RR_ENC(A4_paslh, "0000","000","1","---","ddddd") |
| 1290 | CONDA32_RR_ENC(A4_pasrh, "0000","001","1","---","ddddd") |
| 1291 | CONDA32_RR_ENC(A4_pzxtb, "0000","100","1","---","ddddd") |
| 1292 | CONDA32_RR_ENC(A4_psxtb, "0000","101","1","---","ddddd") |
| 1293 | CONDA32_RR_ENC(A4_pzxth, "0000","110","1","---","ddddd") |
| 1294 | CONDA32_RR_ENC(A4_psxth, "0000","111","1","---","ddddd") |
| 1295 | |
| 1296 | |
| 1297 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0001 -------- PP------ --------","[#1] Rx=(#u16)") |
| 1298 | DEF_ENC32(A2_tfril, ICLASS_ALU2op" 0001 ii1xxxxx PPiiiiii iiiiiiii") |
| 1299 | |
| 1300 | |
| 1301 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0010 -------- PP------ --------","[#2] Rx=(#u16)") |
| 1302 | DEF_ENC32(A2_tfrih, ICLASS_ALU2op" 0010 ii1xxxxx PPiiiiii iiiiiiii") |
| 1303 | |
| 1304 | |
| 1305 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0011 -------- PP------ --------","[#3] Rd=(Pu,Rs,#s8)") |
| 1306 | DEF_ENC32(C2_muxir, ICLASS_ALU2op" 0011 0uusssss PP0iiiii iiiddddd") |
| 1307 | DEF_ENC32(C2_muxri, ICLASS_ALU2op" 0011 1uusssss PP0iiiii iiiddddd") |
| 1308 | |
| 1309 | DEF_ENC32(A4_combineri, ICLASS_ALU2op" 0011 -00sssss PP1iiiii iiiddddd") /* Rdd = (Rs,#s8) */ |
| 1310 | DEF_ENC32(A4_combineir, ICLASS_ALU2op" 0011 -01sssss PP1iiiii iiiddddd") /* Rdd = (Rs,#s8) */ |
| 1311 | DEF_ENC32(A4_rcmpeqi, ICLASS_ALU2op" 0011 -10sssss PP1iiiii iiiddddd") /* Rd = (Rs,#s8) */ |
| 1312 | DEF_ENC32(A4_rcmpneqi, ICLASS_ALU2op" 0011 -11sssss PP1iiiii iiiddddd") /* Rd = (Rs,#s8) */ |
| 1313 | |
| 1314 | |
| 1315 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0100 -------- PP------ --------","[#4] (Pu) Rd=(Rs,#s8)") |
| 1316 | DEF_FIELD32( ICLASS_ALU2op" 0100 -------- PP!----- --------",A32a_DN,"Dot-new") |
| 1317 | DEF_FIELD32( ICLASS_ALU2op" 0100 !------- PP------ --------",A32a_PS,"Predicate sense") |
| 1318 | DEF_ENC32(A2_paddit, ICLASS_ALU2op" 0100 0uusssss PP0iiiii iiiddddd") |
| 1319 | DEF_ENC32(A2_padditnew, ICLASS_ALU2op" 0100 0uusssss PP1iiiii iiiddddd") |
| 1320 | DEF_ENC32(A2_paddif, ICLASS_ALU2op" 0100 1uusssss PP0iiiii iiiddddd") |
| 1321 | DEF_ENC32(A2_paddifnew, ICLASS_ALU2op" 0100 1uusssss PP1iiiii iiiddddd") |
| 1322 | |
| 1323 | |
| 1324 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0101 -------- PP------ --------","[#5] Pd=(Rs,#s10)") |
| 1325 | DEF_ENC32(C2_cmpeqi, ICLASS_ALU2op" 0101 00isssss PPiiiiii iii000dd") |
| 1326 | DEF_ENC32(C2_cmpgti, ICLASS_ALU2op" 0101 01isssss PPiiiiii iii000dd") |
| 1327 | DEF_ENC32(C2_cmpgtui, ICLASS_ALU2op" 0101 100sssss PPiiiiii iii000dd") |
| 1328 | |
| 1329 | DEF_ENC32(C4_cmpneqi, ICLASS_ALU2op" 0101 00isssss PPiiiiii iii100dd") |
| 1330 | DEF_ENC32(C4_cmpltei, ICLASS_ALU2op" 0101 01isssss PPiiiiii iii100dd") |
| 1331 | DEF_ENC32(C4_cmplteui, ICLASS_ALU2op" 0101 100sssss PPiiiiii iii100dd") |
| 1332 | |
| 1333 | |
| 1334 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0110 -------- PP------ --------","[#6] Rd=(Rs,#s10)") |
| 1335 | ALU32_IRR_ENC(A2_andir, "0110","00i","i","iii","ddddd") |
| 1336 | ALU32_IRR_ENC(A2_subri, "0110","01i","i","iii","ddddd") |
| 1337 | ALU32_IRR_ENC(A2_orir, "0110","10i","i","iii","ddddd") |
| 1338 | |
| 1339 | |
| 1340 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0111 -------- PP------ --------","[#7] Reserved") |
| 1341 | |
| 1342 | |
| 1343 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 1000 -------- PP------ --------","[#8] Rd=#s16") |
| 1344 | DEF_ENC32(A2_tfrsi, ICLASS_ALU2op" 1000 ii-iiiii PPiiiiii iiiddddd") |
| 1345 | |
| 1346 | |
| 1347 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 1001 -------- PP------ --------","[#9] Reserved") |
| 1348 | |
| 1349 | |
| 1350 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 101- -------- PP------ --------","[#10,#11] Rd=(Pu,#s8,#S8)") |
| 1351 | DEF_ENC32(C2_muxii, ICLASS_ALU2op" 101u uIIIIIII PPIiiiii iiiddddd") |
| 1352 | |
| 1353 | |
| 1354 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 1100 -------- PP------ --------","[#12] Rdd=(#s8,#S8)") |
| 1355 | DEF_ENC32(A2_combineii, ICLASS_ALU2op" 1100 0IIIIIII PPIiiiii iiiddddd") |
| 1356 | DEF_ENC32(A4_combineii, ICLASS_ALU2op" 1100 1--IIIII PPIiiiii iiiddddd") |
| 1357 | |
| 1358 | |
| 1359 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 1101 -------- PP------ --------","[#13] Reserved") |
| 1360 | |
| 1361 | |
| 1362 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 1110 -------- PP------ --------","[#14] (Pu) Rd=#s12") |
| 1363 | DEF_FIELD32( ICLASS_ALU2op" 1110 ---0---- PP!----- --------",A32c_DN,"Dot-new") |
| 1364 | DEF_FIELD32( ICLASS_ALU2op" 1110 !--0---- PP------ --------",A32c_PS,"Predicate sense") |
| 1365 | DEF_ENC32(C2_cmovenewit,ICLASS_ALU2op" 1110 0uu0iiii PP1iiiii iiiddddd") |
| 1366 | DEF_ENC32(C2_cmovenewif,ICLASS_ALU2op" 1110 1uu0iiii PP1iiiii iiiddddd") |
| 1367 | DEF_ENC32(C2_cmoveit, ICLASS_ALU2op" 1110 0uu0iiii PP0iiiii iiiddddd") |
| 1368 | DEF_ENC32(C2_cmoveif, ICLASS_ALU2op" 1110 1uu0iiii PP0iiiii iiiddddd") |
| 1369 | |
| 1370 | |
| 1371 | DEF_FIELDROW_DESC32( ICLASS_ALU2op" 1111 -------- PP------ --------","[#15] nop") |
| 1372 | DEF_ENC32(A2_nop, ICLASS_ALU2op" 1111 -------- PP------ --------") |
| 1373 | |
| 1374 | |
| 1375 | |
| 1376 | |
| 1377 | |
| 1378 | |
| 1379 | |
| 1380 | |
| 1381 | |
| 1382 | |
| 1383 | |
| 1384 | |
| 1385 | /*******************************/ |
| 1386 | /* */ |
| 1387 | /* */ |
| 1388 | /* ALU32_3op */ |
| 1389 | /* */ |
| 1390 | /* */ |
| 1391 | /*******************************/ |
| 1392 | |
| 1393 | |
| 1394 | #define V2A32_RRR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ |
| 1395 | DEF_ENC32(TAG, ICLASS_ALU3op" "MAJ4" "MIN3"sssss PP"SMOD1"ttttt "VMIN3 DSTCHARS) |
| 1396 | |
| 1397 | #define V2A32_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ |
| 1398 | DEF_ENC32(TAG, ICLASS_ALU3op" "MAJ4" "MIN3"sssss PP"SMOD1"----- "VMIN3 DSTCHARS) |
| 1399 | |
| 1400 | |
| 1401 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0000 -------- PP------ --------","[#0] Reserved") |
| 1402 | |
| 1403 | |
| 1404 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0001 -------- PP------ --------","[#1] Rd=(Rs,Rt)") |
| 1405 | V2A32_RRR_ENC(A2_and, "0001","000","-","---","ddddd") |
| 1406 | V2A32_RRR_ENC(A2_or, "0001","001","-","---","ddddd") |
| 1407 | V2A32_RRR_ENC(A2_xor, "0001","011","-","---","ddddd") |
| 1408 | V2A32_RRR_ENC(A4_andn, "0001","100","-","---","ddddd") |
| 1409 | V2A32_RRR_ENC(A4_orn, "0001","101","-","---","ddddd") |
| 1410 | |
| 1411 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0010 -------- PP------ --------","[#2] Pd=(Rs,Rt)") |
| 1412 | V2A32_RRR_ENC(C2_cmpeq, "0010","-00","-","---","000dd") |
| 1413 | V2A32_RRR_ENC(C2_cmpgt, "0010","-10","-","---","000dd") |
| 1414 | V2A32_RRR_ENC(C2_cmpgtu, "0010","-11","-","---","000dd") |
| 1415 | |
| 1416 | V2A32_RRR_ENC(C4_cmpneq, "0010","-00","-","---","100dd") |
| 1417 | V2A32_RRR_ENC(C4_cmplte, "0010","-10","-","---","100dd") |
| 1418 | V2A32_RRR_ENC(C4_cmplteu, "0010","-11","-","---","100dd") |
| 1419 | |
| 1420 | |
| 1421 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0011 -------- PP------ --------","[#3] Rd=(Rs,Rt)") |
| 1422 | V2A32_RRR_ENC(A2_add, "0011","000","-","---","ddddd") |
| 1423 | V2A32_RRR_ENC(A2_sub, "0011","001","-","---","ddddd") |
| 1424 | V2A32_RRR_ENC(A2_combine_hh, "0011","100","-","---","ddddd") |
| 1425 | V2A32_RRR_ENC(A2_combine_hl, "0011","101","-","---","ddddd") |
| 1426 | V2A32_RRR_ENC(A2_combine_lh, "0011","110","-","---","ddddd") |
| 1427 | V2A32_RRR_ENC(A2_combine_ll, "0011","111","-","---","ddddd") |
| 1428 | V2A32_RRR_ENC(A4_rcmpeq, "0011","010","-","---","ddddd") |
| 1429 | V2A32_RRR_ENC(A4_rcmpneq, "0011","011","-","---","ddddd") |
| 1430 | |
| 1431 | |
| 1432 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0100 -------- PP------ --------","[#4] Rd=(Pu,Rs,Rt)") |
| 1433 | V2A32_RRR_ENC(C2_mux, "0100","---","-","-uu","ddddd") |
| 1434 | |
| 1435 | |
| 1436 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0101 -------- PP------ --------","[#5] Rdd=(Rs,Rt)") |
| 1437 | V2A32_RRR_ENC(A2_combinew, "0101","0--","-","---","ddddd") |
| 1438 | V2A32_RRR_ENC(S2_packhl, "0101","1--","-","---","ddddd") |
| 1439 | |
| 1440 | |
| 1441 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0110 -------- PP------ --------","[#6] Rd=(Rs,Rt)") |
| 1442 | V2A32_RRR_ENC(A2_svaddh, "0110","000","-","---","ddddd") |
| 1443 | V2A32_RRR_ENC(A2_svaddhs, "0110","001","-","---","ddddd") |
| 1444 | V2A32_RRR_ENC(A2_svadduhs, "0110","011","-","---","ddddd") |
| 1445 | V2A32_RRR_ENC(A2_svsubh, "0110","100","-","---","ddddd") |
| 1446 | V2A32_RRR_ENC(A2_svsubhs, "0110","101","-","---","ddddd") |
| 1447 | V2A32_RRR_ENC(A2_svsubuhs, "0110","111","-","---","ddddd") |
| 1448 | V2A32_RRR_ENC(A2_addsat, "0110","010","-","---","ddddd") |
| 1449 | V2A32_RRR_ENC(A2_subsat, "0110","110","-","---","ddddd") |
| 1450 | |
| 1451 | |
| 1452 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0111 -------- PP------ --------","[#7] Rd=(Rs,Rt)") |
| 1453 | V2A32_RRR_ENC(A2_svavgh, "0111","-00","-","---","ddddd") |
| 1454 | V2A32_RRR_ENC(A2_svavghs, "0111","-01","-","---","ddddd") |
| 1455 | V2A32_RRR_ENC(A2_svnavgh, "0111","-11","-","---","ddddd") |
| 1456 | |
| 1457 | |
| 1458 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1000 -------- PP------ --------","[#8] Reserved") |
| 1459 | |
| 1460 | |
| 1461 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1001 -------- PP------ --------","[#9] (Pu) Rd=(Rs,Rt)") |
| 1462 | V2A32_RRR_ENC(A2_pandt, "1001","-00","0","0uu","ddddd") |
| 1463 | V2A32_RRR_ENC(A2_pandtnew, "1001","-00","1","0uu","ddddd") |
| 1464 | V2A32_RRR_ENC(A2_pandf, "1001","-00","0","1uu","ddddd") |
| 1465 | V2A32_RRR_ENC(A2_pandfnew, "1001","-00","1","1uu","ddddd") |
| 1466 | V2A32_RRR_ENC(A2_port, "1001","-01","0","0uu","ddddd") |
| 1467 | V2A32_RRR_ENC(A2_portnew, "1001","-01","1","0uu","ddddd") |
| 1468 | V2A32_RRR_ENC(A2_porf, "1001","-01","0","1uu","ddddd") |
| 1469 | V2A32_RRR_ENC(A2_porfnew, "1001","-01","1","1uu","ddddd") |
| 1470 | V2A32_RRR_ENC(A2_pxort, "1001","-11","0","0uu","ddddd") |
| 1471 | V2A32_RRR_ENC(A2_pxortnew, "1001","-11","1","0uu","ddddd") |
| 1472 | V2A32_RRR_ENC(A2_pxorf, "1001","-11","0","1uu","ddddd") |
| 1473 | V2A32_RRR_ENC(A2_pxorfnew, "1001","-11","1","1uu","ddddd") |
| 1474 | |
| 1475 | |
| 1476 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1010 -------- PP------ --------","[#10] Reserved") |
| 1477 | |
| 1478 | |
| 1479 | |
| 1480 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1011 -------- PP------ --------","[#11] (Pu) Rd=(Rs,Rt)") |
| 1481 | V2A32_RRR_ENC(A2_paddt, "1011","0-0","0","0uu","ddddd") |
| 1482 | V2A32_RRR_ENC(A2_paddtnew, "1011","0-0","1","0uu","ddddd") |
| 1483 | V2A32_RRR_ENC(A2_paddf, "1011","0-0","0","1uu","ddddd") |
| 1484 | V2A32_RRR_ENC(A2_paddfnew, "1011","0-0","1","1uu","ddddd") |
| 1485 | V2A32_RRR_ENC(A2_psubt, "1011","0-1","0","0uu","ddddd") |
| 1486 | V2A32_RRR_ENC(A2_psubtnew, "1011","0-1","1","0uu","ddddd") |
| 1487 | V2A32_RRR_ENC(A2_psubf, "1011","0-1","0","1uu","ddddd") |
| 1488 | V2A32_RRR_ENC(A2_psubfnew, "1011","0-1","1","1uu","ddddd") |
| 1489 | |
| 1490 | |
| 1491 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1100 -------- PP------ --------","[#12] Reserved") |
| 1492 | |
| 1493 | |
| 1494 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1101 -------- PP------ --------","[#13] (Pu) Rdd=(Rs,Rt)") |
| 1495 | V2A32_RRR_ENC(C2_ccombinewnewt, "1101","000","1","0uu","ddddd") |
| 1496 | V2A32_RRR_ENC(C2_ccombinewnewf, "1101","000","1","1uu","ddddd") |
| 1497 | V2A32_RRR_ENC(C2_ccombinewt, "1101","000","0","0uu","ddddd") |
| 1498 | V2A32_RRR_ENC(C2_ccombinewf, "1101","000","0","1uu","ddddd") |
| 1499 | |
| 1500 | |
| 1501 | |
| 1502 | |
| 1503 | |
| 1504 | |
| 1505 | DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1110 -------- PP------ --------","[#14] Reserved") |
| 1506 | |
| 1507 | |
| 1508 | |
| 1509 | |
| 1510 | |
| 1511 | |
| 1512 | |
| 1513 | |
| 1514 | |
| 1515 | /*******************************/ |
| 1516 | /* */ |
| 1517 | /* */ |
| 1518 | /* S */ |
| 1519 | /* */ |
| 1520 | /* */ |
| 1521 | /*******************************/ |
| 1522 | |
| 1523 | DEF_CLASS32(ICLASS_S2op" ---- -------- PP------ --------",S_2op) |
| 1524 | DEF_FIELD32(ICLASS_S2op" !!!! -------- PP------ --------",STYPEB_RegType,"Register Type") |
| 1525 | DEF_FIELD32(ICLASS_S2op" ---- !!------ PP------ --------",S2_MajOp,"Major Opcode") |
| 1526 | DEF_FIELD32(ICLASS_S2op" ---- -------- PP------ !!!-----",S2_MinOp,"Minor Opcode") |
| 1527 | |
| 1528 | DEF_CLASS32(ICLASS_S3op" ---- -------- PP------ --------",S_3op) |
| 1529 | DEF_FIELD32(ICLASS_S3op" !!!! -------- PP------ --------",STYPEA_RegType,"Register Type") |
| 1530 | DEF_FIELD32(ICLASS_S3op" ---- !!------ PP------ --------",S3_Maj,"Major Opcode") |
| 1531 | DEF_FIELD32(ICLASS_S3op" ---- -------- PP------ !!------",S3_Min,"Minor Opcode") |
| 1532 | |
| 1533 | |
| 1534 | #define SH_RRR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ |
| 1535 | DEF_ENC32(TAG,ICLASS_S3op" "MAJ4" "MIN3"sssss PP"SMOD1"ttttt "VMIN3 DSTCHARS) |
| 1536 | |
| 1537 | #define SH_RRRiENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ |
| 1538 | DEF_ENC32(TAG,ICLASS_S3op" "MAJ4" "MIN3"iiiii PP"SMOD1"ttttt "VMIN3 DSTCHARS) |
| 1539 | |
| 1540 | #define SH_RRR_ENCX(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ |
| 1541 | DEF_ENC32(TAG,ICLASS_S3op" "MAJ4" "MIN3"sssss PP"SMOD1"xxxxx "VMIN3 DSTCHARS) |
| 1542 | |
| 1543 | #define SH3_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ |
| 1544 | DEF_ENC32(TAG,ICLASS_S3op" "MAJ4" "MIN3"sssss PP"SMOD1"----- "VMIN3 DSTCHARS) |
| 1545 | |
| 1546 | #define SH_PPP_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ |
| 1547 | DEF_ENC32(TAG,ICLASS_S3op" "MAJ4" "MIN3"---ss PP"SMOD1"---tt "VMIN3 DSTCHARS) |
| 1548 | |
| 1549 | #define SH2_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ |
| 1550 | DEF_ENC32(TAG,ICLASS_S2op" "MAJ4" "MIN3"sssss PP"SMOD1"----- "VMIN3 DSTCHARS) |
| 1551 | |
| 1552 | #define SH2_PPP_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ |
| 1553 | DEF_ENC32(TAG,ICLASS_S2op" "MAJ4" "MIN3"---ss PP"SMOD1"---tt "VMIN3 DSTCHARS) |
| 1554 | |
| 1555 | #define SH_RRI4_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \ |
| 1556 | DEF_ENC32(TAG,ICLASS_S2op" "MAJ4" "MIN3 "sssss PP00iiii " VMIN3 DSTCHARS) |
| 1557 | |
| 1558 | #define SH_RRI5_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \ |
| 1559 | DEF_ENC32(TAG,ICLASS_S2op" "MAJ4" "MIN3 "sssss PP0iiiii " VMIN3 DSTCHARS) |
| 1560 | |
| 1561 | #define SH_RRI6_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \ |
| 1562 | DEF_ENC32(TAG,ICLASS_S2op" "MAJ4" "MIN3 "sssss PPiiiiii " VMIN3 DSTCHARS) |
| 1563 | |
| 1564 | #define RSHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DMOD1,DSTCHARS) \ |
| 1565 | SH_RRR_ENC(S2_asr_r_##TAGEND,MAJ4,MIN3,SMOD1,"00"DMOD1,DSTCHARS) \ |
| 1566 | SH_RRR_ENC(S2_lsr_r_##TAGEND,MAJ4,MIN3,SMOD1,"01"DMOD1,DSTCHARS) \ |
| 1567 | SH_RRR_ENC(S2_asl_r_##TAGEND,MAJ4,MIN3,SMOD1,"10"DMOD1,DSTCHARS) \ |
| 1568 | SH_RRR_ENC(S2_lsl_r_##TAGEND,MAJ4,MIN3,SMOD1,"11"DMOD1,DSTCHARS) |
| 1569 | |
| 1570 | |
| 1571 | #define I5SHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ |
| 1572 | SH_RRI5_ENC(S2_asr_i_##TAGEND,MAJ4,MIN3,SMOD1 "00",DSTCHARS) \ |
| 1573 | SH_RRI5_ENC(S2_lsr_i_##TAGEND,MAJ4,MIN3,SMOD1 "01",DSTCHARS) \ |
| 1574 | SH_RRI5_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) \ |
| 1575 | SH_RRI5_ENC(S6_rol_i_##TAGEND,MAJ4,MIN3,SMOD1 "11",DSTCHARS) |
| 1576 | |
| 1577 | #define I5SHIFTTYPES_NOROL(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ |
| 1578 | SH_RRI5_ENC(S2_asr_i_##TAGEND,MAJ4,MIN3,SMOD1 "00",DSTCHARS) \ |
| 1579 | SH_RRI5_ENC(S2_lsr_i_##TAGEND,MAJ4,MIN3,SMOD1 "01",DSTCHARS) \ |
| 1580 | SH_RRI5_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) |
| 1581 | |
| 1582 | #define I5SHIFTTYPES_NOASR(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ |
| 1583 | SH_RRI5_ENC(S2_lsr_i_##TAGEND,MAJ4,MIN3,SMOD1 "01",DSTCHARS) \ |
| 1584 | SH_RRI5_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) \ |
| 1585 | SH_RRI5_ENC(S6_rol_i_##TAGEND,MAJ4,MIN3,SMOD1 "11",DSTCHARS) |
| 1586 | |
| 1587 | #define I4SHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ |
| 1588 | SH_RRI4_ENC(S2_asr_i_##TAGEND,MAJ4,MIN3,SMOD1 "00",DSTCHARS) \ |
| 1589 | SH_RRI4_ENC(S2_lsr_i_##TAGEND,MAJ4,MIN3,SMOD1 "01",DSTCHARS) \ |
| 1590 | SH_RRI4_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) |
| 1591 | |
| 1592 | #define I5ASHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ |
| 1593 | SH_RRI5_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) |
| 1594 | |
| 1595 | #define I4ASHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ |
| 1596 | SH_RRI4_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) |
| 1597 | |
| 1598 | #define I6SHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ |
| 1599 | SH_RRI6_ENC(S2_asr_i_##TAGEND,MAJ4,MIN3,SMOD1 "00",DSTCHARS) \ |
| 1600 | SH_RRI6_ENC(S2_lsr_i_##TAGEND,MAJ4,MIN3,SMOD1 "01",DSTCHARS) \ |
| 1601 | SH_RRI6_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) \ |
| 1602 | SH_RRI6_ENC(S6_rol_i_##TAGEND,MAJ4,MIN3,SMOD1 "11",DSTCHARS) \ |
| 1603 | |
| 1604 | #define I6SHIFTTYPES_NOASR(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ |
| 1605 | SH_RRI6_ENC(S2_lsr_i_##TAGEND,MAJ4,MIN3,SMOD1 "01",DSTCHARS) \ |
| 1606 | SH_RRI6_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) \ |
| 1607 | SH_RRI6_ENC(S6_rol_i_##TAGEND,MAJ4,MIN3,SMOD1 "11",DSTCHARS) |
| 1608 | |
| 1609 | |
| 1610 | |
| 1611 | DEF_FIELDROW_DESC32(ICLASS_S2op" 0000 -------- PP------ --------","[#0] Rdd=(Rss,#u6)") |
| 1612 | /* EJP: there is actually quite a bit of space here, look at the reserved bits */ |
| 1613 | I6SHIFTTYPES(p, "0000","000","0","ddddd") |
| 1614 | I5SHIFTTYPES_NOROL(vw, "0000","010","0","ddddd") |
| 1615 | I4SHIFTTYPES(vh, "0000","100","0","ddddd") |
| 1616 | |
| 1617 | |
| 1618 | |
| 1619 | /* False assume an immediate */ |
| 1620 | SH2_RR_ENC(S2_vsathub_nopack, "0000","000","-","1 00","ddddd") |
| 1621 | SH2_RR_ENC(S2_vsatwuh_nopack, "0000","000","-","1 01","ddddd") |
| 1622 | SH2_RR_ENC(S2_vsatwh_nopack, "0000","000","-","1 10","ddddd") |
| 1623 | SH2_RR_ENC(S2_vsathb_nopack, "0000","000","-","1 11","ddddd") |
| 1624 | |
| 1625 | SH_RRI4_ENC(S5_vasrhrnd, "0000","001", "0 00","ddddd") |
| 1626 | |
| 1627 | SH2_RR_ENC(A2_vabsh, "0000","010","-","1 00","ddddd") |
| 1628 | SH2_RR_ENC(A2_vabshsat, "0000","010","-","1 01","ddddd") |
| 1629 | SH2_RR_ENC(A2_vabsw, "0000","010","-","1 10","ddddd") |
| 1630 | SH2_RR_ENC(A2_vabswsat, "0000","010","-","1 11","ddddd") |
| 1631 | |
| 1632 | SH2_RR_ENC(A2_notp, "0000","100","-","1 00","ddddd") |
| 1633 | SH2_RR_ENC(A2_negp, "0000","100","-","1 01","ddddd") |
| 1634 | SH2_RR_ENC(A2_absp, "0000","100","-","1 10","ddddd") |
| 1635 | SH2_RR_ENC(A2_vconj, "0000","100","-","1 11","ddddd") |
| 1636 | |
| 1637 | SH2_RR_ENC(S2_deinterleave, "0000","110","-","1 00","ddddd") |
| 1638 | SH2_RR_ENC(S2_interleave, "0000","110","-","1 01","ddddd") |
| 1639 | SH2_RR_ENC(S2_brevp, "0000","110","-","1 10","ddddd") |
| 1640 | SH_RRI6_ENC(S2_asr_i_p_rnd, "0000","110", "1 11","ddddd") |
| 1641 | |
| 1642 | SH2_RR_ENC(F2_conv_df2d, "0000","111","0","0 00","ddddd") |
| 1643 | SH2_RR_ENC(F2_conv_df2ud, "0000","111","0","0 01","ddddd") |
| 1644 | SH2_RR_ENC(F2_conv_ud2df, "0000","111","0","0 10","ddddd") |
| 1645 | SH2_RR_ENC(F2_conv_d2df, "0000","111","0","0 11","ddddd") |
| 1646 | SH2_RR_ENC(F2_conv_df2d_chop, "0000","111","0","1 10","ddddd") |
| 1647 | SH2_RR_ENC(F2_conv_df2ud_chop,"0000","111","0","1 11","ddddd") |
| 1648 | |
| 1649 | |
| 1650 | |
| 1651 | DEF_FIELDROW_DESC32(ICLASS_S2op" 0001 -------- PP------ --------","[#1] Rdd=(Rss,#u6,#U6)") |
| 1652 | DEF_ENC32(S2_extractup,ICLASS_S2op" 0001 IIIsssss PPiiiiii IIIddddd") |
| 1653 | |
| 1654 | |
| 1655 | DEF_FIELDROW_DESC32(ICLASS_S2op" 0010 -------- PP------ --------","[#2] Rxx=(Rss,#u6)") |
| 1656 | I6SHIFTTYPES(p_nac, "0010","00-","0","xxxxx") |
| 1657 | I6SHIFTTYPES(p_acc, "0010","00-","1","xxxxx") |
| 1658 | I6SHIFTTYPES(p_and, "0010","01-","0","xxxxx") |
| 1659 | I6SHIFTTYPES(p_or, "0010","01-","1","xxxxx") |
| 1660 | I6SHIFTTYPES_NOASR(p_xacc, "0010","10-","0","xxxxx") |
| 1661 | |
| 1662 | |
| 1663 | DEF_FIELDROW_DESC32(ICLASS_S2op" 0011 -------- PP------ --------","[#3] Rxx=(Rss,#u6,#U6)") |
| 1664 | DEF_ENC32(S2_insertp,ICLASS_S2op" 0011 IIIsssss PPiiiiii IIIxxxxx") |
| 1665 | |
| 1666 | |
| 1667 | DEF_FIELDROW_DESC32(ICLASS_S2op" 0100 -------- PP------ --------","[#4] Rdd=(Rs)") |
| 1668 | SH2_RR_ENC(S2_vsxtbh, "0100","00-","-","00-","ddddd") |
| 1669 | SH2_RR_ENC(S2_vzxtbh, "0100","00-","-","01-","ddddd") |
| 1670 | SH2_RR_ENC(S2_vsxthw, "0100","00-","-","10-","ddddd") |
| 1671 | SH2_RR_ENC(S2_vzxthw, "0100","00-","-","11-","ddddd") |
| 1672 | SH2_RR_ENC(A2_sxtw, "0100","01-","-","00-","ddddd") |
| 1673 | SH2_RR_ENC(S2_vsplatrh, "0100","01-","-","01-","ddddd") |
| 1674 | SH2_RR_ENC(S6_vsplatrbp, "0100","01-","-","10-","ddddd") |
| 1675 | |
| 1676 | SH2_RR_ENC(F2_conv_sf2df, "0100","1--","-","000","ddddd") |
| 1677 | SH2_RR_ENC(F2_conv_uw2df, "0100","1--","-","001","ddddd") |
| 1678 | SH2_RR_ENC(F2_conv_w2df, "0100","1--","-","010","ddddd") |
| 1679 | SH2_RR_ENC(F2_conv_sf2ud, "0100","1--","-","011","ddddd") |
| 1680 | SH2_RR_ENC(F2_conv_sf2d, "0100","1--","-","100","ddddd") |
| 1681 | SH2_RR_ENC(F2_conv_sf2ud_chop, "0100","1--","-","101","ddddd") |
| 1682 | SH2_RR_ENC(F2_conv_sf2d_chop, "0100","1--","-","110","ddddd") |
| 1683 | |
| 1684 | |
| 1685 | DEF_FIELDROW_DESC32(ICLASS_S2op" 0101 -------- PP------ --------","[#5] Pd=(Rs,#u6)") |
| 1686 | DEF_ENC32(S2_tstbit_i,ICLASS_S2op" 0101 000sssss PP0iiiii ------dd") |
| 1687 | DEF_ENC32(C2_tfrrp, ICLASS_S2op" 0101 010sssss PP------ ------dd") |
| 1688 | DEF_ENC32(C2_bitsclri,ICLASS_S2op" 0101 100sssss PPiiiiii ------dd") |
| 1689 | DEF_ENC32(S4_ntstbit_i,ICLASS_S2op"0101 001sssss PP0iiiii ------dd") |
| 1690 | DEF_ENC32(C4_nbitsclri,ICLASS_S2op"0101 101sssss PPiiiiii ------dd") |
| 1691 | DEF_ENC32(F2_sfclass, ICLASS_S2op"0101 111sssss PP0iiiii ------dd") |
| 1692 | |
| 1693 | |
| 1694 | DEF_FIELDROW_DESC32(ICLASS_S2op" 0110 -------- PP------ --------","[#6] Rdd=(Pt)") |
| 1695 | DEF_ENC32(C2_mask, ICLASS_S2op" 0110 --- ----- PP----tt --- ddddd") |
| 1696 | |
| 1697 | |
| 1698 | DEF_FIELDROW_DESC32(ICLASS_S2op" 0111 -------- PP------ --------","[#7] Rx=(Rs,#u4,#S6)") |
| 1699 | DEF_ENC32(S2_tableidxb,ICLASS_S2op" 0111 00isssss PPIIIIII iiixxxxx") |
| 1700 | DEF_ENC32(S2_tableidxh,ICLASS_S2op" 0111 01isssss PPIIIIII iiixxxxx") |
| 1701 | DEF_ENC32(S2_tableidxw,ICLASS_S2op" 0111 10isssss PPIIIIII iiixxxxx") |
| 1702 | DEF_ENC32(S2_tableidxd,ICLASS_S2op" 0111 11isssss PPIIIIII iiixxxxx") |
| 1703 | |
| 1704 | |
| 1705 | DEF_FIELDROW_DESC32(ICLASS_S2op" 1000 -------- PP------ --------","[#8] Rd=(Rss,#u6)") |
| 1706 | SH2_RR_ENC(S2_vsathub, "1000","000","-","000","ddddd") |
| 1707 | SH2_RR_ENC(S2_vsatwh, "1000","000","-","010","ddddd") |
| 1708 | SH2_RR_ENC(S2_vsatwuh, "1000","000","-","100","ddddd") |
| 1709 | SH2_RR_ENC(S2_vsathb, "1000","000","-","110","ddddd") |
| 1710 | SH2_RR_ENC(S2_clbp, "1000","010","-","000","ddddd") |
| 1711 | SH2_RR_ENC(S2_cl0p, "1000","010","-","010","ddddd") |
| 1712 | SH2_RR_ENC(S2_cl1p, "1000","010","-","100","ddddd") |
| 1713 | SH2_RR_ENC(S2_ct0p, "1000","111","-","010","ddddd") |
| 1714 | SH2_RR_ENC(S2_ct1p, "1000","111","-","100","ddddd") |
| 1715 | SH2_RR_ENC(S2_vtrunohb, "1000","100","-","000","ddddd") |
| 1716 | SH2_RR_ENC(S2_vtrunehb, "1000","100","-","010","ddddd") |
| 1717 | SH2_RR_ENC(S2_vrndpackwh, "1000","100","-","100","ddddd") |
| 1718 | SH2_RR_ENC(S2_vrndpackwhs, "1000","100","-","110","ddddd") |
| 1719 | SH2_RR_ENC(A2_sat, "1000","110","-","000","ddddd") |
| 1720 | SH2_RR_ENC(A2_roundsat, "1000","110","-","001","ddddd") |
| 1721 | SH_RRI5_ENC(S2_asr_i_svw_trun, "1000","110", "010","ddddd") |
| 1722 | SH_RRI5_ENC(A4_bitspliti, "1000","110", "100","ddddd") |
| 1723 | |
| 1724 | SH_RRI5_ENC(A7_clip, "1000","110", "101","ddddd") |
| 1725 | SH_RRI5_ENC(A7_vclip, "1000","110", "110","ddddd") |
| 1726 | |
| 1727 | |
| 1728 | SH2_RR_ENC(S4_clbpnorm, "1000","011","-","000","ddddd") |
| 1729 | SH_RRI6_ENC(S4_clbpaddi, "1000","011", "010","ddddd") |
| 1730 | SH2_RR_ENC(S5_popcountp, "1000","011","-","011","ddddd") |
| 1731 | |
| 1732 | SH_RRI4_ENC(S5_asrhub_rnd_sat, "1000","011", "100","ddddd") |
| 1733 | SH_RRI4_ENC(S5_asrhub_sat, "1000","011", "101","ddddd") |
| 1734 | |
| 1735 | SH2_RR_ENC(F2_conv_df2sf, "1000","000","-","001","ddddd") |
| 1736 | SH2_RR_ENC(F2_conv_ud2sf, "1000","001","-","001","ddddd") |
| 1737 | SH2_RR_ENC(F2_conv_d2sf, "1000","010","-","001","ddddd") |
| 1738 | SH2_RR_ENC(F2_conv_df2uw, "1000","011","-","001","ddddd") |
| 1739 | SH2_RR_ENC(F2_conv_df2w, "1000","100","-","001","ddddd") |
| 1740 | SH2_RR_ENC(F2_conv_df2uw_chop, "1000","101","-","001","ddddd") |
| 1741 | SH2_RR_ENC(F2_conv_df2w_chop, "1000","111","-","001","ddddd") |
| 1742 | |
| 1743 | |
| 1744 | |
| 1745 | DEF_FIELDROW_DESC32(ICLASS_S2op" 1001 -------- PP------ --------","[#9] Rd=(Ps,Pt)") |
| 1746 | DEF_ENC32(C2_vitpack, ICLASS_S2op" 1001 -00 ---ss PP----tt --- ddddd") |
| 1747 | DEF_ENC32(C2_tfrpr, ICLASS_S2op" 1001 -1- ---ss PP------ --- ddddd") |
| 1748 | |
| 1749 | |
| 1750 | DEF_FIELDROW_DESC32(ICLASS_S2op" 1010 -------- PP------ --------","[#10] Rdd=(Rss,#u6,#U6)") |
| 1751 | DEF_ENC32(S4_extractp,ICLASS_S2op" 1010 IIIsssss PPiiiiii IIIddddd") |
| 1752 | |
| 1753 | |
| 1754 | DEF_FIELDROW_DESC32(ICLASS_S2op" 1011 -------- PP------ --------","[#11] Rd=(Rs)") |
| 1755 | SH2_RR_ENC(F2_conv_uw2sf, "1011","001","-","000","ddddd") |
| 1756 | SH2_RR_ENC(F2_conv_w2sf, "1011","010","-","000","ddddd") |
| 1757 | SH2_RR_ENC(F2_conv_sf2uw, "1011","011","-","000","ddddd") |
| 1758 | SH2_RR_ENC(F2_conv_sf2w, "1011","100","-","000","ddddd") |
| 1759 | SH2_RR_ENC(F2_conv_sf2uw_chop, "1011","011","-","001","ddddd") |
| 1760 | SH2_RR_ENC(F2_conv_sf2w_chop, "1011","100","-","001","ddddd") |
| 1761 | SH2_RR_ENC(F2_sffixupr, "1011","101","-","000","ddddd") |
| 1762 | SH2_RR_ENC(F2_sfinvsqrta, "1011","111","-","0ee","ddddd") |
| 1763 | |
| 1764 | |
| 1765 | DEF_FIELDROW_DESC32(ICLASS_S2op" 1100 -------- PP------ --------","[#12] Rd=(Rs,#u6)") |
| 1766 | I5SHIFTTYPES(r, "1100","000", "0 ","ddddd") |
| 1767 | SH_RRI5_ENC(S2_asl_i_r_sat, "1100","010", "010","ddddd") |
| 1768 | SH_RRI5_ENC(S2_asr_i_r_rnd, "1100","010", "000","ddddd") |
| 1769 | |
| 1770 | SH2_RR_ENC(S2_svsathb, "1100","10-","-", "00-","ddddd") |
| 1771 | SH2_RR_ENC(S2_svsathub, "1100","10-","-", "01-","ddddd") |
| 1772 | |
| 1773 | SH_RRI5_ENC(A4_cround_ri, "1100","111", "00-","ddddd") |
| 1774 | SH_RRI6_ENC(A7_croundd_ri, "1100","111", "01-","ddddd") |
| 1775 | SH_RRI5_ENC(A4_round_ri, "1100","111", "10-","ddddd") |
| 1776 | SH_RRI5_ENC(A4_round_ri_sat, "1100","111", "11-","ddddd") |
| 1777 | |
| 1778 | DEF_ENC32(S2_setbit_i, ICLASS_S2op" 1100 110sssss PP0iiiii 000ddddd") |
| 1779 | DEF_ENC32(S2_clrbit_i, ICLASS_S2op" 1100 110sssss PP0iiiii 001ddddd") |
| 1780 | DEF_ENC32(S2_togglebit_i,ICLASS_S2op" 1100 110sssss PP0iiiii 010ddddd") |
| 1781 | |
| 1782 | DEF_ENC32(S4_clbaddi ,ICLASS_S2op" 1100 001sssss PPiiiiii 000ddddd") |
| 1783 | |
| 1784 | |
| 1785 | |
| 1786 | /* False read #u6 */ |
| 1787 | SH2_RR_ENC(S2_clb, "1100","000","-","1 00","ddddd") |
| 1788 | SH2_RR_ENC(S2_cl0, "1100","000","-","1 01","ddddd") |
| 1789 | SH2_RR_ENC(S2_cl1, "1100","000","-","1 10","ddddd") |
| 1790 | SH2_RR_ENC(S2_clbnorm, "1100","000","-","1 11","ddddd") |
| 1791 | SH2_RR_ENC(S2_ct0, "1100","010","-","1 00","ddddd") |
| 1792 | SH2_RR_ENC(S2_ct1, "1100","010","-","1 01","ddddd") |
| 1793 | SH2_RR_ENC(S2_brev, "1100","010","-","1 10","ddddd") |
| 1794 | SH2_RR_ENC(S2_vsplatrb, "1100","010","-","1 11","ddddd") |
| 1795 | SH2_RR_ENC(A2_abs, "1100","100","-","1 00","ddddd") |
| 1796 | SH2_RR_ENC(A2_abssat, "1100","100","-","1 01","ddddd") |
| 1797 | SH2_RR_ENC(A2_negsat, "1100","100","-","1 10","ddddd") |
| 1798 | SH2_RR_ENC(A2_swiz, "1100","100","-","1 11","ddddd") |
| 1799 | SH2_RR_ENC(A2_sath, "1100","110","-","1 00","ddddd") |
| 1800 | SH2_RR_ENC(A2_satuh, "1100","110","-","1 01","ddddd") |
| 1801 | SH2_RR_ENC(A2_satub, "1100","110","-","1 10","ddddd") |
| 1802 | SH2_RR_ENC(A2_satb, "1100","110","-","1 11","ddddd") |
| 1803 | |
| 1804 | |
| 1805 | DEF_FIELDROW_DESC32(ICLASS_S2op" 1101 -------- PP------ --------","[#13] Rd=(Rs,#u6,#U6)") |
| 1806 | DEF_ENC32(S2_extractu, ICLASS_S2op" 1101 0IIsssss PP0iiiii IIIddddd") |
| 1807 | DEF_ENC32(S4_extract, ICLASS_S2op" 1101 1IIsssss PP0iiiii IIIddddd") |
| 1808 | DEF_ENC32(S2_mask, ICLASS_S2op" 1101 0II----- PP1iiiii IIIddddd") |
| 1809 | |
| 1810 | |
| 1811 | |
| 1812 | |
| 1813 | |
| 1814 | |
| 1815 | DEF_FIELDROW_DESC32(ICLASS_S2op" 1110 -------- PP------ --------","[#14] Rx=(Rs,#u6)") |
| 1816 | I5SHIFTTYPES(r_nac, "1110","00-","0","xxxxx") |
| 1817 | I5SHIFTTYPES(r_acc, "1110","00-","1","xxxxx") |
| 1818 | I5SHIFTTYPES(r_and, "1110","01-","0","xxxxx") |
| 1819 | I5SHIFTTYPES(r_or, "1110","01-","1","xxxxx") |
| 1820 | I5SHIFTTYPES_NOASR(r_xacc,"1110","10-","0","xxxxx") |
| 1821 | |
| 1822 | |
| 1823 | DEF_FIELDROW_DESC32(ICLASS_S2op" 1111 -------- PP------ --------","[#15] Rs=(Rs,#u6,#U6)") |
| 1824 | DEF_ENC32(S2_insert, ICLASS_S2op" 1111 0IIsssss PP0iiiii IIIxxxxx") |
| 1825 | |
| 1826 | |
| 1827 | |
| 1828 | |
| 1829 | |
| 1830 | /*************************/ |
| 1831 | /* S_3_operand */ |
| 1832 | /*************************/ |
| 1833 | |
| 1834 | |
| 1835 | DEF_FIELDROW_DESC32(ICLASS_S3op" 0000 -------- PP------ --------","[#0] Rdd=(Rss,Rtt,#u3)") |
| 1836 | SH_RRR_ENC(S2_valignib, "0000","0--","-","iii","ddddd") |
| 1837 | SH_RRR_ENC(S2_vspliceib, "0000","1--","-","iii","ddddd") |
| 1838 | |
| 1839 | |
| 1840 | DEF_FIELDROW_DESC32(ICLASS_S3op" 0001 -------- PP------ --------","[#1] Rdd=(Rss,Rtt)") |
| 1841 | SH_RRR_ENC(S2_extractup_rp, "0001","00-","-","00-","ddddd") |
| 1842 | SH_RRR_ENC(S2_shuffeb, "0001","00-","-","01-","ddddd") |
| 1843 | SH_RRR_ENC(S2_shuffob, "0001","00-","-","10-","ddddd") |
| 1844 | SH_RRR_ENC(S2_shuffeh, "0001","00-","-","11-","ddddd") |
| 1845 | |
| 1846 | SH_RRR_ENC(S2_shuffoh, "0001","10-","-","000","ddddd") |
| 1847 | SH_RRR_ENC(S2_vtrunewh, "0001","10-","-","010","ddddd") |
| 1848 | SH_RRR_ENC(S6_vtrunehb_ppp, "0001","10-","-","011","ddddd") |
| 1849 | SH_RRR_ENC(S2_vtrunowh, "0001","10-","-","100","ddddd") |
| 1850 | SH_RRR_ENC(S6_vtrunohb_ppp, "0001","10-","-","101","ddddd") |
| 1851 | SH_RRR_ENC(S2_lfsp, "0001","10-","-","110","ddddd") |
| 1852 | |
| 1853 | SH_RRR_ENC(S4_vxaddsubw, "0001","01-","-","000","ddddd") |
| 1854 | SH_RRR_ENC(A5_vaddhubs, "0001","01-","-","001","ddddd") |
| 1855 | SH_RRR_ENC(S4_vxsubaddw, "0001","01-","-","010","ddddd") |
| 1856 | SH_RRR_ENC(S4_vxaddsubh, "0001","01-","-","100","ddddd") |
| 1857 | SH_RRR_ENC(S4_vxsubaddh, "0001","01-","-","110","ddddd") |
| 1858 | |
| 1859 | SH_RRR_ENC(S4_vxaddsubhr, "0001","11-","-","00-","ddddd") |
| 1860 | SH_RRR_ENC(S4_vxsubaddhr, "0001","11-","-","01-","ddddd") |
| 1861 | SH_RRR_ENC(S4_extractp_rp, "0001","11-","-","10-","ddddd") |
| 1862 | SH_RRR_ENC(S2_cabacdecbin, "0001","11-","-","11-","ddddd") /* implicit P0 write */ |
| 1863 | |
| 1864 | |
| 1865 | DEF_FIELDROW_DESC32(ICLASS_S3op" 0010 -------- PP------ --------","[#2] Rdd=(Rss,Rtt,Pu)") |
| 1866 | SH_RRR_ENC(S2_valignrb, "0010","0--","-","-uu","ddddd") |
| 1867 | SH_RRR_ENC(S2_vsplicerb, "0010","100","-","-uu","ddddd") |
| 1868 | SH_RRR_ENC(A4_addp_c, "0010","110","-","-xx","ddddd") |
| 1869 | SH_RRR_ENC(A4_subp_c, "0010","111","-","-xx","ddddd") |
| 1870 | |
| 1871 | |
| 1872 | DEF_FIELDROW_DESC32(ICLASS_S3op" 0011 -------- PP------ --------","[#3] Rdd=(Rss,Rt)") |
| 1873 | RSHIFTTYPES(vw, "0011","00-","-","-","ddddd") |
| 1874 | RSHIFTTYPES(vh, "0011","01-","-","-","ddddd") |
| 1875 | RSHIFTTYPES(p, "0011","10-","-","-","ddddd") |
| 1876 | SH_RRR_ENC(S2_vcrotate, "0011","11-","-","00-","ddddd") |
| 1877 | SH_RRR_ENC(S2_vcnegh, "0011","11-","-","01-","ddddd") |
| 1878 | SH_RRR_ENC(S4_vrcrotate, "0011","11-","i","11i","ddddd") |
| 1879 | |
| 1880 | |
| 1881 | DEF_FIELDROW_DESC32(ICLASS_S3op" 0100 -------- PP------ --------","[#4] Rd=(Rs,Rt,#u3)") |
| 1882 | DEF_ENC32(S2_addasl_rrri, ICLASS_S3op" 0100 000 sssss PP0ttttt iiiddddd") |
| 1883 | |
| 1884 | |
| 1885 | |
| 1886 | DEF_FIELDROW_DESC32(ICLASS_S3op" 0101 -------- PP------ --------","[#5] Rd=(Rss,Rt)") |
| 1887 | SH_RRR_ENC(S2_asr_r_svw_trun, "0101","---","-","010","ddddd") |
| 1888 | SH_RRR_ENC(M4_cmpyi_wh, "0101","---","-","100","ddddd") |
| 1889 | SH_RRR_ENC(M4_cmpyr_wh, "0101","---","-","110","ddddd") |
| 1890 | SH_RRR_ENC(M4_cmpyi_whc, "0101","---","-","101","ddddd") |
| 1891 | SH_RRR_ENC(M4_cmpyr_whc, "0101","---","-","111","ddddd") |
| 1892 | |
| 1893 | DEF_FIELDROW_DESC32(ICLASS_S3op" 0110 -------- PP------ --------","[#6] Rd=(Rs,Rt)") |
| 1894 | SH_RRR_ENC(S2_asr_r_r_sat, "0110","00-","-","00-","ddddd") \ |
| 1895 | SH_RRR_ENC(S2_asl_r_r_sat, "0110","00-","-","10-","ddddd") |
| 1896 | |
| 1897 | RSHIFTTYPES(r, "0110","01-","-","-","ddddd") |
| 1898 | |
| 1899 | SH_RRR_ENC(S2_setbit_r, "0110","10-","-","00-","ddddd") |
| 1900 | SH_RRR_ENC(S2_clrbit_r, "0110","10-","-","01-","ddddd") |
| 1901 | SH_RRR_ENC(S2_togglebit_r, "0110","10-","-","10-","ddddd") |
| 1902 | SH_RRRiENC(S4_lsli, "0110","10-","-","11i","ddddd") |
| 1903 | |
| 1904 | SH_RRR_ENC(A4_cround_rr, "0110","11-","-","00-","ddddd") |
| 1905 | SH_RRR_ENC(A7_croundd_rr, "0110","11-","-","01-","ddddd") |
| 1906 | SH_RRR_ENC(A4_round_rr, "0110","11-","-","10-","ddddd") |
| 1907 | SH_RRR_ENC(A4_round_rr_sat, "0110","11-","-","11-","ddddd") |
| 1908 | |
| 1909 | |
| 1910 | |
| 1911 | |
| 1912 | DEF_FIELDROW_DESC32(ICLASS_S3op" 0111 -------- PP------ --------","[#7] Pd=(Rs,Rt)") |
| 1913 | SH_RRR_ENC(S2_tstbit_r, "0111","000","-","---","---dd") |
| 1914 | SH_RRR_ENC(C2_bitsset, "0111","010","-","---","---dd") |
| 1915 | SH_RRR_ENC(C2_bitsclr, "0111","100","-","---","---dd") |
| 1916 | SH_RRR_ENC(A4_cmpheq, "0111","110","-","011","---dd") |
| 1917 | SH_RRR_ENC(A4_cmphgt, "0111","110","-","100","---dd") |
| 1918 | SH_RRR_ENC(A4_cmphgtu, "0111","110","-","101","---dd") |
| 1919 | SH_RRR_ENC(A4_cmpbeq, "0111","110","-","110","---dd") |
| 1920 | SH_RRR_ENC(A4_cmpbgtu, "0111","110","-","111","---dd") |
| 1921 | SH_RRR_ENC(A4_cmpbgt, "0111","110","-","010","---dd") |
| 1922 | SH_RRR_ENC(S4_ntstbit_r, "0111","001","-","---","---dd") |
| 1923 | SH_RRR_ENC(C4_nbitsset, "0111","011","-","---","---dd") |
| 1924 | SH_RRR_ENC(C4_nbitsclr, "0111","101","-","---","---dd") |
| 1925 | |
| 1926 | SH_RRR_ENC(F2_sfcmpge, "0111","111","-","000","---dd") |
| 1927 | SH_RRR_ENC(F2_sfcmpuo, "0111","111","-","001","---dd") |
| 1928 | SH_RRR_ENC(F2_sfcmpeq, "0111","111","-","011","---dd") |
| 1929 | SH_RRR_ENC(F2_sfcmpgt, "0111","111","-","100","---dd") |
| 1930 | |
| 1931 | |
| 1932 | DEF_FIELDROW_DESC32(ICLASS_S3op" 1000 -------- PP------ --------","[#8] Rx=(Rs,Rtt)") |
| 1933 | SH_RRR_ENC(S2_insert_rp, "1000","---","-","---","xxxxx") |
| 1934 | |
| 1935 | |
| 1936 | DEF_FIELDROW_DESC32(ICLASS_S3op" 1001 -------- PP------ --------","[#9] Rd=(Rs,Rtt)") |
| 1937 | SH_RRR_ENC(S2_extractu_rp, "1001","00-","-","00-","ddddd") |
| 1938 | SH_RRR_ENC(S4_extract_rp, "1001","00-","-","01-","ddddd") |
| 1939 | |
| 1940 | |
| 1941 | DEF_FIELDROW_DESC32(ICLASS_S3op" 1010 -------- PP------ --------","[#10] Rxx=(Rss,Rtt)") |
| 1942 | SH_RRR_ENC(S2_insertp_rp, "1010","0--","0","---","xxxxx") |
| 1943 | SH_RRR_ENC(M4_xor_xacc, "1010","10-","0","000","xxxxx") |
| 1944 | |
| 1945 | DEF_FIELDROW_DESC32(ICLASS_S3op" 1011 -------- PP------ --------","[#11] Rxx=(Rss,Rt)") |
| 1946 | RSHIFTTYPES(p_or, "1011","000","-","-","xxxxx") |
| 1947 | RSHIFTTYPES(p_and, "1011","010","-","-","xxxxx") |
| 1948 | RSHIFTTYPES(p_nac, "1011","100","-","-","xxxxx") |
| 1949 | RSHIFTTYPES(p_acc, "1011","110","-","-","xxxxx") |
| 1950 | RSHIFTTYPES(p_xor, "1011","011","-","-","xxxxx") |
| 1951 | |
| 1952 | SH_RRR_ENCX(A4_vrmaxh, "1011","001","0","001","uuuuu") |
| 1953 | SH_RRR_ENCX(A4_vrmaxuh, "1011","001","1","001","uuuuu") |
| 1954 | SH_RRR_ENCX(A4_vrmaxw, "1011","001","0","010","uuuuu") |
| 1955 | SH_RRR_ENCX(A4_vrmaxuw, "1011","001","1","010","uuuuu") |
| 1956 | |
| 1957 | SH_RRR_ENCX(A4_vrminh, "1011","001","0","101","uuuuu") |
| 1958 | SH_RRR_ENCX(A4_vrminuh, "1011","001","1","101","uuuuu") |
| 1959 | SH_RRR_ENCX(A4_vrminw, "1011","001","0","110","uuuuu") |
| 1960 | SH_RRR_ENCX(A4_vrminuw, "1011","001","1","110","uuuuu") |
| 1961 | |
| 1962 | SH_RRR_ENC(S2_vrcnegh, "1011","001","1","111","xxxxx") |
| 1963 | |
| 1964 | SH_RRR_ENC(S4_vrcrotate_acc, "1011","101","i","--i","xxxxx") |
| 1965 | |
| 1966 | |
| 1967 | DEF_FIELDROW_DESC32(ICLASS_S3op" 1100 -------- PP------ --------","[#12] Rx=(Rs,Rt)") |
| 1968 | RSHIFTTYPES(r_or, "1100","00-","-","-","xxxxx") |
| 1969 | RSHIFTTYPES(r_and, "1100","01-","-","-","xxxxx") |
| 1970 | RSHIFTTYPES(r_nac, "1100","10-","-","-","xxxxx") |
| 1971 | RSHIFTTYPES(r_acc, "1100","11-","-","-","xxxxx") |
| 1972 | |
| 1973 | |
| 1974 | DEF_FIELDROW_DESC32(ICLASS_S3op" 1101 -------- PP------ --------","[#13] Reserved") |
| 1975 | DEF_FIELDROW_DESC32(ICLASS_S3op" 1110 -------- PP------ --------","[#14] Reserved") |
| 1976 | |
| 1977 | |
| 1978 | DEF_FIELDROW_DESC32(ICLASS_S3op" 1111 -------- PP------ --------","[#14] User Instruction") |
| 1979 | |
| 1980 | |
| 1981 | |
| 1982 | |
| 1983 | |
| 1984 | |
| 1985 | |
| 1986 | |
| 1987 | |
| 1988 | |
| 1989 | |
| 1990 | |
| 1991 | |
| 1992 | /*******************************/ |
| 1993 | /* */ |
| 1994 | /* */ |
| 1995 | /* ALU64 */ |
| 1996 | /* */ |
| 1997 | /* */ |
| 1998 | /*******************************/ |
| 1999 | DEF_CLASS32(ICLASS_ALU64" ---- -------- PP------ --------",ALU64) |
| 2000 | DEF_FIELD32(ICLASS_ALU64" !!!! -------- PP------ --------",ALU64_RegType,"Register Type") |
| 2001 | DEF_FIELD32(ICLASS_ALU64" 0--- !!!----- PP------ --------",A_MajOp,"Major Opcode") |
| 2002 | DEF_FIELD32(ICLASS_ALU64" 0--- -------- PP------ !!!-----",A_MinOp,"Minor Opcode") |
| 2003 | DEF_FIELD32(ICLASS_ALU64" 11-- -------- PP------ ---!!!!!",A_MajOp,"Major Opcode") |
| 2004 | |
| 2005 | |
| 2006 | |
| 2007 | #define ALU64_RRR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ |
| 2008 | DEF_ENC32(TAG, ICLASS_ALU64" "MAJ4" "MIN3"sssss PP"SMOD1"ttttt "VMIN3 DSTCHARS) |
| 2009 | |
| 2010 | #define LEGACY_ALU64_RRR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ |
| 2011 | LEGACY_DEF_ENC32(TAG, ICLASS_ALU64" "MAJ4" "MIN3"sssss PP"SMOD1"ttttt "VMIN3 DSTCHARS) |
| 2012 | |
| 2013 | |
| 2014 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 0000 -------- PP------ --------","[#0] Rd=(Rss,Rtt)") |
| 2015 | ALU64_RRR_ENC(S2_parityp, "0000","---","-","---","ddddd") |
| 2016 | |
| 2017 | |
| 2018 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 0001 -------- PP------ --------","[#1] Rdd=(Pu,Rss,Rtt)") |
| 2019 | ALU64_RRR_ENC(C2_vmux, "0001","---","-","-uu","ddddd") |
| 2020 | |
| 2021 | |
| 2022 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 0010 -------- PP------ --------","[#2] Pd=(Rss,Rtt)") |
| 2023 | ALU64_RRR_ENC(A2_vcmpweq, "0010","0--","0","000","---dd") |
| 2024 | ALU64_RRR_ENC(A2_vcmpwgt, "0010","0--","0","001","---dd") |
| 2025 | ALU64_RRR_ENC(A2_vcmpwgtu, "0010","0--","0","010","---dd") |
| 2026 | ALU64_RRR_ENC(A2_vcmpheq, "0010","0--","0","011","---dd") |
| 2027 | ALU64_RRR_ENC(A2_vcmphgt, "0010","0--","0","100","---dd") |
| 2028 | ALU64_RRR_ENC(A2_vcmphgtu, "0010","0--","0","101","---dd") |
| 2029 | ALU64_RRR_ENC(A2_vcmpbeq, "0010","0--","0","110","---dd") |
| 2030 | ALU64_RRR_ENC(A2_vcmpbgtu, "0010","0--","0","111","---dd") |
| 2031 | |
| 2032 | ALU64_RRR_ENC(A4_vcmpbeq_any, "0010","0--","1","000","---dd") |
| 2033 | ALU64_RRR_ENC(A6_vcmpbeq_notany, "0010","0--","1","001","---dd") |
| 2034 | ALU64_RRR_ENC(A4_vcmpbgt, "0010","0--","1","010","---dd") |
| 2035 | ALU64_RRR_ENC(A4_tlbmatch, "0010","0--","1","011","---dd") |
| 2036 | ALU64_RRR_ENC(A4_boundscheck_lo, "0010","0--","1","100","---dd") |
| 2037 | ALU64_RRR_ENC(A4_boundscheck_hi, "0010","0--","1","101","---dd") |
| 2038 | |
| 2039 | ALU64_RRR_ENC(C2_cmpeqp, "0010","100","-","000","---dd") |
| 2040 | ALU64_RRR_ENC(C2_cmpgtp, "0010","100","-","010","---dd") |
| 2041 | ALU64_RRR_ENC(C2_cmpgtup, "0010","100","-","100","---dd") |
| 2042 | |
| 2043 | ALU64_RRR_ENC(F2_dfcmpeq, "0010","111","-","000","---dd") |
| 2044 | ALU64_RRR_ENC(F2_dfcmpgt, "0010","111","-","001","---dd") |
| 2045 | ALU64_RRR_ENC(F2_dfcmpge, "0010","111","-","010","---dd") |
| 2046 | ALU64_RRR_ENC(F2_dfcmpuo, "0010","111","-","011","---dd") |
| 2047 | |
| 2048 | |
| 2049 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 0011 -------- PP------ --------","[#3] Rdd=(Rss,Rtt)") |
| 2050 | ALU64_RRR_ENC(A2_vaddub, "0011","000","-","000","ddddd") |
| 2051 | ALU64_RRR_ENC(A2_vaddubs, "0011","000","-","001","ddddd") |
| 2052 | ALU64_RRR_ENC(A2_vaddh, "0011","000","-","010","ddddd") |
| 2053 | ALU64_RRR_ENC(A2_vaddhs, "0011","000","-","011","ddddd") |
| 2054 | ALU64_RRR_ENC(A2_vadduhs, "0011","000","-","100","ddddd") |
| 2055 | ALU64_RRR_ENC(A2_vaddw, "0011","000","-","101","ddddd") |
| 2056 | ALU64_RRR_ENC(A2_vaddws, "0011","000","-","110","ddddd") |
| 2057 | ALU64_RRR_ENC(A2_addp, "0011","000","-","111","ddddd") |
| 2058 | |
| 2059 | ALU64_RRR_ENC(A2_vsubub, "0011","001","-","000","ddddd") |
| 2060 | ALU64_RRR_ENC(A2_vsububs, "0011","001","-","001","ddddd") |
| 2061 | ALU64_RRR_ENC(A2_vsubh, "0011","001","-","010","ddddd") |
| 2062 | ALU64_RRR_ENC(A2_vsubhs, "0011","001","-","011","ddddd") |
| 2063 | ALU64_RRR_ENC(A2_vsubuhs, "0011","001","-","100","ddddd") |
| 2064 | ALU64_RRR_ENC(A2_vsubw, "0011","001","-","101","ddddd") |
| 2065 | ALU64_RRR_ENC(A2_vsubws, "0011","001","-","110","ddddd") |
| 2066 | ALU64_RRR_ENC(A2_subp, "0011","001","-","111","ddddd") |
| 2067 | |
| 2068 | ALU64_RRR_ENC(A2_vavgub, "0011","010","-","000","ddddd") |
| 2069 | ALU64_RRR_ENC(A2_vavgubr, "0011","010","-","001","ddddd") |
| 2070 | ALU64_RRR_ENC(A2_vavgh, "0011","010","-","010","ddddd") |
| 2071 | ALU64_RRR_ENC(A2_vavghr, "0011","010","-","011","ddddd") |
| 2072 | ALU64_RRR_ENC(A2_vavghcr, "0011","010","-","100","ddddd") |
| 2073 | ALU64_RRR_ENC(A2_vavguh, "0011","010","-","101","ddddd") |
| 2074 | ALU64_RRR_ENC(A2_vavguhr, "0011","010","-","11-","ddddd") |
| 2075 | |
| 2076 | ALU64_RRR_ENC(A2_vavgw, "0011","011","-","000","ddddd") |
| 2077 | ALU64_RRR_ENC(A2_vavgwr, "0011","011","-","001","ddddd") |
| 2078 | ALU64_RRR_ENC(A2_vavgwcr, "0011","011","-","010","ddddd") |
| 2079 | ALU64_RRR_ENC(A2_vavguw, "0011","011","-","011","ddddd") |
| 2080 | ALU64_RRR_ENC(A2_vavguwr, "0011","011","-","100","ddddd") |
| 2081 | ALU64_RRR_ENC(A2_addpsat, "0011","011","-","101","ddddd") |
| 2082 | ALU64_RRR_ENC(A2_addspl, "0011","011","-","110","ddddd") |
| 2083 | ALU64_RRR_ENC(A2_addsph, "0011","011","-","111","ddddd") |
| 2084 | |
| 2085 | ALU64_RRR_ENC(A2_vnavgh, "0011","100","-","000","ddddd") |
| 2086 | ALU64_RRR_ENC(A2_vnavghr, "0011","100","-","001","ddddd") |
| 2087 | ALU64_RRR_ENC(A2_vnavghcr, "0011","100","-","010","ddddd") |
| 2088 | ALU64_RRR_ENC(A2_vnavgw, "0011","100","-","011","ddddd") |
| 2089 | ALU64_RRR_ENC(A2_vnavgwr, "0011","100","-","10-","ddddd") |
| 2090 | ALU64_RRR_ENC(A2_vnavgwcr, "0011","100","-","11-","ddddd") |
| 2091 | |
| 2092 | ALU64_RRR_ENC(A2_vminub, "0011","101","-","000","ddddd") |
| 2093 | ALU64_RRR_ENC(A2_vminh, "0011","101","-","001","ddddd") |
| 2094 | ALU64_RRR_ENC(A2_vminuh, "0011","101","-","010","ddddd") |
| 2095 | ALU64_RRR_ENC(A2_vminw, "0011","101","-","011","ddddd") |
| 2096 | ALU64_RRR_ENC(A2_vminuw, "0011","101","-","100","ddddd") |
| 2097 | ALU64_RRR_ENC(A2_vmaxuw, "0011","101","-","101","ddddd") |
| 2098 | ALU64_RRR_ENC(A2_minp, "0011","101","-","110","ddddd") |
| 2099 | ALU64_RRR_ENC(A2_minup, "0011","101","-","111","ddddd") |
| 2100 | |
| 2101 | ALU64_RRR_ENC(A2_vmaxub, "0011","110","-","000","ddddd") |
| 2102 | ALU64_RRR_ENC(A2_vmaxh, "0011","110","-","001","ddddd") |
| 2103 | ALU64_RRR_ENC(A2_vmaxuh, "0011","110","-","010","ddddd") |
| 2104 | ALU64_RRR_ENC(A2_vmaxw, "0011","110","-","011","ddddd") |
| 2105 | ALU64_RRR_ENC(A2_maxp, "0011","110","-","100","ddddd") |
| 2106 | ALU64_RRR_ENC(A2_maxup, "0011","110","-","101","ddddd") |
| 2107 | ALU64_RRR_ENC(A2_vmaxb, "0011","110","-","110","ddddd") |
| 2108 | ALU64_RRR_ENC(A2_vminb, "0011","110","-","111","ddddd") |
| 2109 | |
| 2110 | ALU64_RRR_ENC(A2_andp, "0011","111","-","000","ddddd") |
| 2111 | ALU64_RRR_ENC(A2_orp, "0011","111","-","010","ddddd") |
| 2112 | ALU64_RRR_ENC(A2_xorp, "0011","111","-","100","ddddd") |
| 2113 | ALU64_RRR_ENC(A4_andnp, "0011","111","-","001","ddddd") |
| 2114 | ALU64_RRR_ENC(A4_ornp, "0011","111","-","011","ddddd") |
| 2115 | |
| 2116 | ALU64_RRR_ENC(A4_modwrapu, "0011","111","-","111","ddddd") |
| 2117 | |
| 2118 | |
| 2119 | |
| 2120 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 0100 -------- PP------ --------","[#4] Rdd=(Rs,Rt)") |
| 2121 | LEGACY_ALU64_RRR_ENC(S2_packhl, "0100","--0","-","---","ddddd") |
| 2122 | ALU64_RRR_ENC(A4_bitsplit, "0100","--1","-","---","ddddd") |
| 2123 | |
| 2124 | |
| 2125 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 0101 -------- PP------ --------","[#5] Rd=(Rs,Rt)") |
| 2126 | ALU64_RRR_ENC(A2_addh_l16_ll, "0101","000","-","00-","ddddd") |
| 2127 | ALU64_RRR_ENC(A2_addh_l16_hl, "0101","000","-","01-","ddddd") |
| 2128 | ALU64_RRR_ENC(A2_addh_l16_sat_ll,"0101","000","-","10-","ddddd") |
| 2129 | ALU64_RRR_ENC(A2_addh_l16_sat_hl,"0101","000","-","11-","ddddd") |
| 2130 | |
| 2131 | ALU64_RRR_ENC(A2_subh_l16_ll, "0101","001","-","00-","ddddd") |
| 2132 | ALU64_RRR_ENC(A2_subh_l16_hl, "0101","001","-","01-","ddddd") |
| 2133 | ALU64_RRR_ENC(A2_subh_l16_sat_ll,"0101","001","-","10-","ddddd") |
| 2134 | ALU64_RRR_ENC(A2_subh_l16_sat_hl,"0101","001","-","11-","ddddd") |
| 2135 | |
| 2136 | ALU64_RRR_ENC(A2_addh_h16_ll, "0101","010","-","000","ddddd") |
| 2137 | ALU64_RRR_ENC(A2_addh_h16_lh, "0101","010","-","001","ddddd") |
| 2138 | ALU64_RRR_ENC(A2_addh_h16_hl, "0101","010","-","010","ddddd") |
| 2139 | ALU64_RRR_ENC(A2_addh_h16_hh, "0101","010","-","011","ddddd") |
| 2140 | ALU64_RRR_ENC(A2_addh_h16_sat_ll,"0101","010","-","100","ddddd") |
| 2141 | ALU64_RRR_ENC(A2_addh_h16_sat_lh,"0101","010","-","101","ddddd") |
| 2142 | ALU64_RRR_ENC(A2_addh_h16_sat_hl,"0101","010","-","110","ddddd") |
| 2143 | ALU64_RRR_ENC(A2_addh_h16_sat_hh,"0101","010","-","111","ddddd") |
| 2144 | |
| 2145 | ALU64_RRR_ENC(A2_subh_h16_ll, "0101","011","-","000","ddddd") |
| 2146 | ALU64_RRR_ENC(A2_subh_h16_lh, "0101","011","-","001","ddddd") |
| 2147 | ALU64_RRR_ENC(A2_subh_h16_hl, "0101","011","-","010","ddddd") |
| 2148 | ALU64_RRR_ENC(A2_subh_h16_hh, "0101","011","-","011","ddddd") |
| 2149 | ALU64_RRR_ENC(A2_subh_h16_sat_ll,"0101","011","-","100","ddddd") |
| 2150 | ALU64_RRR_ENC(A2_subh_h16_sat_lh,"0101","011","-","101","ddddd") |
| 2151 | ALU64_RRR_ENC(A2_subh_h16_sat_hl,"0101","011","-","110","ddddd") |
| 2152 | ALU64_RRR_ENC(A2_subh_h16_sat_hh,"0101","011","-","111","ddddd") |
| 2153 | |
| 2154 | LEGACY_ALU64_RRR_ENC(A2_addsat, "0101","100","-","0--","ddddd") |
| 2155 | LEGACY_ALU64_RRR_ENC(A2_subsat, "0101","100","-","1--","ddddd") |
| 2156 | |
| 2157 | ALU64_RRR_ENC(A2_min, "0101","101","-","0--","ddddd") |
| 2158 | ALU64_RRR_ENC(A2_minu, "0101","101","-","1--","ddddd") |
| 2159 | |
| 2160 | ALU64_RRR_ENC(A2_max, "0101","110","-","0--","ddddd") |
| 2161 | ALU64_RRR_ENC(A2_maxu, "0101","110","-","1--","ddddd") |
| 2162 | |
| 2163 | ALU64_RRR_ENC(S4_parity, "0101","111","-","---","ddddd") |
| 2164 | |
| 2165 | |
| 2166 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 0110 -------- PP------ --------","[#6] Rd=#u10 ") |
| 2167 | DEF_ENC32(F2_sfimm_p, ICLASS_ALU64" 0110 00i ----- PPiiiiii iiiddddd") |
| 2168 | DEF_ENC32(F2_sfimm_n, ICLASS_ALU64" 0110 01i ----- PPiiiiii iiiddddd") |
| 2169 | |
| 2170 | |
| 2171 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 0111 -------- PP------ --------","[#7] Rd=(Rs,Rt,#u6)") |
| 2172 | DEF_ENC32(M4_mpyrr_addi, ICLASS_ALU64" 0111 0ii sssss PPittttt iiiddddd") |
| 2173 | |
| 2174 | |
| 2175 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 1000 -------- PP------ --------","[#8] Rd=(Rs,#u6,#U6)") |
| 2176 | DEF_ENC32(M4_mpyri_addi, ICLASS_ALU64" 1000 Iii sssss PPiddddd iiiIIIII") |
| 2177 | |
| 2178 | |
| 2179 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 1001 -------- PP------ --------","[#9] Rdd=#u10 ") |
| 2180 | DEF_ENC32(F2_dfimm_p, ICLASS_ALU64" 1001 00i ----- PPiiiiii iiiddddd") |
| 2181 | DEF_ENC32(F2_dfimm_n, ICLASS_ALU64" 1001 01i ----- PPiiiiii iiiddddd") |
| 2182 | |
| 2183 | |
| 2184 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 1010 -------- PP------ --------","[#10] Rx=(Rs,Rx,#s10)") |
| 2185 | DEF_ENC32(S4_or_andix, ICLASS_ALU64" 1010 01i xxxxx PPiiiiii iiiuuuuu") |
| 2186 | DEF_ENC32(S4_or_andi, ICLASS_ALU64" 1010 00i sssss PPiiiiii iiixxxxx") |
| 2187 | DEF_ENC32(S4_or_ori, ICLASS_ALU64" 1010 10i sssss PPiiiiii iiixxxxx") |
| 2188 | |
| 2189 | |
| 2190 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 1011 -------- PP------ --------","[#11] Rd=(Rs,Rd,#s6)") |
| 2191 | DEF_ENC32(S4_addaddi, ICLASS_ALU64" 1011 0ii sssss PPiddddd iiiuuuuu") |
| 2192 | DEF_ENC32(S4_subaddi, ICLASS_ALU64" 1011 1ii sssss PPiddddd iiiuuuuu") |
| 2193 | |
| 2194 | |
| 2195 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 1100 -------- PP------ --------","[#12] Pd=(Rss,#s8)") |
| 2196 | DEF_ENC32(A4_vcmpbeqi, ICLASS_ALU64"1100 000sssss PP-iiiii iii00-dd") |
| 2197 | DEF_ENC32(A4_vcmpbgti, ICLASS_ALU64"1100 001sssss PP-iiiii iii00-dd") |
| 2198 | DEF_ENC32(A4_vcmpbgtui, ICLASS_ALU64"1100 010sssss PP-0iiii iii00-dd") |
| 2199 | DEF_ENC32(A4_vcmpheqi, ICLASS_ALU64"1100 000sssss PP-iiiii iii01-dd") |
| 2200 | DEF_ENC32(A4_vcmphgti, ICLASS_ALU64"1100 001sssss PP-iiiii iii01-dd") |
| 2201 | DEF_ENC32(A4_vcmphgtui, ICLASS_ALU64"1100 010sssss PP-0iiii iii01-dd") |
| 2202 | DEF_ENC32(A4_vcmpweqi, ICLASS_ALU64"1100 000sssss PP-iiiii iii10-dd") |
| 2203 | DEF_ENC32(A4_vcmpwgti, ICLASS_ALU64"1100 001sssss PP-iiiii iii10-dd") |
| 2204 | DEF_ENC32(A4_vcmpwgtui, ICLASS_ALU64"1100 010sssss PP-0iiii iii10-dd") |
| 2205 | |
| 2206 | DEF_ENC32(F2_dfclass, ICLASS_ALU64"1100 100sssss PP-000ii iii10-dd") |
| 2207 | |
| 2208 | |
| 2209 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 1101 -------- PP------ --------","[#13] Pd=(Rs,#s8)") |
| 2210 | DEF_ENC32(A4_cmpbeqi, ICLASS_ALU64"1101 -00sssss PP-iiiii iii00-dd") |
| 2211 | DEF_ENC32(A4_cmpbgti, ICLASS_ALU64"1101 -01sssss PP-iiiii iii00-dd") |
| 2212 | DEF_ENC32(A4_cmpbgtui, ICLASS_ALU64"1101 -10sssss PP-0iiii iii00-dd") |
| 2213 | DEF_ENC32(A4_cmpheqi, ICLASS_ALU64"1101 -00sssss PP-iiiii iii01-dd") |
| 2214 | DEF_ENC32(A4_cmphgti, ICLASS_ALU64"1101 -01sssss PP-iiiii iii01-dd") |
| 2215 | DEF_ENC32(A4_cmphgtui, ICLASS_ALU64"1101 -10sssss PP-0iiii iii01-dd") |
| 2216 | |
| 2217 | |
| 2218 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 1110 -------- PP------ --------","[#14] Rx=(#u9,op(Rx,#u5))") |
| 2219 | |
| 2220 | #define OP_OPI_RI(TAG,OPB)\ |
| 2221 | DEF_ENC32(S4_andi_##TAG##_ri,ICLASS_ALU64" 1110 iiixxxxx PPiIIIII iii"OPB"i00-")\ |
| 2222 | DEF_ENC32(S4_ori_##TAG##_ri, ICLASS_ALU64" 1110 iiixxxxx PPiIIIII iii"OPB"i01-")\ |
| 2223 | DEF_ENC32(S4_addi_##TAG##_ri,ICLASS_ALU64" 1110 iiixxxxx PPiIIIII iii"OPB"i10-")\ |
| 2224 | DEF_ENC32(S4_subi_##TAG##_ri,ICLASS_ALU64" 1110 iiixxxxx PPiIIIII iii"OPB"i11-") |
| 2225 | |
| 2226 | OP_OPI_RI(asl,"0") |
| 2227 | OP_OPI_RI(lsr,"1") |
| 2228 | |
| 2229 | |
| 2230 | DEF_FIELDROW_DESC32(ICLASS_ALU64" 1111 -------- PP------ --------","[#15] Rd=(Rs,Ru,#u6:2)") |
| 2231 | DEF_ENC32(M4_mpyri_addr_u2, ICLASS_ALU64" 1111 0ii sssss PPiddddd iiiuuuuu") |
| 2232 | DEF_ENC32(M4_mpyri_addr, ICLASS_ALU64" 1111 1ii sssss PPiddddd iiiuuuuu") |