| 1 | /* |
| 2 | * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | /* |
| 19 | * For registers that have individual fields, explain them here |
| 20 | * DEF_REG_FIELD(tag, |
| 21 | * bit start offset, |
| 22 | * width |
| 23 | */ |
| 24 | |
| 25 | /* USR fields */ |
| 26 | DEF_REG_FIELD(USR_OVF, 0, 1) |
| 27 | DEF_REG_FIELD(USR_FPINVF, 1, 1) |
| 28 | DEF_REG_FIELD(USR_FPDBZF, 2, 1) |
| 29 | DEF_REG_FIELD(USR_FPOVFF, 3, 1) |
| 30 | DEF_REG_FIELD(USR_FPUNFF, 4, 1) |
| 31 | DEF_REG_FIELD(USR_FPINPF, 5, 1) |
| 32 | |
| 33 | DEF_REG_FIELD(USR_LPCFG, 8, 2) |
| 34 | |
| 35 | DEF_REG_FIELD(USR_FPRND, 22, 2) |
| 36 | |
| 37 | DEF_REG_FIELD(USR_FPINVE, 25, 1) |
| 38 | DEF_REG_FIELD(USR_FPDBZE, 26, 1) |
| 39 | DEF_REG_FIELD(USR_FPOVFE, 27, 1) |
| 40 | DEF_REG_FIELD(USR_FPUNFE, 28, 1) |
| 41 | DEF_REG_FIELD(USR_FPINPE, 29, 1) |
| 42 | |
| 43 | DEF_REG_FIELD(IPENDAD_IAD, 16, 16) |
| 44 | DEF_REG_FIELD(IPENDAD_IPEND, 0, 16) |
| 45 | |
| 46 | DEF_REG_FIELD(SCHEDCFG_EN, 8, 1) |
| 47 | DEF_REG_FIELD(SCHEDCFG_INTNO, 0, 4) |
| 48 | DEF_REG_FIELD(BESTWAIT_PRIO, 0, 9) |
| 49 | |
| 50 | |
| 51 | /* PTE (aka TLB entry) fields */ |
| 52 | DEF_REG_FIELD(PTE_PPD, 0, 24) |
| 53 | DEF_REG_FIELD(PTE_C, 24, 4) |
| 54 | DEF_REG_FIELD(PTE_U, 28, 1) |
| 55 | DEF_REG_FIELD(PTE_R, 29, 1) |
| 56 | DEF_REG_FIELD(PTE_W, 30, 1) |
| 57 | DEF_REG_FIELD(PTE_X, 31, 1) |
| 58 | DEF_REG_FIELD(PTE_VPN, 32, 20) |
| 59 | DEF_REG_FIELD(PTE_ASID, 52, 7) |
| 60 | DEF_REG_FIELD(PTE_ATR0, 59, 1) |
| 61 | DEF_REG_FIELD(PTE_ATR1, 60, 1) |
| 62 | DEF_REG_FIELD(PTE_PA35, 61, 1) |
| 63 | DEF_REG_FIELD(PTE_G, 62, 1) |
| 64 | DEF_REG_FIELD(PTE_V, 63, 1) |
| 65 | |
| 66 | /* SYSCFG fields */ |
| 67 | DEF_REG_FIELD(SYSCFG_MMUEN, 0, 1) |
| 68 | DEF_REG_FIELD(SYSCFG_ICEN, 1, 1) |
| 69 | DEF_REG_FIELD(SYSCFG_DCEN, 2, 1) |
| 70 | DEF_REG_FIELD(SYSCFG_ISDBTRUSTED, 3, 1) |
| 71 | DEF_REG_FIELD(SYSCFG_GIE, 4, 1) |
| 72 | DEF_REG_FIELD(SYSCFG_ISDBREADY, 5, 1) |
| 73 | DEF_REG_FIELD(SYSCFG_PCYCLEEN, 6, 1) |
| 74 | DEF_REG_FIELD(SYSCFG_V2X, 7, 1) |
| 75 | DEF_REG_FIELD(SYSCFG_IGNOREDABORT, 8, 1) |
| 76 | DEF_REG_FIELD(SYSCFG_PM, 9, 1) |
| 77 | DEF_REG_FIELD(SYSCFG_TLBLOCK, 11, 1) |
| 78 | DEF_REG_FIELD(SYSCFG_K0LOCK, 12, 1) |
| 79 | DEF_REG_FIELD(SYSCFG_BQ, 13, 1) |
| 80 | DEF_REG_FIELD(SYSCFG_PRIO, 14, 1) |
| 81 | DEF_REG_FIELD(SYSCFG_DMT, 15, 1) |
| 82 | DEF_REG_FIELD(SYSCFG_L2CFG, 16, 3) |
| 83 | DEF_REG_FIELD(SYSCFG_ITCM, 19, 1) |
| 84 | DEF_REG_FIELD(SYSCFG_L2NWA, 21, 1) |
| 85 | DEF_REG_FIELD(SYSCFG_L2NRA, 22, 1) |
| 86 | DEF_REG_FIELD(SYSCFG_L2WB, 23, 1) |
| 87 | DEF_REG_FIELD(SYSCFG_L2P, 24, 1) |
| 88 | DEF_REG_FIELD(SYSCFG_SLVCTL0, 25, 2) |
| 89 | DEF_REG_FIELD(SYSCFG_SLVCTL1, 27, 2) |
| 90 | DEF_REG_FIELD(SYSCFG_L2PARTSIZE, 29, 2) |
| 91 | DEF_REG_FIELD(SYSCFG_L2GCA, 31, 1) |
| 92 | |
| 93 | /* SSR fields */ |
| 94 | DEF_REG_FIELD(SSR_CAUSE, 0, 8) |
| 95 | DEF_REG_FIELD(SSR_ASID, 8, 7) |
| 96 | DEF_REG_FIELD(SSR_UM, 16, 1) |
| 97 | DEF_REG_FIELD(SSR_EX, 17, 1) |
| 98 | DEF_REG_FIELD(SSR_IE, 18, 1) |
| 99 | DEF_REG_FIELD(SSR_GM, 19, 1) |
| 100 | DEF_REG_FIELD(SSR_V0, 20, 1) |
| 101 | DEF_REG_FIELD(SSR_V1, 21, 1) |
| 102 | DEF_REG_FIELD(SSR_BVS, 22, 1) |
| 103 | DEF_REG_FIELD(SSR_CE, 23, 1) |
| 104 | DEF_REG_FIELD(SSR_PE, 24, 1) |
| 105 | DEF_REG_FIELD(SSR_BP, 25, 1) |
| 106 | DEF_REG_FIELD(SSR_XE2, 26, 1) |
| 107 | DEF_REG_FIELD(SSR_XA, 27, 3) |
| 108 | DEF_REG_FIELD(SSR_SS, 30, 1) |
| 109 | DEF_REG_FIELD(SSR_XE, 31, 1) |
| 110 | |
| 111 | /* misc registers */ |
| 112 | DEF_REG_FIELD(IMASK_MASK, 0, 16) |
| 113 | |
| 114 | DEF_REG_FIELD(STID_PRIO, 16, 8) |
| 115 | DEF_REG_FIELD(STID_STID, 0, 8) |
| 116 | |
| 117 | /* MODECTL fields */ |
| 118 | DEF_REG_FIELD(MODECTL_E, 0, 8) |
| 119 | DEF_REG_FIELD(MODECTL_W, 16, 8) |
| 120 | |
| 121 | DEF_REG_FIELD(CCR_L1ICP, 0, 2) |
| 122 | DEF_REG_FIELD(CCR_L1DCP, 3, 2) |
| 123 | DEF_REG_FIELD(CCR_L2CP, 6, 2) |
| 124 | |
| 125 | DEF_REG_FIELD(CCR_HFI, 16, 1) |
| 126 | DEF_REG_FIELD(CCR_HFD, 17, 1) |
| 127 | DEF_REG_FIELD(CCR_HFIL2, 18, 1) |
| 128 | DEF_REG_FIELD(CCR_HFDL2, 19, 1) |
| 129 | DEF_REG_FIELD(CCR_SFD, 20, 1) |
| 130 | |
| 131 | DEF_REG_FIELD(CCR_GIE, 24, 1) |
| 132 | DEF_REG_FIELD(CCR_GTE, 25, 1) |
| 133 | DEF_REG_FIELD(CCR_GEE, 26, 1) |
| 134 | DEF_REG_FIELD(CCR_GRE, 27, 1) |
| 135 | DEF_REG_FIELD(CCR_VV1, 29, 1) |
| 136 | DEF_REG_FIELD(CCR_VV2, 30, 1) |
| 137 | DEF_REG_FIELD(CCR_VV3, 31, 1) |
| 138 | |
| 139 | /* ISDB ST fields */ |
| 140 | DEF_REG_FIELD(ISDBST_WAITRUN, 24, 8) |
| 141 | DEF_REG_FIELD(ISDBST_ONOFF, 16, 8) |
| 142 | DEF_REG_FIELD(ISDBST_DEBUGMODE, 8, 8) |
| 143 | DEF_REG_FIELD(ISDBST_STUFFSTATUS, 5, 1) |
| 144 | DEF_REG_FIELD(ISDBST_CMDSTATUS, 4, 1) |
| 145 | DEF_REG_FIELD(ISDBST_PROCMODE, 3, 1) |
| 146 | DEF_REG_FIELD(ISDBST_MBXINSTATUS, 2, 1) |
| 147 | DEF_REG_FIELD(ISDBST_MBXOUTSTATUS, 1, 1) |
| 148 | DEF_REG_FIELD(ISDBST_READY, 0, 1) |