| 1 | /* |
| 2 | * QEMU HPPA CPU |
| 3 | * |
| 4 | * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see |
| 18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qapi/error.h" |
| 23 | #include "qemu/qemu-print.h" |
| 24 | #include "qemu/timer.h" |
| 25 | #include "cpu.h" |
| 26 | #include "qemu/module.h" |
| 27 | #include "exec/translation-block.h" |
| 28 | #include "exec/target_page.h" |
| 29 | #include "fpu/softfloat.h" |
| 30 | #include "tcg/tcg.h" |
| 31 | #include "hw/hppa/hppa_hardware.h" |
| 32 | #include "accel/tcg/cpu-loop.h" |
| 33 | #include "accel/tcg/cpu-ops.h" |
| 34 | |
| 35 | static void hppa_cpu_set_pc(CPUState *cs, vaddr value) |
| 36 | { |
| 37 | HPPACPU *cpu = HPPA_CPU(cs); |
| 38 | |
| 39 | #ifdef CONFIG_USER_ONLY |
| 40 | value |= PRIV_USER; |
| 41 | #endif |
| 42 | cpu->env.iaoq_f = value; |
| 43 | cpu->env.iaoq_b = value + 4; |
| 44 | } |
| 45 | |
| 46 | static vaddr hppa_cpu_get_pc(CPUState *cs) |
| 47 | { |
| 48 | CPUHPPAState *env = cpu_env(cs); |
| 49 | |
| 50 | return hppa_form_gva_mask(env->gva_offset_mask, |
| 51 | (env->psw & PSW_C ? env->iasq_f : 0), |
| 52 | env->iaoq_f & -4); |
| 53 | } |
| 54 | |
| 55 | static TCGTBCPUState hppa_get_tb_cpu_state(CPUState *cs) |
| 56 | { |
| 57 | CPUHPPAState *env = cpu_env(cs); |
| 58 | uint32_t flags = 0; |
| 59 | uint64_t cs_base = 0; |
| 60 | vaddr pc; |
| 61 | |
| 62 | /* |
| 63 | * TB lookup assumes that PC contains the complete virtual address. |
| 64 | * If we leave space+offset separate, we'll get ITLB misses to an |
| 65 | * incomplete virtual address. This also means that we must separate |
| 66 | * out current cpu privilege from the low bits of IAOQ_F. |
| 67 | */ |
| 68 | pc = hppa_cpu_get_pc(env_cpu(env)); |
| 69 | flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; |
| 70 | |
| 71 | /* |
| 72 | * The only really interesting case is if IAQ_Back is on the same page |
| 73 | * as IAQ_Front, so that we can use goto_tb between the blocks. In all |
| 74 | * other cases, we'll be ending the TranslationBlock with one insn and |
| 75 | * not linking between them. |
| 76 | */ |
| 77 | if (env->iasq_f != env->iasq_b) { |
| 78 | cs_base |= CS_BASE_DIFFSPACE; |
| 79 | } else if ((env->iaoq_f ^ env->iaoq_b) & TARGET_PAGE_MASK) { |
| 80 | cs_base |= CS_BASE_DIFFPAGE; |
| 81 | } else { |
| 82 | cs_base |= env->iaoq_b & ~TARGET_PAGE_MASK; |
| 83 | } |
| 84 | |
| 85 | /* ??? E, T, H, L bits need to be here, when implemented. */ |
| 86 | flags |= env->psw_n * PSW_N; |
| 87 | flags |= env->psw_xb; |
| 88 | flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); |
| 89 | |
| 90 | #ifdef CONFIG_USER_ONLY |
| 91 | flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; |
| 92 | #else |
| 93 | if ((env->sr[4] == env->sr[5]) |
| 94 | & (env->sr[4] == env->sr[6]) |
| 95 | & (env->sr[4] == env->sr[7])) { |
| 96 | flags |= TB_FLAG_SR_SAME; |
| 97 | } |
| 98 | if ((env->psw & PSW_W) && |
| 99 | (env->dr[2] & HPPA64_DIAG_SPHASH_ENABLE)) { |
| 100 | flags |= TB_FLAG_SPHASH; |
| 101 | } |
| 102 | #endif |
| 103 | |
| 104 | return (TCGTBCPUState){ .pc = pc, .flags = flags, .cs_base = cs_base }; |
| 105 | } |
| 106 | |
| 107 | static void hppa_cpu_synchronize_from_tb(CPUState *cs, |
| 108 | const TranslationBlock *tb) |
| 109 | { |
| 110 | HPPACPU *cpu = HPPA_CPU(cs); |
| 111 | |
| 112 | /* IAQ is always up-to-date before goto_tb. */ |
| 113 | cpu->env.psw_n = (tb->flags & PSW_N) != 0; |
| 114 | cpu->env.psw_xb = tb->flags & (PSW_X | PSW_B); |
| 115 | } |
| 116 | |
| 117 | static void hppa_restore_state_to_opc(CPUState *cs, |
| 118 | const TranslationBlock *tb, |
| 119 | const uint64_t *data) |
| 120 | { |
| 121 | CPUHPPAState *env = cpu_env(cs); |
| 122 | |
| 123 | env->iaoq_f = (env->iaoq_f & TARGET_PAGE_MASK) | data[0]; |
| 124 | if (data[1] != INT32_MIN) { |
| 125 | env->iaoq_b = env->iaoq_f + data[1]; |
| 126 | } |
| 127 | env->unwind_breg = data[2]; |
| 128 | /* |
| 129 | * Since we were executing the instruction at IAOQ_F, and took some |
| 130 | * sort of action that provoked the cpu_restore_state, we can infer |
| 131 | * that the instruction was not nullified. |
| 132 | */ |
| 133 | env->psw_n = 0; |
| 134 | } |
| 135 | |
| 136 | #ifndef CONFIG_USER_ONLY |
| 137 | static bool hppa_cpu_has_work(CPUState *cs) |
| 138 | { |
| 139 | return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); |
| 140 | } |
| 141 | #endif /* !CONFIG_USER_ONLY */ |
| 142 | |
| 143 | static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) |
| 144 | { |
| 145 | CPUHPPAState *env = cpu_env(cs); |
| 146 | |
| 147 | if (env->psw & (ifetch ? PSW_C : PSW_D)) { |
| 148 | return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); |
| 149 | } |
| 150 | /* mmu disabled */ |
| 151 | return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; |
| 152 | } |
| 153 | |
| 154 | static void hppa_cpu_disas_set_info(const CPUState *cs, disassemble_info *info) |
| 155 | { |
| 156 | info->mach = bfd_mach_hppa20; |
| 157 | info->endian = BFD_ENDIAN_BIG; |
| 158 | info->print_insn = print_insn_hppa; |
| 159 | } |
| 160 | |
| 161 | #ifndef CONFIG_USER_ONLY |
| 162 | static G_NORETURN |
| 163 | void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
| 164 | MMUAccessType access_type, int mmu_idx, |
| 165 | uintptr_t retaddr) |
| 166 | { |
| 167 | HPPACPU *cpu = HPPA_CPU(cs); |
| 168 | CPUHPPAState *env = &cpu->env; |
| 169 | |
| 170 | cs->exception_index = EXCP_UNALIGN; |
| 171 | cpu_restore_state(cs, retaddr); |
| 172 | hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); |
| 173 | |
| 174 | cpu_loop_exit(cs); |
| 175 | } |
| 176 | #endif /* CONFIG_USER_ONLY */ |
| 177 | |
| 178 | static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) |
| 179 | { |
| 180 | CPUState *cs = CPU(dev); |
| 181 | HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev); |
| 182 | Error *local_err = NULL; |
| 183 | |
| 184 | cpu_common_realize(cs, &local_err); |
| 185 | if (local_err != NULL) { |
| 186 | error_propagate(errp, local_err); |
| 187 | return; |
| 188 | } |
| 189 | |
| 190 | qemu_init_vcpu(cs); |
| 191 | acc->parent_realize(dev, errp); |
| 192 | |
| 193 | #ifndef CONFIG_USER_ONLY |
| 194 | { |
| 195 | HPPACPU *cpu = HPPA_CPU(cs); |
| 196 | |
| 197 | cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
| 198 | hppa_cpu_alarm_timer, cpu); |
| 199 | hppa_ptlbe(&cpu->env); |
| 200 | } |
| 201 | #endif |
| 202 | |
| 203 | /* Use pc-relative instructions always to simplify the translator. */ |
| 204 | tcg_cflags_set(cs, CF_PCREL); |
| 205 | } |
| 206 | |
| 207 | static void hppa_cpu_reset_hold(Object *obj, ResetType type) |
| 208 | { |
| 209 | HPPACPUClass *scc = HPPA_CPU_GET_CLASS(obj); |
| 210 | CPUState *cs = CPU(obj); |
| 211 | HPPACPU *cpu = HPPA_CPU(obj); |
| 212 | CPUHPPAState *env = &cpu->env; |
| 213 | |
| 214 | if (scc->parent_phases.hold) { |
| 215 | scc->parent_phases.hold(obj, type); |
| 216 | } |
| 217 | cs->exception_index = -1; |
| 218 | cs->halted = 0; |
| 219 | cpu_set_pc(cs, 0xf0000004); |
| 220 | |
| 221 | memset(env, 0, offsetof(CPUHPPAState, end_reset_fields)); |
| 222 | |
| 223 | cpu_hppa_loaded_fr0(env); |
| 224 | |
| 225 | /* 64-bit machines start with space-register hashing enabled in %dr2 */ |
| 226 | env->dr[2] = hppa_is_pa20(env) ? HPPA64_DIAG_SPHASH_ENABLE : 0; |
| 227 | |
| 228 | cpu_hppa_put_psw(env, PSW_M); |
| 229 | } |
| 230 | |
| 231 | static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) |
| 232 | { |
| 233 | ObjectClass *oc; |
| 234 | char *typename; |
| 235 | |
| 236 | typename = g_strdup_printf(HPPA_CPU_TYPE_NAME("%s"), cpu_model); |
| 237 | oc = object_class_by_name(typename); |
| 238 | g_free(typename); |
| 239 | |
| 240 | return oc; |
| 241 | } |
| 242 | |
| 243 | #ifndef CONFIG_USER_ONLY |
| 244 | #include "hw/core/sysemu-cpu-ops.h" |
| 245 | |
| 246 | static const struct SysemuCPUOps hppa_sysemu_ops = { |
| 247 | .has_work = hppa_cpu_has_work, |
| 248 | .get_phys_addr_debug = hppa_cpu_get_phys_addr_debug, |
| 249 | }; |
| 250 | #endif |
| 251 | |
| 252 | static const TCGCPUOps hppa_tcg_ops = { |
| 253 | /* PA-RISC 1.x processors have a strong memory model. */ |
| 254 | /* |
| 255 | * ??? While we do not yet implement PA-RISC 2.0, those processors have |
| 256 | * a weak memory model, but with TLB bits that force ordering on a per-page |
| 257 | * basis. It's probably easier to fall back to a strong memory model. |
| 258 | */ |
| 259 | .guest_default_memory_order = TCG_MO_ALL, |
| 260 | .mttcg_supported = true, |
| 261 | |
| 262 | .initialize = hppa_translate_init, |
| 263 | .translate_code = hppa_translate_code, |
| 264 | .get_tb_cpu_state = hppa_get_tb_cpu_state, |
| 265 | .synchronize_from_tb = hppa_cpu_synchronize_from_tb, |
| 266 | .restore_state_to_opc = hppa_restore_state_to_opc, |
| 267 | .mmu_index = hppa_cpu_mmu_index, |
| 268 | |
| 269 | #ifndef CONFIG_USER_ONLY |
| 270 | .tlb_fill_align = hppa_cpu_tlb_fill_align, |
| 271 | .pointer_wrap = cpu_pointer_wrap_notreached, |
| 272 | .cpu_exec_interrupt = hppa_cpu_exec_interrupt, |
| 273 | .cpu_exec_halt = hppa_cpu_has_work, |
| 274 | .cpu_exec_reset = cpu_reset, |
| 275 | .do_interrupt = hppa_cpu_do_interrupt, |
| 276 | .do_unaligned_access = hppa_cpu_do_unaligned_access, |
| 277 | .do_transaction_failed = hppa_cpu_do_transaction_failed, |
| 278 | #endif /* !CONFIG_USER_ONLY */ |
| 279 | }; |
| 280 | |
| 281 | static void hppa_cpu_class_base_init(ObjectClass *oc, const void *data) |
| 282 | { |
| 283 | HPPACPUClass *acc = HPPA_CPU_CLASS(oc); |
| 284 | /* Make sure all CPU models define a HPPACPUDef */ |
| 285 | g_assert(!object_class_is_abstract(oc) && data != NULL); |
| 286 | acc->def = data; |
| 287 | /* |
| 288 | * Verify assumptions made in hppa_abs_to_phys_pa2_w1() on the size |
| 289 | * of the physical address space. |
| 290 | */ |
| 291 | g_assert(acc->def->phys_addr_bits <= 54); |
| 292 | } |
| 293 | |
| 294 | static void hppa_cpu_class_init(ObjectClass *oc, const void *data) |
| 295 | { |
| 296 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 297 | CPUClass *cc = CPU_CLASS(oc); |
| 298 | HPPACPUClass *acc = HPPA_CPU_CLASS(oc); |
| 299 | ResettableClass *rc = RESETTABLE_CLASS(oc); |
| 300 | |
| 301 | device_class_set_parent_realize(dc, hppa_cpu_realizefn, |
| 302 | &acc->parent_realize); |
| 303 | |
| 304 | resettable_class_set_parent_phases(rc, NULL, hppa_cpu_reset_hold, NULL, |
| 305 | &acc->parent_phases); |
| 306 | |
| 307 | cc->class_by_name = hppa_cpu_class_by_name; |
| 308 | cc->dump_state = hppa_cpu_dump_state; |
| 309 | cc->set_pc = hppa_cpu_set_pc; |
| 310 | cc->get_pc = hppa_cpu_get_pc; |
| 311 | cc->gdb_read_register = hppa_cpu_gdb_read_register; |
| 312 | cc->gdb_write_register = hppa_cpu_gdb_write_register; |
| 313 | #ifndef CONFIG_USER_ONLY |
| 314 | dc->vmsd = &vmstate_hppa_cpu; |
| 315 | cc->sysemu_ops = &hppa_sysemu_ops; |
| 316 | #endif |
| 317 | cc->disas_set_info = hppa_cpu_disas_set_info; |
| 318 | cc->gdb_num_core_regs = 128; |
| 319 | cc->tcg_ops = &hppa_tcg_ops; |
| 320 | } |
| 321 | |
| 322 | static const TypeInfo hppa_cpu_type_infos[] = { |
| 323 | { |
| 324 | .name = TYPE_HPPA_CPU, |
| 325 | .parent = TYPE_CPU, |
| 326 | .instance_size = sizeof(HPPACPU), |
| 327 | .instance_align = __alignof(HPPACPU), |
| 328 | .abstract = true, |
| 329 | .class_size = sizeof(HPPACPUClass), |
| 330 | .class_init = hppa_cpu_class_init, |
| 331 | .class_base_init = hppa_cpu_class_base_init, |
| 332 | }, |
| 333 | { |
| 334 | .name = TYPE_HPPA_CPU_PA_7300LC, |
| 335 | .parent = TYPE_HPPA_CPU, |
| 336 | .class_data = &(const HPPACPUDef) { |
| 337 | .phys_addr_bits = 32, |
| 338 | .is_pa20 = false, |
| 339 | }, |
| 340 | }, |
| 341 | { |
| 342 | .name = TYPE_HPPA_CPU_PA_8500, |
| 343 | .parent = TYPE_HPPA_CPU, |
| 344 | .class_data = &(const HPPACPUDef) { |
| 345 | .phys_addr_bits = 40, |
| 346 | .is_pa20 = true, |
| 347 | }, |
| 348 | }, |
| 349 | { |
| 350 | .name = TYPE_HPPA_CPU_PA_8700, |
| 351 | .parent = TYPE_HPPA_CPU, |
| 352 | .class_data = &(const HPPACPUDef) { |
| 353 | .phys_addr_bits = 44, |
| 354 | .is_pa20 = true, |
| 355 | }, |
| 356 | }, |
| 357 | }; |
| 358 | |
| 359 | DEFINE_TYPES(hppa_cpu_type_infos) |