| 1 | /* |
| 2 | * PA-RISC emulation cpu definitions for qemu. |
| 3 | * |
| 4 | * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef HPPA_CPU_H |
| 21 | #define HPPA_CPU_H |
| 22 | |
| 23 | #include "cpu-qom.h" |
| 24 | #include "exec/cpu-common.h" |
| 25 | #include "exec/cpu-interrupt.h" |
| 26 | #include "exec/target_long.h" |
| 27 | #include "system/memory.h" |
| 28 | #include "qemu/cpu-float.h" |
| 29 | #include "qemu/interval-tree.h" |
| 30 | #include "hw/core/registerfields.h" |
| 31 | |
| 32 | #define MMU_KERNEL_IDX 0 |
| 33 | #define MMU_KERNEL_P_IDX 1 |
| 34 | #define MMU_PL1_IDX 2 |
| 35 | #define MMU_PL1_P_IDX 3 |
| 36 | #define MMU_PL2_IDX 4 |
| 37 | #define MMU_PL2_P_IDX 5 |
| 38 | #define MMU_USER_IDX 6 |
| 39 | #define MMU_USER_P_IDX 7 |
| 40 | #define MMU_ABS_IDX 8 |
| 41 | #define MMU_ABS_W_IDX 9 |
| 42 | |
| 43 | #define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) >= MMU_ABS_IDX) |
| 44 | #define MMU_IDX_TO_PRIV(MIDX) ((MIDX) / 2) |
| 45 | #define MMU_IDX_TO_P(MIDX) ((MIDX) & 1) |
| 46 | #define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P)) |
| 47 | |
| 48 | #define PRIV_KERNEL 0 |
| 49 | #define PRIV_USER 3 |
| 50 | |
| 51 | /* No need to flush MMU_ABS*_IDX */ |
| 52 | #define HPPA_MMU_FLUSH_MASK \ |
| 53 | (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \ |
| 54 | 1 << MMU_PL1_IDX | 1 << MMU_PL1_P_IDX | \ |
| 55 | 1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \ |
| 56 | 1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX) |
| 57 | |
| 58 | /* Indices to flush for access_id changes. */ |
| 59 | #define HPPA_MMU_FLUSH_P_MASK \ |
| 60 | (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \ |
| 61 | 1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX) |
| 62 | |
| 63 | /* Hardware exceptions, interrupts, faults, and traps. */ |
| 64 | #define EXCP_HPMC 1 /* high priority machine check */ |
| 65 | #define EXCP_POWER_FAIL 2 |
| 66 | #define EXCP_RC 3 /* recovery counter */ |
| 67 | #define EXCP_EXT_INTERRUPT 4 /* external interrupt */ |
| 68 | #define EXCP_LPMC 5 /* low priority machine check */ |
| 69 | #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ |
| 70 | #define EXCP_IMP 7 /* instruction memory protection trap */ |
| 71 | #define EXCP_ILL 8 /* illegal instruction trap */ |
| 72 | #define EXCP_BREAK 9 /* break instruction */ |
| 73 | #define EXCP_PRIV_OPR 10 /* privileged operation trap */ |
| 74 | #define EXCP_PRIV_REG 11 /* privileged register trap */ |
| 75 | #define EXCP_OVERFLOW 12 /* signed overflow trap */ |
| 76 | #define EXCP_COND 13 /* trap-on-condition */ |
| 77 | #define EXCP_ASSIST 14 /* assist exception trap */ |
| 78 | #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ |
| 79 | #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ |
| 80 | #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ |
| 81 | #define EXCP_DMP 18 /* data memory protection trap */ |
| 82 | #define EXCP_DMB 19 /* data memory break trap */ |
| 83 | #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ |
| 84 | #define EXCP_PAGE_REF 21 /* page reference trap */ |
| 85 | #define EXCP_ASSIST_EMU 22 /* assist emulation trap */ |
| 86 | #define EXCP_HPT 23 /* high-privilege transfer trap */ |
| 87 | #define EXCP_LPT 24 /* low-privilege transfer trap */ |
| 88 | #define EXCP_TB 25 /* taken branch trap */ |
| 89 | #define EXCP_DMAR 26 /* data memory access rights trap */ |
| 90 | #define EXCP_DMPI 27 /* data memory protection id trap */ |
| 91 | #define EXCP_UNALIGN 28 /* unaligned data reference trap */ |
| 92 | #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ |
| 93 | |
| 94 | /* Exceptions for linux-user emulation. */ |
| 95 | #define EXCP_SYSCALL 30 |
| 96 | #define EXCP_SYSCALL_LWS 31 |
| 97 | |
| 98 | /* Emulated hardware TOC button */ |
| 99 | #define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */ |
| 100 | |
| 101 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */ |
| 102 | |
| 103 | /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ |
| 104 | #define PSW_I 0x00000001 |
| 105 | #define PSW_D 0x00000002 |
| 106 | #define PSW_P 0x00000004 |
| 107 | #define PSW_Q 0x00000008 |
| 108 | #define PSW_R 0x00000010 |
| 109 | #define PSW_F 0x00000020 |
| 110 | #define PSW_G 0x00000040 /* PA1.x only */ |
| 111 | #define PSW_O 0x00000080 /* PA2.0 only */ |
| 112 | #define PSW_CB 0x0000ff00 |
| 113 | #define PSW_M 0x00010000 |
| 114 | #define PSW_V 0x00020000 |
| 115 | #define PSW_C 0x00040000 |
| 116 | #define PSW_B 0x00080000 |
| 117 | #define PSW_X 0x00100000 |
| 118 | #define PSW_N 0x00200000 |
| 119 | #define PSW_L 0x00400000 |
| 120 | #define PSW_H 0x00800000 |
| 121 | #define PSW_T 0x01000000 |
| 122 | #define PSW_S 0x02000000 |
| 123 | #define PSW_E 0x04000000 |
| 124 | #define PSW_W 0x08000000 /* PA2.0 only */ |
| 125 | #define PSW_Z 0x40000000 /* PA1.x only */ |
| 126 | #define PSW_Y 0x80000000 /* PA1.x only */ |
| 127 | |
| 128 | #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ |
| 129 | | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) |
| 130 | |
| 131 | /* ssm/rsm instructions number PSW_W and PSW_E differently */ |
| 132 | #define PSW_SM_I PSW_I /* Enable External Interrupts */ |
| 133 | #define PSW_SM_D PSW_D |
| 134 | #define PSW_SM_P PSW_P |
| 135 | #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ |
| 136 | #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ |
| 137 | #define PSW_SM_E 0x100 |
| 138 | #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ |
| 139 | |
| 140 | #define CR_RC 0 |
| 141 | #define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */ |
| 142 | #define PDC_PSW_WIDE_BIT 2 |
| 143 | #define CR_PID1 8 |
| 144 | #define CR_PID2 9 |
| 145 | #define CR_PID3 12 |
| 146 | #define CR_PID4 13 |
| 147 | #define CR_SCRCCR 10 |
| 148 | #define CR_SAR 11 |
| 149 | #define CR_IVA 14 |
| 150 | #define CR_EIEM 15 |
| 151 | #define CR_IT 16 |
| 152 | #define CR_IIASQ 17 |
| 153 | #define CR_IIAOQ 18 |
| 154 | #define CR_IIR 19 |
| 155 | #define CR_ISR 20 |
| 156 | #define CR_IOR 21 |
| 157 | #define CR_IPSW 22 |
| 158 | #define CR_EIRR 23 |
| 159 | |
| 160 | FIELD(FPSR, ENA_I, 0, 1) |
| 161 | FIELD(FPSR, ENA_U, 1, 1) |
| 162 | FIELD(FPSR, ENA_O, 2, 1) |
| 163 | FIELD(FPSR, ENA_Z, 3, 1) |
| 164 | FIELD(FPSR, ENA_V, 4, 1) |
| 165 | FIELD(FPSR, ENABLES, 0, 5) |
| 166 | FIELD(FPSR, D, 5, 1) |
| 167 | FIELD(FPSR, T, 6, 1) |
| 168 | FIELD(FPSR, RM, 9, 2) |
| 169 | FIELD(FPSR, CQ, 11, 11) |
| 170 | FIELD(FPSR, CQ0_6, 15, 7) |
| 171 | FIELD(FPSR, CQ0_4, 17, 5) |
| 172 | FIELD(FPSR, CQ0_2, 19, 3) |
| 173 | FIELD(FPSR, CQ0, 21, 1) |
| 174 | FIELD(FPSR, CA, 15, 7) |
| 175 | FIELD(FPSR, CA0, 21, 1) |
| 176 | FIELD(FPSR, C, 26, 1) |
| 177 | FIELD(FPSR, FLG_I, 27, 1) |
| 178 | FIELD(FPSR, FLG_U, 28, 1) |
| 179 | FIELD(FPSR, FLG_O, 29, 1) |
| 180 | FIELD(FPSR, FLG_Z, 30, 1) |
| 181 | FIELD(FPSR, FLG_V, 31, 1) |
| 182 | FIELD(FPSR, FLAGS, 27, 5) |
| 183 | |
| 184 | typedef struct HPPATLBEntry { |
| 185 | union { |
| 186 | IntervalTreeNode itree; |
| 187 | struct HPPATLBEntry *unused_next; |
| 188 | }; |
| 189 | |
| 190 | hwaddr pa; |
| 191 | |
| 192 | unsigned entry_valid : 1; |
| 193 | |
| 194 | unsigned u : 1; |
| 195 | unsigned t : 1; |
| 196 | unsigned d : 1; |
| 197 | unsigned b : 1; |
| 198 | unsigned ar_type : 3; |
| 199 | unsigned ar_pl1 : 2; |
| 200 | unsigned ar_pl2 : 2; |
| 201 | unsigned access_id : 16; |
| 202 | } HPPATLBEntry; |
| 203 | |
| 204 | typedef struct CPUArchState { |
| 205 | target_ulong iaoq_f; /* front */ |
| 206 | target_ulong iaoq_b; /* back, aka next instruction */ |
| 207 | |
| 208 | target_ulong gr[32]; |
| 209 | uint64_t fr[32]; |
| 210 | uint64_t sr[8]; /* stored shifted into place for gva */ |
| 211 | |
| 212 | uint32_t psw; /* All psw bits except the following: */ |
| 213 | uint32_t psw_xb; /* X and B, in their normal positions */ |
| 214 | target_ulong psw_n; /* boolean */ |
| 215 | target_long psw_v; /* in bit 31 */ |
| 216 | |
| 217 | /* Splitting the carry-borrow field into the MSB and "the rest", allows |
| 218 | * for "the rest" to be deleted when it is unused, but the MSB is in use. |
| 219 | * In addition, it's easier to compute carry-in for bit B+1 than it is to |
| 220 | * compute carry-out for bit B (3 vs 4 insns for addition, assuming the |
| 221 | * host has the appropriate add-with-carry insn to compute the msb). |
| 222 | * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. |
| 223 | */ |
| 224 | target_ulong psw_cb; /* in least significant bit of next nibble */ |
| 225 | target_ulong psw_cb_msb; /* boolean */ |
| 226 | |
| 227 | uint64_t gva_offset_mask; /* cached address mask based on PSW and %dr2 */ |
| 228 | uint64_t iasq_f; |
| 229 | uint64_t iasq_b; |
| 230 | |
| 231 | uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ |
| 232 | float_status fp_status; |
| 233 | |
| 234 | target_ulong cr[32]; /* control registers */ |
| 235 | target_ulong cr_back[2]; /* back of cr17/cr18 */ |
| 236 | target_ulong shadow[7]; /* shadow registers */ |
| 237 | target_ulong dr[32]; /* diagnose registers */ |
| 238 | |
| 239 | /* |
| 240 | * During unwind of a memory insn, the base register of the address. |
| 241 | * This is used to construct CR_IOR for pa2.0. |
| 242 | */ |
| 243 | uint32_t unwind_breg; |
| 244 | |
| 245 | /* |
| 246 | * ??? The number of entries isn't specified by the architecture. |
| 247 | * BTLBs are not supported in 64-bit machines. |
| 248 | */ |
| 249 | #define PA10_BTLB_FIXED 16 |
| 250 | #define PA10_BTLB_VARIABLE 0 |
| 251 | #define HPPA_TLB_ENTRIES 256 |
| 252 | |
| 253 | /* Index for round-robin tlb eviction. */ |
| 254 | uint32_t tlb_last; |
| 255 | |
| 256 | /* |
| 257 | * For pa1.x, the partial initialized, still invalid tlb entry |
| 258 | * which has had ITLBA performed, but not yet ITLBP. |
| 259 | */ |
| 260 | HPPATLBEntry *tlb_partial; |
| 261 | |
| 262 | /* Linked list of all invalid (unused) tlb entries. */ |
| 263 | HPPATLBEntry *tlb_unused; |
| 264 | |
| 265 | /* Root of the search tree for all valid tlb entries. */ |
| 266 | IntervalTreeRoot tlb_root; |
| 267 | |
| 268 | HPPATLBEntry tlb[HPPA_TLB_ENTRIES]; |
| 269 | |
| 270 | /* Fields up to this point are cleared by a CPU reset */ |
| 271 | struct {} end_reset_fields; |
| 272 | |
| 273 | target_ulong kernel_entry; /* Linux kernel was loaded here */ |
| 274 | target_ulong cmdline_or_bootorder; |
| 275 | target_ulong initrd_base, initrd_end; |
| 276 | } CPUHPPAState; |
| 277 | |
| 278 | /** |
| 279 | * HPPACPU: |
| 280 | * @env: #CPUHPPAState |
| 281 | * |
| 282 | * An HPPA CPU. |
| 283 | */ |
| 284 | struct ArchCPU { |
| 285 | CPUState parent_obj; |
| 286 | |
| 287 | CPUHPPAState env; |
| 288 | QEMUTimer *alarm_timer; |
| 289 | }; |
| 290 | |
| 291 | /** |
| 292 | * HPPACPUDef: |
| 293 | * @phys_addr_bits: Number of bits in the physical address space. |
| 294 | * @is_pa20: Whether the CPU model follows the PA-RISC 2.0 or 1.1 spec. |
| 295 | * |
| 296 | * Configuration options for a HPPA CPU model. |
| 297 | */ |
| 298 | typedef struct HPPACPUDef { |
| 299 | uint8_t phys_addr_bits; |
| 300 | bool is_pa20; |
| 301 | } HPPACPUDef; |
| 302 | |
| 303 | /** |
| 304 | * HPPACPUClass: |
| 305 | * @parent_realize: The parent class' realize handler. |
| 306 | * @parent_phases: The parent class' reset phase handlers. |
| 307 | * |
| 308 | * An HPPA CPU model. |
| 309 | */ |
| 310 | struct HPPACPUClass { |
| 311 | CPUClass parent_class; |
| 312 | |
| 313 | DeviceRealize parent_realize; |
| 314 | ResettablePhases parent_phases; |
| 315 | const HPPACPUDef *def; |
| 316 | }; |
| 317 | |
| 318 | static inline const HPPACPUDef *hppa_def(CPUHPPAState *env) |
| 319 | { |
| 320 | return HPPA_CPU_GET_CLASS(env_cpu(env))->def; |
| 321 | } |
| 322 | |
| 323 | static inline uint8_t hppa_phys_addr_bits(CPUHPPAState *env) |
| 324 | { |
| 325 | return hppa_def(env)->phys_addr_bits; |
| 326 | } |
| 327 | |
| 328 | static inline bool hppa_is_pa20(CPUHPPAState *env) |
| 329 | { |
| 330 | return hppa_def(env)->is_pa20; |
| 331 | } |
| 332 | |
| 333 | static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) |
| 334 | { |
| 335 | return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; |
| 336 | } |
| 337 | |
| 338 | void hppa_translate_init(void); |
| 339 | void hppa_translate_code(CPUState *cs, TranslationBlock *tb, |
| 340 | int *max_insns, vaddr pc, void *host_pc); |
| 341 | |
| 342 | #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU |
| 343 | |
| 344 | static inline vaddr hppa_form_gva_mask(uint64_t gva_offset_mask, |
| 345 | uint64_t spc, target_ulong off) |
| 346 | { |
| 347 | #ifdef CONFIG_USER_ONLY |
| 348 | return off & gva_offset_mask; |
| 349 | #else |
| 350 | return spc | (off & gva_offset_mask); |
| 351 | #endif |
| 352 | } |
| 353 | |
| 354 | static inline vaddr hppa_form_gva(CPUHPPAState *env, uint64_t spc, |
| 355 | target_ulong off) |
| 356 | { |
| 357 | return hppa_form_gva_mask(env->gva_offset_mask, spc, off); |
| 358 | } |
| 359 | |
| 360 | hwaddr hppa_abs_to_phys_pa1x(uint8_t phys_addr_bits, vaddr addr); |
| 361 | hwaddr hppa_abs_to_phys_pa2_w0(uint8_t phys_addr_bits, vaddr addr); |
| 362 | hwaddr hppa_abs_to_phys_pa2_w1(uint8_t phys_addr_bits, vaddr addr); |
| 363 | |
| 364 | /* |
| 365 | * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. |
| 366 | * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the |
| 367 | * same value. |
| 368 | */ |
| 369 | #define TB_FLAG_SR_SAME PSW_I |
| 370 | #define TB_FLAG_PRIV_SHIFT 8 |
| 371 | #define TB_FLAG_UNALIGN 0x400 |
| 372 | #define TB_FLAG_SPHASH 0x800 |
| 373 | #define CS_BASE_DIFFPAGE (1 << 12) |
| 374 | #define CS_BASE_DIFFSPACE (1 << 13) |
| 375 | |
| 376 | target_ulong cpu_hppa_get_psw(CPUHPPAState *env); |
| 377 | void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); |
| 378 | void update_gva_offset_mask(CPUHPPAState *env); |
| 379 | void cpu_hppa_loaded_fr0(CPUHPPAState *env); |
| 380 | |
| 381 | #ifdef CONFIG_USER_ONLY |
| 382 | static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } |
| 383 | #else |
| 384 | void cpu_hppa_change_prot_id(CPUHPPAState *env); |
| 385 | #endif |
| 386 | |
| 387 | int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
| 388 | int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
| 389 | void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); |
| 390 | #ifndef CONFIG_USER_ONLY |
| 391 | void hppa_ptlbe(CPUHPPAState *env); |
| 392 | hwaddr hppa_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr); |
| 393 | void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled); |
| 394 | bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, |
| 395 | MMUAccessType access_type, int mmu_idx, |
| 396 | MemOp memop, int size, bool probe, uintptr_t ra); |
| 397 | void hppa_cpu_do_interrupt(CPUState *cpu); |
| 398 | bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); |
| 399 | int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, |
| 400 | int type, MemOp mop, hwaddr *pphys, int *pprot); |
| 401 | void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
| 402 | vaddr addr, unsigned size, |
| 403 | MMUAccessType access_type, |
| 404 | int mmu_idx, MemTxAttrs attrs, |
| 405 | MemTxResult response, uintptr_t retaddr); |
| 406 | extern const MemoryRegionOps hppa_io_eir_ops; |
| 407 | extern const VMStateDescription vmstate_hppa_cpu; |
| 408 | void hppa_cpu_alarm_timer(void *); |
| 409 | #endif |
| 410 | G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); |
| 411 | |
| 412 | #endif /* HPPA_CPU_H */ |