| 1 | # |
| 2 | # HPPA instruction decode definitions. |
| 3 | # |
| 4 | # Copyright (c) 2018 Richard Henderson <rth@twiddle.net> |
| 5 | # |
| 6 | # This library is free software; you can redistribute it and/or |
| 7 | # modify it under the terms of the GNU Lesser General Public |
| 8 | # License as published by the Free Software Foundation; either |
| 9 | # version 2.1 of the License, or (at your option) any later version. |
| 10 | # |
| 11 | # This library is distributed in the hope that it will be useful, |
| 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | # Lesser General Public License for more details. |
| 15 | # |
| 16 | # You should have received a copy of the GNU Lesser General Public |
| 17 | # License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | # |
| 19 | |
| 20 | #### |
| 21 | # Field definitions |
| 22 | #### |
| 23 | |
| 24 | %assemble_sr3 13:1 14:2 |
| 25 | %assemble_sr3x 13:1 14:2 !function=expand_sr3x |
| 26 | |
| 27 | %assemble_11a 4:12 0:1 !function=expand_11a |
| 28 | %assemble_12 0:s1 2:1 3:10 !function=expand_shl2 |
| 29 | %assemble_12a 3:13 0:1 !function=expand_12a |
| 30 | %assemble_16 0:16 !function=expand_16 |
| 31 | %assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 |
| 32 | %assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 |
| 33 | %assemble_sp 14:2 !function=sp0_if_wide |
| 34 | |
| 35 | %assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11 |
| 36 | |
| 37 | %lowsign_11 0:s1 1:10 |
| 38 | |
| 39 | %sm_imm 16:10 !function=expand_sm_imm |
| 40 | |
| 41 | %rm64 1:1 16:5 |
| 42 | %rt64 6:1 0:5 |
| 43 | %ra64 7:1 21:5 |
| 44 | %rb64 12:1 16:5 |
| 45 | %rc64 8:1 13:3 9:2 |
| 46 | %rc32 13:3 9:2 |
| 47 | |
| 48 | %im5_0 0:s1 1:4 |
| 49 | %im5_16 16:s1 17:4 |
| 50 | %len5 0:5 !function=assemble_6 |
| 51 | %len6_8 8:1 0:5 !function=assemble_6 |
| 52 | %len6_12 12:1 0:5 !function=assemble_6 |
| 53 | %cpos6_11 11:1 5:5 |
| 54 | %ma_to_m 5:1 13:1 !function=ma_to_m |
| 55 | %ma2_to_m 2:2 !function=ma_to_m |
| 56 | %pos_to_m 0:1 !function=pos_to_m |
| 57 | %neg_to_m 0:1 !function=neg_to_m |
| 58 | %a_to_m 2:1 !function=neg_to_m |
| 59 | %cmpbid_c 13:2 !function=cmpbid_c |
| 60 | %d_5 5:1 !function=pa20_d |
| 61 | %d_11 11:1 !function=pa20_d |
| 62 | %d_13 13:1 !function=pa20_d |
| 63 | |
| 64 | #### |
| 65 | # Argument set definitions |
| 66 | #### |
| 67 | |
| 68 | &empty |
| 69 | |
| 70 | # All insns that need to form a virtual address should use this set. |
| 71 | &ldst t b x disp sp m scale size |
| 72 | |
| 73 | &rr_cf_d t r cf d |
| 74 | &rrr t r1 r2 |
| 75 | &rrr_cf t r1 r2 cf |
| 76 | &rrr_cf_d t r1 r2 cf d |
| 77 | &rrr_sh t r1 r2 sh |
| 78 | &rrr_cf_d_sh t r1 r2 cf d sh |
| 79 | &rri t r i |
| 80 | &rri_cf t r i cf |
| 81 | &rri_cf_d t r i cf d |
| 82 | |
| 83 | &rrb_c_f disp n c f r1 r2 |
| 84 | &rrb_c_d_f disp n c d f r1 r2 |
| 85 | &rib_c_f disp n c f r i |
| 86 | &rib_c_d_f disp n c d f r i |
| 87 | |
| 88 | #### |
| 89 | # Format definitions |
| 90 | #### |
| 91 | |
| 92 | @rr_cf_d ...... r:5 ..... cf:4 ...... . t:5 &rr_cf_d d=%d_5 |
| 93 | @rrr ...... r2:5 r1:5 .... ....... t:5 &rrr |
| 94 | @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf |
| 95 | @rrr_cf_d ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d d=%d_5 |
| 96 | @rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh |
| 97 | @rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_d_sh d=%d_5 |
| 98 | @rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d_sh d=%d_5 sh=0 |
| 99 | @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 |
| 100 | @rri_cf_d ...... r:5 t:5 cf:4 . ........... \ |
| 101 | &rri_cf_d d=%d_11 i=%lowsign_11 |
| 102 | |
| 103 | @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ |
| 104 | &rrb_c_f disp=%assemble_12 |
| 105 | @rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \ |
| 106 | &rrb_c_d_f disp=%assemble_12 |
| 107 | @rib_cf ...... r:5 ..... c:3 ........... n:1 . \ |
| 108 | &rib_c_f disp=%assemble_12 i=%im5_16 |
| 109 | @rib_cdf ...... r:5 ..... c:3 ........... n:1 . \ |
| 110 | &rib_c_d_f disp=%assemble_12 i=%im5_16 |
| 111 | |
| 112 | #### |
| 113 | # System |
| 114 | #### |
| 115 | |
| 116 | break 000000 ----- ----- --- 00000000 ----- |
| 117 | |
| 118 | mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3 |
| 119 | mtctl 000000 t:5 r:5 --- 11000010 00000 |
| 120 | mtsarcm 000000 01011 r:5 --- 11000110 00000 |
| 121 | mtsm 000000 00000 r:5 000 11000011 00000 |
| 122 | |
| 123 | mfia 000000 ----- 00000 --- 10100101 t:5 |
| 124 | mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3 |
| 125 | mfctl 000000 r:5 00000- e:1 -01000101 t:5 |
| 126 | |
| 127 | sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma |
| 128 | |
| 129 | ldsid 000000 b:5 ----- sp:2 0 10000101 t:5 |
| 130 | |
| 131 | rsm 000000 .......... 000 01110011 t:5 i=%sm_imm |
| 132 | ssm 000000 .......... 000 01101011 t:5 i=%sm_imm |
| 133 | |
| 134 | rfi 000000 ----- ----- --- 01100000 00000 |
| 135 | rfi_r 000000 ----- ----- --- 01100101 00000 |
| 136 | |
| 137 | # These are artificial instructions used by QEMU firmware. |
| 138 | # They are allocated from the unassigned instruction space. |
| 139 | halt 1111 1111 1111 1101 1110 1010 1101 0000 |
| 140 | reset 1111 1111 1111 1101 1110 1010 1101 0001 |
| 141 | getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010 |
| 142 | |
| 143 | #### |
| 144 | # Memory Management |
| 145 | #### |
| 146 | |
| 147 | @addrx ...... b:5 x:5 .. ........ m:1 ..... \ |
| 148 | &ldst disp=0 scale=0 t=0 sp=0 size=0 |
| 149 | |
| 150 | nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp |
| 151 | nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index |
| 152 | nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce |
| 153 | fic 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a |
| 154 | fic 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f |
| 155 | fic 000001 ..... ..... --- 0001011 . ----- @addrx # fice |
| 156 | nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc |
| 157 | |
| 158 | probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5 |
| 159 | |
| 160 | # pa1.x tlb insert instructions |
| 161 | ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 |
| 162 | ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ |
| 163 | sp=%assemble_sr3x data=0 |
| 164 | |
| 165 | # pcxl and pcxl2 Fast TLB Insert instructions |
| 166 | ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 |
| 167 | # workaround for non-standard encoding as used in HP-UX 9 |
| 168 | ixtlbxf 000001 01001 r:5 01 0 data:1 01000 addr:1 0 00000 |
| 169 | |
| 170 | # pa2.0 tlb insert idtlbt and iitlbt instructions |
| 171 | ixtlbt 000001 r2:5 r1:5 000 data:1 100000 0 00000 # idtlbt |
| 172 | |
| 173 | # pdtlb, pitlb |
| 174 | pxtlb 000001 b:5 x:5 sp:2 01001000 m:1 ----- \ |
| 175 | &ldst disp=0 scale=0 size=0 t=0 |
| 176 | pxtlb 000001 b:5 x:5 ... 0001000 m:1 ----- \ |
| 177 | &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x |
| 178 | |
| 179 | # ... pa20 local |
| 180 | pxtlb_l 000001 b:5 x:5 sp:2 01011000 m:1 ----- \ |
| 181 | &ldst disp=0 scale=0 size=0 t=0 |
| 182 | pxtlb_l 000001 b:5 x:5 ... 0011000 m:1 ----- \ |
| 183 | &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x |
| 184 | |
| 185 | # pdtlbe, pitlbe |
| 186 | pxtlbe 000001 b:5 x:5 sp:2 01001001 m:1 ----- \ |
| 187 | &ldst disp=0 scale=0 size=0 t=0 |
| 188 | pxtlbe 000001 b:5 x:5 ... 0001001 m:1 ----- \ |
| 189 | &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x |
| 190 | |
| 191 | lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \ |
| 192 | &ldst disp=0 scale=0 size=0 |
| 193 | |
| 194 | lci 000001 ----- ----- -- 01001100 0 t:5 |
| 195 | |
| 196 | #### |
| 197 | # Arith/Log |
| 198 | #### |
| 199 | |
| 200 | andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d |
| 201 | and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d |
| 202 | or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d |
| 203 | xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d |
| 204 | uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d |
| 205 | ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf |
| 206 | cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d |
| 207 | uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d |
| 208 | uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d |
| 209 | dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d |
| 210 | dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d |
| 211 | |
| 212 | add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh |
| 213 | add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh |
| 214 | add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh |
| 215 | { |
| 216 | add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 |
| 217 | hshladd 000010 ..... ..... 0000 0111.. 0 ..... @rrr_sh |
| 218 | } |
| 219 | add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 |
| 220 | |
| 221 | sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d |
| 222 | sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d |
| 223 | sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d |
| 224 | sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d |
| 225 | { |
| 226 | sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d |
| 227 | hshradd 000010 ..... ..... 0000 0101.. 0 ..... @rrr_sh |
| 228 | } |
| 229 | sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d |
| 230 | |
| 231 | ldil 001000 t:5 ..................... i=%assemble_21 |
| 232 | addil 001010 r:5 ..................... i=%assemble_21 |
| 233 | ldo 001101 b:5 t:5 ................ i=%assemble_16 |
| 234 | |
| 235 | addi 101101 ..... ..... .... 0 ........... @rri_cf |
| 236 | addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf |
| 237 | addi_tc 101100 ..... ..... .... 0 ........... @rri_cf |
| 238 | addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf |
| 239 | |
| 240 | subi 100101 ..... ..... .... 0 ........... @rri_cf |
| 241 | subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf |
| 242 | |
| 243 | cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d |
| 244 | |
| 245 | hadd 000010 ..... ..... 00000011 11 0 ..... @rrr |
| 246 | hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr |
| 247 | hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr |
| 248 | |
| 249 | havg 000010 ..... ..... 00000010 11 0 ..... @rrr |
| 250 | |
| 251 | hshl 111110 00000 r:5 100010 i:4 0 t:5 &rri |
| 252 | hshr_s 111110 r:5 00000 110011 i:4 0 t:5 &rri |
| 253 | hshr_u 111110 r:5 00000 110010 i:4 0 t:5 &rri |
| 254 | |
| 255 | hsub 000010 ..... ..... 00000001 11 0 ..... @rrr |
| 256 | hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr |
| 257 | hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr |
| 258 | |
| 259 | mixh_l 111110 ..... ..... 1 00 00100000 ..... @rrr |
| 260 | mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr |
| 261 | mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr |
| 262 | mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr |
| 263 | |
| 264 | permh 111110 r1:5 r2:5 0 c0:2 0 c1:2 c2:2 c3:2 0 t:5 |
| 265 | |
| 266 | #### |
| 267 | # Index Mem |
| 268 | #### |
| 269 | |
| 270 | @ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0 |
| 271 | @ldim5 ...... b:5 ..... sp:2 ......... t:5 \ |
| 272 | &ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m |
| 273 | @stim5 ...... b:5 t:5 sp:2 ......... ..... \ |
| 274 | &ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m |
| 275 | |
| 276 | ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5 |
| 277 | ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx |
| 278 | st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 |
| 279 | ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2 |
| 280 | ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2 |
| 281 | ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 size=3 |
| 282 | ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx size=3 |
| 283 | lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2 |
| 284 | lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2 |
| 285 | lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 size=3 |
| 286 | lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3 |
| 287 | sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2 |
| 288 | sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3 |
| 289 | stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0 |
| 290 | stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=%im5_0 |
| 291 | |
| 292 | @fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ |
| 293 | &ldst t=%rt64 disp=0 size=2 |
| 294 | @fldstwi ...... b:5 ..... sp:2 . ....... . ..... \ |
| 295 | &ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2 |
| 296 | |
| 297 | fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx |
| 298 | fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi |
| 299 | fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx |
| 300 | fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi |
| 301 | |
| 302 | @fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \ |
| 303 | &ldst disp=0 size=3 |
| 304 | @fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \ |
| 305 | &ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3 |
| 306 | |
| 307 | fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx |
| 308 | fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi |
| 309 | fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx |
| 310 | fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi |
| 311 | |
| 312 | #### |
| 313 | # Offset Mem |
| 314 | #### |
| 315 | |
| 316 | @ldstim11 ...... b:5 t:5 ................ \ |
| 317 | &ldst sp=%assemble_sp disp=%assemble_11a \ |
| 318 | m=%ma2_to_m x=0 scale=0 size=3 |
| 319 | @ldstim14 ...... b:5 t:5 ................ \ |
| 320 | &ldst sp=%assemble_sp disp=%assemble_16 \ |
| 321 | x=0 scale=0 m=0 |
| 322 | @ldstim14m ...... b:5 t:5 ................ \ |
| 323 | &ldst sp=%assemble_sp disp=%assemble_16 \ |
| 324 | x=0 scale=0 m=%neg_to_m |
| 325 | @ldstim12m ...... b:5 t:5 ................ \ |
| 326 | &ldst sp=%assemble_sp disp=%assemble_12a \ |
| 327 | x=0 scale=0 m=%pos_to_m |
| 328 | |
| 329 | # LDB, LDH, LDW, LDWM |
| 330 | ld 010000 ..... ..... .. .............. @ldstim14 size=0 |
| 331 | ld 010001 ..... ..... .. .............. @ldstim14 size=1 |
| 332 | ld 010010 ..... ..... .. .............. @ldstim14 size=2 |
| 333 | ld 010011 ..... ..... .. .............. @ldstim14m size=2 |
| 334 | ld 010111 ..... ..... .. ...........10. @ldstim12m size=2 |
| 335 | |
| 336 | # STB, STH, STW, STWM |
| 337 | st 011000 ..... ..... .. .............. @ldstim14 size=0 |
| 338 | st 011001 ..... ..... .. .............. @ldstim14 size=1 |
| 339 | st 011010 ..... ..... .. .............. @ldstim14 size=2 |
| 340 | st 011011 ..... ..... .. .............. @ldstim14m size=2 |
| 341 | st 011111 ..... ..... .. ...........10. @ldstim12m size=2 |
| 342 | |
| 343 | fldw 010110 b:5 ..... ................ \ |
| 344 | &ldst disp=%assemble_12a sp=%assemble_sp \ |
| 345 | t=%rm64 m=%a_to_m x=0 scale=0 size=2 |
| 346 | fldw 010111 b:5 ..... .............0.. \ |
| 347 | &ldst disp=%assemble_12a sp=%assemble_sp \ |
| 348 | t=%rm64 m=0 x=0 scale=0 size=2 |
| 349 | |
| 350 | fstw 011110 b:5 ..... ................ \ |
| 351 | &ldst disp=%assemble_12a sp=%assemble_sp \ |
| 352 | t=%rm64 m=%a_to_m x=0 scale=0 size=2 |
| 353 | fstw 011111 b:5 ..... .............0.. \ |
| 354 | &ldst disp=%assemble_12a sp=%assemble_sp \ |
| 355 | t=%rm64 m=0 x=0 scale=0 size=2 |
| 356 | |
| 357 | ld 010100 ..... ..... .. ............0. @ldstim11 |
| 358 | fldd 010100 ..... ..... .. ............1. @ldstim11 |
| 359 | |
| 360 | st 011100 ..... ..... .. ............0. @ldstim11 |
| 361 | fstd 011100 ..... ..... .. ............1. @ldstim11 |
| 362 | |
| 363 | #### |
| 364 | # Floating-point Multiply Add |
| 365 | #### |
| 366 | |
| 367 | &mpyadd rm1 rm2 ta ra tm |
| 368 | @mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd |
| 369 | |
| 370 | fmpyadd_f 000110 ..... ..... ..... ..... 1 ..... @mpyadd |
| 371 | fmpyadd_d 000110 ..... ..... ..... ..... 0 ..... @mpyadd |
| 372 | fmpysub_f 100110 ..... ..... ..... ..... 1 ..... @mpyadd |
| 373 | fmpysub_d 100110 ..... ..... ..... ..... 0 ..... @mpyadd |
| 374 | |
| 375 | #### |
| 376 | # Conditional Branches |
| 377 | #### |
| 378 | |
| 379 | bb_sar 110000 00000 r:5 c:1 1 . ........... n:1 . \ |
| 380 | disp=%assemble_12 d=%d_13 |
| 381 | bb_imm 110001 p:5 r:5 c:1 1 . ........... n:1 . \ |
| 382 | disp=%assemble_12 d=%d_13 |
| 383 | |
| 384 | movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 |
| 385 | movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 |
| 386 | |
| 387 | cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=0 f=0 |
| 388 | cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=0 f=1 |
| 389 | cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=1 f=0 |
| 390 | cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=1 f=1 |
| 391 | cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=0 f=0 |
| 392 | cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=0 f=1 |
| 393 | cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \ |
| 394 | &rib_c_d_f d=1 disp=%assemble_12 c=%cmpbid_c i=%im5_16 |
| 395 | |
| 396 | addb 101000 ..... ..... ... ........... . . @rrb_cf f=0 |
| 397 | addb 101010 ..... ..... ... ........... . . @rrb_cf f=1 |
| 398 | addbi 101001 ..... ..... ... ........... . . @rib_cf f=0 |
| 399 | addbi 101011 ..... ..... ... ........... . . @rib_cf f=1 |
| 400 | |
| 401 | #### |
| 402 | # Shift, Extract, Deposit |
| 403 | #### |
| 404 | |
| 405 | shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5 |
| 406 | shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=0 |
| 407 | shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \ |
| 408 | d=1 cpos=%cpos6_11 |
| 409 | |
| 410 | extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=0 len=%len5 |
| 411 | extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=1 len=%len6_8 |
| 412 | extr_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 ..... d=0 len=%len5 |
| 413 | extr_imm 110110 r:5 t:5 c:3 .. se:1 ..... ..... \ |
| 414 | d=1 len=%len6_12 pos=%cpos6_11 |
| 415 | |
| 416 | dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=0 len=%len5 |
| 417 | dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=1 len=%len6_8 |
| 418 | dep_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 ..... d=0 len=%len5 |
| 419 | dep_imm 111100 t:5 r:5 c:3 .. nz:1 ..... ..... \ |
| 420 | d=1 len=%len6_12 cpos=%cpos6_11 |
| 421 | depi_sar 110101 t:5 ..... c:3 10 nz:1 d:1 . 000 ..... \ |
| 422 | i=%im5_16 len=%len6_8 |
| 423 | depi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 ..... \ |
| 424 | d=0 i=%im5_16 len=%len5 |
| 425 | depi_imm 111101 t:5 ..... c:3 .. nz:1 ..... ..... \ |
| 426 | d=1 i=%im5_16 len=%len6_12 cpos=%cpos6_11 |
| 427 | |
| 428 | #### |
| 429 | # Branch External |
| 430 | #### |
| 431 | |
| 432 | &BE b l n disp sp |
| 433 | @be ...... b:5 ..... ... ........... n:1 . \ |
| 434 | &BE disp=%assemble_17 sp=%assemble_sr3 |
| 435 | |
| 436 | be 111000 ..... ..... ... ........... . . @be l=0 |
| 437 | be 111001 ..... ..... ... ........... . . @be l=31 |
| 438 | |
| 439 | #### |
| 440 | # Branch |
| 441 | #### |
| 442 | |
| 443 | &BL l n disp |
| 444 | @bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17 |
| 445 | |
| 446 | # B,L and B,L,PUSH |
| 447 | bl 111010 ..... ..... 000 ........... . . @bl |
| 448 | bl 111010 ..... ..... 100 ........... . . @bl |
| 449 | # B,L (long displacement) |
| 450 | bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \ |
| 451 | disp=%assemble_22 |
| 452 | b_gate 111010 ..... ..... 001 ........... . . @bl |
| 453 | blr 111010 l:5 x:5 010 00000000000 n:1 0 |
| 454 | nopbts 111010 00000 00000 010 0---------1 0 1 # clrbts/popbts |
| 455 | nopbts 111010 00000 ----- 010 00000000000 0 1 # pushbts/pushnom |
| 456 | bv 111010 b:5 x:5 110 00000000000 n:1 0 |
| 457 | bve 111010 b:5 00000 110 10000000000 n:1 - l=0 |
| 458 | bve 111010 b:5 00000 111 10000000000 n:1 - l=2 |
| 459 | |
| 460 | #### |
| 461 | # FP Fused Multiple-Add |
| 462 | #### |
| 463 | |
| 464 | fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \ |
| 465 | rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64 |
| 466 | fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32 |
| 467 | |
| 468 | #### |
| 469 | # FP operations |
| 470 | #### |
| 471 | |
| 472 | &fclass01 r t |
| 473 | &fclass2 r1 r2 c y |
| 474 | &fclass3 r1 r2 t |
| 475 | |
| 476 | @f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01 |
| 477 | @f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01 |
| 478 | @f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2 |
| 479 | @f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3 |
| 480 | |
| 481 | @f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \ |
| 482 | &fclass01 r=%ra64 t=%rt64 |
| 483 | @f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01 |
| 484 | |
| 485 | @f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \ |
| 486 | &fclass01 r=%ra64 t=%rt64 |
| 487 | @f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64 |
| 488 | @f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64 |
| 489 | @f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01 |
| 490 | |
| 491 | @f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \ |
| 492 | &fclass2 r1=%ra64 r2=%rb64 |
| 493 | @f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2 |
| 494 | |
| 495 | @f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \ |
| 496 | &fclass3 r1=%ra64 r2=%rb64 t=%rt64 |
| 497 | @f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 &fclass3 |
| 498 | |
| 499 | # Floating point class 0 |
| 500 | |
| 501 | fid_f 001100 00000 00000 000 00 000000 00000 |
| 502 | |
| 503 | fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0 |
| 504 | fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0 |
| 505 | fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0 |
| 506 | frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0 |
| 507 | fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0 |
| 508 | fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0 |
| 509 | |
| 510 | fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0 |
| 511 | fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0 |
| 512 | fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0 |
| 513 | frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0 |
| 514 | fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0 |
| 515 | fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0 |
| 516 | |
| 517 | fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0 |
| 518 | fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0 |
| 519 | fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0 |
| 520 | frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0 |
| 521 | fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0 |
| 522 | fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0 |
| 523 | |
| 524 | fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0 |
| 525 | fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0 |
| 526 | fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0 |
| 527 | frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0 |
| 528 | fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0 |
| 529 | fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0 |
| 530 | |
| 531 | # Floating point class 1 |
| 532 | |
| 533 | # float/float |
| 534 | fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1 |
| 535 | fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1 |
| 536 | |
| 537 | fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1 |
| 538 | fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1 |
| 539 | |
| 540 | # int/float |
| 541 | fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1 |
| 542 | fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1 |
| 543 | fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1 |
| 544 | fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1 |
| 545 | |
| 546 | fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1 |
| 547 | fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1 |
| 548 | fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1 |
| 549 | fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1 |
| 550 | |
| 551 | # float/int |
| 552 | fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1 |
| 553 | fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1 |
| 554 | fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1 |
| 555 | fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1 |
| 556 | |
| 557 | fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1 |
| 558 | fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1 |
| 559 | fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1 |
| 560 | fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1 |
| 561 | |
| 562 | # float/int truncate |
| 563 | fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1 |
| 564 | fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1 |
| 565 | fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1 |
| 566 | fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1 |
| 567 | |
| 568 | fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1 |
| 569 | fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1 |
| 570 | fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1 |
| 571 | fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1 |
| 572 | |
| 573 | # uint/float |
| 574 | fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1 |
| 575 | fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1 |
| 576 | fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1 |
| 577 | fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1 |
| 578 | |
| 579 | fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1 |
| 580 | fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1 |
| 581 | fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1 |
| 582 | fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1 |
| 583 | |
| 584 | # float/int |
| 585 | fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1 |
| 586 | fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1 |
| 587 | fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1 |
| 588 | fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1 |
| 589 | |
| 590 | fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1 |
| 591 | fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1 |
| 592 | fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1 |
| 593 | fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1 |
| 594 | |
| 595 | # float/int truncate |
| 596 | fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1 |
| 597 | fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1 |
| 598 | fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1 |
| 599 | fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1 |
| 600 | |
| 601 | fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1 |
| 602 | fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1 |
| 603 | fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1 |
| 604 | fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1 |
| 605 | |
| 606 | # Floating point class 2 |
| 607 | |
| 608 | ftest 001100 00000 00000 y:3 00 10000 1 c:5 |
| 609 | |
| 610 | fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2 |
| 611 | fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2 |
| 612 | |
| 613 | fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2 |
| 614 | fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2 |
| 615 | |
| 616 | # Floating point class 3 |
| 617 | |
| 618 | fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3 |
| 619 | fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3 |
| 620 | fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3 |
| 621 | fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3 |
| 622 | |
| 623 | fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3 |
| 624 | fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3 |
| 625 | fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3 |
| 626 | fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3 |
| 627 | |
| 628 | fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3 |
| 629 | fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3 |
| 630 | fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3 |
| 631 | fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3 |
| 632 | |
| 633 | fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3 |
| 634 | fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3 |
| 635 | fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3 |
| 636 | fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3 |
| 637 | |
| 638 | xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 |
| 639 | |
| 640 | # diag |
| 641 | { |
| 642 | [ |
| 643 | diag_btlb 000101 00 0000 0000 0000 0001 0000 0000 |
| 644 | diag_cout 000101 00 0000 0000 0000 0001 0000 0001 |
| 645 | |
| 646 | # For 32-bit PA-7300LC (PCX-L2) |
| 647 | diag_getshadowregs_pa1 000101 00 0000 0000 0001 1010 0000 0000 |
| 648 | diag_putshadowregs_pa1 000101 00 0000 0000 0001 1010 0100 0000 |
| 649 | diag_mfdiag 000101 dr:5 rt:5 0000 0110 0000 0000 |
| 650 | diag_mtdiag 000101 dr:5 r1:5 0001 0110 0000 0000 |
| 651 | |
| 652 | # For 64-bit PA8700 (PCX-W2) |
| 653 | diag_mfdiag 000101 dr:5 0 0000 0000 1000 101 rt:5 |
| 654 | diag_mtdiag 000101 dr:5 r1:5 0001 1000 0100 0000 |
| 655 | ] |
| 656 | diag_unimp 000101 i:26 |
| 657 | } |