| 1 | /* |
| 2 | * HPPA memory access helper routines |
| 3 | * |
| 4 | * Copyright (c) 2017 Helge Deller |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "qemu/log.h" |
| 22 | #include "cpu.h" |
| 23 | #include "exec/cputlb.h" |
| 24 | #include "accel/tcg/cpu-loop.h" |
| 25 | #include "accel/tcg/cpu-mmu-index.h" |
| 26 | #include "accel/tcg/probe.h" |
| 27 | #include "exec/page-protection.h" |
| 28 | #include "exec/target_page.h" |
| 29 | #include "exec/helper-proto.h" |
| 30 | #include "hw/core/cpu.h" |
| 31 | #include "hw/hppa/hppa_hardware.h" |
| 32 | #include "trace.h" |
| 33 | |
| 34 | hwaddr hppa_abs_to_phys_pa1x(uint8_t phys_addr_bits, vaddr addr) |
| 35 | { |
| 36 | return extract64(addr, 0, phys_addr_bits); |
| 37 | } |
| 38 | |
| 39 | hwaddr hppa_abs_to_phys_pa2_w1(uint8_t phys_addr_bits, vaddr addr) |
| 40 | { |
| 41 | /* |
| 42 | * Figure H-8 "62-bit Absolute Accesses when PSW W-bit is 1" describes |
| 43 | * an algorithm in which a 62-bit absolute address is transformed to |
| 44 | * a 64-bit physical address. This must then be combined with that |
| 45 | * pictured in Figure H-11 "Physical Address Space Mapping", in which |
| 46 | * the full physical address is truncated to the N-bit physical address |
| 47 | * supported by the implementation. |
| 48 | * |
| 49 | * Since the supported physical address space is below 54 bits, the |
| 50 | * H-8 algorithm is moot and all that is left is to truncate. |
| 51 | */ |
| 52 | return sextract64(addr, 0, phys_addr_bits); |
| 53 | } |
| 54 | |
| 55 | hwaddr hppa_abs_to_phys_pa2_w0(uint8_t phys_addr_bits, vaddr addr) |
| 56 | { |
| 57 | /* |
| 58 | * See Figure H-10, "Absolute Accesses when PSW W-bit is 0", |
| 59 | * combined with Figure H-11, as above. |
| 60 | */ |
| 61 | if (likely(extract32(addr, 28, 4) != 0xf)) { |
| 62 | /* Memory address space */ |
| 63 | addr = (uint32_t)addr; |
| 64 | } else if (extract32(addr, 24, 4) != 0) { |
| 65 | /* I/O address space */ |
| 66 | addr = (int32_t)addr; |
| 67 | } else { |
| 68 | /* |
| 69 | * PDC address space: |
| 70 | * Figures H-10 and H-11 of the parisc2.0 spec do not specify |
| 71 | * where to map into the 64-bit PDC address space, but verification |
| 72 | * on physical A500, C3700 and C8000 machines show that PDC is always |
| 73 | * mapped at 0xfffffff0f0000000, independed if the CPU has 40 or 44 |
| 74 | * physical bits. |
| 75 | */ |
| 76 | addr = (uint32_t)addr; |
| 77 | addr |= ((uint64_t) FIRMWARE_HIGH) << 32; |
| 78 | } |
| 79 | return addr; |
| 80 | } |
| 81 | |
| 82 | static HPPATLBEntry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) |
| 83 | { |
| 84 | IntervalTreeNode *i = interval_tree_iter_first(&env->tlb_root, addr, addr); |
| 85 | |
| 86 | if (i) { |
| 87 | HPPATLBEntry *ent = container_of(i, HPPATLBEntry, itree); |
| 88 | trace_hppa_tlb_find_entry(env, ent, ent->entry_valid, |
| 89 | ent->itree.start, ent->itree.last, ent->pa); |
| 90 | return ent; |
| 91 | } |
| 92 | trace_hppa_tlb_find_entry_not_found(env, addr); |
| 93 | return NULL; |
| 94 | } |
| 95 | |
| 96 | static void hppa_flush_tlb_ent(CPUHPPAState *env, HPPATLBEntry *ent, |
| 97 | bool force_flush_btlb) |
| 98 | { |
| 99 | CPUState *cs = env_cpu(env); |
| 100 | bool is_btlb; |
| 101 | |
| 102 | if (!ent->entry_valid) { |
| 103 | return; |
| 104 | } |
| 105 | |
| 106 | trace_hppa_tlb_flush_ent(env, ent, ent->itree.start, |
| 107 | ent->itree.last, ent->pa); |
| 108 | |
| 109 | tlb_flush_range_by_mmuidx(cs, ent->itree.start, |
| 110 | ent->itree.last - ent->itree.start + 1, |
| 111 | HPPA_MMU_FLUSH_MASK, TARGET_LONG_BITS); |
| 112 | |
| 113 | /* Never clear BTLBs, unless forced to do so. */ |
| 114 | is_btlb = ent < &env->tlb[HPPA_BTLB_ENTRIES(env)]; |
| 115 | if (is_btlb && !force_flush_btlb) { |
| 116 | return; |
| 117 | } |
| 118 | |
| 119 | interval_tree_remove(&ent->itree, &env->tlb_root); |
| 120 | memset(ent, 0, sizeof(*ent)); |
| 121 | |
| 122 | if (!is_btlb) { |
| 123 | ent->unused_next = env->tlb_unused; |
| 124 | env->tlb_unused = ent; |
| 125 | } |
| 126 | } |
| 127 | |
| 128 | static void hppa_flush_tlb_range(CPUHPPAState *env, vaddr va_b, vaddr va_e) |
| 129 | { |
| 130 | IntervalTreeNode *i, *n; |
| 131 | |
| 132 | i = interval_tree_iter_first(&env->tlb_root, va_b, va_e); |
| 133 | for (; i ; i = n) { |
| 134 | HPPATLBEntry *ent = container_of(i, HPPATLBEntry, itree); |
| 135 | |
| 136 | /* |
| 137 | * Find the next entry now: In the normal case the current entry |
| 138 | * will be removed, but in the BTLB case it will remain. |
| 139 | */ |
| 140 | n = interval_tree_iter_next(i, va_b, va_e); |
| 141 | hppa_flush_tlb_ent(env, ent, false); |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | static HPPATLBEntry *hppa_alloc_tlb_ent(CPUHPPAState *env) |
| 146 | { |
| 147 | HPPATLBEntry *ent = env->tlb_unused; |
| 148 | |
| 149 | if (ent == NULL) { |
| 150 | uint32_t btlb_entries = HPPA_BTLB_ENTRIES(env); |
| 151 | uint32_t i = env->tlb_last; |
| 152 | |
| 153 | if (i < btlb_entries || i >= ARRAY_SIZE(env->tlb)) { |
| 154 | i = btlb_entries; |
| 155 | } |
| 156 | env->tlb_last = i + 1; |
| 157 | |
| 158 | ent = &env->tlb[i]; |
| 159 | hppa_flush_tlb_ent(env, ent, false); |
| 160 | } |
| 161 | |
| 162 | env->tlb_unused = ent->unused_next; |
| 163 | return ent; |
| 164 | } |
| 165 | |
| 166 | #define ACCESS_ID_MASK 0xffff |
| 167 | |
| 168 | /* Return the set of protections allowed by a PID match. */ |
| 169 | static int match_prot_id_1(uint32_t access_id, uint32_t prot_id) |
| 170 | { |
| 171 | if (((access_id ^ (prot_id >> 1)) & ACCESS_ID_MASK) == 0) { |
| 172 | return (prot_id & 1 |
| 173 | ? PAGE_EXEC | PAGE_READ |
| 174 | : PAGE_EXEC | PAGE_READ | PAGE_WRITE); |
| 175 | } |
| 176 | return 0; |
| 177 | } |
| 178 | |
| 179 | static int match_prot_id32(CPUHPPAState *env, uint32_t access_id) |
| 180 | { |
| 181 | int r, i; |
| 182 | |
| 183 | for (i = CR_PID1; i <= CR_PID4; ++i) { |
| 184 | r = match_prot_id_1(access_id, env->cr[i]); |
| 185 | if (r) { |
| 186 | return r; |
| 187 | } |
| 188 | } |
| 189 | return 0; |
| 190 | } |
| 191 | |
| 192 | static int match_prot_id64(CPUHPPAState *env, uint32_t access_id) |
| 193 | { |
| 194 | int r, i; |
| 195 | |
| 196 | for (i = CR_PID1; i <= CR_PID4; ++i) { |
| 197 | r = match_prot_id_1(access_id, env->cr[i]); |
| 198 | if (r) { |
| 199 | return r; |
| 200 | } |
| 201 | r = match_prot_id_1(access_id, env->cr[i] >> 32); |
| 202 | if (r) { |
| 203 | return r; |
| 204 | } |
| 205 | } |
| 206 | return 0; |
| 207 | } |
| 208 | |
| 209 | int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, |
| 210 | int type, MemOp mop, hwaddr *pphys, int *pprot) |
| 211 | { |
| 212 | hwaddr phys; |
| 213 | int prot, r_prot, w_prot, x_prot, priv; |
| 214 | HPPATLBEntry *ent; |
| 215 | int ret = -1; |
| 216 | |
| 217 | /* Virtual translation disabled. Map absolute to physical. */ |
| 218 | if (MMU_IDX_MMU_DISABLED(mmu_idx)) { |
| 219 | const uint8_t phys_addr_bits = hppa_phys_addr_bits(env); |
| 220 | switch (mmu_idx) { |
| 221 | case MMU_ABS_W_IDX: |
| 222 | phys = hppa_abs_to_phys_pa2_w1(phys_addr_bits, addr); |
| 223 | break; |
| 224 | case MMU_ABS_IDX: |
| 225 | if (hppa_is_pa20(env)) { |
| 226 | phys = hppa_abs_to_phys_pa2_w0(phys_addr_bits, addr); |
| 227 | } else { |
| 228 | phys = hppa_abs_to_phys_pa1x(phys_addr_bits, addr); |
| 229 | } |
| 230 | break; |
| 231 | default: |
| 232 | g_assert_not_reached(); |
| 233 | } |
| 234 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 235 | goto egress_align; |
| 236 | } |
| 237 | |
| 238 | /* Find a valid tlb entry that matches the virtual address. */ |
| 239 | ent = hppa_find_tlb(env, addr); |
| 240 | if (ent == NULL) { |
| 241 | phys = 0; |
| 242 | prot = 0; |
| 243 | ret = (type == PAGE_EXEC) ? EXCP_ITLB_MISS : EXCP_DTLB_MISS; |
| 244 | goto egress; |
| 245 | } |
| 246 | |
| 247 | /* We now know the physical address. */ |
| 248 | phys = ent->pa + (addr - ent->itree.start); |
| 249 | |
| 250 | /* Map TLB access_rights field to QEMU protection. */ |
| 251 | priv = MMU_IDX_TO_PRIV(mmu_idx); |
| 252 | r_prot = (priv <= ent->ar_pl1) * PAGE_READ; |
| 253 | w_prot = (priv <= ent->ar_pl2) * PAGE_WRITE; |
| 254 | x_prot = (ent->ar_pl2 <= priv && priv <= ent->ar_pl1) * PAGE_EXEC; |
| 255 | switch (ent->ar_type) { |
| 256 | case 0: /* read-only: data page */ |
| 257 | prot = r_prot; |
| 258 | break; |
| 259 | case 1: /* read/write: dynamic data page */ |
| 260 | prot = r_prot | w_prot; |
| 261 | break; |
| 262 | case 2: /* read/execute: normal code page */ |
| 263 | prot = r_prot | x_prot; |
| 264 | break; |
| 265 | case 3: /* read/write/execute: dynamic code page */ |
| 266 | prot = r_prot | w_prot | x_prot; |
| 267 | break; |
| 268 | default: /* execute: promote to privilege level type & 3 */ |
| 269 | prot = x_prot; |
| 270 | break; |
| 271 | } |
| 272 | |
| 273 | /* |
| 274 | * No guest access type indicates a non-architectural access from |
| 275 | * within QEMU. Bypass checks for access, D, B, P and T bits. |
| 276 | */ |
| 277 | if (type == 0) { |
| 278 | goto egress; |
| 279 | } |
| 280 | |
| 281 | if (unlikely(!(prot & type))) { |
| 282 | /* Not allowed -- Inst/Data Memory Access Rights Fault. */ |
| 283 | ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR; |
| 284 | goto egress; |
| 285 | } |
| 286 | |
| 287 | /* access_id == 0 means public page and no check is performed */ |
| 288 | if (ent->access_id && MMU_IDX_TO_P(mmu_idx)) { |
| 289 | int access_prot = (hppa_is_pa20(env) |
| 290 | ? match_prot_id64(env, ent->access_id) |
| 291 | : match_prot_id32(env, ent->access_id)); |
| 292 | if (unlikely(!(type & access_prot))) { |
| 293 | /* Not allowed -- Inst/Data Memory Protection Id Fault. */ |
| 294 | ret = type & PAGE_EXEC ? EXCP_IMP : EXCP_DMPI; |
| 295 | goto egress; |
| 296 | } |
| 297 | /* Otherwise exclude permissions not allowed (i.e WD). */ |
| 298 | prot &= access_prot; |
| 299 | } |
| 300 | |
| 301 | /* |
| 302 | * In reverse priority order, check for conditions which raise faults. |
| 303 | * Remove PROT bits that cover the condition we want to check, |
| 304 | * so that the resulting PROT will force a re-check of the |
| 305 | * architectural TLB entry for the next access. |
| 306 | */ |
| 307 | if (unlikely(ent->t)) { |
| 308 | prot &= PAGE_EXEC; |
| 309 | if (!(type & PAGE_EXEC)) { |
| 310 | /* The T bit is set -- Page Reference Fault. */ |
| 311 | ret = EXCP_PAGE_REF; |
| 312 | } |
| 313 | } |
| 314 | if (unlikely(!ent->d)) { |
| 315 | prot &= PAGE_READ | PAGE_EXEC; |
| 316 | if (type & PAGE_WRITE) { |
| 317 | /* The D bit is not set -- TLB Dirty Bit Fault. */ |
| 318 | ret = EXCP_TLB_DIRTY; |
| 319 | } |
| 320 | } |
| 321 | if (unlikely(ent->b)) { |
| 322 | prot &= PAGE_READ | PAGE_EXEC; |
| 323 | if (type & PAGE_WRITE) { |
| 324 | /* |
| 325 | * The B bit is set -- Data Memory Break Fault. |
| 326 | * Except when PSW_X is set, allow this single access to succeed. |
| 327 | * The write bit will be invalidated for subsequent accesses. |
| 328 | */ |
| 329 | if (env->psw_xb & PSW_X) { |
| 330 | prot |= PAGE_WRITE_INV; |
| 331 | } else { |
| 332 | ret = EXCP_DMB; |
| 333 | } |
| 334 | } |
| 335 | } |
| 336 | |
| 337 | egress_align: |
| 338 | if (addr & ((1u << memop_alignment_bits(mop)) - 1)) { |
| 339 | ret = EXCP_UNALIGN; |
| 340 | } |
| 341 | |
| 342 | egress: |
| 343 | *pphys = phys; |
| 344 | *pprot = prot; |
| 345 | trace_hppa_tlb_get_physical_address(env, ret, prot, addr, phys); |
| 346 | return ret; |
| 347 | } |
| 348 | |
| 349 | hwaddr hppa_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) |
| 350 | { |
| 351 | HPPACPU *cpu = HPPA_CPU(cs); |
| 352 | hwaddr phys; |
| 353 | int prot, excp, mmu_idx; |
| 354 | |
| 355 | /* If the (data) mmu is disabled, bypass translation. */ |
| 356 | /* ??? We really ought to know if the code mmu is disabled too, |
| 357 | in order to get the correct debugging dumps. */ |
| 358 | mmu_idx = (cpu->env.psw & PSW_D ? MMU_KERNEL_IDX : |
| 359 | cpu->env.psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); |
| 360 | |
| 361 | excp = hppa_get_physical_address(&cpu->env, addr, mmu_idx, 0, 0, |
| 362 | &phys, &prot); |
| 363 | |
| 364 | /* Since we're translating for debugging, the only error that is a |
| 365 | hard error is no translation at all. Otherwise, while a real cpu |
| 366 | access might not have permission, the debugger does. */ |
| 367 | return excp == EXCP_DTLB_MISS ? -1 : phys; |
| 368 | } |
| 369 | |
| 370 | void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled) |
| 371 | { |
| 372 | if (env->psw & PSW_Q) { |
| 373 | /* |
| 374 | * For pa1.x, the offset and space never overlap, and so we |
| 375 | * simply extract the high and low part of the virtual address. |
| 376 | * |
| 377 | * For pa2.0, the formation of these are described in section |
| 378 | * "Interruption Parameter Registers", page 2-15. |
| 379 | */ |
| 380 | env->cr[CR_IOR] = (uint32_t)addr; |
| 381 | env->cr[CR_ISR] = addr >> 32; |
| 382 | |
| 383 | if (hppa_is_pa20(env)) { |
| 384 | if (mmu_disabled) { |
| 385 | /* |
| 386 | * If data translation was disabled, the ISR contains |
| 387 | * the upper portion of the abs address, zero-extended. |
| 388 | */ |
| 389 | env->cr[CR_ISR] &= 0x3fffffff; |
| 390 | } else { |
| 391 | /* |
| 392 | * If data translation was enabled, the upper two bits |
| 393 | * of the IOR (the b field) are equal to the two space |
| 394 | * bits from the base register used to form the gva. |
| 395 | */ |
| 396 | uint64_t b; |
| 397 | |
| 398 | b = env->unwind_breg ? env->gr[env->unwind_breg] : 0; |
| 399 | b >>= (env->psw & PSW_W ? 62 : 30); |
| 400 | env->cr[CR_IOR] |= b << 62; |
| 401 | } |
| 402 | } |
| 403 | } |
| 404 | } |
| 405 | |
| 406 | G_NORETURN static void |
| 407 | raise_exception_with_ior(CPUHPPAState *env, int excp, uintptr_t retaddr, |
| 408 | vaddr addr, bool mmu_disabled) |
| 409 | { |
| 410 | CPUState *cs = env_cpu(env); |
| 411 | |
| 412 | cs->exception_index = excp; |
| 413 | cpu_restore_state(cs, retaddr); |
| 414 | hppa_set_ior_and_isr(env, addr, mmu_disabled); |
| 415 | |
| 416 | cpu_loop_exit(cs); |
| 417 | } |
| 418 | |
| 419 | void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
| 420 | vaddr addr, unsigned size, |
| 421 | MMUAccessType access_type, |
| 422 | int mmu_idx, MemTxAttrs attrs, |
| 423 | MemTxResult response, uintptr_t retaddr) |
| 424 | { |
| 425 | CPUHPPAState *env = cpu_env(cs); |
| 426 | |
| 427 | qemu_log_mask(LOG_GUEST_ERROR, "HPMC at " TARGET_FMT_lx ":" TARGET_FMT_lx |
| 428 | " while accessing I/O at %#08" HWADDR_PRIx "\n", |
| 429 | env->iasq_f, env->iaoq_f, physaddr); |
| 430 | |
| 431 | /* FIXME: Enable HPMC exceptions when firmware has clean device probing */ |
| 432 | if (0) { |
| 433 | raise_exception_with_ior(env, EXCP_HPMC, retaddr, addr, |
| 434 | MMU_IDX_MMU_DISABLED(mmu_idx)); |
| 435 | } |
| 436 | } |
| 437 | |
| 438 | bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, |
| 439 | MMUAccessType type, int mmu_idx, |
| 440 | MemOp memop, int size, bool probe, uintptr_t ra) |
| 441 | { |
| 442 | CPUHPPAState *env = cpu_env(cs); |
| 443 | int prot, excp, a_prot; |
| 444 | hwaddr phys; |
| 445 | |
| 446 | switch (type) { |
| 447 | case MMU_INST_FETCH: |
| 448 | a_prot = PAGE_EXEC; |
| 449 | break; |
| 450 | case MMU_DATA_STORE: |
| 451 | a_prot = PAGE_WRITE; |
| 452 | break; |
| 453 | default: |
| 454 | a_prot = PAGE_READ; |
| 455 | break; |
| 456 | } |
| 457 | |
| 458 | excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, memop, |
| 459 | &phys, &prot); |
| 460 | if (unlikely(excp >= 0)) { |
| 461 | if (probe) { |
| 462 | return false; |
| 463 | } |
| 464 | trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx); |
| 465 | |
| 466 | /* Failure. Raise the indicated exception. */ |
| 467 | raise_exception_with_ior(env, excp, ra, addr, |
| 468 | MMU_IDX_MMU_DISABLED(mmu_idx)); |
| 469 | } |
| 470 | |
| 471 | trace_hppa_tlb_fill_success(env, addr & TARGET_PAGE_MASK, |
| 472 | phys & TARGET_PAGE_MASK, size, type, mmu_idx); |
| 473 | |
| 474 | /* |
| 475 | * Success! Store the translation into the QEMU TLB. |
| 476 | * Note that we always install a single-page entry, because that |
| 477 | * is what works best with softmmu -- anything else will trigger |
| 478 | * the large page protection mask. We do not require this, |
| 479 | * because we record the large page here in the hppa tlb. |
| 480 | */ |
| 481 | memset(out, 0, sizeof(*out)); |
| 482 | out->phys_addr = phys; |
| 483 | out->prot = prot; |
| 484 | out->attrs = MEMTXATTRS_UNSPECIFIED; |
| 485 | out->lg_page_size = TARGET_PAGE_BITS; |
| 486 | |
| 487 | return true; |
| 488 | } |
| 489 | |
| 490 | /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ |
| 491 | void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong addr, target_ulong reg) |
| 492 | { |
| 493 | HPPATLBEntry *ent; |
| 494 | |
| 495 | /* Zap any old entries covering ADDR. */ |
| 496 | addr &= TARGET_PAGE_MASK; |
| 497 | hppa_flush_tlb_range(env, addr, addr + TARGET_PAGE_SIZE - 1); |
| 498 | |
| 499 | ent = env->tlb_partial; |
| 500 | if (ent == NULL) { |
| 501 | ent = hppa_alloc_tlb_ent(env); |
| 502 | env->tlb_partial = ent; |
| 503 | } |
| 504 | |
| 505 | /* Note that ent->entry_valid == 0 already. */ |
| 506 | ent->itree.start = addr; |
| 507 | ent->itree.last = addr + TARGET_PAGE_SIZE - 1; |
| 508 | ent->pa = extract32(reg, 5, 20) << TARGET_PAGE_BITS; |
| 509 | trace_hppa_tlb_itlba(env, ent, ent->itree.start, ent->itree.last, ent->pa); |
| 510 | } |
| 511 | |
| 512 | static void set_access_bits_pa11(CPUHPPAState *env, HPPATLBEntry *ent, |
| 513 | target_ulong reg) |
| 514 | { |
| 515 | ent->access_id = extract32(reg, 1, 18); |
| 516 | ent->u = extract32(reg, 19, 1); |
| 517 | ent->ar_pl2 = extract32(reg, 20, 2); |
| 518 | ent->ar_pl1 = extract32(reg, 22, 2); |
| 519 | ent->ar_type = extract32(reg, 24, 3); |
| 520 | ent->b = extract32(reg, 27, 1); |
| 521 | ent->d = extract32(reg, 28, 1); |
| 522 | ent->t = extract32(reg, 29, 1); |
| 523 | ent->entry_valid = 1; |
| 524 | |
| 525 | interval_tree_insert(&ent->itree, &env->tlb_root); |
| 526 | trace_hppa_tlb_itlbp(env, ent, ent->access_id, ent->u, ent->ar_pl2, |
| 527 | ent->ar_pl1, ent->ar_type, ent->b, ent->d, ent->t); |
| 528 | } |
| 529 | |
| 530 | /* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */ |
| 531 | void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong addr, target_ulong reg) |
| 532 | { |
| 533 | HPPATLBEntry *ent = env->tlb_partial; |
| 534 | |
| 535 | if (ent) { |
| 536 | env->tlb_partial = NULL; |
| 537 | if (ent->itree.start <= addr && addr <= ent->itree.last) { |
| 538 | set_access_bits_pa11(env, ent, reg); |
| 539 | return; |
| 540 | } |
| 541 | } |
| 542 | qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n"); |
| 543 | } |
| 544 | |
| 545 | static void itlbt_pa20(CPUHPPAState *env, target_ulong r1, |
| 546 | target_ulong r2, vaddr va_b) |
| 547 | { |
| 548 | HPPATLBEntry *ent; |
| 549 | vaddr va_e; |
| 550 | uint64_t va_size; |
| 551 | int mask_shift; |
| 552 | |
| 553 | mask_shift = 2 * (r1 & 0xf); |
| 554 | va_size = (uint64_t)TARGET_PAGE_SIZE << mask_shift; |
| 555 | va_b &= -va_size; |
| 556 | va_e = va_b + va_size - 1; |
| 557 | |
| 558 | hppa_flush_tlb_range(env, va_b, va_e); |
| 559 | ent = hppa_alloc_tlb_ent(env); |
| 560 | |
| 561 | ent->itree.start = va_b; |
| 562 | ent->itree.last = va_e; |
| 563 | |
| 564 | /* Extract all 52 bits present in the page table entry. */ |
| 565 | ent->pa = r1 << (TARGET_PAGE_BITS - 5); |
| 566 | /* Align per the page size. */ |
| 567 | ent->pa &= TARGET_PAGE_MASK << mask_shift; |
| 568 | /* Ignore the bits beyond physical address space. */ |
| 569 | ent->pa = sextract64(ent->pa, 0, hppa_phys_addr_bits(env)); |
| 570 | |
| 571 | ent->t = extract64(r2, 61, 1); |
| 572 | ent->d = extract64(r2, 60, 1); |
| 573 | ent->b = extract64(r2, 59, 1); |
| 574 | ent->ar_type = extract64(r2, 56, 3); |
| 575 | ent->ar_pl1 = extract64(r2, 54, 2); |
| 576 | ent->ar_pl2 = extract64(r2, 52, 2); |
| 577 | ent->u = extract64(r2, 51, 1); |
| 578 | /* o = bit 50 */ |
| 579 | /* p = bit 49 */ |
| 580 | ent->access_id = extract64(r2, 1, 31); |
| 581 | ent->entry_valid = 1; |
| 582 | |
| 583 | interval_tree_insert(&ent->itree, &env->tlb_root); |
| 584 | trace_hppa_tlb_itlba(env, ent, ent->itree.start, ent->itree.last, ent->pa); |
| 585 | trace_hppa_tlb_itlbp(env, ent, ent->access_id, ent->u, |
| 586 | ent->ar_pl2, ent->ar_pl1, ent->ar_type, |
| 587 | ent->b, ent->d, ent->t); |
| 588 | } |
| 589 | |
| 590 | void HELPER(idtlbt_pa20)(CPUHPPAState *env, target_ulong r1, target_ulong r2) |
| 591 | { |
| 592 | vaddr va_b = deposit64(env->cr[CR_IOR], 32, 32, env->cr[CR_ISR]); |
| 593 | itlbt_pa20(env, r1, r2, va_b); |
| 594 | } |
| 595 | |
| 596 | void HELPER(iitlbt_pa20)(CPUHPPAState *env, target_ulong r1, target_ulong r2) |
| 597 | { |
| 598 | vaddr va_b = deposit64(env->cr[CR_IIAOQ], 32, 32, env->cr[CR_IIASQ]); |
| 599 | itlbt_pa20(env, r1, r2, va_b); |
| 600 | } |
| 601 | |
| 602 | /* Purge (Insn/Data) TLB. */ |
| 603 | static void ptlb_work(CPUState *cpu, run_on_cpu_data data) |
| 604 | { |
| 605 | vaddr start = data.target_ptr; |
| 606 | vaddr end; |
| 607 | |
| 608 | /* |
| 609 | * PA2.0 allows a range of pages encoded into GR[b], which we have |
| 610 | * copied into the bottom bits of the otherwise page-aligned address. |
| 611 | * PA1.x will always provide zero here, for a single page flush. |
| 612 | */ |
| 613 | end = start & 0xf; |
| 614 | start &= TARGET_PAGE_MASK; |
| 615 | end = (vaddr)TARGET_PAGE_SIZE << (2 * end); |
| 616 | end = start + end - 1; |
| 617 | |
| 618 | hppa_flush_tlb_range(cpu_env(cpu), start, end); |
| 619 | } |
| 620 | |
| 621 | /* This is local to the current cpu. */ |
| 622 | void HELPER(ptlb_l)(CPUHPPAState *env, target_ulong addr) |
| 623 | { |
| 624 | trace_hppa_tlb_ptlb_local(env); |
| 625 | ptlb_work(env_cpu(env), RUN_ON_CPU_TARGET_PTR(addr)); |
| 626 | } |
| 627 | |
| 628 | /* This is synchronous across all processors. */ |
| 629 | void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) |
| 630 | { |
| 631 | CPUState *src = env_cpu(env); |
| 632 | CPUState *cpu; |
| 633 | bool wait = false; |
| 634 | |
| 635 | trace_hppa_tlb_ptlb(env); |
| 636 | run_on_cpu_data data = RUN_ON_CPU_TARGET_PTR(addr); |
| 637 | |
| 638 | CPU_FOREACH(cpu) { |
| 639 | if (cpu != src) { |
| 640 | async_run_on_cpu(cpu, ptlb_work, data); |
| 641 | wait = true; |
| 642 | } |
| 643 | } |
| 644 | if (wait) { |
| 645 | async_safe_run_on_cpu(src, ptlb_work, data); |
| 646 | } else { |
| 647 | ptlb_work(src, data); |
| 648 | } |
| 649 | } |
| 650 | |
| 651 | void hppa_ptlbe(CPUHPPAState *env) |
| 652 | { |
| 653 | uint32_t btlb_entries = HPPA_BTLB_ENTRIES(env); |
| 654 | uint32_t i; |
| 655 | |
| 656 | /* Zap the (non-btlb) tlb entries themselves. */ |
| 657 | memset(&env->tlb[btlb_entries], 0, |
| 658 | sizeof(env->tlb) - btlb_entries * sizeof(env->tlb[0])); |
| 659 | env->tlb_last = btlb_entries; |
| 660 | env->tlb_partial = NULL; |
| 661 | |
| 662 | /* Put them all onto the unused list. */ |
| 663 | env->tlb_unused = &env->tlb[btlb_entries]; |
| 664 | for (i = btlb_entries; i < ARRAY_SIZE(env->tlb) - 1; ++i) { |
| 665 | env->tlb[i].unused_next = &env->tlb[i + 1]; |
| 666 | } |
| 667 | |
| 668 | /* Re-initialize the interval tree with only the btlb entries. */ |
| 669 | memset(&env->tlb_root, 0, sizeof(env->tlb_root)); |
| 670 | for (i = 0; i < btlb_entries; ++i) { |
| 671 | if (env->tlb[i].entry_valid) { |
| 672 | interval_tree_insert(&env->tlb[i].itree, &env->tlb_root); |
| 673 | } |
| 674 | } |
| 675 | |
| 676 | tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK); |
| 677 | } |
| 678 | |
| 679 | /* Purge (Insn/Data) TLB entry. This affects an implementation-defined |
| 680 | number of pages/entries (we choose all), and is local to the cpu. */ |
| 681 | void HELPER(ptlbe)(CPUHPPAState *env) |
| 682 | { |
| 683 | trace_hppa_tlb_ptlbe(env); |
| 684 | qemu_log_mask(CPU_LOG_MMU, "FLUSH ALL TLB ENTRIES\n"); |
| 685 | hppa_ptlbe(env); |
| 686 | } |
| 687 | |
| 688 | void cpu_hppa_change_prot_id(CPUHPPAState *env) |
| 689 | { |
| 690 | tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_P_MASK); |
| 691 | } |
| 692 | |
| 693 | void HELPER(change_prot_id)(CPUHPPAState *env) |
| 694 | { |
| 695 | cpu_hppa_change_prot_id(env); |
| 696 | } |
| 697 | |
| 698 | target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong addr) |
| 699 | { |
| 700 | hwaddr phys; |
| 701 | int prot, excp; |
| 702 | |
| 703 | excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, 0, 0, |
| 704 | &phys, &prot); |
| 705 | if (excp >= 0) { |
| 706 | if (excp == EXCP_DTLB_MISS) { |
| 707 | excp = EXCP_NA_DTLB_MISS; |
| 708 | } |
| 709 | trace_hppa_tlb_lpa_failed(env, addr); |
| 710 | raise_exception_with_ior(env, excp, GETPC(), addr, false); |
| 711 | } |
| 712 | trace_hppa_tlb_lpa_success(env, addr, phys); |
| 713 | return phys; |
| 714 | } |
| 715 | |
| 716 | /* |
| 717 | * diag_btlb() emulates the PDC PDC_BLOCK_TLB firmware call to |
| 718 | * allow operating systems to modify the Block TLB (BTLB) entries. |
| 719 | * For implementation details see page 1-13 in |
| 720 | * https://parisc.wiki.kernel.org/images-parisc/e/ef/Pdc11-v0.96-Ch1-procs.pdf |
| 721 | */ |
| 722 | void HELPER(diag_btlb)(CPUHPPAState *env) |
| 723 | { |
| 724 | unsigned int phys_page, len, slot; |
| 725 | int mmu_idx = cpu_mmu_index(env_cpu(env), 0); |
| 726 | uintptr_t ra = GETPC(); |
| 727 | HPPATLBEntry *btlb; |
| 728 | uint64_t virt_page; |
| 729 | uint32_t *vaddr; |
| 730 | uint32_t btlb_entries = HPPA_BTLB_ENTRIES(env); |
| 731 | |
| 732 | /* BTLBs are not supported on 64-bit CPUs */ |
| 733 | if (btlb_entries == 0) { |
| 734 | env->gr[28] = -1; /* nonexistent procedure */ |
| 735 | return; |
| 736 | } |
| 737 | |
| 738 | env->gr[28] = 0; /* PDC_OK */ |
| 739 | |
| 740 | switch (env->gr[25]) { |
| 741 | case 0: |
| 742 | /* return BTLB parameters */ |
| 743 | qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_INFO\n"); |
| 744 | vaddr = probe_access(env, env->gr[24], 4 * sizeof(uint32_t), |
| 745 | MMU_DATA_STORE, mmu_idx, ra); |
| 746 | if (vaddr == NULL) { |
| 747 | env->gr[28] = -10; /* invalid argument */ |
| 748 | } else { |
| 749 | vaddr[0] = cpu_to_be32(1); |
| 750 | vaddr[1] = cpu_to_be32(16 * 1024); |
| 751 | vaddr[2] = cpu_to_be32(PA10_BTLB_FIXED); |
| 752 | vaddr[3] = cpu_to_be32(PA10_BTLB_VARIABLE); |
| 753 | } |
| 754 | break; |
| 755 | case 1: |
| 756 | /* insert BTLB entry */ |
| 757 | virt_page = env->gr[24]; /* upper 32 bits */ |
| 758 | virt_page <<= 32; |
| 759 | virt_page |= env->gr[23]; /* lower 32 bits */ |
| 760 | phys_page = env->gr[22]; |
| 761 | len = env->gr[21]; |
| 762 | slot = env->gr[19]; |
| 763 | qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_INSERT " |
| 764 | "0x%08llx-0x%08llx: vpage 0x%llx for phys page 0x%04x len %d " |
| 765 | "into slot %d\n", |
| 766 | (long long) virt_page << TARGET_PAGE_BITS, |
| 767 | (long long) (virt_page + len) << TARGET_PAGE_BITS, |
| 768 | (long long) virt_page, phys_page, len, slot); |
| 769 | if (slot < btlb_entries) { |
| 770 | btlb = &env->tlb[slot]; |
| 771 | |
| 772 | /* Force flush of possibly existing BTLB entry. */ |
| 773 | hppa_flush_tlb_ent(env, btlb, true); |
| 774 | |
| 775 | /* Create new BTLB entry */ |
| 776 | btlb->itree.start = virt_page << TARGET_PAGE_BITS; |
| 777 | btlb->itree.last = btlb->itree.start + len * TARGET_PAGE_SIZE - 1; |
| 778 | btlb->pa = phys_page << TARGET_PAGE_BITS; |
| 779 | set_access_bits_pa11(env, btlb, env->gr[20]); |
| 780 | btlb->t = 0; |
| 781 | btlb->d = 1; |
| 782 | } else { |
| 783 | env->gr[28] = -10; /* invalid argument */ |
| 784 | } |
| 785 | break; |
| 786 | case 2: |
| 787 | /* Purge BTLB entry */ |
| 788 | slot = env->gr[22]; |
| 789 | qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE slot %d\n", |
| 790 | slot); |
| 791 | if (slot < btlb_entries) { |
| 792 | btlb = &env->tlb[slot]; |
| 793 | hppa_flush_tlb_ent(env, btlb, true); |
| 794 | } else { |
| 795 | env->gr[28] = -10; /* invalid argument */ |
| 796 | } |
| 797 | break; |
| 798 | case 3: |
| 799 | /* Purge all BTLB entries */ |
| 800 | qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE_ALL\n"); |
| 801 | for (slot = 0; slot < btlb_entries; slot++) { |
| 802 | btlb = &env->tlb[slot]; |
| 803 | hppa_flush_tlb_ent(env, btlb, true); |
| 804 | } |
| 805 | break; |
| 806 | default: |
| 807 | env->gr[28] = -2; /* nonexistent option */ |
| 808 | break; |
| 809 | } |
| 810 | } |
| 811 | |
| 812 | uint64_t HELPER(b_gate_priv)(CPUHPPAState *env, uint64_t iaoq_f) |
| 813 | { |
| 814 | vaddr gva = hppa_form_gva(env, env->iasq_f, iaoq_f); |
| 815 | HPPATLBEntry *ent = hppa_find_tlb(env, gva); |
| 816 | |
| 817 | if (ent == NULL) { |
| 818 | raise_exception_with_ior(env, EXCP_ITLB_MISS, GETPC(), gva, false); |
| 819 | } |
| 820 | |
| 821 | /* |
| 822 | * There should be no need to check page permissions, as that will |
| 823 | * already have been done by tb_lookup via get_page_addr_code. |
| 824 | * All we need at this point is to check the ar_type. |
| 825 | * |
| 826 | * No change for non-gateway pages or for priv decrease. |
| 827 | */ |
| 828 | if (ent->ar_type & 4) { |
| 829 | int old_priv = iaoq_f & 3; |
| 830 | int new_priv = ent->ar_type & 3; |
| 831 | |
| 832 | if (new_priv < old_priv) { |
| 833 | iaoq_f = (iaoq_f & -4) | new_priv; |
| 834 | } |
| 835 | } |
| 836 | return iaoq_f; |
| 837 | } |
| 838 | |
| 839 | void HELPER(update_gva_offset_mask)(CPUHPPAState *env) |
| 840 | { |
| 841 | update_gva_offset_mask(env); |
| 842 | } |