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1 /*
2 * i386 CPU dump to FILE
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "qemu/qemu-print.h"
23 #ifndef CONFIG_USER_ONLY
24 #include "hw/i386/apic_internal.h"
25 #endif
26
27 /***********************************************************/
28 /* x86 debug */
29
30 static const char * const cc_op_str[] = {
31 [CC_OP_DYNAMIC] = "DYNAMIC",
32
33 [CC_OP_EFLAGS] = "EFLAGS",
34 [CC_OP_ADCX] = "ADCX",
35 [CC_OP_ADOX] = "ADOX",
36 [CC_OP_ADCOX] = "ADCOX",
37
38 [CC_OP_MULB] = "MULB",
39 [CC_OP_MULW] = "MULW",
40 [CC_OP_MULL] = "MULL",
41 [CC_OP_MULQ] = "MULQ",
42
43 [CC_OP_ADDB] = "ADDB",
44 [CC_OP_ADDW] = "ADDW",
45 [CC_OP_ADDL] = "ADDL",
46 [CC_OP_ADDQ] = "ADDQ",
47
48 [CC_OP_ADCB] = "ADCB",
49 [CC_OP_ADCW] = "ADCW",
50 [CC_OP_ADCL] = "ADCL",
51 [CC_OP_ADCQ] = "ADCQ",
52
53 [CC_OP_SUBB] = "SUBB",
54 [CC_OP_SUBW] = "SUBW",
55 [CC_OP_SUBL] = "SUBL",
56 [CC_OP_SUBQ] = "SUBQ",
57
58 [CC_OP_SBBB] = "SBBB",
59 [CC_OP_SBBW] = "SBBW",
60 [CC_OP_SBBL] = "SBBL",
61 [CC_OP_SBBQ] = "SBBQ",
62
63 [CC_OP_LOGICB] = "LOGICB",
64 [CC_OP_LOGICW] = "LOGICW",
65 [CC_OP_LOGICL] = "LOGICL",
66 [CC_OP_LOGICQ] = "LOGICQ",
67
68 [CC_OP_INCB] = "INCB",
69 [CC_OP_INCW] = "INCW",
70 [CC_OP_INCL] = "INCL",
71 [CC_OP_INCQ] = "INCQ",
72
73 [CC_OP_DECB] = "DECB",
74 [CC_OP_DECW] = "DECW",
75 [CC_OP_DECL] = "DECL",
76 [CC_OP_DECQ] = "DECQ",
77
78 [CC_OP_SHLB] = "SHLB",
79 [CC_OP_SHLW] = "SHLW",
80 [CC_OP_SHLL] = "SHLL",
81 [CC_OP_SHLQ] = "SHLQ",
82
83 [CC_OP_SARB] = "SARB",
84 [CC_OP_SARW] = "SARW",
85 [CC_OP_SARL] = "SARL",
86 [CC_OP_SARQ] = "SARQ",
87
88 [CC_OP_BMILGB] = "BMILGB",
89 [CC_OP_BMILGW] = "BMILGW",
90 [CC_OP_BMILGL] = "BMILGL",
91 [CC_OP_BMILGQ] = "BMILGQ",
92
93 [CC_OP_POPCNT] = "POPCNT",
94
95 [CC_OP_SBB_SELF] = "SBBx,x",
96 };
97
98 static void
99 cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f,
100 const char *name, struct SegmentCache *sc)
101 {
102 #ifdef TARGET_X86_64
103 if (env->hflags & HF_CS64_MASK) {
104 qemu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name,
105 sc->selector, sc->base, sc->limit,
106 sc->flags & 0x00ffff00);
107 } else
108 #endif
109 {
110 qemu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector,
111 (uint32_t)sc->base, sc->limit,
112 sc->flags & 0x00ffff00);
113 }
114
115 if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK))
116 goto done;
117
118 qemu_fprintf(f, " DPL=%d ",
119 (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT);
120 if (sc->flags & DESC_S_MASK) {
121 if (sc->flags & DESC_CS_MASK) {
122 qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" :
123 ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16"));
124 qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-',
125 (sc->flags & DESC_R_MASK) ? 'R' : '-');
126 } else {
127 qemu_fprintf(f, (sc->flags & DESC_B_MASK
128 || env->hflags & HF_LMA_MASK)
129 ? "DS " : "DS16");
130 qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-',
131 (sc->flags & DESC_W_MASK) ? 'W' : '-');
132 }
133 qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-');
134 } else {
135 static const char *sys_type_name[2][16] = {
136 { /* 32 bit mode */
137 "Reserved", "TSS16-avl", "LDT", "TSS16-busy",
138 "CallGate16", "TaskGate", "IntGate16", "TrapGate16",
139 "Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
140 "CallGate32", "Reserved", "IntGate32", "TrapGate32"
141 },
142 { /* 64 bit mode */
143 "<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
144 "Reserved", "Reserved", "Reserved", "Reserved",
145 "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
146 "Reserved", "IntGate64", "TrapGate64"
147 }
148 };
149 qemu_fprintf(f, "%s",
150 sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0]
151 [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]);
152 }
153 done:
154 qemu_fprintf(f, "\n");
155 }
156
157 #ifndef CONFIG_USER_ONLY
158
159 /* ARRAY_SIZE check is not required because
160 * DeliveryMode(dm) has a size of 3 bit.
161 */
162 static inline const char *dm2str(uint32_t dm)
163 {
164 static const char *str[] = {
165 "Fixed",
166 "...",
167 "SMI",
168 "...",
169 "NMI",
170 "INIT",
171 "...",
172 "ExtINT"
173 };
174 return str[dm];
175 }
176
177 static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer)
178 {
179 uint32_t dm = (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT;
180 qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s",
181 name, lvt,
182 lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi",
183 lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge",
184 lvt & APIC_LVT_MASKED ? "masked" : "",
185 lvt & APIC_LVT_DELIV_STS ? "pending" : "",
186 !is_timer ?
187 "" : lvt & APIC_LVT_TIMER_PERIODIC ?
188 "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ?
189 "tsc-deadline" : "one-shot",
190 dm2str(dm));
191 if (dm != APIC_DM_NMI) {
192 qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK);
193 } else {
194 qemu_printf("\n");
195 }
196 }
197
198 /* ARRAY_SIZE check is not required because
199 * destination shorthand has a size of 2 bit.
200 */
201 static inline const char *shorthand2str(uint32_t shorthand)
202 {
203 const char *str[] = {
204 "no-shorthand", "self", "all-self", "all"
205 };
206 return str[shorthand];
207 }
208
209 static inline uint8_t divider_conf(uint32_t divide_conf)
210 {
211 uint8_t divide_val = ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3);
212
213 return divide_val == 7 ? 1 : 2 << divide_val;
214 }
215
216 static inline void mask2str(char *str, uint32_t val, uint8_t size)
217 {
218 while (size--) {
219 *str++ = (val >> size) & 1 ? '1' : '0';
220 }
221 *str = 0;
222 }
223
224 #define MAX_LOGICAL_APIC_ID_MASK_SIZE 16
225
226 static void dump_apic_icr(APICCommonState *s, CPUX86State *env)
227 {
228 uint32_t icr = s->icr[0], icr2 = s->icr[1];
229 uint8_t dest_shorthand = \
230 (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT;
231 bool logical_mod = icr & APIC_ICR_DEST_MOD;
232 char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1];
233 uint32_t dest_field;
234 bool x2apic;
235
236 qemu_printf("ICR\t 0x%08x %s %s %s %s\n",
237 icr,
238 logical_mod ? "logical" : "physical",
239 icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge",
240 icr & APIC_ICR_LEVEL ? "assert" : "de-assert",
241 shorthand2str(dest_shorthand));
242
243 qemu_printf("ICR2\t 0x%08x", icr2);
244 if (dest_shorthand != 0) {
245 qemu_printf("\n");
246 return;
247 }
248 x2apic = env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC;
249 dest_field = x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT;
250
251 if (!logical_mod) {
252 if (x2apic) {
253 qemu_printf(" cpu %u (X2APIC ID)\n", dest_field);
254 } else {
255 qemu_printf(" cpu %u (APIC ID)\n",
256 dest_field & APIC_LOGDEST_XAPIC_ID);
257 }
258 return;
259 }
260
261 if (s->dest_mode == 0xf) { /* flat mode */
262 mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8);
263 qemu_printf(" mask %s (APIC ID)\n", apic_id_str);
264 } else if (s->dest_mode == 0) { /* cluster mode */
265 if (x2apic) {
266 mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16);
267 qemu_printf(" cluster %u mask %s (X2APIC ID)\n",
268 dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_str);
269 } else {
270 mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4);
271 qemu_printf(" cluster %u mask %s (APIC ID)\n",
272 dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_str);
273 }
274 }
275 }
276
277 static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab,
278 uint32_t *tmr_tab)
279 {
280 int i, empty = true;
281
282 qemu_printf("%s\t ", name);
283 for (i = 0; i < 256; i++) {
284 if (apic_get_bit(ireg_tab, i)) {
285 qemu_printf("%u%s ", i,
286 apic_get_bit(tmr_tab, i) ? "(level)" : "");
287 empty = false;
288 }
289 }
290 qemu_printf("%s\n", empty ? "(none)" : "");
291 }
292
293 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
294 {
295 X86CPU *cpu = X86_CPU(cs);
296 APICCommonState *s = cpu->apic_state;
297 if (!s) {
298 qemu_printf("local apic state not available\n");
299 return;
300 }
301 uint32_t *lvt = s->lvt;
302
303 qemu_printf("dumping local APIC state for CPU %-2u\n\n",
304 CPU(cpu)->cpu_index);
305 dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false);
306 dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false);
307 dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false);
308 dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false);
309 dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false);
310 dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true);
311
312 qemu_printf("Timer\t DCR=0x%x (divide by %u) initial_count = %u"
313 " current_count = %u\n",
314 s->divide_conf & APIC_DCR_MASK,
315 divider_conf(s->divide_conf),
316 s->initial_count, apic_get_current_count(s));
317
318 qemu_printf("SPIV\t 0x%08x APIC %s, focus=%s, spurious vec %u\n",
319 s->spurious_vec,
320 s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disabled",
321 s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off",
322 s->spurious_vec & APIC_VECTOR_MASK);
323
324 dump_apic_icr(s, &cpu->env);
325
326 qemu_printf("ESR\t 0x%08x\n", s->esr);
327
328 dump_apic_interrupt("ISR", s->isr, s->tmr);
329 dump_apic_interrupt("IRR", s->irr, s->tmr);
330
331 qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x",
332 s->arb_id, s->tpr, s->dest_mode, s->log_dest);
333 if (s->dest_mode == 0) {
334 qemu_printf("(cluster %u: id %u)",
335 s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT,
336 s->log_dest & APIC_LOGDEST_XAPIC_ID);
337 }
338 qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s));
339 }
340
341 #endif /* !CONFIG_USER_ONLY */
342
343 #define DUMP_CODE_BYTES_TOTAL 50
344 #define DUMP_CODE_BYTES_BACKWARD 20
345
346 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
347 {
348 X86CPU *cpu = X86_CPU(cs);
349 CPUX86State *env = &cpu->env;
350 int eflags, i, nb;
351 static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
352
353 eflags = cpu_compute_eflags(env);
354 #ifdef TARGET_X86_64
355 if (env->hflags & HF_CS64_MASK) {
356 qemu_fprintf(f, "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
357 "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
358 "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
359 "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n",
360 env->regs[R_EAX],
361 env->regs[R_EBX],
362 env->regs[R_ECX],
363 env->regs[R_EDX],
364 env->regs[R_ESI],
365 env->regs[R_EDI],
366 env->regs[R_EBP],
367 env->regs[R_ESP],
368 env->regs[8],
369 env->regs[9],
370 env->regs[10],
371 env->regs[11],
372 env->regs[12],
373 env->regs[13],
374 env->regs[14],
375 env->regs[15]);
376
377 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APXF) {
378 qemu_fprintf(f, "R16=%016" PRIx64 " R17=%016" PRIx64 " R18=%016" PRIx64 " R19=%016" PRIx64 "\n"
379 "R20=%016" PRIx64 " R21=%016" PRIx64 " R22=%016" PRIx64 " R23=%016" PRIx64 "\n"
380 "R24=%016" PRIx64 " R25=%016" PRIx64 " R26=%016" PRIx64 " R27=%016" PRIx64 "\n"
381 "R28=%016" PRIx64 " R29=%016" PRIx64 " R30=%016" PRIx64 " R31=%016" PRIx64 "\n",
382 env->regs[16],
383 env->regs[17],
384 env->regs[18],
385 env->regs[19],
386 env->regs[20],
387 env->regs[21],
388 env->regs[22],
389 env->regs[23],
390 env->regs[24],
391 env->regs[25],
392 env->regs[26],
393 env->regs[27],
394 env->regs[28],
395 env->regs[29],
396 env->regs[30],
397 env->regs[31]);
398 }
399
400 qemu_fprintf(f, "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
401 env->eip, eflags,
402 eflags & DF_MASK ? 'D' : '-',
403 eflags & CC_O ? 'O' : '-',
404 eflags & CC_S ? 'S' : '-',
405 eflags & CC_Z ? 'Z' : '-',
406 eflags & CC_A ? 'A' : '-',
407 eflags & CC_P ? 'P' : '-',
408 eflags & CC_C ? 'C' : '-',
409 env->hflags & HF_CPL_MASK,
410 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
411 (env->a20_mask >> 20) & 1,
412 (env->hflags >> HF_SMM_SHIFT) & 1,
413 cs->halted);
414 } else
415 #endif
416 {
417 qemu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
418 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
419 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
420 (uint32_t)env->regs[R_EAX],
421 (uint32_t)env->regs[R_EBX],
422 (uint32_t)env->regs[R_ECX],
423 (uint32_t)env->regs[R_EDX],
424 (uint32_t)env->regs[R_ESI],
425 (uint32_t)env->regs[R_EDI],
426 (uint32_t)env->regs[R_EBP],
427 (uint32_t)env->regs[R_ESP],
428 (uint32_t)env->eip, eflags,
429 eflags & DF_MASK ? 'D' : '-',
430 eflags & CC_O ? 'O' : '-',
431 eflags & CC_S ? 'S' : '-',
432 eflags & CC_Z ? 'Z' : '-',
433 eflags & CC_A ? 'A' : '-',
434 eflags & CC_P ? 'P' : '-',
435 eflags & CC_C ? 'C' : '-',
436 env->hflags & HF_CPL_MASK,
437 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
438 (env->a20_mask >> 20) & 1,
439 (env->hflags >> HF_SMM_SHIFT) & 1,
440 cs->halted);
441 }
442
443 for(i = 0; i < 6; i++) {
444 cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]);
445 }
446 cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt);
447 cpu_x86_dump_seg_cache(env, f, "TR", &env->tr);
448
449 #ifdef TARGET_X86_64
450 if (env->hflags & HF_LMA_MASK) {
451 qemu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
452 env->gdt.base, env->gdt.limit);
453 qemu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
454 env->idt.base, env->idt.limit);
455 qemu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
456 (uint32_t)env->cr[0],
457 env->cr[2],
458 env->cr[3],
459 (uint32_t)env->cr[4]);
460 for(i = 0; i < 4; i++)
461 qemu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);
462 qemu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",
463 env->dr[6], env->dr[7]);
464 } else
465 #endif
466 {
467 qemu_fprintf(f, "GDT= %08x %08x\n",
468 (uint32_t)env->gdt.base, env->gdt.limit);
469 qemu_fprintf(f, "IDT= %08x %08x\n",
470 (uint32_t)env->idt.base, env->idt.limit);
471 qemu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
472 (uint32_t)env->cr[0],
473 (uint32_t)env->cr[2],
474 (uint32_t)env->cr[3],
475 (uint32_t)env->cr[4]);
476 for(i = 0; i < 4; i++) {
477 qemu_fprintf(f, "DR%d=" TARGET_FMT_lx " ", i, env->dr[i]);
478 }
479 qemu_fprintf(f, "\nDR6=" TARGET_FMT_lx " DR7=" TARGET_FMT_lx "\n",
480 env->dr[6], env->dr[7]);
481 }
482 if (flags & CPU_DUMP_CCOP) {
483 const char *cc_op_name = NULL;
484 char cc_op_buf[32];
485
486 if ((unsigned)env->cc_op < ARRAY_SIZE(cc_op_str)) {
487 cc_op_name = cc_op_str[env->cc_op];
488 }
489 if (cc_op_name == NULL) {
490 snprintf(cc_op_buf, sizeof(cc_op_buf), "[%d]", env->cc_op);
491 cc_op_name = cc_op_buf;
492 }
493 #ifdef TARGET_X86_64
494 if (env->hflags & HF_CS64_MASK) {
495 qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%s\n",
496 env->cc_src, env->cc_dst,
497 cc_op_name);
498 } else
499 #endif
500 {
501 qemu_fprintf(f, "CCS=%08x CCD=%08x CCO=%s\n",
502 (uint32_t)env->cc_src, (uint32_t)env->cc_dst,
503 cc_op_name);
504 }
505 }
506 qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
507 if (flags & CPU_DUMP_FPU) {
508 int fptag;
509 const uint64_t avx512_mask = XSTATE_OPMASK_MASK | \
510 XSTATE_ZMM_Hi256_MASK | \
511 XSTATE_Hi16_ZMM_MASK | \
512 XSTATE_YMM_MASK | XSTATE_SSE_MASK,
513 avx_mask = XSTATE_YMM_MASK | XSTATE_SSE_MASK;
514 fptag = 0;
515 for(i = 0; i < 8; i++) {
516 fptag |= ((!env->fptags[i]) << i);
517 }
518 update_mxcsr_from_sse_status(env);
519 qemu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
520 env->fpuc,
521 (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
522 env->fpstt,
523 fptag,
524 env->mxcsr);
525 for(i=0;i<8;i++) {
526 CPU_LDoubleU u;
527 u.d = env->fpregs[i].d;
528 qemu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
529 i, u.l.lower, u.l.upper);
530 if ((i & 1) == 1)
531 qemu_fprintf(f, "\n");
532 else
533 qemu_fprintf(f, " ");
534 }
535
536 if ((env->xcr0 & avx512_mask) == avx512_mask) {
537 /* XSAVE enabled AVX512 */
538 for (i = 0; i < NB_OPMASK_REGS; i++) {
539 qemu_fprintf(f, "Opmask%02d=%016"PRIx64"%s", i,
540 env->opmask_regs[i], ((i & 3) == 3) ? "\n" : " ");
541 }
542
543 nb = (env->hflags & HF_CS64_MASK) ? 32 : 8;
544 for (i = 0; i < nb; i++) {
545 qemu_fprintf(f, "ZMM%02d=%016"PRIx64" %016"PRIx64" %016"PRIx64
546 " %016"PRIx64" %016"PRIx64" %016"PRIx64
547 " %016"PRIx64" %016"PRIx64"\n",
548 i,
549 env->xmm_regs[i].ZMM_Q(7),
550 env->xmm_regs[i].ZMM_Q(6),
551 env->xmm_regs[i].ZMM_Q(5),
552 env->xmm_regs[i].ZMM_Q(4),
553 env->xmm_regs[i].ZMM_Q(3),
554 env->xmm_regs[i].ZMM_Q(2),
555 env->xmm_regs[i].ZMM_Q(1),
556 env->xmm_regs[i].ZMM_Q(0));
557 }
558 } else if ((env->xcr0 & avx_mask) == avx_mask) {
559 /* XSAVE enabled AVX */
560 nb = env->hflags & HF_CS64_MASK ? 16 : 8;
561 for (i = 0; i < nb; i++) {
562 qemu_fprintf(f, "YMM%02d=%016"PRIx64" %016"PRIx64" %016"PRIx64
563 " %016"PRIx64"\n", i,
564 env->xmm_regs[i].ZMM_Q(3),
565 env->xmm_regs[i].ZMM_Q(2),
566 env->xmm_regs[i].ZMM_Q(1),
567 env->xmm_regs[i].ZMM_Q(0));
568 }
569 } else { /* SSE and below cases */
570 nb = env->hflags & HF_CS64_MASK ? 16 : 8;
571 for (i = 0; i < nb; i++) {
572 qemu_fprintf(f, "XMM%02d=%016"PRIx64" %016"PRIx64"%s",
573 i,
574 env->xmm_regs[i].ZMM_Q(1),
575 env->xmm_regs[i].ZMM_Q(0),
576 (i & 1) ? "\n" : " ");
577 }
578 }
579 }
580 if (flags & CPU_DUMP_CODE) {
581 target_ulong base = env->segs[R_CS].base + env->eip;
582 target_ulong offs = MIN(env->eip, DUMP_CODE_BYTES_BACKWARD);
583 uint8_t code;
584 char codestr[3];
585
586 qemu_fprintf(f, "Code=");
587 for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
588 if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) {
589 snprintf(codestr, sizeof(codestr), "%02x", code);
590 } else {
591 snprintf(codestr, sizeof(codestr), "??");
592 }
593 qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "",
594 i == offs ? "<" : "", codestr, i == offs ? ">" : "");
595 }
596 qemu_fprintf(f, "\n");
597 }
598 }